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GVT71512DA18T-6 [CYPRESS]

Standard SRAM, 512KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
GVT71512DA18T-6
型号： GVT71512DA18T-6
厂家： CYPRESS    CYPRESS
描述：

Standard SRAM, 512KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

静态存储器 内存集成电路
文件： 总27页 (文件大小：320K)
中文：  中文翻译
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CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
256K x 36/512K x 18 Pipelined SRAM  
eral circuitry and a 2-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a pos-  
itive-edge-triggered Clock Input (CLK). The synchronous in-  
puts include all addresses, all data inputs, address-pipelining  
Features  
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Fast clock speed: 225, 200, 166, and 150 MHz  
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns  
• Optimal for depth expansion (one cycle chip deselect  
to eliminate bus contention)  
• 3.3V –5% and +10% power supply  
• 3.3V or 2.5V I/O supply  
• 5V tolerant inputs except I/Os  
Chip Enable (CE), depth-expansion Chip Enables (CE and  
2
CE ), burst control inputs (ADSC, ADSP, and ADV), Write En-  
2
ables (BWa, BWb, BWc, BWd, and BWE), and global write  
(GW). However, the CE chip enable input is only available for  
2
TA(GVTI)/A(CY) package version.  
Asynchronous inputs include the Output Enable (OE) and  
burst mode control (MODE). The data outputs (Q), enabled by  
OE, are also asynchronous.  
• Clamp diodes to V at all inputs and outputs  
SS  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Multiple chip enables for depth expansion:  
three chip enables for TA(GVTI)/A(CY) package version  
and two chip enables for B(GVTI)/BG(CY) and  
T(GVTI)/AJ(CY) package versions  
• Address pipeline capability  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst se-  
quence)  
• Automatic power-down for portable applications  
Addresses and chip enables are registered with either Ad-  
dress Status Processor (ADSP) or Address Status Controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the Burst Advance Pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed WRITE cycle. WRITE cycles can be one  
to four bytes wide as controlled by the write control inputs.  
Individual byte write allows individual byte to be written. BWa  
controls DQa. BWb controls DQb. BWc controls DQc. BWd  
controls DQd. BWa, BWb, BWc, and BWd can be active only  
with BWE being LOW. GW being LOW causes all bytes to be  
written. The x18 version only has 18 data inputs/outputs (DQa  
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and  
DQd).  
• JTAG boundary scan for B(GVTI)/BG(CY) and  
T(GVTI)/AJ(CY) package version  
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-  
sions, four pins are used to implement JTAG test capabilities:  
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),  
and Test Data-Out (TDO). The JTAG circuitry is used to serially  
shift data to and from the device. JTAG inputs use  
LVTTL/LVCMOS levels to shift data during this testing mode of  
operation. The TA package version does not offer the JTAG  
capability.  
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid  
Array) and 100-pin TQFP packages  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low power CMOS designs using advanced tri-  
ple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high valued  
resistors.  
The CY7C1360A1/GVT71256DA36 and CY7C1362A1/  
GVT71512DA18 operate from a +3.3V power supply. All inputs  
and outputs are LVTTL compatible.  
The CY7C1360A1/GVT71256DA36 and CY7C1362A1/  
GVT71512DA18 SRAMs integrate 262,144x36 and  
524,288x18 SRAM cells with advanced synchronous periph-  
Selection Guide  
7C1360A1-225 7C1360A1-200 7C1360A1-166 7C1360A1-150  
71256DA36-4.4 71256DA36-5 71256DA36-6 71256DA36-6.7  
7C1362A1-225 7C1362A1-200 7C1362A1-166 7C1362A1-150  
71512DA18-4.4  
71512DA18-5  
71512DA18-6 71512DA18-6.7  
Maximum Access Time (ns)  
2.5  
570  
10  
3.0  
510  
10  
3.5  
425  
10  
3.5  
380  
10  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Commercial  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
May 18, 2000  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Functional Block Diagram—256K x 36[1]  
BYTE a WRITE  
BWa#  
BWE#  
D
Q
CLK  
BYTE b WRITE  
BWb#  
D
Q
GW#  
BYTE c WRITE  
BWc#  
D
Q
BYTE d WRITE  
BWd#  
D
Q
ENABLE  
CE#  
CE2  
D
Q
D
Q
[2]  
CE2#  
OE#  
ZZ  
Power Down Logic  
Input  
Register  
ADSP#  
16  
A
Address  
Register  
OUTPUT  
REGISTER  
ADSC#  
DQa,DQb  
DQc,DQd  
CLR  
D
Q
ADV#  
A1-A0  
MODE  
Binary  
Counter  
& Logic  
Functional Block Diagram—512K x 18[1]  
BYTE b  
WRITE  
BWb#  
BWE#  
D
Q
BYTE a  
WRITE  
BWa#  
GW#  
D
Q
ENABLE  
CE#  
CE2  
[2]  
D
Q
D
Q
CE2#  
ZZ  
Power Down Logic  
OE#  
ADSP#  
Input  
Register  
17  
A
Address  
Register  
OUTPUT  
REGISTER  
ADSC#  
DQa,D  
Qb  
CLR  
D
Q
ADV#  
A1-A0  
MODE  
Binary  
Counter  
& Logic  
Notes:  
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.  
2. CE2 is for TA version only.  
2
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Pin Configurations  
100-Pin TQFP  
Top View  
DQc  
1
DQb  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
NC  
VCCQ  
VSS  
NC  
A
NC  
NC  
VCCQ  
VSS  
NC  
DPa  
DQa  
DQa  
VSS  
VCCQ  
DQa  
DQa  
VSS  
NC  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQc  
2
DQb  
DQb  
VCCQ  
VSS  
DQb  
DQb  
DQb  
DQb  
VSS  
VCCQ  
DQb  
DQb  
VSS  
DQc  
3
VCCQ  
VSS  
DQc  
4
5
6
DQc  
7
NC  
DQc  
8
DQb  
DQb  
VSS  
VCCQ  
DQb  
DQb  
NC  
DQc  
9
9
VSS  
10  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VCCQ  
11  
DQc  
12  
DQc  
13  
NC  
14  
VCC  
15  
NC  
VCC  
ZZ  
VCC  
NC  
CY7C1362A1/GVT71512DA18  
(512K x 18)  
CY7C1360A1/GVT71256DA36  
NC  
VSS  
DQd  
DQd  
VCCQ  
VSS  
DQd  
DQd  
DQd  
DQd  
VSS  
VCCQ  
DQd  
DQd  
DQd  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VCC  
ZZ  
(256K X 36)  
T Package Version  
VSS  
DQb  
DQb  
VCCQ  
VSS  
DQb  
DQb  
DQb  
NC  
VSS  
VCCQ  
NC  
NC  
NC  
DQa  
DQa  
VCCQ  
VSS  
DQa  
DQa  
DQa  
DQa  
VSS  
VCCQ  
DQa  
DQa  
DQa  
DQa  
DQa  
VCCQ  
VSS  
DQa  
DQa  
NC  
T Package Version  
NC  
VSS  
VDDQ  
NC  
NC  
NC  
DQc  
DQc  
DQc  
VCCQ  
VSS  
DQc  
DQc  
DQc  
DQc  
VSS  
VCCQ  
DQc  
DQc  
NC  
VCC  
NC  
DQb  
DQb  
DQb  
VCCQ  
VSS  
DQb  
DQb  
DQb  
DQb  
VSS  
VCCQ  
DQb  
DQb  
VSS  
NC  
VCC  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
NC  
VCCQ  
VSS  
NC  
A
NC  
NC  
VCCQ  
VSS  
NC  
DQa  
DQa  
DQa  
VSS  
VCCQ  
DQa  
DQa  
VSS  
NC  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
DQb  
DQb  
VSS  
VCCQ  
DQb  
DQb  
NC  
9
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VCC  
NC  
CY7C1362A1/GVT71512DA18  
(512K x 18)  
CY7C1360A1/GVT71256DA36  
(256K X 36)  
VCC  
ZZ  
VSS  
ZZ  
VSS  
DQb  
DQb  
VCCQ  
VSS  
DQb  
DQb  
DQb  
NC  
VSS  
VCCQ  
NC  
NC  
NC  
DQd  
DQd  
VCCQ  
VSS  
DQd  
DQd  
DQd  
DQd  
VSS  
VCCQ  
DQd  
DQd  
DQd  
DQa  
DQa  
VCCQ  
VSS  
DQa  
DQa  
DQa  
DQa  
VSS  
VCCQ  
DQa  
DQa  
DQa  
DQa  
DQa  
VCCQ  
VSS  
DQa  
DQa  
NC  
TA Package Version  
TA Package Version  
NC  
VSS  
VCCQ  
NC  
NC  
NC  
3
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Pin Configurations (continued)  
119-Ball BGA  
Top View  
256Kx36  
4
1
2
A
3
A
A
A
5
A
A
A
6
7
A
B
C
D
E
F
V
ADSP  
ADSC  
A
V
CCQ  
CCQ  
NC  
NC  
CE  
A
A
NC  
NC  
2
V
A
CC  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
V
NC  
CE  
V
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
SS  
SS  
SS  
SS  
SS  
SS  
V
V
V
V
V
OE  
V
CCQ  
CCQ  
G
H
J
DQc  
BWc  
ADV  
GW  
BWb  
DQb  
DQc  
V
V
DQb  
SS  
SS  
V
V
NC  
V
NC  
V
V
CCQ  
CCQ  
CC  
CC  
CC  
K
L
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
A
V
CLK  
NC  
V
DQa  
DQa  
DQa  
DQa  
DQa  
A
DQa  
SS  
SS  
DQd  
BWd  
BWa  
DQa  
M
N
P
R
T
V
V
V
V
BWE  
A1  
V
V
V
V
CCQ  
CCQ  
SS  
SS  
SS  
SS  
SS  
SS  
DQd  
DQa  
DQd  
A0  
DQa  
NC  
ZZ  
MODE  
A
V
NC  
A
CC  
NC  
NC  
A
NC  
U
V
TCK  
V
CCQ  
CCQ  
512Kx18  
1
2
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
A
ADSP  
ADSC  
A
V
CCQ  
CCQ  
NC  
NC  
CE  
A
CE  
A
NC  
NC  
2
2
V
CC  
DQb  
NC  
NC  
DQb  
NC  
V
NC  
CE  
V
V
V
V
V
DQa  
NC  
NC  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
V
V
DQa  
V
OE  
DQa  
NC  
V
CCQ  
CCQ  
G
H
J
NC  
DQb  
NC  
BWb  
ADV  
GW  
DQa  
DQb  
V
DQa  
NC  
SS  
V
V
NC  
V
NC  
V
V
CCQ  
CCQ  
CC  
CC  
CC  
K
L
NC  
DQb  
NC  
DQb  
NC  
DQb  
A
V
V
V
V
V
CLK  
NC  
V
NC  
DQa  
NC  
DQa  
NC  
A
DQa  
SS  
SS  
SS  
SS  
SS  
SS  
DQb  
BWa  
NC  
M
N
P
R
T
V
BWE  
A1  
V
V
V
V
CCQ  
CCQ  
SS  
SS  
SS  
DQb  
NC  
NC  
A0  
DQa  
NC  
ZZ  
MODE  
A
V
NC  
A
CC  
NC  
A
NC  
A
U
V
TCK  
V
CCQ  
CCQ  
4
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
256K X 36 Pin Descriptions  
X36 PBGA Pins  
X36 QFP Pins  
Name  
Type  
Description  
4P  
4N  
37  
36  
A0  
A1  
A
Input-  
Addresses: These inputs are registered and must meet  
Synchronous the set-up and hold times around the rising edge of CLK.  
The burst counter generates internal addresses associ-  
ated with A0 and A1, during burst cycle and wait cycle.  
2A, 3A, 5A, 6A, 3B,  
5B, 6B, 2C, 3C, 5C,  
35, 34, 33, 32,  
100, 99, 82, 81,  
6C, 2R, 6R, 3T, 4T, 5T 44, 45, 46, 47, 48,  
49, 50  
92 (T Version)  
43 (TA Version)  
5L  
5G  
3G  
3L  
93  
94  
95  
96  
BWa  
BWb  
BWc  
BWd  
Input-  
Byte Write: A byte write is LOW for a WRITE cycle and  
Synchronous HIGH for a READ cycle. BWa controls DQa. BWb con-  
trols DQb. BWc controls DQc. BWd controls DQd. Data  
I/O are high impedance if either of these inputs are LOW,  
conditioned by BWE being LOW.  
4M  
4H  
87  
88  
BWE  
GW  
Input-  
Write Enable: This active LOW input gates byte write  
Synchronous operations and must meet the set-up and hold times  
around the rising edge of CLK.  
Input-  
Global Write: This active LOW input allows a full 36-bit  
Synchronous WRITE to occur independent of the BWE and BWn lines  
and must meet the set-up and hold times around the  
rising edge of CLK.  
4K  
89  
CLK  
CE  
Input-  
Clock: This signal registers the addresses, data, chip  
Synchronous enables, write control and burst control inputs on its ris-  
ing edge. All synchronous inputs must meet set-up and  
hold times around the clock’s rising edge.  
4E  
2B  
98  
97  
Input-  
Chip Enable: This active LOW input is used to enable the  
Synchronous device and to gate ADSP.  
CE  
CE  
Input-  
Chip Enable: This active HIGH input is used to enable  
2
2
Synchronous the device.  
- (not available for PB- 92 (for TA Version  
Input-  
Chip Enable: This active LOW input is used to enable the  
GA)  
only)  
Synchronous device. Not available for B and T package versions.  
4F  
86  
OE  
Input  
Output Enable: This active LOW asynchronous input en-  
ables the data output drivers.  
4G  
4A  
83  
84  
ADV  
Input-  
Address Advance: This active LOW input is used to con-  
Synchronous trol the internal burst counter. A HIGH on this pin gener-  
ates wait cycle (no address advance).  
ADSP  
ADSC  
Input-  
Address Status Processor: This active LOW input, along  
Synchronous with CE being LOW, causes a new external address to  
be registered and a READ cycle is initiated using the new  
address.  
4B  
85  
Input-  
Address Status Controller: This active LOW input caus-  
Synchronous es device to be deselected or selected along with new  
external address to be registered. A READ or WRITE  
cycle is initiated depending upon write control inputs.  
3R  
7T  
31  
64  
MODE  
ZZ  
Input-  
Static  
Mode: This input selects the burst sequence. A LOW on  
this pin selects Linear Burst. A NC or HIGH on this pin  
selects Interleaved Burst.  
Input-  
Snooze: This active HIGH input puts the device in low  
Asynchronous power consumption standby mode. For normal opera-  
tion, this input has to be either LOW or NC (No Connect).  
5
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
256K X 36 Pin Descriptions (continued)  
X36 PBGA Pins  
X36 QFP Pins  
Name  
Type  
Description  
(a) 6P, 7P, 7N, 6N,  
6M, 6L, 7L, 6K, 7K,  
(b) 7H, 6H, 7G, 6G, (b) 68, 69, 72, 73,  
6F, 6E, 7E, 7D, 6D, 74, 75, 78, 79, 80  
(c) 2D, 1D, 1E, 2E, 2F, (c) 1, 2, 3, 6, 7, 8,  
(a) 51, 52, 53, 56,  
57, 58, 59, 62, 63  
DQa  
DQb  
DQc  
DQd  
Input/  
Output  
Data Inputs/Outputs: First Byte is DQa. Second Byte is  
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data  
must meet set-up and hold times around the rising edge  
of CLK.  
1G, 2G, 1H, 2H,  
(d) 1K, 2K, 1L, 2L,  
2M, 1N, 2N, 1P, 2P  
9, 12, 13  
(d) 18, 19, 22, 23,  
24, 25, 28, 29, 30  
2U  
3U  
4U  
38  
39  
43  
TMS  
TDI  
TCK  
Input  
IEEE 1149.1 test inputs. LVTTL-level inputs. Not avail-  
able for TA package version.  
for B and T version  
5U  
42  
TDO  
Output  
IEEE 1149.1 test output. LVTTL-level output. Not avail-  
able for TA package version.  
for B and T version  
4C, 2J, 4J, 6J, 4R  
15, 41, 65, 91  
V
Supply  
Ground  
Core power Supply: +3.3V –5% and +10%  
CC  
3D, 5D, 3E, 5E, 3F, 5F, 5, 10, 17, 21, 26,  
3H, 5H, 3K, 5K, 3M, 40, 55, 60, 67, 71,  
V
Ground: GND.  
SS  
5M, 3N, 5N, 3P, 5P  
76, 90  
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,  
V
I/O Supply  
-
Output Buffer Supply: +2.5V or +3.3V.  
CCQ  
1M, 7M, 1U, 7U  
61, 70, 77  
14, 16, 66  
1B, 7B, 1C, 7C, 4D,  
3J, 5J, 4L, 1R, 5R,  
7R, 1T, 2T, 6T, 6U  
NC  
No Connect: These signals are not internally connected.  
User can leave it floating or connect it to V or V  
.
CC  
SS  
38, 39, 42 for TA  
Version  
512K X 18 Pin Descriptions  
X18 PBGA Pins  
X18 QFP Pins  
Name  
Type  
Description  
4P  
4N  
37  
36  
A0  
A1  
A
Input-  
Addresses: These inputs are registered and must meet  
Synchronous the set up and hold times around the rising edge of CLK.  
The burst counter generates internal addresses associ-  
ated with A0 and A1, during burst cycle and wait cycle.  
2A, 3A, 5A, 6A, 3B,  
5B, 6B, 2C, 3C, 5C,  
35, 34, 33, 32,  
100, 99, 82, 81,  
6C, 2R, 6R, 2T, 3T, 80, 48, 47, 46, 45,  
5T, 6T  
44, 49, 50  
92 (T Version)  
43 (TA Version)  
5L  
3G  
93  
94  
BWa  
BWb  
Input-  
Byte Write Enables: A byte write enable is LOW for a  
Synchronous WRITE cycle and HIGH for a READ cycle. BWa controls  
DQa. BWb controls DQb. Data I/O are high impedance if  
either of these inputs are LOW, conditioned by BWE be-  
ing LOW.  
4M  
4H  
87  
88  
BWE  
GW  
Input-  
Write Enable: This active LOW input gates byte write op-  
Synchronous erations and must meet the set-up and hold times around  
the rising edge of CLK.  
Input-  
Global Write: This active LOW input allows a full 18-bit  
Synchronous WRITE to occur independent of the BWE and WEn lines  
and must meet the set-up and hold times around the ris-  
ing edge of CLK.  
4K  
4E  
89  
98  
CLK  
CE  
Input-  
Clock: This signal registers the addresses, data, chip en-  
Synchronous ables, write control and burst control inputs on its rising  
edge. All synchronous inputs must meet set-up and hold  
times around the clock’s rising edge.  
Input-  
Chip Enable: This active LOW input is used to enable the  
Synchronous device and to gate ADSP.  
6
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
512K X 18 Pin Descriptions (continued)  
X18 PBGA Pins  
X18 QFP Pins  
Name  
Type  
Description  
2B  
97  
CE  
Input-  
Chip Enable: This active HIGH input is used to enable the  
2
Synchronous device.  
- (not available for  
PBGA)  
92 (for TA Version  
only)  
CE  
Input-  
Chip Enable: This active LOW input is used to enable the  
2
Synchronous device. Not available for B and T package versions.  
4F  
86  
OE  
Input  
Output Enable: This active LOW asynchronous input en-  
ables the data output drivers.  
4G  
83  
ADV  
Input-  
Address Advance: This active LOW input is used to con-  
Synchronous trol the internal burst counter. A HIGH on this pin gener-  
ates wait cycle (no address advance).  
4A  
4B  
84  
85  
ADSP  
ADSC  
Input-  
Address Status Processor: This active LOW input, along  
Synchronous with CE being LOW, causes a new external address to be  
registered and a READ cycle is initiated using the new  
address.  
Input-  
Address Status Controller: This active LOW input causes  
Synchronous device to be deselected or selected along with new exter-  
nal address to be registered. A READ or WRITE cycle is  
initiated depending upon write control inputs.  
3R  
7T  
31  
64  
MODE  
ZZ  
Input-  
Static  
Mode: This input selects the burst sequence. A LOW on  
this pin selects Linear Burst. A NC or HIGH on this pin  
selects Interleaved Burst.  
Input-  
Snooze: This active HIGH input puts the device in low  
Asynchronous power consumption standby mode. For normaloperation,  
this input has to be either LOW or NC (No Connect).  
(a) 6D, 7E, 6F, 7G, (a) 58, 59, 62, 63,  
6H, 7K, 6L, 6N, 7P 68, 69, 72, 73, 74  
(b) 1D, 2E, 2G, 1H, (b)8, 9, 12, 13, 18,  
DQa  
DQb  
Input/  
Output  
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb.  
Input data must meet set up and hold times around the  
rising edge of CLK.  
2K, 1L, 2M, 1N, 2P  
19, 22, 23, 24  
2U  
3U  
4U  
38  
39  
43  
TMS  
TDI  
TCK  
Input  
IEEE 1149.1 test inputs. LVTTL-levelinputs. Not available  
for TA package version.  
for B and T version  
5U  
42  
TDO  
Output  
IEEE 1149.1 test output. LVTTL-level output. Not avail-  
able for TA package version.  
for B and T version  
4C, 2J, 4J, 6J, 4R  
3D, 5D, 3E, 5E, 3F,  
15, 41,65, 91  
V
Supply  
Ground  
Core power Supply: +3.3V –5% and +10%  
CC  
5, 10, 17, 21, 26,  
V
Ground: GND.  
SS  
5F, 5G, 3H, 5H, 3K, 40, 55, 60, 67, 71,  
5K, 3L, 3M, 5M, 3N,  
5N, 3P, 5P  
76, 90  
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,  
V
I/O Supply  
-
Output Buffer Supply: +2.5V or +3.3V.  
CCQ  
1M, 7M, 1U, 7U  
61, 70, 77  
1B, 7B, 1C, 7C, 2D,  
4D, 7D, 1E, 6E, 2F,  
1-3, 6, 7, 14, 16,  
25, 28-30, 51-53,  
NC  
No Connect: These signals are not internally connected.  
User can leave it floating or connect it to V or V  
.
CC  
SS  
1G, 6G, 2H, 7H, 3J, 56, 57, 66, 75, 78,  
5J, 1K, 6K, 2L, 4L,  
7L, 6M, 2N, 7N, 1P,  
6P, 1R, 5R, 7R, 1T,  
4T, 6U  
79, 80, 95, 96  
38, 39, 42 for TA  
Version  
7
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Burst Address Table (MODE = NC/V  
)
Burst Address Table (MODE = GND)  
CC  
First  
Address  
(external)  
Second  
Address  
(internal)  
Third  
Address  
(internal)  
Fourth  
Address  
(internal)  
First  
Address  
(external)  
Second  
Address  
(internal)  
Third  
Address  
(internal)  
Fourth  
Address  
(internal)  
A...A00  
A...A01  
A...A10  
A...A11  
A...A01  
A...A00  
A...A11  
A...A10  
A...A10  
A...A11  
A...A00  
A...A01  
A...A11  
A...A10  
A...A01  
A...A00  
A...A00  
A...A01  
A...A10  
A...A11  
A...A01  
A...A10  
A...A11  
A...A00  
A...A10  
A...A11  
A...A00  
A...A01  
A...A11  
A...A00  
A...A01  
A...A10  
Truth Table[3, 4, 5, 6, 7, 8, 9]  
Operation  
Address Used CE CE  
CE ADSP ADSC ADV WRITE OE CLK  
DQ  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Q
2
2
Deselected Cycle, Power Down None  
Deselected Cycle, Power Down None  
Deselected Cycle, Power Down None  
Deselected Cycle, Power Down None  
Deselected Cycle, Power Down None  
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L
X
L
L
L
H
H
L
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
WRITE Cycle, Begin Burst  
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
External  
L
X
X
L
External  
External  
External  
External  
Next  
L
L
L
H
X
L
High-Z  
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
High-Z  
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next  
L
H
L
High-Z  
Q
Next  
L
Next  
L
H
X
X
L
High-Z  
D
WRITE Cycle, Continue Burst Next  
WRITE Cycle, Continue Burst Next  
L
L
L
D
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
Current  
H
H
H
H
H
H
H
H
H
H
L
Q
Current  
Current  
Current  
H
L
High-Z  
Q
H
X
X
High-Z  
D
WRITE Cycle, Suspend Burst Current  
WRITE Cycle, Suspend Burst Current  
L
D
Notes:  
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.  
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.  
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.  
4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.  
5. All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.  
6. Suspending burst generates wait cycle.  
7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout  
the input data hold time.  
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.  
9. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for  
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.  
8
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Partial Truth Table for READ/WRITE[10]  
Function  
GW  
H
BWE  
BWa  
BWb  
BWc  
X
BWd  
X
READ  
READ  
H
L
L
L
X
X
H
L
X
H
H
L
H
H
H
WRITE one byte  
WRITE all bytes  
WRITE all bytes  
H
H
H
H
L
L
L
L
X
X
X
X
Note:  
10. For X18 product, There are only BWa and BWb.  
TDO - Test Data Out (OUTPUT)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TDO output pin is used to serially clock data-out from the  
registers. The output that is active depending on the state of  
the TAP state machine (refer to Figure 1, TAP Controller State  
Diagram). Output changes in response to the falling edge of  
TCK. This is the output side of the serial registers placed be-  
tween TDI and TDO. TDO is connected to the Least Significant  
Bit (LSB) of any register. (See Figure 2.)  
Overview  
This device incorporates a serial boundary scan access port  
(TAP). This port is designed to operate in a manner consistent  
with IEEE Standard 1149.1-1990 (commonly referred to as  
JTAG), but does not implement all of the functions required for  
IEEE 1149.1 compliance. Certain functions have been modi-  
fied or eliminated because their implementation places extra  
delays in the critical speed path of the device. Nevertheless,  
the device supports the standard TAP controller architecture  
(the TAP controller is the state machine that controls the TAPs  
operation) and can be expected to function in a manner that  
does not conflict with the operation of devices with IEEE Stan-  
dard 1149.1 compliant TAPs. The TAP operates using LVTTL/  
LVCMOS logic level signaling.  
Performing a TAP Reset  
The TAP circuitry does not have a reset pin (TRST, which is  
optional in the IEEE 1149.1 specification). A RESET can be  
performed for the TAP controller by forcing TMS HIGH (V  
)
CC  
for five rising edges of TCK and pre-loads the instruction reg-  
ister with the IDCODE command. This type of reset does not  
affect the operation of the system logic. The reset affects test  
logic only.  
Disabling the JTAG Feature  
At power-up, the TAP is reset internally to ensure that TDO is  
in a High-Z state.  
It is possible to use this device without using the JTAG feature.  
To disable the TAP controller without interfering with normal  
operation of the device, TCK should be tied LOW (V ) to pre-  
vent clocking the device. TDI and TMS are internally pulled up  
and may be unconnected. They may alternately be pulled up  
SS  
Test Access Port (TAP) Registers  
Overview  
to V  
through a resistor. TDO should be left unconnected.  
CC  
The various TAP registers are selected (one at a time) via the  
sequences of ones and zeros input to the TMS pin as the TCK  
is strobed. Each of the TAPs registers are serial shift registers  
that capture serial input data on the rising edge of TCK and  
push serial data out on subsequent falling edge of TCK. When  
a register is selected, it is connected between the TDI and  
TDO pins.  
Upon power-up the device will come up in a reset state which  
will not interfere with the operation of the device.  
Test Access Port (TAP)  
TCK - Test Clock (INPUT)  
Clocks all TAP events. All inputs are captured on the rising  
edge of TCK and all outputs propagate from the falling edge of  
TCK.  
Instruction Register  
The instruction register holds the instructions that are execut-  
ed by the TAP controller when it is moved into the run test/idle  
or the various data register states. The instructions are three  
bits long. The register can be loaded when it is placed between  
the TDI and TDO pins. The parallel outputs of the instruction  
register are automatically preloaded with the IDCODE instruc-  
tion upon power-up or whenever the controller is placed in the  
test-logic reset state. When the TAP controller is in the Cap-  
ture-IR state, the two least significant bits of the serial instruc-  
tion register are loaded with a binary “01” pattern to allow for  
fault isolation of the board-level serial test data path.  
TMS - Test Mode Select (INPUT)  
The TMS input is sampled on the rising edge of TCK. This is  
the command input for the TAP controller state machine. It is  
allowable to leave this pin unconnected if the TAP is not used.  
The pin is pulled up internally, resulting in a logic HIGH level.  
TDI - Test Data In (INPUT)  
The TDI input is sampled on the rising edge of TCK. This is the  
input side of the serial registers placed between TDI and TDO.  
The register placed between TDI and TDO is determined by  
the state of the TAP controller state machine and the instruc-  
tion that is currently loaded in the TAP instruction register (refer  
to Figure 1, TAP Controller State Diagram). It is allowable to  
leave this pin unconnected if it is not used in an application.  
The pin is pulled up internally, resulting in a logic HIGH level.  
TDI is connected to the Most Significant Bit (MSB) of any reg-  
ister. (See Figure 2.)  
Bypass Register  
The bypass register is a single-bit register that can be placed  
between TDI and TDO. It allows serial test data to be passed  
through the device TAP to another device in the scan chain  
with minimum delay. The bypass register is set LOW (V  
when the BYPASS instruction is executed.  
)
SS  
9
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Boundary Scan Register  
The TAP controller does recognize an all-0 instruction. When  
an EXTEST instruction is loaded into the instruction register,  
the device responds as if a SAMPLE/PRELOAD instruction  
has been loaded. There is one difference between two instruc-  
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places  
the device outputs in a High-Z state.  
The Boundary scan register is connected to all the input and  
bidirectional I/O pins (not counting the TAP pins) on the device.  
This also includes a number of NC pins that are reserved for  
future needs. There are a total of 70 bits for x36 device and 51  
bits for x18 device. The boundary scan register, under the con-  
trol of the TAP controller, is loaded with the contents of the  
device I/O ring when the controller is in Capture-DR state and  
then is placed between the TDI and TDO pins when the con-  
troller is moved to Shift-DR state. The EXTEST, SAM-  
PLE/PRELOAD and SAMPLE-Z instructions can be used to  
capture the contents of the I/O ring.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the ID register when the controller is in Cap-  
ture-DR mode and places the ID register between the TDI and  
TDO pins in Shift-DR mode. The IDCODE instruction is the  
default instruction loaded in the instruction upon power-up and  
at any time the TAP controller is placed in the test-logic reset  
state.  
The Boundary Scan Order table describes the order in which  
the bits are connected. The first column defines the bit’s posi-  
tion in the boundary scan register. The MSB of the register is  
connected to TDI, and LSB is connected to TDO. The second  
column is the signal name, the third column is the TQFP pin  
number, and the fourth column is the BGA bump number.  
SAMPLE-Z  
If the High-Z instruction is loaded in the instruction register, all  
output pins are forced to a High-Z state and the boundary scan  
register is connected between TDI and TDO pins when the  
TAP controller is in a Shift-DR state.  
Identification (ID) Register  
The ID Register is a 32-bit register that is loaded with a device  
and vendor specific 32-bit code when the controller is put in  
Capture-DR state with the IDCODE command loaded in the  
instruction register. The register is then placed between the  
TDI and TDO pins when the controller is moved into Shift-DR  
state. Bit 0 in the register is the LSB and the first to reach TDO  
when shifting begins. The code is loaded from a 32-bit on-chip  
ROM. It describes various attributes of the device as described  
in the Identification Register Definitions table.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.  
The PRELOAD portion of the command is not implemented in  
this device, so the device TAP controller is not fully IEEE  
1149.1-compliant.  
When the SAMPLE/PRELOAD instruction is loaded in the in-  
struction register and the TAP controller is in the Capture-DR  
state, a snap shot of the data in the device’s input and I/O  
buffers is loaded into the boundary scan register. Because the  
device system clock(s) are independent from the TAP clock  
(TCK), it is possible for the TAP to attempt to capture the input  
and I/O ring contents while the buffers are in transition (i.e., in  
a metastable state). Although allowing the TAP to sample  
metastable inputs will not harm the device, repeatable results  
can not be expected. To guarantee that the boundary scan  
register will capture the correct value of a signal, the device  
input signals must be stabilized long enough to meet the TAP  
TAP Controller Instruction Set  
Overview  
There are two classes of instructions defined in the IEEE Stan-  
dard 1149.1-1990; the standard (public) instructions and de-  
vice specific (private) instructions. Some public instructions  
are mandatory for IEEE 1149.1 compliance. Optional public  
instructions must be implemented in prescribed ways.  
Although the TAP controller in this device follows the IEEE  
1149.1 conventions, it is not IEEE 1149.1 compliant because  
some of the mandatory instructions are not fully implemented.  
The TAP on this device may be used to monitor all input and  
I/O pads, but can not be used to load address, data, or control  
signals into the device or to preload the I/O buffers. In other  
words, the device will not perform IEEE 1149.1 EXTEST, IN-  
TEST, or the preload portion of the SAMPLE/PRELOAD com-  
mand.  
controller’s capture setup plus hold time (t  
plus t ). The  
CS  
CH  
device clock input(s) need not be paused for any other TAP  
operation except capturing the input and I/O ring contents into  
the boundary scan register.  
Moving the controller to Shift-DR state then places the bound-  
ary scan register between the TDI and TDO pins. Because the  
PRELOAD portion of the command is not implemented in this  
device, moving the controller to the Update-DR state with the  
SAMPLE/PRELOAD instruction loaded in the instruction reg-  
ister has the same effect as the Pause-DR command.  
When the TAP controller is placed in Capture-IR state, the two  
least significant bits of the instruction register are loaded with  
01. When the controller is moved to the Shift-IR state the in-  
struction is serially loaded through the TDI input (while the  
previous contents are shifted out at TDO). For all instructions,  
the TAP executes newly loaded instructions only when the con-  
troller is moved to Update-IR state. The TAP instruction sets  
for this device are listed in the following tables.  
BYPASS  
When the BYPASS instruction is loaded in the instruction reg-  
ister and the TAP controller is in the Shift-DR state, the bypass  
register is placed between TDI and TDO. This allows the board  
level scan path to be shortened to facilitate testing of other  
devices in the scan path.  
EXTEST  
Reserved  
EXTEST is an IEEE 1149.1 mandatory public instruction. It is  
to be executed whenever the instruction register is loaded with  
all 0s. EXTEST is not implemented in this device.  
Do not use these instructions. They are reserved for future  
use.  
10  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
TEST-LOGIC  
RESET  
1
0
0
1
1
1
REUN-TEST/  
IDLE  
SELECT  
SELECT  
DR-SCAN  
IR-SCAN  
0
CAPTURE-DR  
0
1
1
CAPTURE-IR  
0
0
SHIFT-DR  
0
1
SHIFT-IR  
0
1
1
EXIT1-DR  
0
1
EXIT1-IR  
0
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
1
0
0
[11]  
Figure 1. TAP Controller State Diagram  
Note:  
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
11  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
0
Bypass Register  
Selection  
Circuitry  
Selection  
Circuitry  
2
1
0
TDO  
TDI  
Instruction Register  
29  
Identification Register  
31 30  
.
.
2
1
1
0
0
.
x
.
.
.
2
[12]  
Boundary Scan Register  
TDI  
TDI  
TAP Controller  
Figure 2. TAP Controller Block Diagram  
TAP Electrical Characteristics (20°C < T < 110°C; V = 3.3V –0.2V and +0.3V unless otherwise noted)  
j
CC  
Parameter  
Description  
Test Conditions  
Min.  
2.0  
Max.  
+ 0.3  
CC  
Unit  
[13, 14]  
V
V
Input High (Logic 1) Voltage  
V
V
IH  
Il  
[13, 14]  
Input Low (Logic 0) Voltage  
Input Leakage Current  
–0.3  
–5.0  
–30  
0.8  
5.0  
30  
V
IL  
0V < V < VCC  
µA  
µA  
µA  
I
IN  
IL  
TMS and TDI Input Leakage Current 0V < V < VCC  
IN  
I
IL  
Output Leakage Current  
Output disabled,  
0V < V < V  
–5.0  
5.0  
O
IN  
CCQ  
[13, 15]  
[13, 15]  
V
LVCMOS Output Low Voltage  
I
I
I
I
= 100 µA  
0.2  
0.4  
V
V
V
V
OLC  
OLC  
OHC  
OLT  
V
LVCMOS Output High Voltage  
= 100 µA  
= 8.0 mA  
= 8.0 mA  
V
– 0.2  
CC  
OHC  
[13]  
V
LVTTL Output Low Voltage  
OLT  
[13]  
V
LVTTL Output High Voltage  
2.4  
OHT  
OHT  
Notes:  
12. X = 69 for the x36 configuration;  
X = 50 for the x18 configuration.  
13. All Voltage referenced to VSS (GND).  
14. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.  
During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).  
15. This parameter is sampled.  
12  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
[16, 17]  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Clock  
Description  
Min.  
Max  
Unit  
t
f
t
t
Clock Cycle Time  
Clock Frequency  
Clock HIGH Time  
Clock LOW Time  
20  
ns  
MHz  
ns  
THTH  
TF  
50  
8
8
THTL  
TLTH  
ns  
Output Times  
t
t
t
t
TCK LOW to TDO Unknown  
TCK LOW to TDO Valid  
TDI Valid to TCK HIGH  
TCK HIGH to TDI Invalid  
0
ns  
ns  
ns  
ns  
TLQX  
TLQV  
DVTH  
THDX  
10  
5
5
Set-up Times  
t
TMS Set-up  
5
5
ns  
ns  
MVTH  
t
Capture Set-up  
CS  
Hold Times  
t
t
TMS Hold  
5
5
ns  
ns  
THMX  
Capture Hold  
CH  
Notes:  
16. CS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.  
17. Test conditions are specified using the load in TAP AC test conditions.  
t
13  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
TAP Timing and Test Conditions  
ALL INPUT PULSES  
3.0V  
1.5V  
TDO  
Z0 = 50  
Ω
50Ω  
20 pF  
VSS  
Vt = 1.5V  
1.5 ns  
1.5 ns  
(b)  
(a)  
14  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Identification Register Definitions  
Instruction Field  
256K x 36  
512K x 18  
Description  
REVISION NUMBER  
(31:28)  
XXXX  
XXXX  
Reserved for revision number.  
DEVICE DEPTH  
(27:23)  
00110  
00100  
00111  
00011  
Defines depth of 256K or 512K words.  
Defines width of x36 or x18 bits.  
DEVICE WIDTH  
(22:18)  
RESERVED  
(17:12)  
XXXXXX  
00011100100  
1
XXXXXX  
00011100100  
1
Reserved for future use.  
CYPRESS JEDEC ID  
CODE (11:1)  
Allows unique identification of DEVICE vendor.  
Indicates the presence of an ID register.  
ID Register Presence  
Indicator (0)  
Scan Register Sizes  
Register Name  
Instruction  
Bypass  
Bit Size (x36)  
Bit Size (x18)  
3
1
3
1
ID  
32  
70  
32  
51  
Boundary Scan  
Instruction Codes  
Instruction  
Code  
Description  
EXTEST  
000  
Captures I/O ring contents. Places the boundary scan register between TDI  
and TDO. Forces all device outputs to High-Z state. This instruction is not  
IEEE 1149.1-compliant.  
IDCODE  
001  
010  
Preloads ID register with vendor ID code and places it between TDI and  
TDO. This instruction does not affect device operations.  
SAMPLE-Z  
Captures I/O ring contents. Places the boundary scan register between TDI  
and TDO. Forces all device outputs to High-Z state.  
RESERVED  
011  
100  
Do not use these instructions; they are reserved for future use.  
SAMPLE/PRELOAD  
Captures I/O ring contents. Places the boundary scan register between TDI  
and TDO. This instruction does not affect device operations. This instruction  
does not implement IEEE 1149.1 PRELOAD function and is therefore not  
1149.1-compliant.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do not use these instructions; they are reserved for future use.  
Do not use these instructions; they are reserved for future use.  
Places the bypass register between TDI and TDO. This instruction does not  
affect device operations.  
15  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Boundary Scan Order (256K x 36)  
Boundary Scan Order (256K x 36)  
Signal  
Name  
Signal  
Name  
Bit#  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
TQFP  
92  
93  
94  
95  
96  
97  
98  
99  
100  
1
Bump ID  
6B  
5L  
Bit#  
1
TQFP  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
56  
57  
58  
59  
62  
63  
64  
68  
69  
72  
73  
74  
75  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
Bump ID  
2R  
3T  
A
A
A
BWa  
BWb  
BWc  
BWd  
2
5G  
3G  
3L  
3
A
4T  
4
A
5T  
5
A
6R  
3B  
5B  
6P  
7N  
6M  
7L  
CE  
2
2B  
4E  
3A  
2A  
2D  
1E  
2F  
6
A
CE  
A
7
A
8
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
ZZ  
A
9
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
DQc  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
2
3
6K  
7P  
6N  
6L  
6
1G  
2H  
1D  
2E  
2G  
1H  
5R  
2K  
1L  
7
8
9
7K  
7T  
12  
13  
14  
18  
19  
22  
23  
24  
25  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
A
6H  
7G  
6F  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
MODE  
A
7E  
6D  
7H  
6G  
6E  
7D  
6A  
5A  
4G  
4A  
4B  
4F  
2M  
1N  
2P  
1K  
2L  
2N  
1P  
3R  
2C  
3C  
5C  
6C  
4N  
4P  
A
ADV  
ADSP  
ADSC  
OE  
A
A
A
BWE  
GW  
CLK  
4M  
4H  
4K  
A1  
A0  
16  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Boundary Scan Order (512K x 18)  
Boundary Scan Order (512K x 18)  
Signal  
Name  
Signal  
Name  
Bit#  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
TQFP  
89  
92  
93  
94  
97  
98  
99  
100  
8
Bump ID  
4K  
Bit#  
1
TQFP  
44  
45  
46  
47  
48  
49  
50  
58  
59  
62  
63  
64  
68  
69  
72  
73  
74  
80  
81  
82  
83  
84  
85  
86  
87  
88  
Bump ID  
2R  
2T  
CLK  
A
A
A
6B  
2
BWa  
BWb  
5L  
3
A
3T  
3G  
2B  
4
A
5T  
CE  
5
A
6R  
3B  
5B  
7P  
6N  
6L  
2
CE  
A
4E  
6
A
3A  
7
A
A
2A  
8
DQa  
DQa  
DQa  
DQa  
ZZ  
DQb  
DQb  
DQb  
DQb  
NC  
DQb  
DQb  
DQb  
DQb  
DQb  
MODE  
A
1D  
2E  
9
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
12  
13  
14  
18  
19  
22  
23  
24  
31  
32  
33  
34  
35  
36  
37  
2G  
1H  
5R  
2K  
7K  
7T  
DQa  
DQa  
DQa  
DQa  
DQa  
A
6H  
7G  
6F  
1L  
2M  
1N  
2P  
7E  
6D  
6T  
3R  
2C  
3C  
5C  
6C  
4N  
4P  
A
6A  
5A  
4G  
4A  
4B  
4F  
A
A
ADV  
ADSP  
ADSC  
OE  
BWE  
GW  
A
A
A1  
A0  
4M  
4H  
17  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Power Dissipation ......................................................... 1.0W  
Short Circuit Output Current........................................ 50 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Voltage on V Supply Relative to V ......... –0.5V to +4.6V  
CC  
SS  
Ambient  
V
...........................................................–0.5V to V +0.5V  
CC  
IN  
[18]  
Range  
Temperature  
V
CC  
Storage Temperature (plastic) .......................–55°C to +150°  
Junction Temperature ...................................................+150°  
Com’l  
0°C to +70°C  
3.3V –5%/+10%  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Test Conditions  
Data Inputs (DQx)  
All Other Inputs  
Min.  
2.0  
2.0  
–0.5  
–5  
Max.  
Unit  
V
[13, 19]  
V
Input High (Logic 1) Voltage  
V
+0.3  
CC  
IHD  
IH  
Il  
V
V
4.6  
V
[13, 19]  
Input Low (Logic 0) Voltage  
Input Leakage Current  
0.8  
5
V
IL  
0V < V < V  
µA  
µA  
µA  
I
IN  
CC  
CC  
[20]  
IL  
MODE and ZZ Input Leakage Current  
Output Leakage Current  
0V < V < V  
–30  
–5  
30  
5
I
IN  
IL  
Output(s) disabled,  
0V < V < V  
O
OUT  
CC  
[13]  
V
Output High Voltage  
I
I
= –5.0 mA  
2.4  
V
V
V
V
V
OH  
OH  
OL  
[13]  
V
Output Low Voltage  
= 8.0 mA  
0.4  
3.6  
OL  
[13]  
V
Supply Voltage  
3.135  
3.135  
2.375  
CC  
[13]  
V
V
I/O Supply Voltage (3.3V)  
V
CCQ  
CCQ  
CC  
CC  
[13]  
I/O Supply Voltage (2.5V)  
V
-4.4  
225  
-5  
-6  
166  
-6.7  
150  
200  
Parameter  
Description  
Conditions  
Typ.  
MHz MHz MHz MHz  
Unit  
I
I
I
I
Power Supply Current: Device selected; all inputs < V or >  
150  
570  
510  
10  
425  
380  
mA  
CC  
IL  
[21, 22, 23]  
Operating  
V ; cycle time > t min.; V = Max.;  
outputs open  
IH  
KC  
CC  
[22, 23]  
CMOS Standby  
Device deselected; V = Max.;  
5
10  
10  
10  
mA  
mA  
mA  
SB2  
SB3  
SB4  
CC  
all inputs < V + 0.2 or > V – 0.2;  
SS  
CC  
all inputs static; CLK frequency = 0  
[22, 23]  
TTL Standby  
Device deselected; all inputs < V  
15  
40  
30  
30  
30  
30  
IL  
or > V ; all inputs static;  
IH  
V
= MAX; CLK frequency = 0  
CC  
[22, 23]  
Clock Running  
Device deselected;  
all inputs < V or > V ; V = Max.;  
125  
110  
90  
80  
IL  
IH  
CC  
CLK cycle time > t Min.  
KC  
Capacitance[15]  
Parameter  
Description  
Test Conditions  
Typ.  
Max.  
Unit  
C
C
Input Capacitance  
T = 25°C, f = 1 MHz,  
5
7
7
8
pF  
pF  
I
A
V
= 3.3V  
CC  
Input/Output Capacitance (DQ)  
O
Notes:  
18. A is the case temperature.  
T
19. Overshoot: VIH < +6.0V for t < tKC /2  
Undershoot:VIL < –2.0V for t < tKC /2.  
20. Output loading is specified with CL=5 pF as in AC Test Loads.  
21.  
ICC is given with no output current. ICC increases with greater output loading and faster cycle times.  
22. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.  
23. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.  
18  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Thermal Resistance  
Description  
Test Conditions  
Symbol  
TQFP Typ.  
Units  
°C/W  
°C/W  
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,  
Θ
Θ
25  
9
JA  
JC  
4-layer PCB  
Thermal Resistance (Junction to Case)  
AC Test Loads and Waveforms for 3.3V I/O  
317  
Ω
3.3V  
DQ  
DQ  
ALL INPUT PULSES  
90%  
3.0V  
0V  
90%  
10%  
Z =50  
Ω
0
10%  
1.0 ns  
50  
Ω
5 pF  
351  
Ω
1.0 ns  
≤
≤
V = 1.5V  
t
(c)  
(a)  
(b)  
AC Test Loads and Waveforms for 2.5V I/O  
DQ  
ALL INPUT PULSES  
90%  
2.5V  
0V  
90%  
Z =50  
Ω
0
50  
10%  
1.0 ns  
Ω
10%  
1.0 ns  
≤
≤
V = 1.25V  
t
(c)  
(a)  
19  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
[24]  
Switching Characteristics Over the Operating Range  
-4.4  
225 MHz  
-5  
-6  
-6.7  
150 MHz  
200 MHz  
166 MHz  
Parameter  
Clock  
Description  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
t
t
t
Clock Cycle Time  
4.4  
2.0  
2.0  
5.0  
2.1  
2.1  
6.0  
2.4  
2.4  
6.7  
2.6  
2.6  
ns  
ns  
ns  
KC  
KH  
KL  
Clock HIGH Time  
Clock LOW Time  
Output Times  
t
Clock to Output Valid  
V
V
= 3.3V  
= 2.5V  
2.5  
3.0  
3.0  
3.5  
3.5  
4.0  
3.5  
4.5  
ns  
KQ  
CCQ  
CCQ  
t
t
t
t
Clock to Output Invalid  
Clock to Output in Low-Z  
Clock to Output in High-Z  
1.25  
0
1.25  
0
1.25  
0
1.25  
0
ns  
ns  
ns  
ns  
KQX  
[15, 25, 26]  
[15, 25, 26]  
KQLZ  
KQHZ  
OEQ  
1.25  
3.0  
2.5  
3.0  
1.25  
3.0  
3.0  
3.5  
1.25  
4.0  
3.5  
4.0  
1.25  
4.0  
3.5  
4.5  
[27]  
OE to Output Valid  
V
V
= 3.3V  
= 2.5V  
CCQ  
CCQ  
[15, 25, 26]  
t
t
OE to Output in Low-Z  
OE to Output in High-Z  
0
0
0
0
ns  
ns  
OELZ  
[15, 25, 26]  
2.5  
2.5  
3.5  
3.5  
OEHZ  
Set-up Times  
[28]  
t
Address, Controls, and Data In  
1.0  
1.0  
1.0  
1.0  
1.3  
1.0  
1.5  
1.0  
ns  
ns  
S
Hold Times  
[28]  
t
Address, Controls, and Data In  
H
Typical Output Buffer Characteristics  
Output High Voltage  
(V)  
Pull-Up Current  
Output Low Voltage  
(V)  
Pull-Down Current  
V
I
(mA) Min.  
I
(mA) Max.  
V
I
(mA) Min.  
I (mA) Max.  
OL  
OH  
OH  
OH  
OL  
OL  
–0.5  
0
–38  
–38  
–38  
–26  
–20  
0
–105  
–105  
–105  
–83  
–70  
–30  
–10  
0
–0.5  
0
0
0
0
0
0.8  
1.25  
1.5  
2.3  
2.7  
2.9  
3.4  
0.4  
0.8  
1.25  
1.6  
2.8  
3.2  
3.4  
10  
20  
31  
40  
40  
40  
40  
20  
40  
63  
80  
80  
80  
80  
0
0
0
0
Notes:  
24. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.  
25. Output loading is specified with CL=5 pF as in part (a) of AC Test Loads.  
26. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ  
.
27. OE is a “don’t care” when a byte write enable is sampled LOW.  
28. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “don’t care” as defined in the truth table.  
20  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Switching Waveforms  
[29, 30]  
Read Timing  
tKC  
tKL  
CLK  
tKH  
tS  
ADSP#  
tH  
ADSC#  
tS  
ADDRESS  
A1  
A2  
tH  
BWa#, BWb#,  
BWc#, BWd#  
BWE#, GW#  
tS  
CE#  
ADV#  
OE#  
DQ  
tS  
tH  
tKQ  
tKQ  
tOEQ  
tOELZ  
tKQLZ  
Q(A1)  
Q(A2)  
Q(A2+1)  
Q(A2+2)  
Q(A2+3)  
Q(A2)  
Q(A2+1)  
SINGLE READ  
BURST READ  
Notes:  
29. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.  
30. For X18 product, there are only BWa and BWb for byte write control.  
21  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Switching Waveforms (continued)  
[29, 30]  
Write Timing  
CLK  
tS  
ADSP#  
tH  
ADSC#  
tS  
A1  
A2  
A3  
ADDRESS  
tH  
BWa#, BWb#,  
BWc#, BWd#,  
BWE#  
GW#  
CE#  
tS  
ADV#  
OE#  
DQ  
tH  
tOEHZ  
tKQX  
Q
D(A1)  
D(A2)  
D(A2+1)  
D(A2+1)  
D(A2+2)  
D(A2+3)  
D(A3)  
D(A3+1)  
D(A3+2)  
SINGLE WRITE  
BURST WRITE  
BURST WRITE  
22  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Switching Waveforms (continued)  
[29, 30]  
Read/Write Timing  
CLK  
tS  
ADSP#  
tH  
ADSC#  
tS  
ADDRESS  
A2  
A3  
A4  
A5  
A1  
tH  
BWa#, BWb#,  
BWc#, BWd#,  
BWE#, GW#  
CE#  
ADV#  
OE#  
DQ  
Q(A1)  
Single Reads  
Q(A2)  
D(A3)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
D(A5)  
D(A5+1)  
Single Write  
Burst Read  
Burst Write  
23  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Ordering Information  
Speed  
(MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
225  
CY7C1360A1-225AJC/  
GVT71256DA36T-4.4  
A101  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
Commercial  
CY7C1360A1-225AC/  
GVT71256DA36TA-4.4  
A101  
CY7C1360A1-225BGC/  
GVT71256DA36B-4.4  
BG119  
A101  
200  
166  
150  
CY7C1360A1-200AJC/  
GVT71256DA36T-5  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
CY7C1360A1-200AC/  
GVT71256DA36TA-5  
A101  
CY7C1360A1-200BGC/  
GVT71256DA36B-5  
BG119  
A101  
CY7C1360A1-166AJC/  
GVT71256DA36T-6  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
CY7C1360A1-166AC/  
GVT71256DA36TA-6  
A101  
CY7C1360A1-166BGC/  
GVT71256DA36B-6  
BG119  
A101  
CY7C1360A1-150AJC/  
GVT71256DA36T-6.7  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
CY7C1360A1-150AC/  
GVT71256DA36TA-6.7  
A101  
CY7C1360A1-150BGC/  
GVT71256DA36B-6.7  
BG119  
24  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Ordering Information (continued)  
Speed  
(MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
225  
CY7C1362A1-225AJC/  
GVT71512DA18T-4.4  
A101  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
Commercial  
CY7C1362A1-225AC/  
GVT71512DA18TA-4.4  
A101  
CY7C1362A1-225BGC/  
GVT71512DA18B-4.4  
BG119  
A101  
200  
166  
150  
CY7C1362A1-200AJC/  
GVT71512DA18T-5  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
CY7C1362A1-200AC/  
GVT71512DA18TA-5  
A101  
CY7C1362A1-200BGC/  
GVT715152DA18B-5  
BG119  
A101  
CY7C1362A1-166AJC/  
GVT715152DA18T-6  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
CY7C1362A1-166AC/  
GVT71512DA18TA-6  
A101  
CY7C1362A1-166BGC/  
GVT71512DA18B-6  
BG119  
A101  
CY7C1362A1-150AJC/  
GVT71512DA18T-6.7  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack  
119-Lead BGA (14 x 22 x 2.4 mm)  
CY7C1362A1-150AC/  
GVT71512DA18TA-6.7  
A101  
CY7C1362A1-150BGC/  
GVT71512DA18B-6.7  
BG119  
Document #: 38-01002-**  
25  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Package Diagrams  
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101  
26  
CY7C1360A1/GVT71256DA36  
CY7C1362A1/GVT71512DA18  
PRELIMINARY  
Package Diagrams (continued)  
119-Lead bga (14 x 22 x 2.4 mm) BG119  
51-85115  
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  

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