IMI145158GXB [CYPRESS]
PLL Frequency Synthesizer, PDSO16, 0.300 INCH, SOIC-16;
| 型号： | IMI145158GXB |
| 厂家： | 
CYPRESS |
| 描述： | PLL Frequency Synthesizer, PDSO16, 0.300 INCH, SOIC-16 光电二极管 |
| 文件： | 总10页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
Product Description
Product Features
The IMI145158 is a member of a family of phaselock
loop synthesizer ICs from International Microcircuits.
This part is a single PLL in a small package for low cost
VHF applications. The IMI145158 is programmed with
standard 3-wire serial lines: data, clock, and enable.
>145 MHz typical input frequency.
-160 dBc/Hz total phase detector noise floor.
No dead zone by design.
Two phase detector outputs:
Blocks in the IMI145158 include a dual modulus
feedback divider for control of an external dual modulus
•
•
Current mode charge pump
Differential logic
prescaler. Prescaler ratios up to 128:129.
Also
included are an “N” counter, reference divider, phase
detector, and charge pump. The reference divider is
programmable from 1 to 16383. Both divider inputs are
biased for high sensitivity to sinewave input signals, and
the reference divider input can be configured to operate
as a crystal oscillator if desired. A buffered reference
signal output is also provided. The phase detector is a
Type IV phase-frequency design, which has inherently
eliminated the “dead zone” crossover distortion. The
loop error signal is provided by both a single-ended
charge pump output and standard differential logic
outputs.
Unambiguous PLL acquisition.
3-line serial programming: data, clock, & enable.
Compatible with the SPI (Serial Peripheral
Interface) on CMOS MCUs.
10-bit N counter: Divider range = 1 to 1023.
7-bit A counter: Divider range = 0 to 127.
14-bit R counter: Divider range = 1 to 16383.
On- or off-chip reference oscillator operation.
Buffered & filtered ref output is provided.
16 Pin SOIC package
Performance improvements of the IMI145158 over
other single loop CMOS PLL devices are in the
operating bandwidth and phase detector noise floor.
With its extremely low phase noise floor and wider input
bandwidth, prescaler ratios can be minimized to allow
wide loop bandwidths for faster settling and lower phase
noise.
Block Diagram
VDD = PIN 4
VSS = PIN 6
14 Bit Shift Register
3
2
14 Bit Latch
14 Bit /R Counter
Control Logic
7
Lock
Detect
LD
1
1
13
OSCin
Fr
2
OSCout
Phase
Detector
A
14
5
REFout
PDout
8
Fin
11
7 Bit /A Counter
7 Bit Latch
10 Bit /N Counter
Enable
16
Phase
Detector
B
Phir
10
9
1
2
1-Bit
Contro
l S/R
Data
10 Bit Latch
15
1
2
3
Clock
Phiv
3
Fv
12
7 Bit Shift Register
10 Bit Shift Register
Mod
Cntrl
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 2.1
5/29/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Page 1 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
Voltage Relative to VSS:
Voltage Relative to VDD
Storage Temperature:
Ambient Temperature:
-0.3V to 7V
0.3V
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
-65ºC to 150ºC
-40ºC to 85ºC
VSS<(Vin or Vout)< VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Pin Description
Pin Number
Name
Xin
Description
1
2
Xtal in (or reference signal input) to the reference oscillator / buffer.
Xtal out (or Reference signal output) of the reference oscillator / buffer.
Buffered reference signal.
Xout
14
10
REFout
DATA
Positive logic shift register input data. The first 14 bits are the reference or
feedback divider programming information, sent MSB first. The final programming
bit (control bit) selects which divider this programming information will be loaded
into:
1 = the reference divider, and 0 = the feedback divider.
A and N Entry Format (Control Bit = 0)
÷
÷
A Counter Bits
N Counter Bits
÷
÷
Last Data Bit In (Bit No. 18)
First Data Bit in (Bit No. 1)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 2.1
5/29/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Page 2 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
Pin Description (Cont.)
Pin Number
Name
Description
R Counter Bits
÷
Last Data Bit In (Bit No. 15)
First Data Bit in (Bit No. 1)
9
11
12
8
CLOCK
ENABLE
Mod Cntrl
fin
On each low-to-high transition, clocks one bit into the on-chip shift register from
the data input.
This signal, when HIGH, latches the information in the shift register into the
selected divider.
This output generates a signal by the on-chip control logic circuitry for controlling
an external dual-modulus prescaler.
Feedback divider input signal. Applied to the positive edge triggered counter, this
signal is intended to be AC coupled. For CMOS logic level input signals, DC
coupling can be used.
4
6
5
VDD
VSS
Circuit positive power supply.
Circuit ground.
PDout
Single-ended charge pump output, usually used with passive loop filters. This
signal operated according to this table:
■ Frequency fv > fr at the phase detector: negative pulses.
■ Frequency fv < fr at the phase detector: positive pulses.
■ Frequency fv = fr at the phase detector: high-impedance state.
Phase detector output. This signal goes LOW when the feedback frequency is
too low.
16
15
7
φR
φV
LD
Phase detector output. This signal goes LOW when the feedback frequency is
too high.
Lock detect output. When the PLL is locked, this signal will be essentially HIGH,
with very narrow negative spikes at the phase detection frequency. If the PLL is
out of lock, this signal will pulse LOW.
3
fv
fr
Output of the feedback divider N.
13
Output of the reference divider R.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Rev 2.1
5/29/2000
Page 3 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
PLL Operating Characteristics
VDD = 5 VOLTS
-40ºC
Min Max Min
25ºC
85ºC
Max
Characteristics
Symbol
Sine*
Typ
170
Max Min
110
Unit
Conditions
Max Operating
Frequency
fin,
160
75
-
typ
225
120
85
-
typ
155
MHz
+ 4 dBm
1.0V p-p
fosc
Sine*
typ
105
120
55
typ 80 MHz
+4 of Bm
1.0 V p-p
Modulus Control Prop. Delay
MCpd
PDNF
10
7.5
10.5
-
12
ns
Dynamic
-160
Synthesizer Phase Noise
Floor
dBc/Hz
@100kHz
Pin
Cin
Cout
Kd
-
-
-
-
6
8
-
4
6
8
-
6
8
pF
Capacitance
Phase Det 1 gain
Phase Det 2 gain
Input
-
6
-
pF
-
0.65
0.8
-
ma/Rad
v / Rad
Vdc
Kd
-
-
VIL
VIH
Vil
1.5
-
1.5
-
1.5
Pins 1, 8 and
10
Voltages
Input
3.5
-
-
-
3.5
-
-
3.5
0.6
4.2
-
-
0.6
-
0.6
0.6
Vdc
Vdc
Pins 9 and 11
Voltage
VIH
VOL
VOH
IOL
4.2
-
-
4.2`
-
-
-
-
Output
0.05
0.0
0.05
0.05
Iout = 0
Static
Voltages
Output
4.95
2.4
1.2
-2.4
-1.2
-
-
-
-
-
4.95 5.0
-
-
-
-
-
4.95
1.6
0.8
-1.6
-0.8
-
-
-
-
-
Logic
2.0
2.8
1.4
-2.8
-1.4
4.0
OSCout
VOL = 0.40
VOH = 4.0
Current
1.0
mA
mA
mA
mA
mA
IOH
Logic
-2.0
-1.0
OSCout
VOH = 4.4
for 2Pi Radians
Icp
CPcur
R=128, N=128,
A=32
Supply
IDD
7.0
7.0
7.0
Currents
fosc=fin=0
VIL = 0
ISB
IPU
-
150
-
40
50
150
-
150
µA
µA
* Sine wave input is not recomended below 10 MHz.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Rev 2.1
5/29/2000
Page 4 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
PLL Operating Characteristics
VDD = 3 VOLTS
-40ºC
Min Max
25ºC
85ºC
Max
Characteristics
Symbol
Sine*
Min
80
Typ
115
Max Min
70
Unit
Conditions
Max Operating
Frequency
fin,
100
60
-
MHz
+4 dBm
1.0V p-p
fosc
Sine*
65
-
95
50
MHz
+4 dBm
1.0V p-p
Modulus Control Prop. Delay MCpd
12
11
15
-
17
ns
Synthesizer Phase Noise
Floor
PDNF
-160
dBc/Hz
Dynamic
Pin
Cin
Cout
Kd
-
-
-
10
10
-
-
-
6
10
10
-
-
-
10
10
pF
Capacitance
6
pF
Phase Det 1 gain
Phase Det 2 gain
0.35
ma/Rad
Kd
-
-
0.48
-
v / Rad
Vdc
Input
VIL
-
0.9
-
-
0.9
-
0.9
Pins 1, 8
and 10
Voltages
VIH
VIL
2.1
-
-
2.1
-
1.65
-
-
2.1
-
-
Input
0.4
0.4
0.4
Vdc
Vdc
Pins 9 and
11
Voltages
VIH
VOL
VOH
IOL
2.5
-
-
2.5
-
-
-
2.5
-
-
Output
0.05
0.0
3.0
2.0
1.0
-2.0
-1.0
2.2
0.05
0.05
Iout = 0
Static
Voltages
2.95
1.6
0.8
-1.6
-0.8
-
-
-
-
-
2.95
1.4
0.7
-1.4
-0.7
-
-
-
-
-
2.95
0.8
0.4
-0.8
-0.4
-
-
-
-
-
Output
Logic
OSCout
VOL = 0.30
VOH = 2.4
VOH = 2.4
Current
mA
mA
mA
mA
IOH
Logic
OSCout
for 2Pi
Radian
Icp
CP cur
R=128,
N=128,
IDD
3.0
3.0
3.0
mA
Supply
Currents
A =32
fosc=fin=0
ISB
-
150
-
40
150
-
150
µA
* Sine wave input is not recommended below 10 MHz.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 2.1
5/29/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Page 5 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
IMI145158 Typical RF Sensitivity Vdd = 5V
IMI145158 Typical Reference Sensitivity Vdd = 3V
0
-5
5
0
-5
-10
-15
-10
-40 5V
-40 3V
25° 5V
25° 3V
85° 3V
-15
dBm
dBm
85° 5V
-20
-25
-30
-35
-20
-25
-30
-35
0
20
40
60
80
100
120
0
50
100
150
200
250
Frequency MHz
Frequency MHz
IMI145158 Typical RF Sensivity Vdd = 3V
IMI145158 Typical Current Vs
0
-5
25.00
20.00
15.00
5V Min Sig
5V Max Sig
3V Min Sig
3V Max Sig
-10
-15
-20
-25
-30
-35
-40
-45
-40 3V
25° 3V
85° 3V
10.00
Current in Ma.
5.00
0.00
10
0
20
40
60
80
100
120
140
30
50
70
90
110
130
150
170
190
Frequency in MHz.
Frequency MHz
145158 Typical Reference Sensitivity Vdd = 5V
15
10
5
0
-5
-10
-40 5V
25° 5V
85° 5V
-15
dBm
-20
-25
-30
-35
-40
0
20
40
60
80
100
120
140
160
180
200
Frequency MHz
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 2.1
5/29/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Page 6 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
Dual Modulus Prescaling
Two particular things should be noticed about this
process. First, the remainder counts are spread
among an equal number of quotient counts by the use
of the prescaler modulus P +1. When the remainder
has been counted, any remaining quotient counts are
handled normally by prescaling by modulus P. This
counter is thus performing
Dual Modulus prescaling is a wide spread method
used to effectively extend the operating frequency of
a digital counter without sacrificing any frequency
resolution. The key to understanding this method is
to remember the basics of division: When any two
integers are divided, a quotient and a remainder will
result.
Ntot = A(P+1) + (N-A)P
Some algebra on this relation yields
When used here in a PLL, the numerator is the
required PLL total feedback divider ratio, called Ntot.
The denominator is the base modulus of the dual
modulus prescaler, P. The quotient is applied directly
to the N counter, and the remainder is applied directly
to the A counter. Both counters count down together
toward zero. While the A counter counts, the MC
(modulus control) output signal is LOW, setting the
prescaler to divide by P + 1. When the A counter
reaches zero, the MC output is set HIGH while the N
counter continues to count down to zero. When the N
counter reaches zero, both counters are reset to the
programmed inputs and the cycle is repeated.
Ntot = AP+A + NP-AP
= NP + A
which is just the definition of integer division. Second,
for this to work, there must be more quotient counts
than remainder counts for all possible values of Ntot in
the synthesizer design. If this were not true, then the N
counter will reach zero and cause the entire divider to
be reset before the A counter is finished. There is a
minimum value for Ntot for which this requirement will
always hold:
Ntot > P2 - P.
Programming Guidelines
The system total divide value (Ntotal) will be dictated by
the application:
For the maximum frequency into the prescaler (FVCO
max), the value used for P must be large enough so
that:
frequency into the prescaler
Ntotal
=
= N*P+A
frequency into the phase detector
A. FVCO max divided by P may not exceed the
frequency capability of Pin 8 of the IMI145158.
B. The period of FVCO divided by P must be greater
than the sum of the times:
N is the number programmed into the ÷ N counter; A is
the number programmed into ÷ A counter. P and P +
1 are two selectable divide ratios available in the two
modulus prescalers. To have a range of Ntotal values
in sequence, the ÷ A counter is programmed from zero
through P-1 for a particular value N in the ÷ N counter.
N is then incremented to N + 1k, and the ÷ A is
sequenced from zero through P - 1 again.
a. Propagation delay through the dual modulus
prescaler.
b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus
control signal.
To maximize system frequency capability, the dual
modulus prescaler’s output must go from low to high
after each group of P or P + 1 input cycles. The
prescaler should divide by P when its modulus control
line is high, and by P + 1 when its modulus control is
low.
A useful simplification in the IMI145158 programming
code can be achieved by choosing the values for P or
8, 16, 32, or 64, or 128. For these cases, the desired
value for Ntotal in binary is used as the program code to
the ÷ A counters in the following manner:
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Rev 2.1
5/29/2000
Page 7 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
Programming Guidelines (Cont.)
A. Assume the ÷ N counter and ÷ A counter contains
“b” bits where 2b = P.
into a single binary counter of 10+b bits in length.
The MSB of this hypothetical counter is to
correspond o the LSB of ÷ A. The system divide
value, Ntotal, now results when the value of Ntotal in
binary is used to program the “new” 10+b bit
counter.
B. Always program all higher order ÷ A counter bits
above “b” to zero.
C. Assume the ÷ N counter and ÷ A counter (with all
the higher order bits above “b” ignored) combined
Connection Diagram:
SOIC Package
Xin
Xout
Fv
1
2
3
4
5
6
7
8
φ R
16
15
14
13
12
11
10
9
φ V
REFout
Fr
VDD
PDout
VSS
LD
Mod Cntrl
ENABLE
DATA
CLOCK
fin
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Rev 2.1
5/29/2000
Page 8 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
Typical Application Circuit
IMI145158
LD
PD
UHF
VCO
fout
DATA
CLOCK
ENABLE
D
C
E
Mod Cntrl
Fin
1000pF
1000pF
P/P+1
VDD VSS
1000pF
1000pF
2K
10
VDD
10 uF
DUAL MODULUS PRESCALER
3V
700
1400
2800
5600
5V
Maximum
Values
for f VCO
(MHz)
8/9
1100
2200
4400
8800
16/17
32/33
64/65
Package Drawing and Dimensions
16 Pin SOIC Outline Dimensions (300 mil)
C
INCHES
MILLIMETERS
L
SYMBOL
MIN
NOM
MAX
MIN
2.35
0.10
2.25
0.33
0.23
10.10
7.40
NOM
MAX
H
E
A
A1
A2
B
0.093
0.004
0.089
0.013
0.009
0.398
0.291
-
-
0.104
0.012
0.093
0.020
0.013
0.413
0.299
-
-
2.65
0.30
2.35
0.51
0.32
10.50
7.60
-
-
D
a
C
D
E
-
-
A2
A
-
-
-
-
A1
e
0.050 BSC
1.27 BSC
e
B
H
L
0.394
0.016
0º
-
-
-
0.419
0.050
8º
10.00
0.40
0º
-
-
-
10.65
1.27
8º
a
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Rev 2.1
5/29/2000
Page 9 of 10
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
Ordering Information
Part Number
Package Type
Production Flow
IMI145158GXB
16 PIN SOIC
Industrial, -40°C to +85°C
* Please contact factory for other options.
Note
: The “x” following the IMI Device Number denotes the device revision. The ordering part number is formed by a
combination of device number, device revision, package style, and screening as shown below.
Marking
: Example:
IMI
145158GXB
Date Code, Lot #
IMI145158GXB
Flow
B = Industrial, -40°C to +85°C
Package
X = Small Outline
Revision
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571
http://www.imicorp.com
Rev 2.1
5/29/2000
Page 10 of 10
相关型号：
©2020 ICPDF网 联系我们和版权申明