IMISM530AYB [CYPRESS]
Processor Specific Clock Generator, 120MHz, CMOS, PDSO20, SSOP-20;
| 型号： | IMISM530AYB |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 120MHz, CMOS, PDSO20, SSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总2页 (文件大小：39K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+/+...when timing is critical
EB530
EB530
SM530 EVALUATION BOARD
DESCRIPTION
The EB530 is an evaluation board used for demonstration and in circuit testing of the SM530 Low EMI clock. The
EB530 includes all of the local circuitry required to operate the SM530 in all functional modes. The purpose of this
Application Note is to provide the user with the information needed to operate the EB530. Located on the EB530
is a dip switch that is connected to all of the programmable inputs of the SM530. The only control line that is not
connected is the STOP input, pin 5. Refer to the SM530 data sheet for detailed data on the operation of the
SM530. There is no evaluation board for the SM532. The EB530 provides the following circuit functions;
•
•
4 layer PCB (1” by 1”).
Separate Digital and Analog Power
and Ground planes.
•
•
Crystal Oscillator circuit
Location included for 3rd overtone
inductor.
•
•
Digital/Analog Power bypass caps.
8 Position Dip Switch
•
•
Test points for REFout and Fout.
14 pin footprint
The EB530 was designed to be used as a simple demonstration board as well as a development tool. The small
size of the EB530 (1” by 1”) allows it to be used in very close proximity to existing clock circuits. The PCB has
been designed to accept a 14 pin DIP header on the bottom side. With the DIP header installed, the EB530 can
replace a 14 pin DIP can oscillator. The loop filter components R1, C6 and C7 are located on the bottom of the
PCB in the area shown in the circle below.
Component Layout
TOP VIEW
BOTTOM VIEW
REF
S1
1
JP1
L2
1
14
Y1
D_C
SSON
R0
14
1
XTAL
2
3
4
Y2
C3
C11
L1
R1
S2
S3
S0
S1
5
6
Loop Filter
7
8
7
8
C7
R1
8
7
C6
Fout
.
Diagram 1
Clock Sources
Two types of clock sources can be provided as input for the SM530. The footprint for an HC/49 type crystal is
provided at Y1 and Y2. The crystal must be a parallel resonant fundamental or third overtone type crystal. If the
crystal is a third overtone, then L1 and C3 must be removed for the circuit to work to properly.
The clock source for the SM530 can also be an external source which can be connected through JP1 on the
EB530. When providing an external clock to OSCin, it is recommended that a capacitor be placed in series with
the signal to compensate for the DC bias of the TTL input at OSCin. If the board does not have jumper pins at
JP1, install a 0.1 uf. capacitor across the feedthru holes at JP1 and connect the external clock source to the
feedthru hole indicated as 1, located between JP1 and Y2.
International Microcircuits,Inc.
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
10/8/98
Rev. 1.0
Page 1 of 2
+/+...when timing is critical
EB530
EB530
SM530 EVALUATION BOARD
Dip Switch Settings
The EB530 includes an 8 position Dip Switch (SW1) that controls the operation of the SM530. The settings for
this dip switch is listed below;
EB530 Range Settings
R0
R1
S0
S1
3
4
7
8
SW-
OSCin = 15 to 30 Mhz @ 5.0 VDC
OP
OP
OP
CL
CL
CL
CL
OP
CL
CL
OP
OP
Fout = X=1
Fout = X=2
Fout = X=4
OSCin = 30 to 60 Mhz @ 5.0 VDC
CL
CL
CL
OP
OP
OP
CL
OP
CL
CL
OP
OP
Fout = X=.5
Fout = X=1
Fout = X=2
OSCin = 60 to 120 Mhz @ 5.0 VDC
OP
OP
OP
OP
OP
OP
CL
OP
CL
CL
OP
OP
Fout = X=.25
Fout = X=.5
Fout = X=1
Table 1.
Fout Modulation and Power Down Selection
S3
S2
S0 and S1 not = 0
Fout State when
(SW1-6)
(SW1-5)
S0 and S1 = 0
1.25 %
2.50 %
5.00 %
10.0 %
0
1
OP
OP
CL
CL
CL
OP
CL
OP
Reserved
Hi-Z
Table 2.
EB530 Schematic Diagram
Through hole xtal
footprint only.
VCC
JP1
VCC
Ext.
1
14
TP1
14 pin DIP
footprint
C1
27 pf
Y1
Note 1.
OUT
GND.
U?
7
8
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
C3
OSCIN
OSCOUT
AVDD
D_C
STOP
S0
LF
AVSS
S1
SSON
REFOUT
OVDD
OVSS
R0
R1
FOUT
S2
DVSS
DVDD
S3
Fout
C8
.033 uf
0.1 uf
L1
1.2 uh
C2
27 PF
Note 3.
VCC
L2
10
1.5uh
+
R2
SM530
C9
.1uf
C11
10uf
VCC
10 ohm
C4
C5
22uf
.1uf
R1
RW1
10K
S1
C7
C6
REWORK
Loop Filter
Note 2.
ANALOG
GND.
PLANE
Notes:
1. Y1 can be any parallel resonant crystal
with approx. 18 pf. load capacitance.
2. Refer to the SM530 Datasheet for proper
loop filter values.
3. If Y1 is a third overtone crystal, install
L1 and C3. If Y1 is a fundamental
crystal, remove L1 and install jumper in
place of C3.
Diagram 2
International Microcircuits,Inc.
10/8/98
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
http:/www.imicorp.com
Rev. 1.0
Page 2 of 2
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CYPRESS
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