JM38510/50501BLX [CYPRESS]
OT PLD, 25ns, TTL, CDIP24, CERAMIC, DIP-24;
| 型号： | JM38510/50501BLX |
| 厂家： | 
CYPRESS |
| 描述： | OT PLD, 25ns, TTL, CDIP24, CERAMIC, DIP-24 时钟 CD 输入元件 可编程逻辑 |
| 文件： | 总24页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
•
High-Performance: f
(w/o feedback)
max
TIBPAL20R’ -15C Series . . . 45 MHz
TIBPAL20R’ -20M Series . . . 41.6 MHz
(TOP VIEW)
•
•
•
High-Performance . . . 45 MHz Min
I
I
I
I
I
I
I
I
V
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
1
24
23
22
21
20
19
18
17
16
15
14
13
CC
Reduced I
of 180 mA Max
CC
2
3
Functionally Equivalent, but Faster Than
PAL20L8, PAL20R4, PAL20R6, PAL20R8
4
5
•
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
6
7
8
I
I
I
9
•
•
Preload Capability on Output Registers
Simplifies Testing
10
11
12
I
I
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
GND
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I/O
PORT
S
I
3-STATE
REGISTERED
Q OUTPUTS
DEVICE
INPUTS O OUTPUTS
(TOP VIEW)
PAL20L8
PAL20R4
PAL20R6
PAL20R8
14
12
12
12
2
0
0
0
0
6
4
2
0
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
4
3
2
1
28 27 26
25
5
I
I
I
I/O
I/O
I/O
description
6
24
23
7
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
8
NC
22 NC
21 I/O
20 I/O
19 I/O
9
I
I
I
10
11
12 13 14 15 16 17 18
NC – No internal connection
Pin assignments in operating mode
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state.
This feature simplifies testing because the registers can be set to an initial state prior to executing the test
sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Copyright 1989, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
TIBPAL20R4’
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
I/O
Q
Q
Q
Q
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25 I/O
I
5
6
7
8
9
I
24
23
Q
Q
I
NC
22 NC
I
I
I
21
20
Q
Q
9
I/O
I/O
I
10
11
10
11
12
I
I
19 I/O
12 13 14 15 16 17 18
GND
OE
TIBPAL20R6’
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
TIBPAL20R8’
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
Q
Q
Q
Q
Q
Q
Q
Q
I
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
NC – No internal connection
Pin assignments in operating mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPAL20L8-15C, TIBPAL20R4-15C
TIBPAL20L8-20M, TIBPAL20R4-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
functional block diagrams (positive logic)
TIBPAL20L8’
≥1
&
EN
O
7
40 X 64
O
7
7
7
7
7
7
7
20 x
I/O
I/O
I/O
I/O
I/O
I/O
14
20
20
I
6
6
TIBPAL20R4’
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
2
40 X 64
1D
8
8
8
20 x
12
20
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
20
7
7
7
4
4
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
functional block diagrams (positive logic)
TIBPAL20R6’
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
Q
Q
2
40 X 64
1D
8
8
20 x
12
20
20
I
8
8
8
6
2
≥1
EN
7
7
2
I/O
I/O
6
TIBPAL20R8’
OE
EN 2
CLK
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
40 X 64
1D
8
8
8
8
8
8
8
20 x
12
20
20
I
8
8
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPAL20L8-15C
TIBPAL20L8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
1
I
Increment
20
0
4
8
12
16
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
I/O
I/O
I/O
I/O
I/O
O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
10 2520
14
13
I
I
I
I
11
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL20R4-15C
TIBPAL20R4-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I/O
I/O
2240
2280
2320
2360
2400
2440
2480
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPAL20R6-15C
TIBPAL20R6-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
1
CLK
Increment
20
0
4
8
12
16
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
Q
C1
2240
2280
2320
2360
2400
2440
2480
I/O
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL20R8-15C
TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
I = 0
1D
120
160
200
240
Q
C1
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
Q
Q
Q
Q
Q
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
C1
2240
2280
2320
2360
2400
2440
2480
I = 0
1D
C1
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
†
0
10
12
15
45
High
Low
†
ns
t
w
Pulse duration, clock
†
t
t
Setup time, input or feedback before clock↑
ns
su
†
Hold time, input or feedback after clock↑
0
0
ns
h
T
A
Operating free-air temperature
25
75
°C
†
f
, t , t , and t do not apply for TIBPAL20L8’.
clock w su
h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
–0.8
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –3.2 mA
= 24 mA
2.4
OH
OL
OH
OL
I
0.3
0.5
20
O, Q outputs
I
V
= 5.25 V,
= 5.25 V,
V
= 2.7 V
= 0.4 V
µA
µA
OZH
CC
CC
O
I/O ports
100
–20
–250
0.1
O, Q outputs
I/O ports
I
V
V
O
OZL
I
I
I
I
V
CC
V
CC
V
CC
= 5.25 V,
= 5.25 V,
= 5.25 V,
V = 5.5 V
I
mA
µA
I
‡
V = 2.7 V
I
25
IH
‡
V = 0.4 V
I
–0.25
mA
mA
IL
§
V
V
= 5.25 V,
= 5.25 V,
V = 0.5 V
O
–30
–70 –130
120 180
OS
CC
V = 0,
CC
I
I
mA
CC
Outputs open,
OE at V
IH
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
With feedback
Without feedback
O, I/O
37
45
40
50
12
8
¶
f
MHz
max
t
pd
t
pd
t
en
t
t
t
I, I/O
CLK↑
OE
R1 = 200 Ω,
R2 = 390 Ω,
See Figure 3
15
12
15
12
18
15
ns
ns
ns
ns
ns
ns
Q
Q
10
8
OE↑
I, I/O
I, I/O
Q
dis
en
dis
O, I/O
O, I/O
12
12
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
= 5 V, T = 25°C.
A
IH IL
CC
¶
1
,
,
f
(with feedback)
max
1
f
(without feedback)
max
t
t
(CLK to Q)
su
does not apply for TIBPAL20L8,.
t
high
t
low
w
pd
w
f
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
–2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
12
†
0
12
12
20
0
41.6
High
Low
†
ns
t
w
Pulse duration, clock
†
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
ns
ns
°C
su
†
h
T
–55
25
125
A
†
f
, t , t , and t do not apply for TIBPAL20L8’.
clock w su
h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
–0.8
3.2
–1.5
IK
CC
CC
CC
CC
I
I
= –2 mA
= 12 mA
= 2.7 V
2.4
V
OH
OL
OH
OL
I
0.3
0.5
100
–20
–250
1
V
I
I
V
µA
OZH
O
O, Q outputs
‡
V
CC
= 5.5 V,
V
O
= 0.4 V
µA
mA
µA
OZL
I/O ports
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 5.5 V
I
CC
I/O ports
All others
100
25
‡
I
V = 2.7 V
I
CC
IH
‡
I
I
V
= 5.5 V,
V = 0.4 V
–0.25
mA
mA
IL
CC
I
§
V
V
= 5.5 V,
= 5.5 V,
V = 0.5 V
O
–30
–70 –250
120 180
OS
CC
CC
V = 0,
CC
I
I
mA
Outputs open,
OE = V
IH
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
With feedback
Without feedback
O, I/O
28.5
41.6
40
50
12
8
¶
f
MHz
max
t
pd
t
pd
t
en
t
t
t
I, I/O
CLK↑
OE
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 3
20
15
20
20
25
20
ns
ns
ns
ns
ns
ns
Q
Q
10
8
OE↑
I, I/O
I, I/O
Q
dis
en
dis
O, I/O
O, I/O
12
12
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. Set V at 0.5 V to
avoid test equipment ground degradation.
= 5 V, T = 25°C.
A
IH IL
CC
O
¶
1
,
,
f
(with feedback)
max
1
f
(without feedback)
max
t
t
(CLK to Q)
su
does not apply for TIBPAL20L8,.
t
high
t
low
w
pd
w
f
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With V
at 5 volts and Pin 1 at V , raise Pin 13 to V
.
CC
IL
IHH
Apply either V or V to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 13 to V . Preload can be verified by observing the
voltage level at the output pin.
IL
IH
IL
V
V
IHH
Pin 13
IL
t
t
d
su
t
t
w
d
V
V
V
V
IH
Pin 1
IL
V
V
IH
OH
OL
Registered I/O
Input
Output
IL
Figure 1. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT, NT, and W packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. t = t = t = 100 ns to 1000 ns V
su IHH
= 10.25 V to 10.75 v
d
h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V
occur until all applicable input and feedback setup times are met.
be monotonic. Following power-up reset, a low-to-high clock transition must not
CC
V
CC
5 V
4 V
†
t
pd
(600 ns TYP, 1000 ns MAX)
V
V
OH
Active Low
Registered Output
1.5 V
OL
‡
t
su
V
V
IH
CLK
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
High-Level
Pulse
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V 1.5 V
Timing
Input
1.5 V
t
w
t
h
t
su
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
Data
Input
Low-Level
Pulse
1.5 V
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
(3.5 V) [3 V]
(0.3 V) [0]
Output
Control
(low-level
enabling)
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
en
t
pd
t
t
t
dis
pd
V
OH
In-Phase
Output
≈ 3.3 V
1.5 V
1.5 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+0.5 V
OL
V
OL
V
OL
t
pd
pd
t
dis
V
OH
t
en
Out-of-Phase
Output
(see Note D)
1.5 V
V
OH
Waveform 2
S1 Open
(see Note B)
V
OL
1.5 V
V
–0.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR ≤ 1 MHz,
t = t ≤ 2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR ≤ 10 MHz, t and t ≤ 2 ns, duty cycle
r
f
r
f
= 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
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D0892
1992 Texas Instruments Incorporated
SRPS021
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
FD
W
5962-87671013A
5962-8767101KA
5962-8767101LA
5962-87671023A
5962-8767102KA
5962-8767102LA
5962-87671033A
5962-8767103KA
5962-8767103LA
5962-87671043A
5962-8767104KA
5962-8767104LA
8412901KA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
28
24
24
28
24
24
28
24
24
28
24
24
24
24
28
24
24
28
24
24
28
24
24
28
24
24
24
24
28
24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
37
15
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-220C-UNLIM
CDIP
LCCC
CFP
JT
FD
W
CDIP
LCCC
CFP
JT
FD
W
CDIP
LCCC
CFP
JT
FD
W
CDIP
CFP
JT
W
8412901LA
CDIP
LCCC
CFP
JT
8412901XA
FK
W
8412902KA
8412902LA
CDIP
LCCC
CFP
JT
8412902XA
FK
W
8412903KA
8412903LA
CDIP
LCCC
CFP
JT
8412903XA
FK
W
8412904KA
8412904LA
CDIP
LCCC
CDIP
CDIP
CDIP
CDIP
PLCC
PDIP
JT
8412904XA
FK
JT
JM38510/50501BLA
JM38510/50502BLA
JM38510/50503BLA
JM38510/50504BLA
TIBPAL20L8-15CFN
TIBPAL20L8-15CNT
JT
JT
JT
FN
NT
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TIBPAL20L8-20MFKB
TIBPAL20L8-20MJT
TIBPAL20L8-20MJTB
TIBPAL20L8-20MWB
TIBPAL20R4-15CFN
TIBPAL20R4-15CNT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
CFP
FK
JT
JT
W
28
24
24
24
28
24
1
1
TBD
TBD
TBD
TBD
TBD
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N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-220C-UNLIM
1
1
PLCC
PDIP
FN
NT
37
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TIBPAL20R4-20MFKB
TIBPAL20R4-20MJT
TIBPAL20R4-20MJTB
TIBPAL20R4-20MWB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
CFP
FK
JT
JT
W
28
24
24
24
1
1
1
1
TBD
TBD
TBD
TBD
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N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
PDIP
Drawing
TIBPAL20R6-15CFN
TIBPAL20R6-15CNT
ACTIVE
ACTIVE
FN
28
24
37
15
TBD
Call TI
Level-1-220C-UNLIM
NT
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TIBPAL20R6-20MFKB
TIBPAL20R6-20MJT
TIBPAL20R6-20MJTB
TIBPAL20R6-20MWB
TIBPAL20R8-15CFN
TIBPAL20R8-15CNT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
CFP
FK
JT
JT
W
28
24
24
24
28
24
1
1
TBD
TBD
TBD
TBD
TBD
Call TI
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N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-220C-UNLIM
1
1
PLCC
PDIP
FN
NT
37
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TIBPAL20R8-20MFKB
TIBPAL20R8-20MJT
TIBPAL20R8-20MJTB
TIBPAL20R8-20MWB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
CFP
FK
JT
JT
W
28
24
24
24
1
1
1
1
TBD
TBD
TBD
TBD
Call TI
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N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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