M5XXLFXI [CYPRESS]
PLL Based Clock Driver, 500 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16;
| 型号： | M5XXLFXI |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 500 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MoBL® Clock
M200/M500
Two-PLL Programmable Clock Generator for
Portable Applications
Features
Benefits
■ Device Operating Voltage Options:
❐ MoBL Clock M200 Family: 1.8V
■ Suitable for cell phone, portable, and consumer electronics
applications
❐ MoBL Clock M500 Family: 2.5V, 3.0V, or 3.3V
■ Multiplehigh-performancePLLsallowsynthesisofunrelated
frequencies
■ Selectable clock output voltages for both MoBL Clock M200
and M500:
❐ 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
■ Application compatibility in multiple output voltage levels
■ Optional Spread Spectrum capable PLLs with Lexmark or
■ Fully integrated ultra low power phase-locked loops (PLLs)
■ Input reference clock frequency range: 1–48 MHz
■ Output clock frequency range: 3–50 MHz
■ Three I2C™ programmable output clocks
■ Programmable output drive strengths
■ 150 ps typical cycle-to-cycle jitter
Linear profile for maximum EMI reduction
■ PLLs can be programmed for system frequency margin tests
■ Meets critical timing requirements in complex system
designs
■ Individually enable or disable each output using I2C
■ Ease of output clock selection using programmable crossbar
switches
■ Optional Spread Spectrum for EMI reduction
■ 16-pin (3x3x0.6 mm) QFN Package
■ Industrial temperature range
Logic Block Diagram
VDD_CLK1
VDD_CLK2
VDD_CLK3
EXCLKIN
REF SEL
CLK1
CLK2
Output
Dividers
and
Crossbar
Switch
PLL1
MUX
and
Control
PLL2
(SS)
Drive
Logic
Strength
Control
CLK3
SCL
I2C
SDA
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-29139 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 10, 2009
[+] Feedback
MoBL® Clock
M200/M500
Pinouts
MoBL Clock M200
Figure 1. Pin Diagram - 16 LD QFN
16
15
14
13
VSS
1
2
3
4
12
11
DNU
MoBL Clock M200
16 LD QFN
CLK1
VDD_CLK3
VDD_CLK1
PD#/OE
10 VDD_CLK2
9
CLK2
5
6
7
8
Table 1. Pin Definitions - MoBL Clock M200 Family (VDD = 1.8V Supply)
Pin Number Name IO
Description
1
2
VSS
Power
Output
GND
CLK1
Programmable Clock Output. Output voltage depends on
VDD_CLK1 voltage
3
4
VDD_CLK1
PD#/OE
Power
Input
Power Supply for CLK1: 1.5V/1.8V/2.5V/3.0V/3.3V
Multifunction Programmable pin: Output Enable or Power Down
Modes
5
6
7
8
9
VSS
SCL
SDA
VSS
CLK2
Power
Input
GND
I2C-Bus Clock Line
I2C-Bus Data Line
GND
Input/Output
Power
Output
Programmable Clock Output. Output voltage depends on
VDD_CLK2 voltage
10
11
12
13
14
VDD_CLK2
VDD_CLK3
DNU
Power
Power
DNU
Power Supply for CLK2: 1.5V/1.8V/2.5V/3.0V/3.3V
Power Supply for output CLK3: 1.5V/1.8V/2.5V/3.0V/3.3V
Do Not Use this pin
GND
VSS
Power
Output
CLK3
Programmable Clock Output. Output voltage depends on
VDD_CLK3 voltage
15
16
VDD
Power
Input
Power Supply: 1.8V
EXCLKIN
1.8V external Reference Clock
Document #: 001-29139 Rev. *A
Page 2 of 14
[+] Feedback
MoBL® Clock
M200/M500
MoBL Clock M500
Figure 2. Pin Diagram - 16 LD QFN
16
15
14
13
VSS
1
2
3
4
12
11
10
9
DNU
CLK1
VDD_CLK3
MoBL Clock M500
16 LD QFN
VDD_CLK1
VDD_CLK2
CLK2
PD#/OE
5
6
7
8
Table 2. Pin Definitions - MoBL Clock M500 Family (VDD = 2.5V, 3.0V or 3.3V Supply)
Pin Number Name IO Description
1
2
VSS
Power
Output
GND
CLK1
Programmable Clock Output. Output voltage depends on
VDD_CLK1 voltage
3
4
VDD_CLK1
PD#/OE
Power
Input
Power Supply for CLK1: 1.5V/1.8V/2.5V/3.0V/3.3V
Multifunction Programmable pin: Output Enable or Power Down
Modes
5
6
7
8
9
VSS
SCL
SDA
VSS
CLK2
Power
Input
GND
I2C-Bus Clock Line
I2C-Bus Data Line
GND
Input/Output
Power
Output
Programmable Clock Output. Output voltage depends on
VDD_CLK2 voltage
10
11
12
13
14
VDD_CLK2
VDD_CLK3
DNU
Power
Power
DNU
Power Supply for CLK2: 1.5V/1.8V/2.5V/3.0V/3.3V
Power Supply for output CLK3: 1.5V/1.8V/2.5V/3.0V/3.3V
Do Not Use this pin
GND
VSS
Power
Output
CLK3
Programmable Clock Output. Output voltage depends on
VDD_CLK3 voltage
15
16
VDD
Power
Input
Power Supply: 2.5V/3.0V/3.3V
EXCLKIN
2.5V/3.0V/3.3V external Reference Clock
Document #: 001-29139 Rev. *A
Page 3 of 14
[+] Feedback
MoBL® Clock
M200/M500
to ±2.50%, or down spread range from –0.25% to –5.0%, with
Lexmark or Linear modulation profile.
General Description
2 Configurable PLLs
PD#/OE Mode
The MoBL® Clock M200/M500 Family of products are two-PLL
Clock Generator ICs designed for cell phone, portable, or
consumer electronics applications. It can be used to generate
two independent output frequencies ranging from 3 to 50MHz
from a single input reference clock.
PD#/OE input (Pin 4) can be programmed to operate as either
power down (PD#) or output enable (OE) mode. Note that power
down shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings. The
PD# turn-on time is limited by the turn-on time of the PLLs.
Disabled outputs are first driven to a low state before turning off.
When off, they are held low by internal weak resistors (~160k
ohms)
2
I C Programming
The MoBL® Clock M200 and M500 have a serial I2C interface
that programs the configuration memory array to synthesize
output frequencies by programmable output divider, spread
characteristics, and drive strength. I2C can also be used for
in-system control of these programmable features.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Input Reference Clocks
Keep Alive Mode
The input to the M200 and M500 are designed to use an external
reference clock with a frequency range of 1 MHz to 48 MHz at
the EXCLKIN pin. The voltage level for the input reference clock
used must follow VDD voltage used for the device as shown in
the DC and AC specifications.
By activating the device in the Keep Alive Mode, power down
mode is changed to power saving mode, which disables all PLLs
and outputs, but preserves the contents of the volatile registers.
Thus, any configuration changes made via the I2C interface are
preserved. By deactivating the Keep Alive Mode, I2C memory is
not preserved during power down, but power consumption is
reduced relative to the Keep Alive Mode.
Output Power Supply Options
There are three clock outputs CLK1, CLK2, and CLK3 driven by
three separate output power supplies: VDD_CLK1, VDD_CLK2,
and VDD_CLK3 respectively. Different voltage level for each of
these power supplies can be used and they can be any of 1.5V,
1.8V, 2.5V, 3.0V, or 3.3V giving user multiple choice of output
clock voltage levels.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 3 shows the typical rise
and fall times for different drive strength settings.
Table 3. Output Drive Strength
Output Source Selection
Rise/Fall Time (ns)
Output Drive Strength
(Typical Value)
These devices have three clock outputs, CLK1, CLK2 and CLK3.
There are three available clock sources for these outputs. These
clock sources are: PLL1, PLL2, or EXCLKIN. Output clock
source selection is done using three out of three crossbar switch.
Thus, any one of these three available clock sources can be
arbitrarily selected for the clock outputs. This gives user a flexi-
bility to have up to two independent clocks and a Reference clock
output.
Low
Mid Low
Mid High
High
6.8
3.4
2.0
1.0
Generic Configuration and Custom Frequency
Spread Spectrum Control
The device is available with Factory Specific programmed
frequencies as shown in the Ordering Information page. This
factory specific programmed part can be used for the device
evaluation purposes. The MoBL® Clock can be custom
programmed to any desired frequencies and listed features. For
customer specific programming and I2C programmable memory
bitmap definitions, please contact local Cypress Field Appli-
cation Engineer (FAE) or sales representative.
The PLL2 has spread spectrum capability for EMI reduction in
the system. The device uses a Cypress proprietary PLL and
Spread Spectrum Clock (SSC) technology to synthesize and
modulate the frequency of the PLL. The spread spectrum feature
can be turned on or off by I2C device programming. It can be
factory programmed to either center spread range from ±0.125%
Document #: 001-29139 Rev. *A
Page 4 of 14
[+] Feedback
MoBL® Clock
M200/M500
2
eight bits must contain the data word intended for storage. After
the receiving the data word, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
I C Serial Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I2C serial interface is provided. This interface is used
to write (and optionally read) control registers that control various
device functions such as enabling individual clock output buffers.
The registers initialize to their default setting upon power up and
therefore, use of this interface is optional. Clock device registers
are normally changed upon system initialization. Any data written
via I2C is volatile and is not retained when the device is powered
down.
The I2C interface uses two signals, SDA and SCL, that operates
up to 400 kbits/s in Read or Write mode. The SDA and SCL
timing and data transfer sequence is shown in Figure 3 on page
6. The basic Write serial format is as follows:
Writing Multiple Bytes
To write multiple bytes at a time, the master must not end the
write sequence with a STOP condition, but instead sends
multiple contiguous bytes of data to be stored. After each byte,
the slave responds with an acknowledge bit, the same as after
the first byte, and accepts data until the acknowledge bit is
responded to by the STOP condition. When receiving multiple
bytes, the MoBL Clock M2xx/M5xx internally increments the
register address.
Read Operations
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illus-
trated in Figure 4 on page 6.
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Device Address
Current Address Read
The device serial interface address is 69H. The device address
is combined with a read/write bit as the LSB and is sent after
each start bit.
The MoBL Clock M2xx/M5xx have an onboard address counter
that retains ‘1’ more than the address of the last word accessed.
If the last word written or read was word ‘n’, then a current
address read operation returns the value stored in location ‘n+1’.
When the MoBL Clock M2xx/M5xx receives the slave address
with the R/W bit set to a ‘1’, it issues an acknowledge and
transmits the 8-bit word. The master device does not
acknowledge the transfer, but generates a STOP condition,
which causes the MoBL Clock M2xx/M5xx to stop transmission.
Data Valid
Data is valid when the clock is HIGH, and can only be transi-
tioned when the clock is LOW, as illustrated in Figure 5 on page
6.
Data Frame
Random Read
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 6 on page 7.
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. To do this, send the address to the MoBL
Clock M2xx/M5xx as part of a write operation. After the word
address is sent, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next, the master reissues the
control byte with the R/W byte set to ‘1’. The MoBL Clock
M2xx/M5xx then issues an acknowledge and transmits the 8-bit
word. The master device does not acknowledge the transfer, but
generates a STOP condition, which causes the MoBL Clock
M200/M500 to stop transmission.
Start Sequence – SDA going LOW when SCL is HIGH indicates
a Start Frame. Every time a start signal is supplied, the next 8-bit
data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Stop Sequence – SDA going HIGH when SCL is HIGH indicates
a Stop Frame. A Stop Frame frees the bus to write to another part
on the same bus or to write to another random register address.
Acknowledge Pulse
During Write Mode, the MoBL Clock M2xx/M5xx responds with
an Acknowledge pulse after every eight bits. This is done by
pulling the SDA line LOW during the N*9th clock cycle, as illus-
trated in Figure 7 on page 7 (N = the number of bytes trans-
mitted). During Read Mode, the master generates the
acknowledge pulse after reading the data packet.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmission of the first 8-bit data word.
This action increments the internal address pointer, and subse-
quently outputs the next 8-bit data word. By continuing to issue
acknowledges instead of STOP conditions, the master serially
reads the entire contents of the slave device memory. When the
internal address pointer points to the FFH register, after the next
increment, the pointer points to the 00H register.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
Document #: 001-29139 Rev. *A
Page 5 of 14
[+] Feedback
MoBL® Clock
M200/M500
Figure 3. Data Transfer Sequence on the Serial Bus
SCL
SDA
STOP
Address or
Acknowledge
Valid
Data may
be changed
Condition
START
Condition
Figure 4. Data Frame Architecture
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
R/W = 0
SDA Write
Multiple
Contiguous
Registers
7-bit
8-bit
8-bit
8-bit
8-bit
Register
Data
(XXH+2)
8-bit
Register
Data
8-bit
Register
Data
(00H)
Device
Address
Register Register Register
Address Data
Data
(XXH+1)
(XXH)
(XXH)
(FFH)
Stop Signal
Start Signal
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
R/W = 1
SDA Read
7-bit
Device
Address
Current
Address
Read
8-bit
Register
Data
Stop Signal
Start Signal
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
R/W = 0
SDA Read
Multiple
Contiguous
Registers
7-bit
Device
Address
8-bit
7-bit
8-bit
Register
Data
8-bit
Register
Data
(XXH+1)
8-bit
Register
Data
8-bit
Register
Data
(00H)
Register Device
Address
(XXH)
Address
+R/W=1
(XXH)
(FFH)
Stop Signal
Start Signal
Repeated
Start bit
Figure 5. Data Valid and Data Transition Periods
Transition
to next Bit
Data Valid
SDA
tDH
tSU
CLKHIGH
VIH
VIL
SCL
CLKLOW
Document #: 001-29139 Rev. *A
Page 6 of 14
[+] Feedback
MoBL® Clock
M200/M500
Serial Programming Interface Timing
Figure 6. Start and Stop Frame
SDA
SCL
Transition
to next Bit
START
STOP
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDA
+
+
+
+
START
D7
D6
D1
D0
DA6
DA5 DA0
R/W
ACK
RA7
RA6 RA1
RA0
ACK
ACK
STOP
+
+
SCL
2
Serial I C Programming Interface Timing Specifications
Parameter
Description
Min
–
Max
400
–
Unit
fSCL
Frequency of SCL
kHz
μs
μs
μs
ns
ns
ns
ns
μs
μs
Start Mode Time from SDA LOW to SCL LOW
SCL LOW Period
0.6
1.3
0.6
250
0
CLKLOW
CLKHIGH
tSU
–
SCL HIGH Period
–
Data Transition to SCL HIGH
Data Hold (SCL LOW to data transition)
Rise Time of SCL and SDA
–
tDH
–
–
300
300
–
Fall Time of SCL and SDA
–
Stop Mode Time from SCL HIGH to SDA HIGH
Stop Mode to Start Mode
0.6
1.3
–
Document #: 001-29139 Rev. *A
Page 7 of 14
[+] Feedback
MoBL® Clock
M200/M500
Absolute Maximum Conditions
Parameter
VDD
Description
Condition
Min
–0.5
–0.5
–0.5
Max
4.4
2.8
4.4
Unit
V
Supply Voltage for MoBL Clock M5xx
Supply Voltage for MoBL Clock M2xx
VDD
V
VDD_CLKX
Supply Voltage for MoBL Clock
M2xx/M5xx
V
VIN
Input Voltage for MoBL Clock M5xx
Input Voltage for MoBL Clock M2xx
Temperature, Storage
Relative to VSS
–0.5
–0.5
–65
VDD+0.5
2.2
V
V
VIN
Relative to VSS
TS
Non Functional
+150
°C
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model)
Flammability Rating
JEDEC EIA/JESD22-A114-E
V-0 @1/8 in.
2000
Volts
ppm
10
3
Moisture Sensitivity Level
Recommended Operating Conditions
The Recommended Operating Conditions table for MoBL Clock M2xx/M5xx family.
Parameter
VDD
Description
VDD Operating voltage for MoBL Clock M5xx
VDD Operating voltage for MoBL Clock M2xx
Output Driver Voltage for MoBL Clock M2xx/M5xx
Industrial Ambient Temperature
Min
Typ
–
Max
3.60
1.95
3.60
85
Unit
V
2.25
1.65
1.43
–40
–
VDD
1.80
–
V
VDD_CLKX
TAI
CLOAD
tPU
V
–
°C
pF
ms
Maximum Load Capacitance
–
15
Power up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
Document #: 001-29139 Rev. *A
Page 8 of 14
[+] Feedback
MoBL® Clock
M200/M500
DC Electrical Specifications
The DC Electrical Specification table for MoBL Clock M2xx/M5xx family (VDD_CLKX = 1.5V/1.8V/2.5V/3.0/3.3V).
Parameter
Description
Conditions
Min
Typ
Max
Unit
V
Output Low Voltage
IOL = 2 mA, drive strength = [00]
–
–
0.4
V
OL
I
OL = 3 mA, drive strength = [01]
OL = 7 mA, drive strength = [10]
I
IOL = 12 mA, drive strength = [11]
IOH = –2 mA, drive strength = [00]
V
Output High Voltage
VDD_CLKX
0.4
–
–
–
V
OH
I
OH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
OH = –12 mA, drive strength = [11]
I
V
V
Output Low Voltage, SDA
IOL = 4 mA
–
–
–
–
0.4
V
V
OLSD
Input Low Voltage of PD#/OE,
SDA and SCL pins
0.2*VDD
IL1
V
V
V
V
Input Low Voltage of EXCLKIN
pin
–
–
–
–
–
0.1*VDD
V
V
V
V
IL2
IH1
IH2
IH3
Input High Voltage of PD#/OE,
SDA and SCL pins
0.8*VDD
0.9*VDD
0.9*VDD
–
–
Input High Voltage of EXCLKIN
for MoBL Clock M5xx
Input High Voltage of EXCLKIN
pin MoBL Clock M2xx
2.2
IIH
Input High Current, PD#/OE
Input Low Current, PD#/OE
VIH = VDD
VIL = 0V
–
–
–
–
10
10
µA
µA
kΩ
IIL
RDN
Pull Down Resistor of clocks
(CLK1-CLK3) in off-state
Clock outputs in off-state by setting
PD# = Low
100
160
250
[1,2]
IDD
Supply Current
Standby Current
All outputs running, CLOAD = 0
PD# = Low, I2C circuit not in Keep
Alive Mode
–
–
15
3
–
–
mA
µA
[1]
IDDS
[2]
CIN
Input Capacitance
SCL, SDA, and PD#/OE inputs
–
–
7
pF
Document #: 001-29139 Rev. *A
Page 9 of 14
[+] Feedback
MoBL® Clock
M200/M500
AC Electrical Specifications
The AC Electrical Specifications table for M2xx/M5xx (VDD_CLKX = 1.5V/1.8V/2.5V/3.0/3.3V) family.
Parameter
FCLK
Description
Conditions
All clock outputs
Min
3
Typ
–
Max
50
Unit
MHz
MHz
%
Clock Output Frequency
FREF
DC
Driven Reference Frequency EXCLKIN Clock
1
–
48
Output Clock Duty Cycle
Duty Cycle as defined in Figure 9 on
45
50
55
page 11
t1/t2, 50% of VDD_CLKX
[2]
TRF1
TRF2
TRF3
TRF4
TCCJ
Output Clock Rise/Fall Time
Measured from 20% to 80% of
VDD_CLKX, as shown in Figure 10 on
page 11, CLOAD = 15 pF, drive
strength [00]
–
–
–
–
6.8
3.4
2.0
1.0
10.0
5.0
ns
ns
ns
ns
[2]
[2]
[2]
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
Measured from 20% to 80% of
VDD_CLKX, as shown in Figure 10 on
page 11, CLOAD = 15 pF, drive
strength [01]
Measured from 20% to 80% of
VDD_CLKX, as shown in Figure 10 on
page 11, CLOAD = 15 pF, drive
strength [10]
3.0
Measured from 20% to 80% of
VDD_CLKX, as shown in Figure 10 on
page 11, CLOAD = 15 pF, drive
strength [11]
1.5
[1,2]
Cycle-to-cycle Jitter
PLL Lock Time
EXCLKIN = CLKx = 48 MHz, CLOAD
= 15 pF, 2 PLLs and 1 output for each
PLL enabled, drive strength = [11]
–
–
150
1
–
3
ps
[2]
TLOCK
ms
Notes
1. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1].
2. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
Document #: 001-29139 Rev. *A
Page 10 of 14
[+] Feedback
MoBL® Clock
M200/M500
Test and Measurement Setup
Figure 8. Test and Measurement Setup
V
DD
Outputs
0.1 μF
C
LOAD
DUT
GND
Voltage and Timing Definitions
Figure 9. Duty Cycle Definition
t1
t2
VDD_CLKX
50% of V
0V
DD_CLKX
Clock
Output
Figure 10. Rise Time = TRF, Fall Time = TRF
TRF
TRF
V DD_CLKX
80% of V
DD_CLKX
20% of VDD_CLKX
0V
Clock
Output
Document #: 001-29139 Rev. *A
Page 11 of 14
[+] Feedback
MoBL® Clock
M200/M500
Ordering Information
Part Number [3]
Frequency Configuration
Other Programmable Features
Package
Production Flow
Pb-Free
M200LFXI
Factory Generic Configuration VDD = 1.8V
16-pin QFN
Industrial, –40°C to 85°C
With EXCLKIN = 19.2MHz
CLK1 = 48.0MHz
VDD_CLKx = 1.5/1.8V2.5/3.0/3.3V
Power Down = Enabled
CLK2 = 27.0MHz
Keep Alive = Disabled
Spread Spectrum = Disabled
Output Drive Strength = [11]
M200LFXIT
M500LFXI
M500LFXIT
Factory Generic Configuration VDD = 1.8V
16-pin QFN-
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
With EXCLKIN = 19.2MHz
CLK1 = 48.0MHz
CLK2 = 27.0MHz
VDD_CLKx = 1.5/1.8/2.5/3.0/3.3V Tape & Reel
Power Down = Enabled
Keep Alive = Disabled
Spread Spectrum = Disabled
Output Drive Strength = [11]
Factory Generic Configuration VDD = 2.5/3.0/3.3V
16-pin QFN
16-pin QFN-
With EXCLKIN = 19.2MHz
CLK1 = 48.0MHz
CLK2 = 27.0MHz
VDD_CLKx = 1.5/1.8V2.5/3.0/3.3V
Power Down = Enabled
Keep Alive = Disabled
Spread Spectrum = Disabled
Output Drive Strength = [11]
Factory Generic Configuration VDD = 2.5/3.0/3.3V
With EXCLKIN = 19.2MHz
VDD_CLKx = 1.5/1.8/2.5/3.0/3.3V Tape & Reel
CLK1 = 48.0MHz
CLK2 = 27.0MHz
Power Down = Enabled
Keep Alive = Disabled
Spread Spectrum = Disabled
Output Drive Strength = [11]
M2xxLFXI
M2xxLFXIT
M5xxLFXI
M5xxLFXIT
Customer Specific Configu-
ration
VDD = 1.8V
VDD_CLKx = 1.5/1.8/2.5/3.0/3.3V
16-pin QFN
16-pin QFN-
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Customer Specific Configu-
ration
VDD = 1.8V
VDD_CLKx = 1.5/1.8/2.5/3.0/3.3V Tape & Reel
Customer Specific Configu-
ration
VDD = 2.5/3.0/3.3V
VDD_CLKx = 1.5/1.8/2.5/3.0/3.3V
16-pin QFN
Customer Specific Configu-
ration
VDD = 2.5/3.0/3.3V
VDD_CLKx = 1.5/1.8/2.5/3.0/3.3V Tape & Reel
16-pin QFN-
Note
3. xx indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative
Document #: 001-29139 Rev. *A
Page 12 of 14
[+] Feedback
MoBL® Clock
M200/M500
Package Drawing and Dimensions
Figure 11. 16-Lead Chip On Lead 3x3 mm QFN Package
001-09116 *C
Document #: 001-29139 Rev. *A
Page 13 of 14
[+] Feedback
MoBL® Clock
M200/M500
Document History Page
Document Title: MoBL® Clock M200/M500 Two-PLL Programmable Clock Generator for Portable Applications
Document Number: 001-29139
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
1535744
2748211
See ECN
08/10/09
RGL/AESA New Data Sheet
*A
TSAI
Posting to external web.
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-29139 Rev. *A
Revised August 10, 2009
Page 14 of 14
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned
in this document may be the trademarks of their respective holders.
[+] Feedback
相关型号：
M5XXLFXIT
PLL Based Clock Driver, 500 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16
CYPRESS
©2020 ICPDF网 联系我们和版权申明