MB89145V2P-SH_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS07-12522-4E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89140 Series

MB89145/146 and MB89P147/PV140

■ DESCRIPTION

The MB89140 series is a line of single-chip microcontrollers that use the F²MC*-8L CPU core which can operate

at low voltage but at high speed. The MB89140 series contains a variety of peripheral functions, such as timers,

a serial interface, an A/D converter, and an external interrupt. The MB89140 series is applicable to a wide range

of applications from welfare products to industrial equipment, including portable devices.

*: F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

• Minimum execution time: 0.5 µs/8-MHz oscillation

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

Bit manipulation instructions, etc.

(Continued)

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

2008.11

MB89140 Series

(Continued)

• Low-voltage operation (when an A/D converter is not used)

• Low current consumption (compatible with dual-clock system)

• High-voltage ports on chip

• Five types of timers

8-bit PWM timer (also usable as a reload timer)

12-bit MPG timer (also usable as a PPG output, PWM output, and reload timer)

8/16-bit timer (also usable as two 8-bit timers)

21-bit time-base timer

• One serial interface

Swichable transfer direction allows communication with various equipment.

• 10-bit A/D converter: 12 channels

Successive approximation type

• External interrupt: 2 channels

Two channels are independent and capable of wake-up from low-power consumption modes. (Rising edge,

falling edge/both edges selectability)

–0.3 V to +7.0 V can be applied to INT1 (N-ch open-drain)

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

Subclock mode

Watch mode

• Reset output and power-on reset selectability

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DS07-12522-4E

MB89140 Series

■ PRODUCT LINEUP

Part number

MB89145

MB89146

MB89P147

MB89PV140

Piggyback/

Parameter

Classification

Mass production products

(mask ROM products)

One-time PROM/

EPROM product

evaluation product

(for evaluation and

development)

ROM size

16 K × 8 bits

(internal mask

ROM)

24 K × 8 bits

(internal mask

ROM)

32 K × 8 bits

(internal PROM)

32 K × 8 bits

(external ROM)

RAM size

512 × 8 bits

768 × 8 bits

1 K × 8 bits

CPU functions

Number of instructions:

Instruction bit length:

Instruction length:

Data bit length:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

Minimum execution time:

Interrupt processing time:

Note:

0.5 µs/8 MHz to 8.0 µs/8 MHz, 61 µs/32.768 kHz

4.5 µs/8 MHz to 72.0 µs/8 MHz, 562.5 µs/32.768 kHz

The above times change according to the gear function.

Ports

High-voltage output port

(P-ch open-drain):

8 (P60 to P67, for heavy current) 16 (P40 to P47, P50 to

P57 for low current)

Buzzer output

(P-ch open-drain, high-voltage): 1 (heavy current)

Output ports (CMOS):

Input ports (CMOS):

4 (P20 to P23)

2 (P70 and P71, function as X0A and XIA pins when

dual-clock system is used.)

I/O ports (CMOS):

I/O ports (N-ch open-drain):

Total:

23 (P00 to P07, P10 to P17, P30, and P32 to P37)

1 (P31)

55

Watch timer

21 bits × 1 (in main clock mode), 15 bits × 1 (at 32.768 kHz)

8-bit PWM timer

(timer 1)

8-bit timer operation

(toggled output capable, operating clock: 1, 2, 8, 16 system clock cycles)

8-bit resolution PWM operation

(conversion cycle: 128 µs to 2.0 ms at 8.0-MHz oscillation, and highest gear speed)

12-bit MPG

(timer 4)

12-bit resolution PWM operation (maximum conversion cycle of 2048.4 µs to 16.4 ms at

8.0 MHz-oscillation, and highest gear speed)

12-bit resolution reload timer operation (toggled output capable)

12-bit resolution PPG operation (minimum resolution of 0.5 µs at 8.0-MHz oscillation, and

highest gear speed)

8/16-bit timer

counter

(timer 2, 3)

8/16-bit timer operation (operating clock, internal clock, external trigger)

8/16-bit event counter operation (Rising edge/falling edge/both edges selectability)

(Continued)

DS07-12522-4E

3

MB89140 Series

(Continued)

Part number

MB89145

Parameter

MB89146

MB89P147

MB89PV140

8-bit serial I/O

8 bits

LSB first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles)

10-bit A/D

converter

10-bit resolution × 12 channels

A/D conversion mode (conversion time of 16.5 µs/8 MHz, and highest gear speed)

Sense mode (conversion time of 9.0 µs/8 MHz, and highest gear speed)

External activation capable

External interrupt

2 independent channels (edge selection, interrupt vector, source flag)

Rising edge/falling edge/both edges selectability

Built-in analog noise canceller

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)

Standby mode

Process

Sleep mode, stop mode, watch mode, and subclock mode

CMOS

Operating

voltage*

2.7 V to 6.0 V

EPROM for use

MBM27C256A-20TV

MBM27C256A-20CZ

* : Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS”.)

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89145

Package

MB89146

MB89PV140

MB89P147

DIP-64P-M01

FPT-64P-M06

MDP-64C-P02

MQP-64C-P01

×

: Available

× : Not available

Note: For more information about each package, see section “■ PACKAGE DIMENSIONS”.

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MB89140 Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

• On the MB89P147, the program area starts from address 8007^Hbut on the MB89PV140 starts from 8000H.

(On the MB89P147, addresses 8000^Hto 8006H comprise the option setting area, option settings can be read

by reading these addresses. On the MB89PV140, addresses 8000^Hto 8006H could also be used as a program

ROM. However, do not use these addresses in order to maintain compatibility of the MB89P147.)

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

• In the case of the MB89PV140, add the current consumed by the EPROM which is connected to the top socket.

• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume

more current than the product with a mask ROM.

However, the current consumption in sleep/stop modes is the same. (For more information, see section

“■ ELECTRICAL CHARACTERISTICS”.)

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product. Before using

options check section “■ MASK OPTIONS”.

Take particular care on the following points:

• Options are fixed on the MB89PV140.

• OntheMB89P147, MB89145, andMB89146, thepull-downresistoroptioncaneither beselected for all affected

pins, or for no pin; it is not possible to specify the pull-down resistor option for individual pins.

4. Subclock Oscillation Feedback Resistor

A built-in oscillation feedback resistor is provided for the subclock oscillator pin on the MB89PV140, but it is not

provided for the MB89145, MB89146, MB89P147. Therefor these products should be connected to an external

oscillation feedback resistor.

DS07-12522-4E

5

MB89140 Series

■ PIN ASSIGNMENT

(Top view)

1

2

3

4

5

6

7

8

VCC

AV^CC

AV^SS

BZ

P67

P66

P65

P64

P63

P62

P61

P60

VFDP

P57

P56

P55

P54

P53

P52

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

65

66

67

68

69

70

71

72

73

74

75

76

77

78

VCC

A14

A13

A8

A15/V^PP

A12

A7

92

91

90

89

88

87

86

85

84

83

82

81

80

79

P00/AN0

P01/AN1

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

P07/AN7

P10/AN8

P11/AN9

P12/ANA

P13/ANB

P14

A6

A5

A4

A3

A2

A1

A0

O1

A9

A11

OE

A10

CE

O8

O7

O6

O5

O4

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

O2

O3

V^SS

P15

P16

P51

P50

P47

P46

P45

P44

P43

P42

P41

Each pin inside the dashed line

is for the MB89PV140 only.

P17/ADST

P30/INT0/TRG

P31/INT1

P32/SCK

P33/SO

P34/SI

P35/EC

P36/PWO1

P37/DTTI

P20

P40

P23/WDG

RST

MODA

X0

P21/PWO0

P22

P70/X0A*

P71/X1A*

X1

V^SS

(DIP-64P-M01)

(MDP-64C-P02)

*: When dual-clock system is selected.

6

DS07-12522-4E

MB89140 Series

(Top view)

P61

P60

VFDP

P57

P56

P55

P54

P53

P52

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

1

2

3

4

5

6

7

8

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P03/AN3

P04/AN4

P05/AN5

P06/AN6

P07/AN7

P10/AN8

P11/AN9

P12/ANA

P13/ANB

P14

85

86

87

88

89

90

91

92

93

77

76

75

74

73

72

71

70

69

9

10

11

12

13

14

15

16

17

18

19

P15

P16

P17/ADST

P30/INT0/TRG

P31/INT1

P32/SCK

P33/SO

P34/SI

P35/EC

Each pin inside the dashed line

is for the MB89PV140 only.

(FPT-64P-M06)

(MQP-64C-P01)

*: When dual-clock system is selected.

• Pin assignment on package top (MB89PV140 only)

Pin no.

65

Pin name

N.C.

A15/VPP

A12

Pin no.

73

Pin name

A2

Pin no.

81

Pin name

N.C.

O4

Pin no.

89

Pin name

OE

66

74

A1

82

90

N.C.

A11

A9

67

75

A0

83

O5

91

68

A7

76

N.C.

O1

84

O6

92

69

A6

77

85

O7

93

A8

70

A5

78

O2

86

O8

94

A13

A14

VCC

71

A4

79

O3

87

CE

95

72

A3

80

V^SS

88

A10

96

N.C.: Internally connected. Do not use.

DS07-12522-4E

7

MB89140 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

SDIP^*1

MDIP^*2

QFP^*3

MQFP^*4

30

31

29

23

24

22

X0

X1

A

C

Main clock crystal oscillator pins

MODA

Operating mode selection pin

Connect directly to V^SSin normal operation. This pin

functions as the V^PPpin in EPROM products.

28

21

RST

D

Reset I/O pin

This pin is an N-ch open-drain output type with a pull-up

resistor, and a hysteresis input type.

“L” is output from this pin by an internal reset source

when the option is set. The internal circuit is initialized

by the input of “L”.

This pin is with a noise canceller.

54 to 61

47 to 54 P07/AN7 to

P00/AN0

G

J

General-purpose I/O ports

The input is a hysteresis input type and with a built-in

noise canceller. Although these ports also serve as an

analog input, analog input does not pass through the

hysteresis input noise canceller.

46

39

P17/ADST

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. Also serves as an A/D converter

external activation.

47 to 49

50 to 53

40 to 42 P16 to P14

J

General-purpose I/O ports

The input is a hysteresis input type and with a built-in

noise canceller.

43 to 46 P13/ANB to

P10/AN8

G

General-purpose I/O ports

The input is a hysteresis input type and with a built-in

noise canceller. Although these ports also serves as an

analog input, analog input does not pass through the

hysteresis input noise canceller.

34,

33

27,

26

P70/X0A,

P71/X1A

B/K

General-purpose I/O ports with a built-in noise

canceller

(single-clock operation)

Function as subclock crystal oscillator pins. (dual-clock

operation)

35

27

28

20

P22

E

General-purpose output port

P23/WDG

General-purpose output port

Also serves as a watchdog output.

36

29

30

P21/PWO0

P20

E

General-purpose output port

Also serves as the PWM output for the 8-bit PWM timer.

37

General-purpose output port

(Continued)

*1: DIP-64P-M01

*2: MDP-64C-P02

*3: FPT-64P-M06

*4: MQP-64C-P01

8

DS07-12522-4E

MB89140 Series

Pin no.

Circuit

type

Pin name

P37/DTTI

Function

SDIP^*1

QFP^*3

MDIP^*2

MQFP^*4

38

31

J

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. When overcurrent is detected, the 12-

bit MPG output can be inactivated by the external edge

input.

39

40

32

33

P36/PWO1

P35/EC

J

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. Also serves as a 12-bit MPG output.

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. Also serves as the external clock input

for the 8/16-bit timer/counter.

41

42

43

44

34

35

36

37

P34/SI

J

F

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. Also serves as the serial data input for

the 8-bit serial interface.

P33/SO

P32/SCK

P31/INT1

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. Also serves as the serial data output

for the 8-bit serial interface.

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. Also serves as the serial transfer clock

for the 8-bit serial interface.

General-purpose I/O port

The output is an N-ch open-drain type. The input is a

hysteresis input type and with a built-in noise canceller.

Also serves as an external interrupt. The interrupt input

is also a hysteresis input type and with a built-in noise

canceller.

45

1

38

58

P30/INT0/TRG

J

General-purpose I/O port

The input is a hysteresis input type and with a built-in

noise canceller. Also serve as an external interrupt or

as an MPG trigger input. The interrupt input is also a

hysteresis input type and with a built-in noise canceller.

BZ

I

Buzzer output-only pin

P-ch high-voltage open-drain output port

19 to 26,

11 to 18

12 to 19,

4 to 11

P47 to P40,

P57 to P50

H

Low-current P-ch high-voltage open-drain output ports

Products with and without a built-in pull-down resistor

between these pins and the VFDP pin are provided.

(Continued)

*1: DIP-64P-M01

*2: MDP-64C-P02

*3: FPT-64P-M06

*4: MQP-64C-P01

DS07-12522-4E

9

MB89140 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

SDIP^*1

MDIP^*2

QFP^*3

MQFP^*4

2 to 9

59 to 64,

1, 2

P67 to P60

H

Heavy-current P-ch high-voltage open-drain output

port

Products with and without a built-in pull-down resistor

between these pins and the VFDP pin are provided.

10

3

VFDP

—

Voltage supply pin for connection to a pull-down

resistor for ports 4, 5, and 6. In products without a built-

in pull-down resistor and in the MB89PV140, this pin

should be left open.

64

32

63

57

25

56

V^CC

—

Power supply pin

V^SS

Power supply (GND) pin

AV^CC

A/D converter power supply pin

Use this pin at the same voltage as V^CC.

62

55

AV^SS

—

A/D converter power supply (GND) pin

Use this pin at the same voltage as V^SS.

*1: DIP-64P-M01

*2: MDP-64C-P02

*3: FPT-64P-M06

*4: MQP-64C-P01

10

DS07-12522-4E

MB89140 Series

• External EPROM pins (MB89PV140 only)

Pin no.

Pin name

I/O

Function

SDIP^*3

MDIP^*4

QFP^*1

MQFP^*2

65

66

A15/VPP

O

“H” level output pin

Address output pins

66

67

68

69

70

71

72

73

74

67

68

69

70

71

72

73

74

75

A12

A7

A6

A5

A4

A3

A2

A1

A0

75

76

77

78

79

O1

O2

O3

I

Data input pins

78

80

V^SS

O

I

Power supply (GND) pin

Data input pins

79

80

81

82

83

82

83

84

85

86

O4

O5

O6

O7

O8

84

87

CE

O

ROM chip enable pin

Outputs “H” during standby.

85

86

88

89

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

87

88

89

91

92

93

A11

A9

A8

O

Address output pins

90

91

92

—

94

95

96

A13

A14

V^CC

O

EPROM power supply pin

65

76

81

90

N.C.

—

Internally connected pins

Be sure to leave them open.

*1: DIP-64P-M01

*2: MDP-64C-P02

*3: FPT-64P-M06

*4: MQP-64C-P01

DS07-12522-4E

11

MB89140 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Standby control signal

Remarks

A

• Crystal or ceramic oscillation type (main clock)

• At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

X1

X0

B

• Crystal or ceramic oscillation type (subclock)

• At an oscillation feedback resistor of approximately

4.5 MΩ/5.0 V

(The built-in feedback resistor is not provided except

on the MB89PV140-102.)

X1A

X0A

C

D

• At an output pull-up resistor (P-ch) of approximately

50 kΩ/5.0 V

R

• CMOS hysteresis input

P-ch

(with noise canceller)

N-ch

Hysteresis input (with noise canceller)

E

F

• CMOS output

P-ch

N-ch

• N-ch open-drain output

• CMOS hysteresis input

(with noise canceller)

N-ch

Hysteresis input (with noise canceller)

(Continued)

12

DS07-12522-4E

MB89140 Series

(Continued)

Type

Circuit

Remarks

G

• CMOS output

• CMOS hysteresis input

P-ch

(with noise canceller, except analog input)

N-ch

Port

Hysteresis input (with noise canceller)

Analog input

H

• P-ch high-voltage open-drain output

• Products with and without a built-in pull-down resistor

are provided (except the MB89PV140).

P-ch

VFDP

I

• P-ch high-voltage open-drain output

P-ch

J

• CMOS output

• CMOS hysteresis input

(with noise canceller)

• Pull-up resistor optional

P-ch

N-ch

Port

Hysteresis input (with noise canceller)

K

• CMOS hysteresis input

(with noise canceller)

Port

Hysteresis input (with noise canceller)

DS07-12522-4E

13

MB89140 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ ELECTRICAL CHARACTERISTICS” is applied between V^CCand VSS. (However, up to

7.0 V can be applied to P31/INT pin, regardless of V^CC)

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

4. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, evenifitoccurs withintherated range. Stabilizingvoltagesuppliedto the IC is therefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 Hz to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

5. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

14

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MB89140 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P147

The MB89P147 is an OTPROM version of the MB89140 series.

1. Features

• 32-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

EPROM mode

(Corresponding addresses on the EPROM programmer)

I/O

0080H

0480H

RAM

Not available

8000H

8007H

0000H

Option area

0007H

PROM

32 KB

EPROM

32 KB

FFFF^H

7FFF^H

3. Programming to the EPROM

In EPROM mode, the MB89P147 functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

When the operating ROM area for a single chip is 32 Kbytes (8007^Hto FFFFH) the PROM can be programmed

as follows:

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007^Hto 7FFFH (note that addresses 8007H to FFFFH

while operating as a single chip assign to 0007H to 7FFFH in EPROM mode).

Load option data into addresses 0000^Hto 0006H of the EPROM programmer. (For information about each

corresponding option, see “5. Setting OTPROM Options”. in section “■ PROGRAMMING TO THE EPROM

WITH PIGGYBACK/EVALUATION DEVICE”)

(3) Program to 0000^Hto 7FFFH with the EPROM programmer.

DS07-12522-4E

15

MB89140 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150 ˚C, 48 h

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu Microelectronics shipping test to a blanked OTPROM microcomputer,

due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.

16

DS07-12522-4E

MB89140 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TV, MBM27C256A-20CZ

2. Memory Space

Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

Corresponding addresses on the EPROM programmer

I/O

0080H

0480H

RAM

Not available

8000H

8007H

0000H

Option area

0007H

PROM

32 KB

EPROM

32 KB

FFFF^H

7FFF^H

3. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007^Hto 7FFFH.

(3) Program to 0000^Hto 7FFFH with the EPROM programmer.

DS07-12522-4E

17

MB89140 Series

4. Setting PROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vacancy

Single/dual-

clock system

Reset pin

output

1: Yes

Power-on

reset

1: Yes

0: No

Reserved

(Write 1 bit (Write 1 bit

to this bit.) to this bit.)

Reserved

8000H

Readable and Readable and Readable and 1: Dual clock

(0000H)

writable

0: Single clock

0: No

Vacancy

P17

P16

P15

P14

8001H

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable and Readable and Readable and Readable and

(0001H)

writable

Vacancy

P37

P36

P35

P34

P33

P32

8002^H

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable and Readable and

(0002H)

writable

Vacancy

8003^H

Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and

(0003H)

writable

Vacancy

8004^H

Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and

(0004H)

writable

Vacancy

8005^H

Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and

(0005H)

writable

Vacancy

8006^H

Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and

(0006H)

writable

Notes: • Initial value is 1 for each bit.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

• The parenthesized addresses are the corresponding addresses on the EPROM programmer.

18

DS07-12522-4E

MB89140 Series

■ BLOCK DIAGRAM

X0

X1

Main clock oscillator

Clock controller

Time-base timer

Buzzer

BZ

8

P70, P71

X0A

Subclock oscillator

(32.768 kHz)

High-voltage port 6

High-voltage port 5

High-voltage port 4

P60 to P67

X1A

CMOS input port

CMOS output port

P50 to P57

P23/WDG

P22

P21/PWO0

P20

P40 to P47

VFDP

8-bit PWM timer

P32/SCK

P33/SO

P34/SI

8-bit serial interface

Mode control

MODA

AVCC

AVSS

10-bit A/D converter

P30/TRG/INT0

P37/DTTI

12-bit MPG

P36/PWO1

P17/ADST

4

P14 to P16

4

8/16-bit

P13/ANB to

P10/AN8

8

P07/AN7 to

P00/AN0

P35/EC

timer/counter

CMOS I/O port

External

interrupt

P31/INT1

(N-ch open-drain)

RAM

CMOS I/O port

Reset circuit

F²MC-8L

CPU

RST

ROM

Other pins

V^CC, VSS

DS07-12522-4E

19

MB89140 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89140 series offer a memory space of 64 Kbytes for storing all of I/O, data, and

program areas. The I/O area is located at the lowest address. The data area is provided immediately above the

I/O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89140 series is structured as illustrated below.

Memory Space

MB89PV140

I/O

MB89145

I/O

MB89146

I/O

MB89P147

I/O

0000H

0080H

0000H

0080H

0000H

0080H

0000H

0080H

RAM

0100H

0200^H

0100H

0200H

0380H

0100H

0200H

Register

0200H

0280H

0480H

8000H

8006H

0480H

8000H

8006H

Not available

*

A000H

C000H

External ROM

32 KB

PROM

32 KB

ROM

24 KB

ROM

16 KB

FFFFH

FFFF^H

FFFFH

*: Since addresses 8000H to 8005H for the MB89P147 comprise an option area, do not use this area for the MB89PV140.

20

DS07-12522-4E

MB89140 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

PC

Initial value

FFFD^H

: Program counter

: Accumulator

A

T

Undefined

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

DS07-12522-4E

21

MB89140 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

22

DS07-12522-4E

MB89140 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used in the MB89140 series. The bank currently in use is

indicated by the register bank pointer (RP).

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

DS07-12522-4E

23

MB89140 Series

■ I/O MAP

Address

00^H

01^H

02^H

03^H

04^H

05^H

06^H

07^H

08^H

09^H

0A^H

0B^H

0C^H

0D^H

0E^H

0F^H

10^H

11^H

12^H

13^H

14^H

15^H

16^H

17^H

18^H

19^H

1A^H

1B^H

1C^H

1D^H

1E^H

1F^H

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

(R/W)

(W)

PDR1

DDR1

Port 1 data direction register

Port 2 data register

(R/W)

PDR2

Vacancy

(R/W)

(W)

SYCC

STBC

WDTC

TBCR

WPCR

PDR3

DDR3

BUZR

EIC

System clock control register

Standby control register

Watchdog timer control register

Time-base timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Buzzer register

(R/W)

(R)

External interrupt control register

Port 4 data register

PDR4

PDR5

PDR6

PDR7

Port 5 data register

Port 6 data register

Port 7 data register

Vacancy

(W)

COMR

CNTR

T3CR

T2CR

T3DR

T2DR

SMR

8-bit PWM timer compare register

8-bit PWM timer control register

Timer 3 control register

Timer 2 control register

Timer 3 data register

Timer 2 data register

Serial mode register

(R/W)

SDR

Serial data register

ADC1

ADC2

A/D converter control register 1

A/D converter control register 2

(Continued)

24

DS07-12522-4E

MB89140 Series

(Continued)

Address

Read/write

(R/W)

(W)

Register name

ADDH

Register description

20^H

21^H

A/D converter data register (H)

ADDL

A/D converter data register (L)

Port input control register 0

Port input control register 1

MPG control register

MPG interrupt status register

MPG compare clear buffer register H

MPG compare clear buffer register L

MPG output buffer register H

MPG output buffer register L

Vacancy

22^H

PCR0

23^H

(W)

PCR1

24^H

(R/W)

(W)

MCNT

25^H

INTSTR

26^H

CMCLBR (H)

CMCLBR (L)

OUTCBR (H)

OUTCBR (L)

27^H

(W)

28^H

(W)

29^H

(W)

2A^H

2B^H

2C^H

2D^H

2E^H

2F^H

Vacancy

30^Hto 77H

78^H

Vacancy

79^H

Vacancy

7A^H

7B^H

7C^H

7D^H

7E^H

7F^H

Vacancy

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

Note: Do not use vacancies.

DS07-12522-4E

25

MB89140 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Rating

Min.

Symbol

Unit

Remarks

Parameter

Max.

VSS + 7.0

VCC + 0.3

7

VSS – 0.3

V^CC

V

Power supply voltage

AV^CC

*2

V^IO1

Except P31

P31

I/O voltage

V^IO2

Average value (operating current ×

“H” level total average output current ΣI^OH

—

–120

–12

mA

operating rate)

P00 to P07, P10 to P17,

P20 to P23, P30, P32 to P37

“H” level maximum output current

“H” level average output current

I^OH

—

–20

–36

mA P40 to P47, P50 to P57

mA P60 to P67, BZ

P00 to P07, P10 to P17,

P20 to P23, P30, P32 to P37

—

–6

mA

Average value (operating current ×

operating rate)^*1

P40 to P47, P50 to P57

mA Average value (operating current ×

operating rate)^*1

I^OHAV

—

–10

–18

P60 to P67, BZ

mA Average value (operating current ×

operating rate)^*1

Average value (operating current ×

“L” level total average output current

“L” level maximum output current

ΣIOLAV

—

150

12

mA

operating rate)^*1

P00 to P07, P10 to P17,

P20 to P23, P30 to P37

IOL

P00 to P07, P10 to P17,

P20 to P23, P30 to P37

“L” level average output current

I^OLAV

—

6

mA

Average value (operating current ×

operating rate)^*1

Power consumption

Operating temperature

Storage temperature

PD

T^A

—

500

+85

mW

°C

–40

–55

T^stg

+150

°C

*1: The total average output current is defined as the average current that flows through all of the relevant pins in

a 100 ms period. The output peak current is defined as the peak value of any one of the relevant pins. The

average output current is defined as the average current that flows through any one of the relevant pins in a

100 ms period.

*2: Use AV^CCand VCC set at the same voltage.

Take care so that AV^CCdoes not exceed VCC, such as when power is turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

26

DS07-12522-4E

MB89140 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

2.7*

6.0*

V

Normal operation assurance range*

V^CC

In watch mode or subclock operation (Only for

the MB89P147, the minimum value is 2.7 V.)

2.2

6.0

AVCC

Power supply voltage

1.5

6.0

V

Retains the RAM state in stop mode

VFDP

V^CC– 40 VCC + 0.3

–40 +85

Operating temperature T^A

°C

* : These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter

Electrical Characteristics”.

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

6

5

Operation assurance range

4

3

2

1

2

3

4

5

6

7

8

Main clock operating frequency (at an instruction cycle of 4/F^CH) (MHz)

2.0

0.8

0.5

Minimum execution time (instruction cycle) (µs)

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F^CH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

DS07-12522-4E

27

MB89140 Series

3. DC Characteristics

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17,

“H” level input

voltage

P30 to P37,

VCC + 0.3

Hysteresis input

V^IHS

0.7 V^CC

—

V

P70, P71,

X0, X1, RST, MODA

—

P00 to P07,

P10 to P17,

“L” level input

voltage

P30 to P37,

V^SS– 0.3

Hysteresis input

V^ILS

—

0.2 VCC

V

P70, P71,

X0, X1, RST, MODA

P00 to P07,

P10 to P17,

P20 to P23,

P30, P32 to P37

V^OH1

I^OH= –2.0 mA

2.4

—

“H” level output

voltage

P40 to P47,

P50 to P57

V^OH2

V^OH3

I^OH= –10 mA

IOH = –18 mA

3.0

—

V

P60 to P67, BZ

P00 to P07,

P10 to P17,

P20 to P23,

P30, P32 to P37

V^OL1

I^OL= 1.8 mA

IOL = 4.0 mA

—

0.4

0.6

V

“L” level output

voltage

V^OL2

RST

P00 to P07,

P10 to P17,

P30 to P37,

P70, P71,

MODA

Without pull-up

resistor for P14

to P17 and P32

to P37

0.45 V < VI < VCC

I^LI1

—

±5

µA

Input leakage

current

With pull-up

resistor

P14 to P17,

P32 to P37

ILI2

V^I= 0.0 V

–200

—

–100

—

–50

–10

–20

µA

P40 to P47,

P50 to P57

V^I= VFDP =

V^CC– 40 V

I^LO1

I^LO2

Output leakage

current

V^I= VFDP =

V^CC– 40 V

P60 to P67, BZ

—

RST

P14 to P17,

P32 to P37

With pull-up

resistor

Pull-up

resistance

R^PULU

VI = 0.0 V

25

50

100

150

kΩ

P40 to P47,

P50 to P57,

P60 to P67

With pull-down

resistor optional

Pull-down

resistance

R^PULD

V^OH= 5.0 V

100

(Continued)

28

DS07-12522-4E

MB89140 Series

(Continued)

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

FCH = 8 MHz

V^CC= 5.0 V

t^inst*2= 0.5 µs

Output open

ICC1

—

9

15

mA

FCH = 8 MHz

V^CC= 3.2 V

t^inst*2= 8.0 µs

Output open

—

1.5

2.5

2

mA

I^CC2

5.0

mA MB89P147

FCH = 8 MHz

V^CC= 5.0 V

I^CCS1

I^CCS2

I^CCL

—

3

1

7

mA

t^inst*2= 0.5 µs

FCH = 8 MHz

V^CC= 3.2 V

t^inst*2= 8.0 µs

1.5

VCC

Subclock mode

F^CL= 32.768 kHz

V^CC= 3.0 V

—

50

1

150

3

µA

Power supply

current^*1

mA MB89P147

Subclock sleep mode

I^CCLS

—

25

50

µA

FCL = 32.768 kHz

V^CC= 3.0 V

Watch mode

F^CL= 32.768 kHz

V^CC= 3.0 V

I^CCT

I^CCH

I^A

—

3

15

10

4

Subclock stop mode

TA = +25°C

—

µA

when A/D

conversion is

activated

FCH = 8 MHz

TA = +25°C

f = 1 MHz

1.5

mA

µA

pF

AVCC

when A/D

conversion is

stopped

IAH

—

1

5

Other than AVCC,

AV^SS, VCC, and

V^SS

Input capacitance CIN

10

—

*1: The power supply current is measured at the external clock.

*2: For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics”.

Note: F^CHindicates the main clock oscillation frequency. When FCH = 8 MHz, the 4/FCH execution time is 0.5 µs, and

the 64/F^CHexecution time is 8 µs.

DS07-12522-4E

29

MB89140 Series

4. AC Characteristics

(1) Reset Timing

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

48 t^XCYL

30

Typ.

—

Max.

—

RST “L” pulse width

RST noise limit width

tZLZH

tZLNC

ns

—

50

80

Note: TXCYL is the oscillation cycle (1/FCH) to input to the X0 pin.

tZLZH

tZLNC

RST

0.2 VCC

(2) Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Condition

Unit

Remarks

Parameter

Min.

—

Max.

50

Power supply rising time

Power supply cut-off time

t^R

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

1

—

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

t^R

tOFF

2.0 V

0.2 V

VCC

30

DS07-12522-4E

MB89140 Series

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Typ.

—

Symbol

Condition

Unit

Remarks

Parameter

Clock frequency

Clock cycle time

Min.

2

Max.

8

F^CH

X0, X1

MHz

kHz

ns

F^CL

X0A, X1A

X0, X1

—

32.768

—

t^XCYL

t^LXCYL

125

—

500

—

X0A, X1A

30.5

µs

—

PWH

PWL

X0

30

—

15.2

—

10

ns

µs

ns

Input clock pulse width

External clock

P^WHL

PWLL

X0A

Input clock rising/falling

time

tCR

tCF

X0, X0A

X0 and X1 Timing and Conditions

tXCYL

PWH

PWL

tCF

tCR

0.8 VCC

X0

0.2 VCC

Main Clock Conditions

When a crystal or ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

C0

C1

DS07-12522-4E

31

MB89140 Series

X0A and X1A Timing and Conditions

tLXCYL

PWHL

PWLL

tCF

tCR

0.8 VCC

X0A

0.2 VCC

Subclock Conditions

MB89PV140

When a crystal or ceramic resonator is used

When an external clock is used

RF = approx. 2 MΩ

X0A

X1A

X0A

C0

X1A

C1

Open

R^D

Mask ROM products and MB89P147

When a crystal or ceramic resonator is used

When an external clock is used

X0A

X1A

X0A

X1A

Open

RF

RD

C0

C1

Note: The subclock oscillator feedback resistor is connected externally in dual-clock mask ROM products and in the

MB89P147. (The subclock oscillator feedback resistor is connected internally in the MB89PV140-102.)

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

(4/F^CH) tinst = 0.5 µs when operating at

F^CH= 8 MHz

4/FCH, 8/FCH, 16/FCH, 64/FCH µs

Instruction cycle

(minimum execution time)

t^inst

t^inst= 61.036 µs when operating at

F^CL= 32.768 kHz

2/F^CL

µs

32

DS07-12522-4E

MB89140 Series

(5) Serial I/O Timing

Parameter

(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

SCK

Condition

Unit Remarks

Min.

2 t^inst*

–200

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

µs

ns

µs

ns

µs

SCK, SO

SI, SCK

SCK, SI

SCK

200

—

Internal shift

clock mode

Valid SI → SCK ↑

1/2 tinst*

1 t^inst*

1 tinst*

0

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

—

SCK

—

External shift

clock mode

SCK, SO

SI, SCK

SCK, SI

200

—

Valid SI → SCK ↑

1/2 tinst*

SCK ↑ → valid SI hold time

—

* : For information on tinst, see “(4) Instruction Cycle”.

Internal Shift Clock Mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.3 VCC

SI

0.3 VCC

External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK

0.2 VCC

tSLOV

2.4 V

SO

SI

0.8 V

tIVSH

tSHIX

0.8 VCC

0.3 VCC

0.8 VCC

0.3 VCC

DS07-12522-4E

33

MB89140 Series

(6) Peripheral Input Timing

(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

Parameter

Min.

Max.

TRG, DTTI,

ADST, EC,

INT0, INT1

Peripheral input “H” pulse width 1

t^ILIH1

—

2 t^inst*

—

µs

TRG, DTTI,

ADST, EC,

INT0, INT1

Peripheral input “L” pulse width 1

t^IHIL1

—

2 t^inst*

—

µs

* : For information on tinst, see “(4) Instruction Cycle”.

(7) Peripheral Input Noise Limit Width

(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

t^IHNC1

Condition

Unit

Remarks

Parameter

Min.

7

Typ.

15

Max.

30

MB89P147/PV140

ns

Peripheral input “H”

level noise limit width 1

All inputs except

INT1 and INT0

Except MB89P147/PV140

MB89P147/PV140

15

7

30

60

15

30

Peripheral input “L” level

noise limit width 1

All inputs except

INT1 and INT0

t^ILNC1

Except MB89P147/PV140

MB89P147/PV140

15

30

50

30

50

30

60

50

100

250

100

250

Interrupt “H” level noise

limit width 2

t^IHNC2

INT1, INT0

Except MB89P147/PV140

MB89P147/PV140

100

50

Interrupt “L” level noise

limit width 2

t^ILNC2

Except MB89P147/PV140

100

tIHIL1

tILIH1

TRG

DTTI

ADST

INT0, INT1

EC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

tILNC1

tILNC2

tIHNC1

tIHNC2

P00 to P07, P01 to P17

0.8 VCC

0.2 VCC

0.8 VCC

P30 to P37, P70, P71

TRG, SCK, SI,

EC, DTTI, ADST

INT1, INT0

0.2 VCC

34

DS07-12522-4E

MB89140 Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = 5.0 V+10%, FCH = 8 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Remarks

Parameter

Resolution

Unit

Min.

—

Typ.

—

Max.

10

—

bit

Total error

—

3.0

2.0

1.5

LSB

—

AVCC = VCC

= 5.0 V

Linearity error

—

Differential linearity error

—

AN0 to

ANB

AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB

Zero transition voltage

V^OT

—

V

AN0 to

ANB

Full-scale transition

voltage

AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC + 0.5 LSB

V^FST

—

V

Interchannel disparity

—

4

LSB

tinst*

—

At 8-MHz

oscillation

A/D mode conversion

time

33

—

AN0 to AVCC = VCC

Analog port input current IAIN

Analog input voltage

—

10

µA

ANB

= 5.0 V

AN0 to

ANB

—

0.0

AVCC

V

* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics”.

Notes: • The smaller |AV^CC- AVss|, the greater the error would become relatively.

• The output impedance of the external circuit connected to an analog input block should be no more than

several kΩ. If the output impedance is too high, the analog voltage sampling time might be insufficient.

Sample & hold circuit

AN

C

60 pF

Comparator

R

Analog channel

selector

Close for approx. 15 to 72 instruction cycles after

activating A/D conversion. (The close time depends

on the register settings.)

DS07-12522-4E

35

MB89140 Series

(1) A/D Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

• Linearity error

The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics

• Differential linearity error

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error

The difference between theoretical and actual values

This error is caused by the zero transition error, full-scale transition error, linearity error, quantization error and

noise.

Theoretical I/O characteristics

V^FST

Total error

3FF

3FE

3FD

3FF

3FE

3FD

Actual conversion

value

1.5 LSB

{1 LSB × N + 0.5 LSB}

004

003

002

001

004

003

002

001

VNT

Actual conversion

value

VOT

1 LSB

Theoretical value

0.5 LSB

AVcc

AVSS

AVcc

AV^SS

Analog input

V^FST– VOT

1022

VNT – {1 LSB × N + 0.5 LSB}

Total error for digital output N =

1 LSB =

(V)

1 LSB

(Continued)

36

DS07-12522-4E

MB89140 Series

(Continued)

004

Zero transition error

Full-scale transition error

Theoretical value

3FF

3FE

3FD

3FC

Actual conversion

value

003

002

001

Actual conversion

value

V^FST

(measured value)

Actual conversion

value

Actual conversion

value

VOT (measured value)

Analog input

AVcc

AVSS

AVcc

AV^SS

Analog input

Linearity error

Differential linearity error

3FF

3FE

3FD

N + 1

Theoretical value

Actual conversion

value

{1 LSB × N + VOT}

N

Actual conversion

value

V(N + 1) T

V^FST

(measured

value)

004

003

002

001

VNT

N – 1

N – 2

VNT

Actual conversion

value

Actual conversion

value

Theoretical value

VOT (measured value)

AV^cc

AVcc

AV^SS

Analog input

V(N + 1) T – VNT

VNT – {1 LSB × N + VOT}

Linearity error for digital output N =

Differential linearity error for digital output N =

– 1

1 LSB

DS07-12522-4E

37

MB89140 Series

■ EXAMPLE CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

V^OLvs. IOL

V^CC– VOH vs. IOH

V^CC– VOH (V)

1.0

V^OL(V)

0.5

V^CC= 2.5 V

TA = +25°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 2.5 V

V^CC= 3.0 V

V^CC= 4.0 V

VCC = 5.0 V

VCC = 6.0 V

0.4

0.3

0.2

0.1

0.0

VCC = 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

0.0

–0.5 –1.0 –1.5 –2.0 –2.5 –3.0

I^OH(mA)

0

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

(3) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)

CMOS hysteresis input

V^IN(V)

5.0

TA = +25°C

4.5

4.0

3.5

V^IHS

3.0

2.5

VILS

2.0

1.5

1.0

0.5

0.0

0

1

2

3

4

5

6

7

V^CC(V)

VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level

V^ILS: Threshold when input voltage in hysteresis characteristics is set to “L” level

38

DS07-12522-4E

MB89140 Series

(4) Power Supply Current (External Clock)

I^CC1vs. VCC, ICC2 vs. VCC

ICC (mA)

ICCS1 vs. VCC, ICCS2 vs. VCC

ICCS (mA)

4.0

FCH = 8 MHz

T^A= +25°C

16

Divide by 4 (ICCS1

)

T^A= +25°C

Divide by 4 (ICC1

)

14

12

10

8

3.0

2.0

1.0

Divide by 64 (ICCS2

)

6

4

Divide by 64 (ICC2

)

2

0

2.0

3.0

4.0

5.0

6.0

7.0

V^CC(V)

2.0

3.0

4.0

5.0

6.0

7.0

V^CC(V)

I^CCLvs. VCC

I^CCLSvs. VCC

ICCL (µA)

ICCLS (µA)

50

200

180

160

140

120

100

80

TA = +25°C

40

30

20

10

60

40

20

0

2.0

3.0

4.0

5.0

6.0

7.0

2.0

3.0

4.0

5.0

6.0

7.0

V^CC(V)

(Continued)

DS07-12522-4E

39

MB89140 Series

(Continued)

I^CCTvs. VCC

I^CCHvs. VCC

I^CCT(µA)

I^CCH(µA)

1.8

18

16

14

TA = +25°C

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

12

10

8

6

4

2

0

2.0

3.0

4.0

5.0

6.0

7.0

2.0

3.0

4.0

5.0

6.0

7.0

V^CC(V)

(5) Pull-up Resistance

RPULL vs. VCC

R^PULL(kΩ)

1,000

500

100

50

TA = +85°C

T^A= +25°C

T^A= –40°C

10

1

2

3

4

5

6

7

V^CC(V)

40

DS07-12522-4E

MB89140 Series

■ MASK OPTIONS

MB89145V1

MB89146V1

MB89145V2

MB89146V2

MB89PV140 MB89PV140

-101 -102

MB89P147V1 MB89P147V2

No.

Power-on reset

With power-on reset

Without power-on reset

Reset pin output

With reset output

Without reset output

Clock mode selection

Single-clock mode

Dual-clock mode

Pull-up resistors

P14 to P17

Fixed to with power-on reset

Specify when ordering masking

Set with EPROM programmer

1

2

3

4

Fixed to with power-on reset

Set with EPROM programmer

Single clock

Dual clock

Specify when ordering masking

(specify by pin)

Set with EPROM programmer

(specify by pin)

Fixed to without pull-up resistor

P32 to P37

Pull-down resistors

P47 to P40

All pins with

Without pull-

All pins with

Without pull-

pull-down

5

down resistor

resistor

down resistor

resistor

P57 to P50

P67 to P60

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89145V1P-SH

MB89145V2P-SH

MB89146V1P-SH

MB89146V2P-SH

MB89P147-V1P-SH

MB89P147-V2P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89145V1PF

MB89145V2PF

MB89146V1PF

MB89146V2PF

MB89P147-V1PF

MB89P147-V2PF

64-pin Plastic QFP

(FPT-64P-M06)

MB89PV140-101C-ES-SH

MB89PV140-102C-ES-SH

64-pin Ceramic MDIP

(MDP-64C-P02)

MB89PV140-101CF-ES

MB89PV140-102CF-ES

64-pin Ceramic MQFP

(MQP-64C-P01)

DS07-12522-4E

41

MB89140 Series

■ PACKAGE DIMENSIONS

64-pin plastic SH-DIP

Lead pitch

1.778mm(70mil)

17 × 58 mm

Package width ×

package length

Sealing method

Mounting height

Plastic mold

5.65 mm MAX

(DIP-64P-M01)

64-pin plastic SH-DIP

(DIP-64P-M01)

Note: Pins width and pins thickness include plating thickness.

58.00 ⁺^–0⁰^.^.⁵²⁵²2.283 ^–⁺^.^.⁰⁰²⁰²⁹

INDEX-1

17.00±0.25

(.669±.010)

INDEX-2

4.95 –⁺0⁰.^.2⁷0⁰

.195 ⁺^–.^.⁰⁰⁰²⁸⁸

0.70 –⁺0⁰.^.1⁵9⁰

.028 ⁺^–.^.⁰⁰⁰²⁷⁰

0.27±0.10

(.011±.004)

3.30 ⁺^–0⁰^.^.³²⁰⁰

.130 –⁺.^.0⁰1⁰2⁸

19.05(.750)

1.378 ⁺–0⁰.^.2⁴0⁰

.0543 ⁺^–.^.⁰⁰⁰¹⁸⁶

0.47±0.10

(.019±.004)

1.00 ⁺^–0^0.50

1.778(.0700)

0~15

M

0.25(.010)

.039 –⁺.^.0⁰²⁰

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2001-2008 FUJITSU MICROELECTRONICS LIMITED D64001S-c-4-6

Please check the latest package dimensions at the following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

DS07-12522-4E

42

MB89140 Series

64-pin plastic QFP

Lead pitch

1.00 mm

Package width ×

package length

14 × 20 mm

Gullwing

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

P-QFP64-14×20-1.00

Code

(Reference)

(FPT-64P-M06)

64-pin plastic QFP

(FPT-64P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

24.70±0.40(.972±.016)

*20.00±0.20(.787±.008)

0.17±0.06

(.007±.002)

51

33

52

32

18.70±0.40

(.736±.016)

Details of "A" part

*14.00±0.20

(.551±.008)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

INDEX

64

20

0~8°

1

19

1.00(.039)

0.42±0.08

(.017±.003)

0.25 ⁺^–0⁰^.^.²¹⁰⁵

M

0.20(.008)

.010 ⁺^–.^.⁰⁰⁰⁰⁸⁶

1.20±0.20

(.047±.008)

(Stand off)

"A"

0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6

Please check the latest package dimensions at the following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

DS07-12522-4E

43

MB89140 Series

64-pin ceramic MDIP

Lead pitch

1.778mm (70mil)

19.05mm (750mil)

Ceramic

Row spacing

Motherboard

material

Mounted

packing material

Plastic

(MDP-64C-P02)

64-pin ceramic MDIP

(MDP-64C-P02)

0°~9°

56.90±0.64

(2.240±.025)

15.24(.600)

TYP

18.75±0.30

(.738±.012)

19.05±0.30

(.750±.012)

INDEX AREA

2.54±0.25

(.100±.010)

0.25±0.05

(.010±.002)

33.02(1.300)REF

1.27±0.25

(.050±.010)

10.16(.400)MAX

0.46⁺^–0⁰^.^.⁰¹⁸³

0.90±0.13

(.035±.005)

3.43±0.38

(.135±.015)

1.778±0.25

(.070±.010)

.018⁺^–.^.⁰⁰⁰⁰³⁵

55.12(2.170)REF

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

1994-2008 FUJITSU MICROELECTRONICS LIMITED M64002SC-1-5

Please check the latest package dimensions at the following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

MB89140 Series

(Continued)

64-pin ceramic MQFP

Lead pitch

1.00 mm

Straight

Ceramic

Lead shape

Motherboard

material

Mounted package

material

Plastic

(MQP-64C-P01)

64-pin ceramic MQFP

(MQP-64C-P01)

18.70(.736)TYP

16.30±0.33

(.642±.013)

15.58±0.20

(.613±.008)

12.00(.472)TYP

INDEX AREA

1.00±0.25

(.039±.010)

1.20 Ð⁺⁰0^..⁴2⁰0

1.00±0.25

(.039±.010)

.047 Ð^+..⁰0¹0⁶8

1.27±0.13

(.050±.005)

18.12±0.20

(.713±.008)

22.30±0.33

(.878±.013)

12.02(.473)

TYP

18.00(.709)

10.16(.400)

14.22(.560)

TYP

0.30(.012)

24.70(.972)

TYP

0.40±0.10

(.016±.004)

1.27±0.13

(.050±.005)

0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.40±0.10

(.016±.004)

1.20 Ð⁺⁰0^..⁴2⁰0

.047 ⁺^Ð..⁰⁰¹⁰⁶⁸

10.82(.426)

MAX

0.15±0.05

0.50(.020)TYP

(.006±.002)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

1994-2008 FUJITSU MICROELECTRONICS LIMITED M64004SC-1-4

Please check the latest package dimensions at the following URL.

http://edevice.fujitsu.com/package/en-search/

DS07-12522-4E

45

MB89140 Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

Change Results

Changed the name of a timer.

Clock timer → Watch timer

■ PRODUCT LINEUP

3

■ PROGRAMMING TO THE EPROM Deleted the “6. EPROM Programmer Socket Adapter”.

ON THE MB89P147

16

17

■ PROGRAMMING TO THE EPROM Deleted the “2. Programming Socket Adapter”.

WITH PIGGYBACK/EVALUATION

DEVICE

■ ELECTRICAL CHARACTERISTICS Changed the unit of “Zero transition voltage” and “Full-scale

35

A/D Converter Electrical

Characteristics

transition voltage”.

mV → V

■ ORDERING INFORMATION

Changed the ordering information.

MB89P147V1P-SH → MB89P147-V1P-SH

MB89P147V2P-SH → MB89P147-V2P-SH

MB89P147V1PF → MB89P147-V1PF

41

MB89P147V2PF → MB89P147-V2PF

MB89PV140C-101-ES-SH → MB89PV140-101C-ES-SH

MB89PV140C-102-ES-SH → MB89PV140-102C-ES-SH

MB89PV140CF-101-ES → MB89PV140-101CF-ES

MB89PV140CF-102-ES → MB89PV140-102CF-ES

The vertical lines marked in the left side of the page show the changes.

46

DS07-12522-4E

MB89140 Series

MEMO

DS07-12522-4E

47

MB89140 Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB89145V2P-SH
厂家：	CYPRESS
描述：	Microcontroller, 8-Bit, MROM, F2MC-8L CPU, 8MHz, CMOS, PDIP64, 17 X 58 MM, 5.65 MM HEIGHT, 1.778 MM PITCH, PLASTIC, SHDIP-64 时钟微控制器光电二极管外围集成电路
文件：	总49页 (文件大小：1439K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89145V2P-SH [CYPRESS]

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