MB90351ASPMC_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13737-6E

16-bit Microcontroller

CMOS

F²MC-16LX MB90350 Series

MB90F351(S), MB90F352(S),MB90F351A(S), MB90F351TA(S), MB90F352A(S), MB90F352TA(S),

MB90F356A(S), MB90F356TA(S), MB90F357A(S), MB90F357TA(S),MB90351A(S), MB90351TA(S),

MB90352A(S), MB90352TA(S),MB90356A(S), MB90356TA(S), MB90357A(S), MB90357TA(S),

MB90V340A-101/102/103/104

■ DESCRIPTION

The MB90350-series with 1 channel FULL-CAN interface and Flash ROM is especially designed for automotive

and industrial applications. Its main feature is the on-board CAN interface, which conforms to V2.0 Part A and

Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full

CAN approach. With the new 0.35μm CMOS technology, FUJITSU SEMICONDUCTOR now offers on-chip Flash-

ROM program memory up to 128 Kbytes.

The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a

major advantage in terms of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external

4 MHz clock. Also, the clock monitor function can monitor main clock and sub clock independently.

As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit,

2 separate 16-bit freerun timers, 2-channel UART and 15-channel 8/10-bit A/D converter.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

For the information for microcontroller supports, see the following web site.

This web site includes the "Customer Design Review Supplement" which provides the latest cautions on

system development and the minimal requirements to be checked to prevent problems before the system

development.

http://edevice.fujitsu.com/micom/en-support/

2010.9

MB90350 Series

■ FEATURES

• Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and

multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).

• Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without

S-suffix only)

• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-

plied PLL clock).

• Built-in clock modulation circuit

• 16 Mbytes CPU memory space

• 24-bit internal addressing

• Clock monitor function (MB90x356x and MB90x357x only)

• Main clock or sub clock is monitored independently.

• Internal CR oscillation clock (100 kHz typical) can be used as sub clock.

• Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions with sign and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

• Increased processing speed

• 4-byte instruction queue

• Powerful interrupt function

• Powerful 8-level, 34-condition interrupt feature

• Up to 8 channels external interrupts are supported.

• Automatic data transfer function independent of CPU

• Extended intelligent I/O service function (EI²OS) : up to 16 channels

• DMA : up to 16 channels

• Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Main timer mode (a timebase timer mode switched from the main clock mode)

• PLL timer mode (a timebase timer mode switched from the PLL clock mode)

• Watch mode (a mode that operates sub clock and watch timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU intermittent operation mode

• Process

• CMOS technology

(Continued)

2

DS07-13737-6E

MB90350 Series

• I/O port

• General-purpose input/output port (CMOS output)

- 49 ports (devices without S-suffix : devices that correspond to sub clock)

- 51 ports (devices with S-suffix : devices that do not correspond to sub clock)

• Sub clock pin (X0A, X1A)

• Yes (using the external oscillation) : devices without S-suffix

• No (using the sub clock mode at internal CR oscillation) : devices with S-suffix

• Timer

• Timebase timer, watch timer, watchdog timer : 1 channel

• 8/16-bit PPG timer : 8-bit × 10 channels or 16-bit × 6 channels

• 16-bit reload timer : 4 channels

• 16- bit input/output timer

- 16-bit freerun timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)

- 16- bit input capture: (ICU) : 6 channels

- 16-bit output compare : (OCU) : 4 channels

• FULL-CAN interface : 1 channel

• Compliant with Ver2.0 part A and Ver2.0 part B CAN specifications

• Flexible message buffering (mailbox and FIFO buffering can be mixed)

• CAN wake-up function

• UART (LIN/SCI) : 2 channels

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available.

• I²C interface : 1 channel

• Up to 400 Kbit/s transfer rate

• DTP/External interrupt : 8 channels, CAN wakeup : 1 channel

• Module for activation of extended intelligent I/O service (EI²OS), DMA, and generation of external interrupt by

external input.

• Delay interrupt generator module

• Generates interrupt request for task switching.

• 8/10-bit A/D converter : 15 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time : 3 μs (at 24-MHz machine clock, including sampling time)

• Program patch function

• Address matching detection for 6 address pointers.

• Capable of changing input voltage level for port

• Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)

• TTL level (corresponds to external bus pins only, initial level of these pins is TTL in external bus mode)

• Low voltage/CPU operation detection reset (devices with T-suffix)

• Detects low voltage (4.0 V 0.3 V) and resets automatically

• Resets automatically when program is runaway and counter is not cleared within interval time

(approx. 262 ms : external 4 MHz)

(Continued)

DS07-13737-6E

3

MB90350 Series

(Continued)

• Dual operation flash memory (only flash memory devices with A-suffix)

• Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.

• Models that support + 125 °C

• Devices without A-suffix (excluding evaluation device) : The maximum operating frequency is 16 MHz

(at T^A= +125 °C) .

• Devices with A-suffix (excluding evaluation device)

: The maximum operating frequency is 24 MHz

(at T^A= +125 °C) .

• Flash security function

• Protects the content of Flash memory (MB90F352x and MB90F357x only)

• External bus interface

• 4 Mbytes external memory space

4

DS07-13737-6E

MB90350 Series

■ PRODUCT LINEUP 1

Part Number

MB90F351,

MB90F352

MB90F351S, MB90F351A, MB90F351TA, MB90F351AS,

MB90F351TAS,

MB90F352TAS

MB90F352S

MB90F352A MB90F352TA MB90F352AS

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

Flash memory Dual operation flash memory

System clock

ROM

RAM

64Kbytes : MB90F351(S) 64Kbytes : MB90F351A(S), MB90F351TA(S)

128Kbytes : MB90F352(S) 128Kbytes : MB90F352A(S), MB90F352TA(S)

4 Kbytes

Emulator-specific

power supply*

⎯

Sub clock pin

(X0A, X1A)

(Max 100 kHz)

Yes

No

Yes

No

Clock monitor

function

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter/Flash programming

4.5 V to 5.5 V : at using external bus

Operating

voltage range

Operating

temperature range

−40 °C to +105 °C (+125 °C

up to 16 MHz machine clock)

−40 °C to +125 °C

Package

LQFP-64

2 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

15 channels

10-bit or 8-bit resolution

Conversion time : Min 3 μs includes sample time (per one channel)

16-bit Reload Timer Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = Machine clock frequency)

(4 channels)

Supports External Event Count function.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = Machine clock frequency)

4 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

(Continued)

DS07-13737-6E

5

MB90350 Series

(Continued)

Part Number

MB90F351,

MB90F351S, MB90F351A, MB90F351TA, MB90F351AS,

MB90F351TAS,

MB90F352TAS

MB90F352

Parameter

MB90F352S

MB90F352A MB90F352TA MB90F352AS

6 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an

interrupt.

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 12

8-bit reload registers for L pulse width × 12

8-bit reload registers for H pulse width × 12

8/16-bit

ProgrammablePulse

Generator

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler + 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

1 channel

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

⎯

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O Ports

Bit-wise settable as input/output or peripheral signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Flash Memory

Data retention time : 10 years

Boot block configuration

Erase can be performed on each block.

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash (MB90F352x only)

Corresponding EVA MB90V340A- MB90V340A-

name 102 101

MB90V340A-102

MB90V340A-101

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

6

DS07-13737-6E

MB90350 Series

■ PRODUCT LINEUP 2

Part Number

MB90351A,

MB90352A

MB90351TA, MB90351AS, MB90351TAS, MB90V340A- MB90V340A-

MB90352TA

MB90352AS MB90352TAS

101

102

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

System clock

MASK ROM

ROM

RAM

64Kbytes : MB90351A(S), MB90351TA(S)

128Kbytes : MB90352A(S), MB90352TA(S)

External

4 Kbytes

30 Kbytes

Yes

Emulator-specific

power supply*

⎯

Sub clock pin

(X0A, X1A)

Yes

No

Yes

(Max 100 kHz)

Clock monitor

function

No

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

No

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter

4.5 V to 5.5 V : at using external bus

Operating

voltage range

5 V 10%

Operating

temperature range

−40 °C to +125 °C

⎯

Package

LQFP-64

2 channels

PGA-299

5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

2 channels

15 channels

24 channels

10-bit or 8-bit resolution

Conversion time : Min 3 μs includes sample time (per one channel)

16-bit Reload Timer Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = Machine clock frequency)

(4 channels)

Supports External Event Count function.

I/O Timer 0 corresponds to

ICU 0/1/2/3, OCU 0/1/2/3.

I/O Timer 1 corresponds to

ICU 4/5/6/7, OCU 4/5/6/7.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to

ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = Machine clock frequency)

(Continued)

DS07-13737-6E

7

MB90350 Series

(Continued)

Part Number

MB90351A,

MB90351TA, MB90351AS, MB90351TAS, MB90V340A- MB90V340A-

MB90352TA MB90352AS MB90352TAS 101 102

MB90352A

Parameter

4 channels

8 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches output compare registers.

A pair of compare registers can be used to generate an output signal.

6 channels

8 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an

interrupt.

8 channels (16-bit)/

16 channels (8-bit)

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 16

8-bit reload counters × 12

8-bit reload registers for

8-bit reload registers for L pulse width × 12

L pulse width × 16

8-bit reload registers for H pulse width × 12

8-bit reload registers for

8/16-bit

ProgrammablePulse

Generator

H pulse width × 16

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler + 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

1 channel

3 channels

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

16 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

⎯

2 channels

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O Ports

Bit-wise settable as input/output or peripheral signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Flash Memory

⎯

Corresponding EVA

name

MB90V340A-102

MB90V340A-101

⎯

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

8

DS07-13737-6E

MB90350 Series

■ PRODUCT LINEUP 3

Part Number

MB90F356A,

MB90F357A

MB90F356TA,

MB90F357TA

MB90F356AS,

MB90F357AS

MB90F356TAS,

MB90F357TAS

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

System clock

Dual operation flash memory

ROM

RAM

64Kbytes : MB90F356A(S), MB90F356TA(S)

128Kbytes : MB90F357A(S), MB90F357TA(S)

4 Kbytes

Emulator-specific

power supply*

⎯

No

Sub clock pin

(X0A, X1A)

Yes

(internal CR oscillation can be used as

sub clock)

Clock monitor

function

Yes

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

3.5 V to 5.5 V : at normal operating (not using A/D converter)

3.5 V to 5.5 V : at using A/D converter/Flash programming

3.5 V to 5.5 V : at using external bus

Operating

voltage range

Operating

temperature range

−40 °C to +125 °C

Package

LQFP-64

2 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

15 channels

10-bit or 8-bit resolution

Conversion time : Min 3 μs includes sample time (per one channel)

16-bit Reload Timer Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = Machine clock frequency)

(4 channels)

Supports External Event Count function.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = Machine clock frequency)

4 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

(Continued)

DS07-13737-6E

9

MB90350 Series

(Continued)

Part Number

MB90F356A,

MB90F357A

MB90F356TA,

MB90F357TA

MB90F356AS,

MB90F357AS

MB90F356TAS,

MB90F357TAS

Parameter

6 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an

interrupt.

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 12

8-bit reload registers for L pulse width × 12

8-bit reload registers for H pulse width × 12

8/16-bit

ProgrammablePulse

Generator

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler + 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

1 channel

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

⎯

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O Ports

Bit-wise settable as input/output or peripheral module signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Flash Memory

Data retention time : 10 years

Boot block configuration

Erase can be performed on each block.

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash (MB90F357x only)

Corresponding EVA

name

MB90V340A-104

MB90V340A-103

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

10

DS07-13737-6E

MB90350 Series

■ PRODUCT LINEUP 4

Part Number

MB90356A,

MB90357A

MB90356TA, MB90356AS, MB90356TAS, MB90V340A- MB90V340A-

MB90357TA

MB90357AS MB90357TAS

103

104

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

System clock

MASK ROM

ROM

RAM

64Kbytes : MB90356A(S), MB90356TA(S)

128Kbytes : MB90357A(S), MB90357TA(S)

External

4 Kbytes

30 Kbytes

Yes

Emulator-specific

power supply*

⎯

No

(internal CR

oscillation

can be used

as sub clock)

Sub clock pin

(X0A, X1A)

Yes

(internal CR oscillation can

be used as sub clock)

Yes

Clock monitor

function

Yes

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

No

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter

4.5 V to 5.5 V : at using external bus

Operating

voltage range

5 V 10%

Operating

temperature range

−40 °C to +125 °C

⎯

Package

LQFP-64

2 channels

PGA-299

5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

I²C (400 Kbps)

A/D Converter

1 channel

2 channels

15 channels

24 channels

10-bit or 8-bit resolution

Conversion time : Min 3 μs includes sample time (per one channel)

16-bit Reload Timer Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = Machine clock frequency)

(4 channels)

Supports External Event Count function.

I/O Timer 0 corresponds to

ICU 0/1/2/3, OCU 0/1/2/3.

I/O Timer 1 corresponds to

ICU 4/5/6/7, OCU 4/5/6/7.

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to

ICU 4/5/6/7, OCU 4/5/6/7.

16-bit I/O Timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = Machine clock frequency)

(Continued)

DS07-13737-6E

11

MB90350 Series

(Continued)

Part Number

MB90356A,

MB90356TA, MB90356AS, MB90356TAS, MB90V340A- MB90V340A-

MB90357TA MB90357AS MB90357TAS 103 104

MB90357A

Parameter

4 channels

8 channels

16-bit Output

Compare

Signals an interrupt when 16-bit I/O Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

6 channels

8 channels

16-bit Input Capture

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an

interrupt.

8 channels (16-bit)/16 chan-

nels (8-bit)

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters × 16

8-bit reload counters × 12

8-bit reload registers for

8-bit reload registers for L pulse width × 12

L pulse width × 16

8-bit reload registers for H pulse width × 12

8-bit reload registers for

8/16-bit

ProgrammablePulse

Generator

H pulse width × 16

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler + 8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 μs@fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

1 channel

3 channels

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

16 channels

External Interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.

⎯

2 channels

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O Ports

Bit-wise settable as input/output or peripheral module signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Flash Memory

⎯

Corresponding EVA

name

MB90V340A-104

MB90V340A-103

⎯

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

12

DS07-13737-6E

MB90350 Series

■ PACKAGES AND PRODUCT CORRESPONDENCE

MB90F351A (S) , MB90F351TA (S)

MB90F352A (S) , MB90F352TA (S)

MB90F356A (S) , MB90F356TA (S)

MB90F357A (S) , MB90F357TA (S)

MB90351A (S) , MB90351TA (S)

MB90352A (S) , MB90352TA (S)

MB90356A (S) , MB90356TA (S)

MB90357A (S) , MB90357TA (S)

MB90V340A

MB90F351

-101

MB90F351S

Package

-102

-103

-104

MB90F352

MB90F352S

PGA-299C-A01

×

FPT-64P-M23

(12 mm , 0.65 mm pitch)

×

FPT-64P-M24

(10 mm , 0.50 mm pitch)

*

* : This device is under development.

: Yes, × : No

Note : Refer to “■ PACKAGE DIMENSIONS” for detail of each package.

DS07-13737-6E

13

MB90350 Series

■ PIN ASSIGNMENTS

• MB90F351(S), MB90F352(S),MB90F351A(S), MB90F351TA(S), MB90F352A(S), MB90F352TA(S),

MB90F356A(S), MB90F356TA(S), MB90F357A(S), MB90F357TA(S),MB90351A(S), MB90351TA(S),

MB90352A(S), MB90352TA(S),MB90356A(S), MB90356TA(S), MB90357A(S), MB90357TA(S),

(TOP VIEW)

(LQFP-64P)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P10/AD08/TIN1

P07/AD07/INT15

Vcc

C

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

P25/A21/IN1/ADTG

P44/SDA0/FRCK0

P45/SCL0/FRCK1

P30/ALE/IN4

P31/RD/IN5

P06/AD06/INT14

P05/AD05/INT13

P04/AD04/INT12

P03/AD03/INT11

P02/AD02/INT10

P01/AD01/INT9

P00/AD00/INT8

MD0

P32/WRL/WR/INT10R

P33/WRH

P34/HRQ/OUT4

P35/HAK/OUT5

P36/RDY/OUT6

P37/CLK/OUT7

P60/AN0

MD1

MD2

P41/X1A*

P40/X0A*

P61/AN1

Vss

AVcc

P43/IN7/TX1

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(FPT-64P-M23, FPT-64P-M24)

* : Devices without S-suffix : X0A, X1A

Devices with S-suffix

: P40, P41

14

DS07-13737-6E

MB90350 Series

■ PIN DESCRIPTION

Pin No.

Pin name

LQFP64*

Circuit

type

Function

46

47

45

X1

X0

Oscillation output pin

Oscillation input pin

Reset input pin

A

E

RST

P62 to P67

AN2 to AN7

General purpose I/O ports

Analog input pins for A/D converter

3 to 8

I

PPG4 (5) , 6 (7) ,

8 (9) , A (B) ,

C (D) , E (F)

Output pins for PPGs

P50

AN8

General purpose I/O port

9

O

I

Analog input pin for A/D converter

Serial data input pin for UART2

General purpose I/O port

SIN2

P51

10

11

12

AN9

Analog input pin for A/D converter

Serial data output pin for UART2

General purpose I/O port

SOT2

P52

AN10

SCK2

P53

I

Analog input pin for A/D converter

Serial clock I/O pin for UART2

General purpose I/O port

AN11

TIN3

I

Analog input pin for A/D converter

Event input pin for reload timer3

General purpose I/O port

P54

13

AN12

TOT3

P55, P56

AN13, AN14

P42

I

Analog input pin for A/D converter

Output pin for reload timer3

General purpose I/O ports

14, 15

Analog input pins for A/D converter

General purpose I/O port

IN6

Data sample input pin for input capture ICU6

RX input pin for CAN1

16

17

F

RX1

INT9R

P43

External interrupt request input pin for INT9

General purpose I/O port

IN7

Data sample input pin for input capture ICU7

TX output pin for CAN1

TX1

General purpose I/O ports

(devices with S-suffix and MB90V340A-101/103)

P40, P41

F

B

19, 20

X0A : Oscillation input pins for sub clock

X1A : Oscillation output pins for sub clock

(devices without S-suffix and MB90V340A-102/104)

X0A, X1A

(Continued)

DS07-13737-6E

15

MB90350 Series

Pin No.

Circuit

LQFP64*

Pin name

Function

type

General purpose I/O ports. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P00 to P07

24 to 31

G

Input/output pins of external address data bus lower 8 bits. This function is

enabled when the external bus is enabled.

AD00 to AD07

INT8 to INT15

P10

External interrupt request input pins for INT8 to INT15

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

32

Input/output pin for external bus address data bus bit 8.

This function is enabled when external bus is enabled.

AD08

TIN1

P11

Event input pin for reload timer1

General purpose I/O port. The register can be set to select whether to use a

pull-up resistor. This function is enabled in single-chip mode.

33

Input/output pin for external bus address data bus bit 9. This function is en-

abled when external bus is enabled.

AD09

TOT1

P12

Output pin for reload timer1

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 10. This function is

enabled when external bus is enabled.

AD10

34

N

SIN3

Serial data input pin for UART3

INT11R

External interrupt request input pin for INT11

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P13

35

36

G

Input/output pin for external bus address data bus bit 11.

This function is enabled when external bus is enabled.

AD11

SOT3

P14

Serial data output pin for UART3

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 12.

This function is enabled when external bus is enabled.

AD12

SCK3

P15

Clock input/output pin for UART3

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

37

38

N

G

Input/output pin for external bus address data bus bit 13.

This function is enabled when external bus is enabled.

AD13

P16

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 14.

This function is enabled when external bus is enabled.

AD14

(Continued)

16

DS07-13737-6E

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P17

39

G

Input/output pin for external bus address data bus bit 15.

This function is enabled when external bus is enabled.

AD15

General purpose I/O ports. The register can be set to select whether to use

a pull-up resistor. In external bus mode, the pins are enabled as a general-

purpose I/O port when the corresponding bit in the external address output

control register (HACR) is 1.

P20 to P23

Output pins for A16 to A19 of the external address data bus.

40 to 43

A16 to A19

G

When the corresponding bit in the external address output control register

(HACR) is 0, the pins are enabled as high address output pins A16 to A19.

PPG9 (8) ,

PPGB (A) ,

PPGD (C) ,

PPGF (E)

Output pins for PPGs

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. In external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output

control register (HACR) is 1.

P24

44

G

Output pin for A20 of the external address data bus. When the correspond-

ing bit in the external address output control register (HACR) is 0, the pin is

enabled as high address output pin A20.

A20

IN0

Data sample input pin for input capture ICU0

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. In external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output

control register (HACR) is 1.

P25

Output pin for A21 of the external address data bus. When the correspond-

ing bit in the external address output control register (HACR) is 0, the pin is

enabled as high address output pin A21.

51

G

A21

IN1

ADTG

P44

Data sample input pin for input capture ICU1

Trigger input pin for A/D converter

General purpose I/O port

52

53

SDA0

FRCK0

P45

H

Serial data I/O pin for I²C 0

Input pin for the 16-bit I/O Timer 0

General purpose I/O port

SCL0

FRCK1

Serial clock I/O pin for I²C 0

Input pin for the 16-bit I/O Timer 1

(Continued)

DS07-13737-6E

17

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P30

54

55

G

Address latch enable output pin. This function is enabled when external bus

is enabled.

ALE

IN4

Data sample input pin for input capture ICU4

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P31

Read strobe output pin for data bus. This function is enabled when external

bus is enabled.

RD

IN5

Data sample input pin for input capture ICU5

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the WR/WRL pin output disabled.

P32

Write strobe output pin for the data bus. This function is enabled when both

the external bus and the WR/WRL pin output are enabled. WRL is used to

write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to

write-strobe 8 bits of the data bus in 8-bit access.

56

G

WR/WRL

INT10R

P33

External interrupt request input pin for INT10

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode, in

external bus 8-bit mode or with the WRH pin output disabled.

57

58

G

Write strobe output pin for the 8 higher bits of the data bus. This function is

enabled when the external bus is enabled, when the external bus 16-bit

mode is selected, and when the WRH output pin is enabled.

WRH

P34

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the hold function disabled.

Hold request input pin. This function is enabled when both the external bus

and the hold function are enabled.

HRQ

OUT4

Waveform output pin for output compare OCU4

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the hold function disabled.

P35

59

60

G

Hold acknowledge output pin. This function is enabled when both the

external bus and the hold function are enabled.

HAK

OUT5

Waveform output pin for output compare OCU5

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the external ready function disabled.

P36

Ready input pin. This function is enabled when both the external bus and

the external ready function are enabled.

RDY

OUT6

Waveform output pin for output compare OCU6

(Continued)

18

DS07-13737-6E

MB90350 Series

(Continued)

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the CLK output disabled.

P37

CLK

61

G

CLK output pin. This function is enabled when both the external bus and

CLK output are enabled.

OUT7

P60, P61

AN0, AN1

AV^CC

Waveform output pin for output compare OCU7

General purpose I/O ports

62, 63

64

I

Analog input pins for A/D converter

VCC power input pin for analog circuits

K

Reference voltage input for the A/D converter. This power supply must be

turned on or off while a voltage higher than or equal to AVRH is applied to

AVCC.

2

AVRH

L

1

AV^SS

MD1, MD0

MD2

K

C

VSS power input pin for analog circuits

Input pins for specifying the operating mode

Input pin for specifying the operating mode

Power (3.5 V to 5.5 V) input pin

22, 23

21

D

49

V^CC

⎯

18, 48

VSS

Power (0 V) input pins

This is the power supply stabilization capacitor pin. It should be connected

to a higher than or equal to 0.1 μF ceramic capacitor.

50

C

K

* : FPT-64P-M23, FPT-64P-M24

DS07-13737-6E

19

MB90350 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

Oscillation circuit

• High-speed oscillation feedback

resistor = approx. 1 MΩ

X1

X0

Xout

A

Standby control signal

Xout

Oscillation circuit

X1A

X0A

• Low-speed oscillation feedback

resistor = approx. 10 MΩ

B

C

Standby control signal

CMOS

Mask ROM device:

• CMOS hysteresis input pin

R

hysteresis

inputs

Flash memory device:

• CMOS input pin

Mask ROM device:

R

• CMOS hysteresis input pin

• Pull-down resistor value: approx. 50 kΩ

CMOS

hysteresis

inputs

D

Pull-down

resistor

Flash memory device:

• CMOS input pin

• No Pull-down

CMOS hysteresis input pin

• Pull-up resistor value: approx. 50 kΩ

Pull-up

resistor

E

R

CMOS

hysteresis

inputs

(Continued)

20

DS07-13737-6E

MB90350 Series

Type

Circuit

Remarks

• CMOS level output

(I^OL= 4 mA, IOH = −4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

P-ch

Pout

Nout

N-ch

R

F

CMOS

hysteresis inputs

Automotive inputs

Standby control for

input shutdown

• CMOS level output

(I^OL= 4 mA, IOH = −4 mA)

Pull-up control

Pout

Pull-up

resistor

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

• TTL input (With the standby-time input

shutdown function)

P-ch

N-ch

Nout

R

G

• Programmable pull-up resistor:

approx. 50 kΩ

CMOS

hysteresis inputs

Automotive inputs

TTL input

Standby control for

input shutdown

• CMOS level output

(I^OL= 3 mA, IOH = −3 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

P-ch

N-ch

Pout

Nout

H

R

CMOS

hysteresis inputs

Automotive inputs

Standby control for

input shutdown

(Continued)

DS07-13737-6E

21

MB90350 Series

Type

Circuit

Remarks

• CMOS level output

(I^OL= 4 mA, IOH = −4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

P-ch

N-ch

Pout

Nout

R

• A/D analog input

I

CMOS

hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Analog input

• Power supply input protection circuit

P-ch

N-ch

K

• A/D converter reference voltage power

supply input pin, with the protection

circuit

• Flash memory devices do not have a

protection circuit against V^CCfor pin

AVRH.

ANE

AVR

P-ch

N-ch

L

ANE

(Continued)

22

DS07-13737-6E

MB90350 Series

(Continued)

Type

Circuit

Remarks

• CMOS level output

pull-up control

(I^OL= 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

pull-up

resistor

Pout

Nout

• TTL input (With the standby-time input

shutdown function)

R

N

• Programmable pull-up resistor:

approx. 50 kΩ

CMOS inputs

Automotive inputs

TTL input

Standby control for

input shutdown

• CMOS level output

(I^OL= 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

P-ch

N-ch

Pout

• Automotive input (With the standby-time

input shutdown function)

• A/D analog input

Nout

R

O

CMOS inputs

Automotive inputs

Standby control for

input shutdown

Analog input

DS07-13737-6E

23

MB90350 Series

■ HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Treatment of unused pins

• Using external clock

• Precautions for when not using a sub clock signal

• Notes on during operation of PLL clock mode

• Power supply pins (V^CC/VSS)

• Pull-up/down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter

• Notes on Energization

• Stabilization of power supply voltage

• Initialization

• Port0 to port3 output during Power-on (External-bus mode)

• Notes on using CAN Function

• Flash security Function

• Correspondence with TA = + 105 °C or more

• Low voltage/CPU operation detection reset circuit

• Internal CR oscillation circuit

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than V^CCor lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.

• The AVCC power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

In using the devices, take sufficient care to avoid exceeding maximum ratings.

For the same reason, also be careful not to let the analog power-supply voltage (AV^CC, AVRH) exceed the digital

power-supply voltage.

2. Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should

be more than 2 kΩ.

Unused I/O pins should be set to the output state and can be left open, or the input state with the above described

connection.

3. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90350 Series

X0

Open

X1

24

DS07-13737-6E

MB90350 Series

4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the

X1A pin open.

5. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempts to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

6. Power supply pins (VCC/VSS)

• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential

are connected inside of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and observe the standard for total output current, be sure to connect the V^CCand VSS pins to the power supply

and ground externally.

Connect V^CCand VSS pins to the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between

V^CCand VSS pins in the vicinity of VCC and VSS pins of the device.

Vcc

Vss

Vcc

Vss

Vcc

MB90350

Series

Vcc

Vss

Vcc

Vss

7. Pull-up/down resistors

The MB90350 series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).

Use external components where needed.

8. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

DS07-13737-6E

25

MB90350 Series

9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after

turning-on the digital power supply (VCC) .

Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make

sure that the voltage does not exceed AVRH or AV^CC(turning on/off the analog and digital power supplies

simultaneously is acceptable).

10. Connection of Unused Pins of A/D Converter if A/D Converter is not used

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.

11. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at

50 μs or more (0.2 V to 2.7 V) .

12. Stabilization of power supply voltage

A sudden change in the power supply voltage may cause the device to malfunction even within the specified

VCC power supply voltage operating range. Therefore, the VCC power supply voltage should be stabilized.

For reference, the power supply voltage should be controlled so that V^CCripple variations (peak-to-peak value)

at commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC power supply voltage and the

coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

13. Initialization

Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,

turn on the power again.

14. Port 0 to port 3 output during Power-on (External-bus mode)

As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of

Port 0 to Port 3 might be unstable.

1/2 VCC

V

CC

Port0 to Port3

Port0 to Port3 outputs Port0 to Port3 outputs = Hi-Z

might be unstable.

15. Notes on using CAN Function

To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR).

If DIRECT bit is set to “0” (initial value), wait states will be performed when accessing CAN registers.

Note : Please refer to section “22.15 CAN Direct Mode Register” in Hardware Manual of MB90350 series for detail

of CAN direct mode register.

26

DS07-13737-6E

MB90350 Series

16. Flash security Function

The security byte is located in the area of the flash memory.

If protection code 01H is written in the security byte, the flash memory is in the protected state by security.

Therefore please do not write 01H in this address if you do not use the security function.

Please refer to following table for the address of the security byte.

Flash memory size

Address for security bit

MB90F352(S)

MB90F352A(S)

MB90F352TA(S)

MB90F357A(S)

MB90F357TA(S)

Embedded 1 Mbit Flash Memory

FE0001^H

17. Correspondence with TA = +105 °C or more

If used exceeding TA = +105 °C, please contact sales representatives for reliability limitations.

18. Low voltage/CPU operation reset circuit

The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when

a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal

is generated.

The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates

an internal reset signal if not cleared within a given time after startup.

(1) Low voltage detection reset circuit

Detection voltage

4.0 V 0.3 V

When a low voltage condition is detected, the low voltage detection flag (LVRC: LVRF) is set to “1” and an internal

reset signal is output.

Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage

condition generates an internal reset and releases stop mode.

During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the

output of this internal reset, the reset output from the low voltage detection reset circuit is suppressed.

(2) CPU operation detection reset circuit

The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts

automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval

elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an

internal reset signal is generated. The internal reset generated from the CPU operation detection circuit has a

width of 5 machine cycles.

Interval time

2²⁰/FC (approx. 262 ms*)

* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.

During recovery from standby mode, the detection period is the maximum interval plus 20 μs.

DS07-13737-6E

27

MB90350 Series

This circuit does not operate in modes where CPU operation is stopped.

The CPU operation detection reset circuit counter is cleared under any of the following conditions.

• “0” writing to CL bit of LVRC register

• Internal reset

• Main oscillation clock stop

• Transit to sleep mode

• Transit to timebase timer mode and watch mode

19. Internal CR oscillation circuit

Value

Parameter

Symbol

Unit

Min

Typ

Max

Oscillation frequency

f^RC

50

100

200

kHz

Oscillation stabilization

wait time

tstab

⎯

100

μs

28

DS07-13737-6E

MB90350 Series

■ BLOCK DIAGRAMS

• MB90V340A-101/102

X0

X0A*

Clock

RST

X1

controller

16LX CPU

X1A*

RAM

I/O Timer 0

FRCK0

30 Kbytes

Input

Capture

IN7 to IN0

8 channels

Output

Compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

5 channels

I/O Timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

Controller

3 channels

UART

5 channels

RX2 to RX0

TX2 to TX0

16-bit

ReloadTimer

4 channels

AVCC

TIN3 to TIN0

AVSS

10-bit

A/D

Converter

24 channels

TOT3 to TOT0

AN23 to AN0

AVRH

AVRL

AD15 to AD00

A21 to A16

ALE

ADTG

RD

10-bit

D/A

Converter

2 channels

External

Bus

Interface

WRL

DA00,DA01

WRH

HRQ

HAK

8/16-bit

PPG

PPGF to PPG0

RDY

16 channels

CLK

I²C interface

2 channels

SDA0,SDA1

SCL0,SCL1

INT7 to INT0

INT15 to INT8

External

Interrupt

(INT11R to INT9R)

DMAC

Clock

CKOT

Monitor

* : MB90V340A-102 only

DS07-13737-6E

29

MB90350 Series

• MB90V340A-103/104

X0

X0A *

RST

X1

X1A*

Clock

controller/

Monitor

F²MC-16LX

Core

FRCK0

I/O Timer 0

CRoscillation

circuit

Input

Capture

IN7 to IN0

8 channels

Output

Compare

8 channels

RAM

30 Kbytes

OUT7 to OUT0

FRCK1

Prescaler

5 channels

I/O Timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

Controller

3 channels

UART

5 channels

RX2 to RX0

TX2 to TX0

16-bit

Reload

Timer

AVCC

AVSS

AN23 to AN0

AVRH

AVRL

TIN3 to TIN0

TOT3 to TOT0

8/10-bit

A/D

Converter

24 channels

4 channels

AD15 to AD00

A23 to A16

ALE

ADTG

10-bit

D/A

Converter

2 channels

RD

WRL

WRH

HRQ

HAK

RDY

CLK

External

Bus

Interface

DA01, DA00

8/16-bit

PPG

16 channels

PPGF to PPG0

I²C interface

2 channels

SDA1, SDA0

SCL1, SCL0

INT15 to INT8

(INT15R to INT8R)

INT7 to INT0

DTP/External

Interrupt

DMA

Clock

Monitor

CKOT

* : MB90V340A-104 only

30

DS07-13737-6E

MB90350 Series

• MB90F352 (S) , MB90F351 (S) , MB90F352A (S) , MB90F352TA (S) , MB90F351A (S) , MB90F351TA (S) ,

MB90352A (S) , MB90352TA (S) , MB90351A (S) , MB90351TA (S)

X0

X0A *¹

RST

Clock

controller

16LX CPU

X1

X1A*¹

Low voltage/

CPU operation

detection

I/O Timer 0

FRCK0

reset*²

Input

Capture

6 channels

RAM

4 Kbytes

IN7 to IN4,

IN1, IN0

ROM/Flash

128 K/64

Kbytes

Output

Compare

4 channels

OUT7 to OUT4

FRCK1

Prescaler

2 channels

I/O Timer 1

SOT3, SOT2

SCK3, SCK2

SIN3, SIN2

CAN

Controller

1 channel

UART

2 channels

RX1

TX1

16-bit

ReloadTimer

4 channels

AVCC

TIN3, TIN1

AVSS

8/10-bit

A/D

Converter

15 channels

TOT3, TOT1

AN14 to AN0

AVRH

AD15 to AD00

A21 to A16

ALE

ADTG

RD

External

Bus

Interface

WRL

WRH

8/16-bit

PPG

10/6 channels

PPGF to PPG8

PPG6, PPG4

HRQ

HAK

RDY

CLK

SDA0

SCL0

I²C interface

1 channel

External

Interrupt

INT15 to INT8

(INT11R to INT9R)

DMAC

*1 : Only for devices without “S”-suffix

*2 : Only for devices with “T”-suffix

DS07-13737-6E

31

MB90350 Series

• MB90F357A (S) , MB90F357TA (S) , MB90F356A (S) , MB90F356TA (S) , MB90357A (S) , MB90357TA (S) ,

MB90356A (S) , MB90356TA (S)

X0

Clock

controller/

monitor

X0A*¹

RST

16LX CPU

X1

X1A*¹

CR

oscillation

circuit

I/O Timer 0

FRCK0

Input

Low voltage detector*²

CPU operation

detector*²

Capture

6 channels

IN7 to IN4,

IN1, IN0

Output

Compare

4 channels

OUT7 to OUT4

FRCK1

RAM

4 Kbytes

I/O Timer 1

ROM/Flash

128 K/64 K

bytes

CAN

Controller

1 channel

RX1

TX1

Prescaler

2 channels

16-bit

Reload Timer

4 channels

TIN3, TIN1

SOT3, SOT2

SCK3, SCK2

SIN3, SIN2

UART

2 channels

TOT3, TOT1

AVCC

AD15 to AD00

A21 to A16

ALE

AVSS

8/10-bit

A/D

AN14 to AN0

Converter

15 channels

RD

External

Bus

Interface

AVRH

ADTG

WRL

WRH

HRQ

HAK

8/16-bit

PPG

10/6 channels

PPGF to PPG8

PPG6, PPG4

RDY

CLK

SDA0

SCL0

I²C interface

1 channel

External

Interrupt

INT15 to INT8

(INT11R to INT9R)

DMAC

*1 : Only for devices without “S”-suffix

*2 : Only for devices with “T”-suffix

32

DS07-13737-6E

MB90350 Series

■ MEMORY MAP

MB90352A (S)

MB90352TA (S)

MB90357A (S)

MB90357TA (S)

MB90F352A (S)

MB90F352TA (S)

MB90F357A (S)

MB90F357TA (S)

MB90F352 (S)

MB90351A (S)

MB90351TA (S)

MB90356A (S)

MB90356TA (S)

MB90F351A (S)

MB90F351TA (S)

MB90F356A (S)

MB90F356TA (S)

MB90F351 (S)

MB90V340A-101

MB90V340A-102

MB90V340A-103

MB90V340A-104

FFFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (F8 bank)

FF0000H

FEFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

FF0000H

FEFFFFH

FF0000H

FE0000H

FDFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FDFFFFH

External access

area

External access

area

FC0000H

FBFFFFH

FB0000H

FAFFFFH

C00100H

00FFFFH

C00100H

00FFFFH

FA0000H

F9FFFFH

F90000H

F8FFFFH

ROM (image of

FF bank)

ROM (image of

FF bank)

F80000H

00FFFFH

008000H

007FFFH

008000H

007FFFH

ROM (image of

FF bank)

Peripheral

008000H

007FFFH

007900H

Peripheral

007900H

0078FFH

RAM 30 Kbytes

001100H

0010FFH

000100H

RAM 4 Kbytes

External access area

Peripheral

RAM 4 Kbytes

External access area

Peripheral

000100H

0000EFH

000000H

0000EFH

000000H

0000EFH

000000H

Peripheral

: No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without

using the far specification in the pointer declaration.

For example, an attempt to access 00C000^Haccesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000^Hand FFFFFFH is visible in bank 00, while the image between FF0000H and

FF7FFF^His visible only in bank FF.

DS07-13737-6E

33

MB90350 Series

■ I/O MAP

Abbrevia-

tion

Address

Register

Port 0 Data Register

Access

Resource name

Initial value

00^H

01H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

XXXXXXXXB

Port 1 Data Register

Port 2 Data Register

Port 3 Data Register

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

02H

03H

04H

05H

06H

07H to 0AH

0B^H

Reserved

Port 5 Analog Input Enable Register

Port 6 Analog Input Enable Register

ADER5

ADER6

R/W

Port 5, A/D

Port 6, A/D

11111111B

0CH

0DH

Reserved

0EH

Input Level Select Register 0

Input Level Select Register 1

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

Port 3 Direction Register

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

ILSR0

ILSR1

R/W

Ports

00000000B

XX000000B

00000000B

XX000000B

X0000000B

00000000B

0FH

10H

DDR0

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

11H

DDR1

12H

DDR2

13H

DDR3

14H

DDR4

15H

DDR5

16H

DDR6

17H to 19H

1A^H

Reserved

DDRA

SIN input Level Setting Register

W

UART2, UART3

X00XXXXXB

1BH

Reserved

PUCR0

PUCR1

PUCR2

PUCR3

Reserved

1CH

Port 0 Pull-up Control Register

Port 1 Pull-up Control Register

Port 2 Pull-up Control Register

Port 3 Pull-up Control Register

R/W

Port 0

Port 1

Port 2

Port 3

00000000B

1DH

1EH

1FH

20H to 37H

38^H

PPG 4 Operation Mode Control Register PPGC4

PPG 5 Operation Mode Control Register PPGC5

W, R/W

R/W

0X000XX1B

0X000001B

000000X0B

16-bitProgrammable

Pulse Generator 4/5

39H

3AH

PPG 4/5 Count Clock Select Register

PPG45

Address Match

Detection 1

3BH

Address Detect Control Register 1

PACSR1

R/W

00000000B

(Continued)

34

DS07-13737-6E

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

3C^H

3DH

3EH

3FH

40^H

41H

42H

43H

44H

45H

46H

47H

48H

49H

4AH

4BH

4C^H

4DH

4EH

4FH

PPG 6 Operation Mode Control Register PPGC6

PPG 7 Operation Mode Control Register PPGC7

W, R/W

R/W

0X000XX1^B

0X000001B

000000X0B

16-bit Programmable

Pulse Generator 6/7

PPG 6/7 Count Clock Select Register

PPG67

Reserved

PPG 8 Operation Mode Control Register PPGC8

PPG 9 Operation Mode Control Register PPGC9

W, R/W

R/W

0X000XX1^B

0X000001B

000000X0B

16-bit Programmable

Pulse Generator 8/9

PPG 8/9 Count Clock Select Register

PPG89

Reserved

PPG A Operation Mode Control Register PPGCA

PPG B Operation Mode Control Register PPGCB

W, R/W

R/W

0X000XX1B

0X000001B

000000X0B

16-bit Programmable

Pulse Generator A/B

PPG A/B Count Clock Select Register

PPGAB

Reserved

PPG C Operation Mode Control Register PPGCC

PPG D Operation Mode Control Register PPGCD

W,R/W

R/W

0X000XX1B

0X000001B

000000X0B

16-bit Programmable

Pulse Generator C/D

PPG C/D Count Clock Select Register

PPGCD

Reserved

PPG E Operation Mode Control Register PPGCE

PPG F Operation Mode Control Register PPGCF

W,R/W

R/W

0X000XX1B

0X000001B

000000X0B

16-bit Programmable

Pulse Generator E/F

PPG E/F Count Clock Select Register

PPGEF

Reserved

Input Capture Control Status

Register 0/1

50^H

ICS01

R/W

00000000B

Input Capture 0/1

51H

Input Capture Edge Register 0/1

ICE01

R/W, R

XXX0X0XXB

52H, 53H

Reserved

Input Capture Control Status

Register 4/5

54H

55H

56H

57H

ICS45

R/W

R

00000000B

XXXXXXXXB

00000000B

XXX000XXB

Input Capture 4/5

Input Capture 6/7

Input Capture Edge Register 4/5

ICE45

Input Capture Control Status

Register 6/7

ICS67

R/W

R/W, R

Input Capture Edge Register 6/7

ICE67

58H to

5BH

Reserved

Output Compare Control Status

Register 4

5C^H

5DH

OCS4

OCS5

R/W

0000XX00B

Output Compare 4/5

Output Compare Control Status

Register 5

0XX00000B

(Continued)

DS07-13737-6E

35

MB90350 Series

Abbrevia-

tion

Address

5E^H

Register

Access

R/W

Resource name

Initial value

0000XX00B

0XX00000B

Output Compare Control Status

Register 6

OCS6

OCS7

Output Compare 6/7

Output Compare Control Status

Register 7

5FH

R/W

60H

61H

62H

63H

64H

65H

66H

67H

68H

69H

6AH

6BH

6CH

6DH

Timer Control Status Register 0

Timer Control Status Register 1

Timer Control Status Register 2

Timer Control Status Register 3

A/D Control Status Register 0

A/D Control Status Register 1

A/D Data Register 0

TMCSR0

TMCSR1

TMCSR2

TMCSR3

ADCS0

R/W

R

00000000B

XXXX0000B

00000000B

XXXX0000B

00000000B

XXXX0000B

00000000B

XXXX0000B

000XXXX0B

0000000XB

00000000B

XXXXXX00B

00000000B

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

ADCS1

ADCR0

A/D Converter

A/D Data Register 1

ADCR1

R

ADC Setting Register 0

ADSR0

R/W

ADC Setting Register 1

ADSR1

Low Voltage/CPU

R/W, W Operation Detection

Reset

Low Voltage/CPU Operation Detection

Reset Control Register

6EH

LVRC

00111000B

6FH

ROM Mirror Function Select Register

ROMM

W

ROM Mirror

XXXXXXX1B

70H to 7FH

Reserved

80^Hto 8FH Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

90H to 9AH

Reserved

DMA Descriptor Channel Specification

Register

9BH

DCSR

R/W

00000000B

DMA

9CH

9DH

DMA Status Register L

DMA Status Register H

DSRL

DSRH

R/W

00000000B

Address Match

Detection 0

9EH

9FH

A0H

Address Detect Control Register 0

Delayed Interrupt/Release Register

PACSR0

DIRR

R/W

00000000B

XXXXXXX0B

00011000B

Delayed Interrupt

Low-power Consumption Mode

Control Register

LowPowerConsumption

Control Circuit

LPMCR W,R/W

LowPowerConsumption

Control Circuit

A1H

Clock Selection Register

CKSCR

R,R/W

11111100B

A2H, A3H

Reserved

(Continued)

36

DS07-13737-6E

MB90350 Series

Abbrevia-

tion

Address

A4^H

Register

Access

R/W

W

Resource name Initial value

DMA Stop Status Register

DSSR

DMA

00000000B

0011XX00^B

Automatic Ready Function Selection

Register

A5H

ARSR

External Memory

Access

A6H

A7H

A8H

A9H

AAH

ABH

ACH

ADH

External Address Output Control Register

Bus Control Signal Selection Register

Watchdog Control Register

HACR

ECSR

WDTC

TBTC

W

00000000B

0000000XB

XXXXX111B

1XX00100B

1X001000B

R,W

Watchdog Timer

Timebase timer

Watch Timer

Timebase Timer Control Register

Watch Timer Control Register

W,R/W

R,R/W

WTC

Reserved

DERL

DERH

DMA Enable Register L

DMA Enable Register H

R/W

00000000B

DMA

Flash Control Status Register

(Flash Devices only. Otherwise

reserved)

AEH

FMCS

R,R/W

Flash Memory

000X0000B

AFH

B0H

B1H

B2H

B3H

B4H

B5H

B6H

B7H

B8H

B9H

BAH

BBH

BCH

BDH

BEH

BFH

Reserved

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

W,R/W

00000111B

Interrupt Control

C0H to

C9H

Reserved

(Continued)

DS07-13737-6E

37

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

CA^H

CBH

CCH

CDH

External Interrupt Enable Register 1

External Interrupt Source Register 1

External Interrupt Level Register 1

ENIR1

EIRR1

ELVR1

R/W

00000000B

XXXXXXXXB

00000000B

External Interrupt 1

External Interrupt Source Select

Register

CEH

EISSR

R/W

00000000B

CFH

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

D8H

D9H

PLL/Sub clock Control register

DMA Buffer Address Pointer L

DMA Buffer Address Pointer M

DMA Buffer Address Pointer H

DMA Control Register

PSCCR

BAPL

BAPM

BAPH

DMACS

IOAL

W

R/W

PLL

XXXX0000B

XXXXXXXXB

00000000B

R/W

DMA

I/O Register Address Pointer L

I/O Register Address Pointer H

Data Counter L

R/W

IOAH

R/W

DCTL

DCTH

SMR2

SCR2

R/W

Data Counter H

R/W

Serial Mode Register 2

W,R/W

Serial Control Register 2

00000000B

Reception/Transmission Data Register

2

RDR2/

TDR2

DAH

DBH

DCH

R/W

00000000B

00001000B

000000XXB

Serial Status Register 2

SSR2

R,R/W

UART2

Extended Communication Control

Register 2

R,W,

R/W

ECCR2

DDH

DEH

Extended Status/Control Register 2

Baud Rate Generator Register 20

Baud Rate Generator Register 21

ESCR2

BGR20

BGR21

R/W

00000100B

00000000B

DFH

E0H to EFH

F0^Hto FFH

Reserved

External area

7900H to

7907H

Reserved

(Continued)

38

DS07-13737-6E

MB90350 Series

Abbrevia-

tion

Address

Register

Reload Register L4

Access

Resource name

Initial value

7908^H

7909H

790AH

790BH

790CH

790DH

790EH

790FH

7910H

7911H

7912H

7913H

7914H

7915H

7916H

7917H

7918H

7919H

791AH

791BH

791CH

791DH

791EH

791FH

7920H

7921H

7922H

7923H

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

PRLLC

PRLHC

PRLLD

PRLHD

PRLLE

PRLHE

PRLLF

PRLHF

IPCP0

IPCP1

R/W

R

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

16-bitProgrammable

Pulse

Reload Register H4

Reload Register L5

Reload Register H5

Reload Register L6

Reload Register H6

Reload Register L7

Reload Register H7

Reload Register L8

Reload Register H8

Reload Register L9

Reload Register H9

Reload Register LA

Reload Register HA

Reload Register LB

Reload Register HB

Reload Register LC

Reload Register HC

Reload Register LD

Reload Register HD

Reload Register LE

Reload Register HE

Reload Register LF

Reload Register HF

Input Capture Register 0

Input Capture Register 1

Generator 4/5

16-bitProgrammable

Pulse

Generator 6/7

16-bitProgrammable

Pulse

Generator 8/9

16-bitProgrammable

Pulse

Generator A/B

16-bitProgrammable

Pulse

Generator C/D

16-bitProgrammable

Pulse

Generator E/F

R

Input Capture 0/1

R

7924H to

7927H

Reserved

7928H

7929H

792AH

792BH

Input Capture Register 4

Input Capture Register 5

IPCP4

IPCP5

R

XXXXXXXXB

Input Capture 4/5

XXXXXXXXB

(Continued)

DS07-13737-6E

39

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

792C^H

792DH

792EH

792FH

Input Capture Register 6

Input Capture Register 7

IPCP6

IPCP7

R

XXXXXXXXB

Input Capture 6/7

7930H to

7937H

Reserved

7938^H

7939H

793AH

793BH

793CH

793DH

793EH

793FH

7940H

7941H

7942H

7943H

7944H

7945H

7946H

7947H

7948H

7949H

794AH

794BH

794CH

794DH

794EH

794FH

Output Compare Register 4

Output Compare Register 5

Output Compare Register 6

Output Compare Register 7

Timer Data Register 0

OCCP4

OCCP5

OCCP6

OCCP7

TCDT0

TCCSL0

TCCSH0

TCDT1

TCCSL1

TCCSH1

R/W

XXXXXXXXB

00000000B

Output Compare 4/5

Output Compare 6/7

I/O Timer 0

Timer Data Register 0

00000000B

Timer Control Status Register 0

Timer Data Register 1

00000000B

0XXXXXXXB

00000000B

Timer Data Register 1

00000000B

I/O Timer 1

Timer Control Status Register 1

00000000B

0XXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

(Continued)

TMR0/

TMRLR0

16-bit Reload

Timer 0

Timer Register 0/Reload Register 0

Timer Register 1/Reload Register 1

Timer Register 2/Reload Register 2

Timer Register 3/Reload Register 3

TMR1/

TMRLR1

16-bit Reload

Timer 1

TMR2/

TMRLR2

16-bit Reload

Timer 2

TMR3/

TMRLR3

16-bit Reload

Timer 3

40

DS07-13737-6E

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

7950^H

7951H

Serial Mode Register 3

Serial Control Register 3

SMR3

SCR3

W, R/W

00000000B

Reception/Transmission Data

Register 3

RDR3/

TDR3

7952H

7953H

7954H

R/W

00000000B

00001000B

000000XXB

Serial Status Register 3

SSR3

R,R/W

UART3

Extended Communication Control

Register 3

R,W,

R/W

ECCR3

7955H

7956H

7957H

Extended Status/Control Register 3

Baud Rate Generator Register 30

Baud Rate Generator Register 31

ESCR3

BGR30

BGR31

R/W

00000100B

00000000B

7958H,

7959H

Reserved

Clock Monitor Function Control

Register

7960^H

CSVCR

R, R/W

Clock Monitor

00011100B

7961H to

796DH

Reserved

796E^H

796FH

7970^H

7971H

7972H

7973H

7974H

7975H

7976H

7977H

7978H

CAN Direct Mode Register

CDMR

R/W

CAN Clock Sync

XXXXXXX0B

Reserved

I²C Bus Status Register 0

I²C Bus Control Register 0

IBSR0

IBCR0

ITBAL0

ITBAH0

ITMKL0

ITMKH0

ISBA0

R

W,R/W

R/W

00000000^B

00000000B

00000000^B

00000000B

11111111^B

00111111B

00000000B

01111111B

00000000B

I²C 10-bit Slave Address Register 0

I²C Interface 0

I²C 10-bit Slave Address Mask Register

0

I²C 7-bit Slave Address Register 0

I²C 7-bit Slave Address Mask Register 0

I²C data register 0

ISMK0

IDAR0

7979H,

797AH

Reserved

ICCR0

Reserved

797B^H

I²C Clock Control Register 0

R/W

I²C Interface 0

00011111B

797CH to

79A1H

79A2^H

79A3H

79A4H

Flash Write Control Register 0

Flash Write Control Register 1

Sector Change Setting Register

FWR0

FWR1

SSR0

R/W

00000000B

00XXXXX0B

Dual Operation

Flash

79A5H to

79C1H

Reserved

(Continued)

DS07-13737-6E

41

MB90350 Series

(Continued)

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

79C2^H

Setting Prohibited

Reserved

79C3^Hto

79DFH

79E0^H

79E1H

79E2H

79E3H

79E4H

79E5H

79E6H

79E7H

79E8H

Detect Address Setting Register 0

Detect Address Setting Register 1

Detect Address Setting Register 2

PADR0

PADR1

PADR2

R/W

XXXXXXXXB

R/W

Address Match

Detection 0

79E9H to

79EFH

Reserved

79F0^H

79F1H

79F2H

79F3H

79F4H

79F5H

79F6H

79F7H

79F8H

Detect Address Setting Register 3

Detect Address Setting Register 4

Detect Address Setting Register 5

PADR3

PADR4

PADR5

R/W

XXXXXXXX^B

XXXXXXXXB

Address Match

Detection 1

79F9H to

7BFFH

Reserved

7C00^Hto

7CFFH

Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

Reserved

7D00^Hto

7DFFH

7E00^Hto

7FFFH

Notes : • Initial value of “X” represents unknown value.

• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved

addresses results reading “X”.

42

DS07-13737-6E

MB90350 Series

■ CAN CONTROLLERS

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

• Supports transmission/reception in standard frame and extended frame formats

• Supports transmitting of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

• 29-bit ID and 8-byte data

• Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message

buffer as ID acceptance mask

• Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)

List of Control Registers

Address

Register

Abbreviation

BVALR

TREQR

TCANR

TCR

Access

R/W

W

Initial Value

CAN1

000080^H

000081H

000082H

000083H

000084H

000085H

000086H

000087H

000088H

000089H

00008AH

00008BH

00008CH

00008DH

00008EH

00008FH

00000000B

Message buffer enable register

Transmit request register

Transmit cancel register

00000000B

Transmission complete register

Receive complete register

Remote request receiving register

Receive overrun register

R/W

00000000B

RCR

00000000B

RRTRR

ROVRR

RIER

00000000B

Reception interrupt

enable register

00000000B

(Continued)

DS07-13737-6E

43

MB90350 Series

(Continued)

Address

Register

Abbreviation

CSR

Access

Initial Value

CAN1

007D00^H

007D01H

007D02H

007D03H

007D04H

007D05H

007D06H

007D07H

007D08H

007D09H

007D0AH

007D0BH

007D0CH

007D0DH

007D0EH

007D0FH

007D10H

007D11H

007D12H

007D13H

007D14H

007D15H

007D16H

007D17H

007D18H

007D19H

007D1AH

007D1BH

R/W, W

R/W, R

0XXXX0X1B

00XXX000B

Control status register

Last event indicator register

Receive/transmit error counter

Bit timing register

000X0000B

XXXXXXXXB

LEIR

R/W

R

00000000B

RTEC

BTR

11111111B

X1111111B

R/W

XXXXXXXXB

IDE register

IDER

00000000B

Transmit RTR register

TRTRR

RFWTR

TIER

Remote frame receive waiting

register

XXXXXXXXB

Transmit interrupt

enable register

00000000B

XXXXXXXX^B

XXXXXXXXB

Acceptance mask

select register

AMSR

AMR0

AMR1

R/W

XXXXXXXXB

Acceptance mask register 0

Acceptance mask register 1

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

44

DS07-13737-6E

MB90350 Series

List of Message Buffers (ID Registers)

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C00^H

to

007C1FH

XXXXXXXXB

to

XXXXXXXXB

General-purpose RAM

ID register 0

⎯

R/W

007C20H

007C21H

007C22H

007C23H

007C24H

007C25H

007C26H

007C27H

007C28H

007C29H

007C2AH

007C2BH

007C2CH

007C2DH

007C2EH

007C2FH

007C30H

007C31H

007C32H

007C33H

007C34H

007C35H

007C36H

007C37H

007C38H

007C39H

007C3AH

007C3BH

007C3CH

007C3DH

007C3EH

007C3FH

XXXXXXXX^B

XXXXXXXXB

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

R/W

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

(Continued)

DS07-13737-6E

45

MB90350 Series

(Continued)

Address

Register

CAN1

Abbreviation

Access

Initial Value

007C40^H

XXXXXXXX^B

XXXXXXXXB

007C41H

ID register 8

007C42H

IDR8

R/W

XXXXXXXXB

007C43H

007C44H

XXXXXXXX^B

XXXXXXXXB

007C45H

ID register 9

007C46H

IDR9

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

R/W

XXXXXXXXB

007C47H

007C48H

XXXXXXXX^B

XXXXXXXXB

007C49H

ID register 10

007C4AH

XXXXXXXXB

007C4BH

007C4CH

XXXXXXXXB

007C4DH

ID register 11

007C4EH

XXXXXXXXB

007C4FH

007C50H

XXXXXXXX^B

XXXXXXXXB

007C51H

ID register 12

007C52H

XXXXXXXXB

007C53H

007C54H

XXXXXXXXB

007C55H

ID register 13

007C56H

XXXXXXXXB

007C57H

007C58H

XXXXXXXX^B

XXXXXXXXB

007C59H

ID register 14

007C5AH

XXXXXXXXB

007C5BH

007C5CH

XXXXXXXX^B

XXXXXXXXB

007C5DH

ID register 15

007C5EH

XXXXXXXXB

XXXXXXXX^B

007C5FH

46

DS07-13737-6E

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers)

Address

CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

XXXXXXXXB

007C60^H

007C61H

007C62H

007C63H

007C64H

007C65H

007C66H

007C67H

007C68H

007C69H

007C6AH

007C6BH

007C6CH

007C6DH

007C6EH

007C6FH

007C70H

007C71H

007C72H

007C73H

007C74H

007C75H

007C76H

007C77H

007C78H

007C79H

007C7AH

007C7BH

007C7CH

007C7DH

007C7EH

007C7FH

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

(Continued)

DS07-13737-6E

47

MB90350 Series

Address

Register

Abbreviation

Access

Initial Value

CAN1

007C80H

to

007C87H

XXXXXXXXB

to

XXXXXXXXB

Data register 0

(8 bytes)

DTR0

R/W

007C88H

to

007C8FH

XXXXXXXXB

to

XXXXXXXXB

Data register 1

(8 bytes)

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

R/W

007C90H

to

007C97H

XXXXXXXXB

to

XXXXXXXXB

Data register 2

(8 bytes)

007C98H

to

007C9FH

XXXXXXXXB

to

XXXXXXXXB

Data register 3

(8 bytes)

007CA0H

to

007CA7H

XXXXXXXXB

to

XXXXXXXXB

Data register 4

(8 bytes)

007CA8H

to

007CAFH

XXXXXXXXB

to

XXXXXXXXB

Data register 5

(8 bytes)

007CB0H

to

007CB7^H

XXXXXXXXB

to

XXXXXXXX^B

Data register 6

(8 bytes)

007CB8H

to

007CBFH

XXXXXXXXB

to

XXXXXXXXB

Data register 7

(8 bytes)

007CC0H

to

007CC7H

XXXXXXXXB

to

XXXXXXXXB

Data register 8

(8 bytes)

007CC8H

to

007CCFH

XXXXXXXXB

to

XXXXXXXXB

Data register 9

(8 bytes)

007CD0H

to

007CD7H

XXXXXXXXB

to

XXXXXXXXB

Data register 10

(8 bytes)

007CD8H

to

007CDFH

XXXXXXXXB

to

XXXXXXXXB

Data register 11

(8 bytes)

007CE0H

to

007CE7H

XXXXXXXXB

to

XXXXXXXXB

Data register 12

(8 bytes)

007CE8H

to

007CEFH

XXXXXXXXB

to

XXXXXXXXB

Data register 13

(8 bytes)

(Continued)

48

DS07-13737-6E

MB90350 Series

(Continued)

Address

Register

Abbreviation

Access

Initial Value

CAN1

007CF0^H

to

007CF7H

XXXXXXXXB

to

XXXXXXXXB

Data register 14

(8 bytes)

DTR14

R/W

007CF8H

to

007CFFH

XXXXXXXXB

to

XXXXXXXXB

Data register 15

(8 bytes)

DTR15

DS07-13737-6E

49

MB90350 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

register

EI²OS

corre-

sponding

Interrupt vector

Number

DMA ch

number

Interrupt cause

Address

FFFFDCH

FFFFD8^H

FFFFD4^H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

Number

Address

Reset

N

⎯

0

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

⎯

INT9 instruction

Exception

N

Reserved

N

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

Reserved

N

CAN 1 RX / Input Capture 6

CAN 1 TX/NS / Input Capture 7

I²C

Y1

N

Reserved

N

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

PPG 4/5

Y1

N

1

2

⎯

3

PPG 6/7

N

PPG 8/9/C/D

N

PPG A/B/E/F

N

Timebase Timer

External Interrupt 8 to 11

Watch Timer

N

Y1

N

⎯

4

External Interrupt 12 to 15

A/D Converter

Y1

N

5

I/O Timer 0 / I/O Timer 1

Input Capture 4/5

Output Compare 4/5

Input Capture 0/1

Output Compare 6/7

Reserved

⎯

6

Y1

N

7

8

9

10

11

12

13

Reserved

N

UART 3 RX

Y2

Y1

0000BDH

UART 3 TX

(Continued)

50

DS07-13737-6E

MB90350 Series

(Continued)

Interrupt cause

Interrupt control

EI²OS

corre-

Interrupt vector

DMA ch

number

register

sponding

Number

#39

Address

FFFF60^H

FFFF5CH

FFFF58H

FFFF54H

Number

Address

UART 2 RX

Y2

Y1

N

14

15

⎯

ICR14

ICR15

0000BEH

UART 2 TX

#40

Flash Memory

Delayed interrupt

#41

0000BFH

N

#42

Y1 : Usable

Y2 : Usable, with EI²OS stop function

: Unusable

Notes : • The peripheral resources sharing the ICR register have the same interrupt level.

N

• When two peripheral resources share the ICR register, only one can use EI²OSat a time.

• When either of the two peripheral resources sharing the ICR register specifies EI²OS, the other one

cannot use interrupts.

DS07-13737-6E

51

MB90350 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VCC

VSS − 0.3 VSS + 6.0

V

Power supply voltage*¹

AVCC

VCC = AVCC*²

AVRH VSS − 0.3 VSS + 6.0

AVCC ≥ AVRH*²

Input voltage*¹

Output voltage*¹

VI

VO

VSS − 0.3 VSS + 6.0

*3

Maximum Clamp Current

I^CLAMP

Σ|ICLAMP|

I^OL

−4.0

⎯

+4.0

40

mA *5

mA *4

Total Maximum Clamp Current

“L” level maximum output current

“L” level average output current

“L” level maximum overall output current

“L” level average overall output current

“H” level maximum output current

“H” level average output current

“H” level maximum overall output current

“H” level average overall output current

15

IOLAV

ΣI^OL

4

100

50

ΣI^OLAV

IOH

−15

−4

I^OHAV

ΣI^OH

−100

−50

ΣIOHAV

MB90F351(S), MB90F352(S)

+105 °C < T^A≤ +125 °C,

Normal operation : maximum

frequency 16 MHz

⎯

240

320

mW

Power consumption

P^D

MB90F351(S), MB90F352(S)

−40 °C < TA ≤ +105 °C,

Normal operation : maximum

frequency 24 MHz

⎯

320

mW Device other than above

−40

−55

+105

+125

+150

°C

Operating temperature

Storage temperature

T^A

°C *6

°C

T^STG

(Continued)

52

DS07-13737-6E

MB90350 Series

(Continued)

*1: This parameter is based on V^SS= AVSS = 0 V

*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AVCC when the power is switched on.

*3: V^Iand VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum

current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI

rating.

*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67

*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,

P50 to P56 (for evaluation device : P50 to P55) , P60 to P67

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

power supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

V

CC

Limiting

resistance

P-ch

N-ch

+B input (0 V to 16 V)

R

*6 : If used exceeding TA = +105 °C, be sure to contact sales for reliability limitations.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS07-13737-6E

53

MB90350 Series

2. Recommended Operating Conditions

(VSS = AVSS = 0 V)

Value

Typ

Parameter

Symbol

Unit

Remarks

Under normal operation

Min

Max

4.0

5.0

5.5

V

Under normal operation, when not using the

A/D converter and not Flash programming.

3.5

5.0

5.5

V^CC,

AVCC

Power supply voltage

4.5

3.0

5.0

5.5

V

When External bus is used.

⎯

Maintains RAM data in stop mode

Use a ceramic capacitor or capacitor of better

Smooth capacitor

CS

0.1

⎯

1.0

μF AC characteristics. Bypass capacitor at the

VCC pin should be greater than this capacitor.

−40

⎯

+105

+125

°C MB90F352(S) fCP ≤ 24MHz

Operating temperature

T^A

*, MB90F352(S) fCP ≤ 16MHz,

°C

Devices with A-suffix

* : If used exceeding T^A= +105 °C, be sure to contact sales for reliability limitations.

• C Pin Connection Diagram

C

S

Operation guaranteed range

24

16

MB90F351(S),

MB90F352(S)

Device other

than above

− 40

+105

+125

Operation temperature TA (°C)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

54

DS07-13737-6E

MB90350 Series

3. DC Characteristics

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Typ

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Max

Pin inputs if CMOS

hysteresis input levels

areselected(exceptP12,

P15, P44, P45, P50)

V^IHS

⎯

0.8 VCC

⎯

VCC + 0.3

V

Pin inputs if

V^IHA

V^IHT

V^IHS

⎯

0.8 VCC

2.0

⎯

VCC + 0.3

V

AUTOMOTIVE input

levels are selected

Pin inputs if TTL input

levels are selected

Input H

voltage

(At V^CC=

5 V 10%)

P12, P15, P50 inputs if

CMOS input levels are

selected

0.7 VCC

P44, P45 inputs if CMOS

hysteresis input levels

are selected

V^IHI

⎯

0.7 VCC

⎯

VCC + 0.3

V

RST input pin (CMOS

hysteresis)

V^IHR

V^IHM

⎯

0.8 VCC

⎯

VCC + 0.3

V

VCC − 0.3

MD input pin

Pin inputs if CMOS

hysteresis input levels

areselected(exceptP12,

P15, P44, P45, P50)

V^ILS

⎯

VSS − 0.3

⎯

0.2 VCC

V

Pin inputs if

V^ILA

V^ILT

V^ILS

⎯

VSS − 0.3

⎯

0.5 VCC

0.8

V

AUTOMOTIVE input

levels are selected

Pin inputs if TTL

input levels are selected

Input L

voltage

(At V^CC=

5 V 10%)

P12, P15, P50 inputs if

CMOS input levels are

selected

0.3 VCC

P44, P45 inputs if CMOS

hysteresis input levels

are selected

V^ILI

⎯

VSS − 0.3

⎯

0.3 VCC

V

RST input pin (CMOS

hysteresis)

V^ILR

V^ILM

V^OH

⎯

VSS − 0.3

VCC − 0.5

⎯

0.2 VCC

VSS + 0.3

⎯

V

MD input pin

Output H

voltage

Normal

outputs

VCC = 4.5 V,

IOH = −4.0 mA

Output H

voltage

I²Ccurrent VCC = 4.5 V,

outputs IOH = −3.0 mA

V^OHI

VCC − 0.5

⎯

V

(Continued)

DS07-13737-6E

55

MB90350 Series

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min Typ Max

Output L

voltage

Normal

outputs

I²C current VCC = 4.5 V,

outputs

VCC = 4.5 V,

IOL = 4.0 mA

V^OL

V^OLI

I^IL

⎯

0.4

1

V

Output L

voltage

IOL = 3.0 mA

Input leak

current

VCC = 5.5 V,

VSS<VI<VCC

⎯

− 1

µA

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P37,

RST

Pull-up

resistance

RUP

⎯

25

50

100 kΩ

Pull-down

resistance

Except Flash

memory devices

R^DOWN

MD2

25

50

48

VCC = 5.0 V,

Internal frequency : 24 MHz,

At normal operation.

⎯

60

65

70

35

mA

V^CC= 5.0 V,

Flash memory

devices

I^CC

Internal frequency : 24 MHz,

At writing FLASH memory.

⎯

53

58

25

V^CC= 5.0 V,

Flash memory

devices

Internal frequency : 24 MHz,

At erasing FLASH memory.

VCC = 5.0 V,

I^CCS

Internal frequency : 24 MHz,

At Sleep mode.

Devices

⎯

0.3

0.4

0.8

1.0

mA without

“T”-suffix

VCC = 5.0 V,

Internal frequency : 2 MHz,

At Main Timer mode

Power supply

current

I^CTS

VCC

Devices

mA

with “T”-suffix

VCC = 5.0 V,

Internal frequency : 24 MHz,

At PLL Timer mode,

external frequency = 4 MHz

I^CTSPLL6

⎯

4

7

mA

MB90F351

MB90F352

MB90F351A

MB90F352A

MB90F356A

MB90F357A

MB90351A

MB90352A

MB90356A

MB90357A

VCC = 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub clock operation

T^A= +25°C

I^CCL

⎯

70

140

μA

(Continued)

56

DS07-13737-6E

MB90350 Series

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Min Typ Max

Sym-

bol

Parameter

Condition

Unit

Remarks

VCC = 5.0 V,

Internal frequency: 8 kHz,

During operating clock

monitor function,

At sub clock operation

TA = +25°C

MB90F356A

MB90F357A

MB90356A

MB90357A

⎯

100

200

µA

VCC = 5.0 V,

Internal CR oscillation/

4 division,

At sub clock operation

T^A= +25°C

MB90F356AS

MB90F357AS

MB90356AS

MB90357AS

µA

MB90F351TA

MB90F352TA

MB90F356TA

MB90F357TA

MB90351TA

MB90352TA

MB90356TA

MB90357TA

VCC = 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub clock operation

TA = +25°C

I^CCL

⎯

120

240

Power supply

current

V^CC= 5.0 V,

VCC

Internal frequency: 8 kHz,

During operating clock

monitor function,

At sub clock operation

TA = +25°C

MB90F356TA

MB90F357TA

MB90356TA

MB90357TA

⎯

150

300

µA

V^CC= 5.0 V,

Internal CR oscillation/

4 division,

At sub clock operation

TA = +25°C

MB90F356TAS

MB90F357TAS

MB90356TAS

MB90357TAS

MB90F351

MB90F352

MB90F351A

MB90F352A

MB90F356A

MB90F357A

MB90351A

MB90352A

MB90356A

MB90357A

VCC = 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub sleep

I^CCLS

⎯

20

50

μA

T^A= +25°C

(Continued)

DS07-13737-6E

57

MB90350 Series

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Min Typ Max

Sym-

bol

Parameter

Condition

Unit

Remarks

VCC = 5.0 V,

Internal frequency: 8 kHz,

During operating clock

monitor function,

At sub sleep

MB90F356A

MB90F357A

MB90356A

MB90357A

⎯

60

200 μA

TA = +25°C

VCC = 5.0 V,

Internal CR oscillation/

4 division,

At sub sleep

TA = +25°C

MB90F356AS

MB90F357AS

MB90356AS

MB90357AS

200 μA

MB90F351TA

MB90F352TA

MB90F356TA

MB90F357TA

MB90351TA

MB90352TA

MB90356TA

MB90357TA

V^CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At sub sleep

I^CCLS

⎯

70

150 μA

TA = +25°C

Power supply

current

V^CC= 5.0 V,

VCC

Internal frequency: 8 kHz,

During operating clock

monitor function,

At sub sleep

MB90F356TA

MB90F357TA

MB90356TA

MB90357TA

⎯

110

300 μA

TA = +25°C

V^CC= 5.0 V,

Internal CR oscillation/

4 division,

At sub sleep

TA = +25°C

MB90F356TAS

MB90F357TAS

MB90356TAS

MB90357TAS

300 μA

MB90F351

MB90F352

MB90F351A

MB90F352A

MB90F356A

MB90F357A

MB90351A

MB90352A

MB90356A

MB90357A

VCC = 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At watch mode

I^CCT

⎯

10

35

μA

T^A= +25°C

(Continued)

58

DS07-13737-6E

MB90350 Series

(Continued)

(MB90F352(S)/MB90F351(S): T^A= −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Min Typ Max

Sym-

bol

Parameter

Condition

Unit

Remarks

VCC = 5.0 V,

Internal frequency: 8 kHz,

During operating clock

monitor function,

At watch mode

MB90F356A

MB90F357A

MB90356A

MB90357A

⎯

25

150 μA

TA = +25°C

VCC = 5.0 V,

Internal CR oscillation/

4 division,

At watch mode

TA = +25°C

MB90F356AS

MB90F357AS

MB90356AS

MB90357AS

150 μA

MB90F351TA

MB90F352TA

MB90F356TA

MB90F357TA

MB90351TA

MB90352TA

MB90356TA

MB90357TA

V^CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

monitor function,

At watch mode

I^CCT

⎯

60

80

140 μA

Power supply

current

TA = +25°C

VCC

V^CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock

monitor function,

At watch mode

MB90F356TA

MB90F357TA

MB90356TA

MB90357TA

250 μA

TA = +25°C

V^CC= 5.0 V,

Internal CR oscillation/

4 division,

At watch mode

T^A= +25°C

MB90F356TAS

MB90F357TAS

MB90356TAS

MB90357TAS

⎯

80

7

250 μA

Devices

25

μA without

VCC = 5.0 V,

At Stop mode,

TA = +25°C

“T”-suffix

I^CCH

Devices

with “T”-suffix

⎯

60

5

130 μA

Other than C, AVCC, AVSS,

AVRH, VCC, VSS,

Input capacity

C^IN

⎯

15

pF

DS07-13737-6E

59

MB90350 Series

4. AC Characteristics

(1) Clock Timing

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

1/2 (at PLL stop)

When using an oscillation circuit

3

⎯

16

MHz

1 multiplied PLL

When using an oscillation circuit

4

⎯

16

12

8

2 multiplied PLL

When using an oscillation circuit

X0, X1

3 multiplied PLL

When using an oscillation circuit

4

4 multiplied PLL

When using an oscillation circuit

4

6

6 multiplied PLL

When using an oscillation circuit

⎯

3

4

f^C

Clock frequency

1/2 (at PLL stop),

When using an external clock

24

12

8

1 multiplied PLL

When using an external clock

4

2 multiplied PLL

When using an external clock

4

X0

3 multiplied PLL

When using an external clock

4

4 multiplied PLL

When using an external clock

4

6

6 multiplied PLL

When using an external clock

⎯

4

f^CL

X0A, X1A

X0, X1

X0

—

62.5

41.67

10

32.768 100

kHz

ns

⎯

333

—

When using an oscillation circuit

When using an external clock

t^CYL

Clock cycle time

ns

tCYLL

X0A, X1A

X0

30.5

⎯

μs

ns

P^WH, PWL

PWHL, PWLL

10

⎯

Input clock pulse width

Duty ratio is about 30% to 70%.

X0A

5

15.2

⎯

μs

Input clock rise and fall

time

t^CR, tCF

X0

⎯

5

ns

When using an external clock

(Continued)

60

DS07-13737-6E

MB90350 Series

(Continued)

(MB90F352(S)/MB90F351(S): T^A= −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

MB90F352/(S), MB90F351/(S)

When using main clock

(T^A≤ +105 °C)

24

1.5

⎯

MHz

MB90F352/(S), MB90F351/(S)

When using main clock

(T^A≤ +125 °C)

Internal operating

clock frequency

(machine clock)

f^CP

f^CPL

tCP

⎯

16

Device other than above,

When using main clock

1.5

⎯

24

50

⎯

8.192

kHz When using sub clock

MB90F352/(S), MB90F351/(S)

When using main clock

(T^A≤ +105 °C)

41.67

62.5

⎯

666

ns

MB90F352/(S), MB90F351/(S)

When using main clock

Internal operating

clock cycle time

(machine clock)

(T^A≤ +125 °C)

Device other than above,

ns

41.67

20

⎯

666

When using main clock

t^CPL

122.1

⎯

μs

When using sub clock

• Clock Timing

t

CYL

0.8 VCC

0.2 VCC

X0

P

WH

PWL

t

CF

tCR

tCYLL

0.8 VCC

0.2 VCC

X0A

PWHL

PWLL

tCF

tCR

DS07-13737-6E

61

MB90350 Series

• PLL guaranteed operation range

Guaranteed operation range

Guaranteed PLL operation range (CS2=1)

5.5

4.5

Guaranteed A/D converter

operation range

3.5

Guaranteed PLL operation range (CS2=0)

1.5

4

8

20

24

Internal clock fCP (MHz)

Guaranteed operation range of MB90350 series

CS2(bit0 of PSCCR register) = 0

Guaranteed oscillation frequency range

4 multiplied 3 multiplied 2 multiplied

(CS=11) (CS=10) (CS=01)

1 multiplied

(CS=00)

20

16

12

8

×1/2

(PLL off)

4.0

1.5

3

4

8

12

20

24

16

External clock fC (MHz) *¹

CS2(bit0 of PSCCR register) = 1

Guaranteed oscillation frequency range

6 multiplied 4 multiplied

(CS=10) (CS=01)

2 multiplied

(CS=00)

24

16

12

8

×1/2

(PLL off)

4.0

1.5

3

4

8

12

24

16

External clock fC (MHz) *²

*1 : Guaranteed 1 multiplied PLL operation range is 4.0 MHz to 20 MHz.

*2 : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz.

External clock frequency and internal operation clock frequency

62

DS07-13737-6E

MB90350 Series

(2) Reset Standby Input

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): T^A= −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter Symbol

Unit

Remarks

Min

Max

500

⎯

ns

Under normal operation

In Stop mode, Sub Clock

mode, Sub Sleep mode

and Watch mode

Oscillation time of oscillator*

Reset input

t^RSTL

⎯

μs

RST

+ 100 μs

time

In Main timer mode and

PLL timer mode

100

* : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators,

the oscillation time is between hundreds of μs to several ms. With an external clock, the oscillation time is 0 ms.

Under normal operation:

tRSTL

RST

0.2 VCC

In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

100 μs

Oscillation time

of oscillator

Oscillation stabilization

waiting time

Instruction execution

Internal reset

DS07-13737-6E

63

MB90350 Series

(3) Power On Reset

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): T^A= −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

30

Power on rise time

Power off time

t^R

VCC

ms

⎯

t^OFF

⎯

ms Due to repetitive operation

tR

2.7 V

V

CC

0.2 V

tOFF

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you start up smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

V

CC

We recommend the slope for

a rise of 50 mV/ms maximum.

3 V

Holds RAM data

V

SS

(4) Clock Output Timing

(T^A= −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)

Value

Parameter

Symbol

CLK

Condition

Unit

Remarks

Min

62.5

41.67

20

Max

⎯

ns

f^CP= 16 MHz

Cycle time

t^CYC

⎯

fCP = 24 MHz

f^CP= 16 MHz

fCP = 24 MHz

⎯

CLK ↑ → CLK ↓

t^CHCL

13

⎯

t^CYC

tCHCL

2.4 V

CLK

0.8 V

64

DS07-13737-6E

MB90350 Series

(5) Bus Timing (Read)

(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Value

Sym-

bol

Condi-

tion

Parameter

Unit Remarks

Min

Max

ALE pulse width

t^LHLL

ALE

tCP/2 − 10

⎯

ns

ALE, A21 to

A16, AD15

to AD00

Valid address → ALE ↓ time

ALE ↓ → Address valid time

Valid address → RD ↓ time

t^AVLL

tCP/2 − 20

tCP/2 − 15

tCP − 15

⎯

ns

ALE, AD15

to AD00

t^LLAX

A21 toA16,

AD15 to

AD00, RD

tAVRL

A21 to A16,

AD15 to

AD00

Valid address → Valid data

t^AVDV

⎯

5 tCP/2 − 60

ns

input

RD pulse width

tRLRH

tRLDV

RD

(n*+3/2) tCP − 20

⎯

RD, AD15 to

AD00

RD ↓ → Valid data input

⎯

(n*+3/2) tCP − 50 ns

RD, AD15 to

AD00

RD ↑ → Data hold time

RD ↑ → ALE ↑ time

tRHDX

tRHLH

tRHAX

0

⎯

ns

RD, ALE

tCP/2 − 15

tCP/2 − 10

RD, A21 to

A16

RD ↑ → Address valid time

A21 to A16,

AD15 to

AD00, CLK

Valid address → CLK ↑ time

t^AVCH

tCP/2 − 16

⎯

ns

RD ↓ → CLK ↑ time

ALE ↓ → RD ↓ time

tRLCH

tLLRL

RD, CLK

ALE, RD

tCP/2 − 15

⎯

ns

* : n: number of ready cycles

DS07-13737-6E

65

MB90350 Series

For 1 cycle of auto-ready

CLK

tRLCH

tAVCH

2.4 V

tLLAX

tAVLL

tLHLL

tRHLH

2.4 V

0.8 V

2.4 V

ALE

RD

tAVRL

tRLRH

2.4 V

0.8 V

tLLRL

tRHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

tRLDV

tRHDX

tAVDV

2.4 V

0.8 V

VIH

VIL

2.4 V

0.8 V

VIH

VIL

AD15 to AD00

Address

Read data

66

DS07-13737-6E

MB90350 Series

(6) Bus Timing (Write)

Parameter

(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Value

Symbol

Condition

Unit Remarks

Min

Max

A21 to A16,

AD15 to AD00,

WR

Valid address → WR ↓ time

tAVWL

t^CP−15

⎯

ns

(n*+3/2)tCP − 20

WR pulse width

tWLWH

tDVWH

WR

⎯

ns

Valid data output → WR ↑

time

AD15 to AD00,

WR

⎯

AD15 to AD00,

WR

WR ↑ → Data hold time

tWHDX

tWHAX

15

⎯

ns

A21 to A16,

WR

WR ↑ → Address valid time

tCP/2 − 10

WR ↑ → ALE ↑ time

WR ↓ → CLK ↑ time

tWHLH

tWLCH

WR, ALE

WR, CLK

tCP/2 − 15

⎯

ns

* : n: Number of ready cycles

For 1 cycle of auto-ready

tWLCH

2.4 V

CLK

tWHLH

2.4 V

ALE

tAVWL

tWLWH

2.4 V

WR (WRL, WRH)

0.8 V

tWHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

tDVWH

tWHDX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to AD00

Address

Write data

DS07-13737-6E

67

MB90350 Series

(7) Ready Input Timing

(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Value

Sym-

Parameter

bol

Condition

Units

Remarks

Min

45

32

0

Max

⎯

ns f^CP= 16 MHz

ns f^CP= 24 MHz

ns

RDY set-up time

RDY hold time

t^RYHS

t^RYHH

RDY

⎯

Note : If the RDY set-up time is insufficient, use the auto-ready function.

2.4 V

CLK

ALE

RD/WR

tRYHS

tRYHH

VIH

RDY

(When WAIT is not used.)

RDY

(When WAIT is used.)

VIL

68

DS07-13737-6E

MB90350 Series

(8) Hold Timing

Parameter

(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Value

Symbol

Condition

Units

Remarks

Min

Max

Pin floating → HAK ↓

tXHAL

tHAHV

HAK

30

t^CP

ns

time

⎯

HAK ↑ time → Pin valid

time

tCP

2 tCP

Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.

2.4 V

HAK

0.8 V

tHAHV

tXHAL

Hi-Z

2.4 V

0.8 V

2.4 V

0.8 V

Each pin

DS07-13737-6E

69

MB90350 Series

(9) UART 2/3

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

SCK2, SCK3

8 t^CP*

⎯

ns

SCK2, SCK3,

SOT2, SOT3

SCK ↓ → SOT delay time

−80

100

60

+80

⎯

Internal shift clock

mode output pins

are

SCK2, SCK3,

SIN2, SIN3

Valid SIN → SCK ↑

t^IVSH

ns

CL = 80 pF + 1 TTL

SCK2, SCK3,

SIN2, SIN3

SCK ↑ → Valid SIN hold time

tSHIX

⎯

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

SCK2, SCK3

4 t^CP

⎯

ns

tSLSH

4 tCP

SCK2, SCK3, External shift clock

SOT2, SOT3 mode output pins

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

⎯

60

150

⎯

ns

are

SCK2, SCK3,

SIN2, SIN3

CL = 80 pF + 1 TTL

SCK2, SCK3,

SIN2, SIN3

SCK ↑ → Valid SIN hold time

⎯

* : Refer to “ (1) Clock timing” rating for t^CP(internal operating clock cycle time).

Notes : • AC characteristic in CLK synchronized mode.

• CL is load capacity value of pins when testing.

• Internal Shift Clock Mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

SOT

0.8 V

tIVSH

tSHIX

VIH

VIL

VIH

VIL

SIN

70

DS07-13737-6E

MB90350 Series

• External Shift Clock Mode

tSLSH

tSHSL

VIH

SCK

VIL

tSLOV

VIL

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

VIH

VIL

VIH

VIL

(10) Trigger Input Timing

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: T^A= −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

INT8 to INT15,

INT9R to INT11R,

ADTG

t^TRGH

tTRGL

Input pulse width

⎯

5 tCP

⎯

ns

VIH

INT8 to INT15,

VIL

INT9R to INT11R,

ADTG

tTRGH

tTRGL

DS07-13737-6E

71

MB90350 Series

(11) Timer Related Resource Input Timing

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): T^A= −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

tTIWH

TIN1, TIN3,

IN0, IN1,

IN4 to IN7

Input pulse width

⎯

4 tCP

⎯

ns

t^TIWL

VIH

TIN1, TIN3,

IN0, IN1,

VIL

tTIWH

IN4 to IN7

tTIWL

(12) Timer Related Resource Output Timing

(MB90F352(S)/MB90F351(S): T^A= −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): T^A= −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

TOT1, TOT3,

PPG4, PPG6,

PPG8 to PPGF

CLK ↑ → T^OUTchange time

tTO

⎯

30

⎯

ns

2.4 V

CLK

2.4 V

0.8 V

TOT1, TOT3,

PPG4, PPG6

PPG8 to PPGF

tTO

72

DS07-13737-6E

MB90350 Series

(13) I²C Timing

(MB90F352(S)/MB90F351(S): TA = −40 °C to +105 °C, VCC = AVCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(MB90F352(S)/MB90F351(S): TA = −40 °C to +125 °C, VCC = AVCC = 5.0 V 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

(Device other than above: T^A= −40 °C to +125 °C, VCC = AVCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Standard-mode Fast-mode*⁴

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

0

100

0

400

kHz

Hold time for (repeated) START condition

SDA↓→SCL↓

tHDSTA

4.0

⎯

0.6

⎯

μs

“L” width of the SCL clock

“H” width of the SCL clock

t^LOW

t^HIGH

4.7

4.0

⎯

1.3

0.6

⎯

μs

Set-up time for a repeated START condition

SCL↑→SDA↓

t^SUSTA

tHDDAT

tSUDAT

t^SUSTO

tBUS

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

0.9*³

⎯

μs

ns

μs

R = 1.7 kΩ,

C = 50 pF*¹

Data hold time

SCL↓→SDA↓↑

Data set-up time

SDA↓↑→SCL↑

250*⁵

4.0

4.7

100*⁵

0.6

1.3

Set-up time for STOP condition

SCL↑→SDA↑

⎯

Bus free time between STOP condition and

START condition

⎯

*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HDDAThas only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

*3 : A Fast-mode I²C -bus device can be used in a Standard-mode I²C-bus system, but the requirement

tSUDAT ≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

*5 : Refer to “• Note of SDA, SCL set-up time”.

• Note of SDA, SCL set-up time

SDA

Input data set-up time

SCL

6 tcp

DS07-13737-6E

73

MB90350 Series

Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending

on the load capacitance or pull-up resistor.

Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be

satisfied.

• Timing definition

SDA

tBUF

tHDSTA

tSUDAT

tLOW

SCL

tHDSTA

tSUSTA

tHIGH

tSUSTO

tHDDAT

fSCL

74

DS07-13737-6E

MB90350 Series

5. A/D Converter

(MB90F352(S)/MB90F351(S): T

Device other than above: T

A

= −40

°

C to

+

105

125

°

C, 3.0 V

≤

AVRH, VCC

=

AVCC

=

5.0 V 10

%

, fCP

≤

24 MHz, VSS

16 MHz, VSS

=

AVSS

=

0 V)

A

(

A

=

−

40 °C to

+125 °C, 3.0 V

≤

AVRH, VCC

=

AVCC

=

5.0 V 10

%

,

f

CP

≤

24 MHz, VSS

=

0 V)

Value

Typ

⎯

Parameter

Symbol

Unit

Remarks

Min

Max

10

Resolution

⎯

bit

Total error

⎯

3.0

2.5

LSB

Nonlinearity error

⎯

Differential

nonlinearity error

⎯

1.9

LSB

V

Zero reading

voltage

AVSS −

1.5 LSB

AVSS +

0.5 LSB

AVSS +

2.5 LSB

V^OT

V^FST

AN0 to AN14

Full scale reading

voltage

AVRH −

3.5 LSB

AVRH −

1.5 LSB

AVRH +

0.5 LSB

V

1.0

2.0

0.5

1.2

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AVCC < 4.5 V

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AVCC < 4.5 V

Compare time

Sampling time

⎯

16,500

μs

∞

Analog port input

current

IAIN

V^AIN

⎯

AN0 to AN14

AVRH

−0.3

AVSS

⎯

+0.3

AVRH

AVCC

μA

V

Analog input

voltage range

Reference

voltage range

AVSS + 2.7

V

I^A

AVCC

⎯

3.5

7.5

5

mA

Power supply

current

IAH

⎯

μA

*

Reference

voltage supply

current

I^R

AVRH

⎯

600

900

5

μA

I^RH

⎯

Offset between

input channels

⎯

AN0 to AN14

⎯

4

LSB

* : If A/D converter is not operating, a current when CPU is stopped is applicable (V^CC= AVCC = AVRH = 5.0 V) .

DS07-13737-6E

75

MB90350 Series

Notes on A/D Converter Section

• About the external impedance of the analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the register value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also

if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.

· Analog input equivalence circuit

R

Analog input

Comparator

C

ON at sampling

MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S),

MB90F356A(S), MB90F357A(S), MB90F356TA(S), MB90F357TA(S),

R

C

4.5 V AV_CC5.5 V 2.0 kΩ (Max) 16.0 pF (Max)

4.0 V AV_CC4.5 V 8.2 kΩ (Max) 16.0 pF (Max)

MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),

MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S),

R

C

4.5 V AV_CC5.5 V 2.0 kΩ (Max) 14.4 pF (Max)

4.0 V AV_CC4.5 V 8.2 kΩ (Max) 14.4 pF (Max)

Note : The value is reference value.

76

DS07-13737-6E

MB90350 Series

• Flash memory device

· Relation between External impedance and minimum sampling time

(MB90F352(S), MB90F351A(S), MB90F352A(S), MB90F351TA(S), MB90F352TA(S), MB90F356A(S),

MB90F357A(S), MB90F356TA(S), MB90F357TA(S))

[External impedance = 0 kΩ to 100 kΩ]

[External impedance = 0 kΩ to 20 kΩ]

4.5 V AV_CC5.5 V

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

4.0 V AV_CC4.5 V

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [μs]

• MASK ROM device

· Relation between External impedance and minimum sampling time

(MB90V340A-101/102/103/104, MB90351A(S), MB90352A(S), MB90351TA(S), MB90352TA(S),

MB90356A(S), MB90357A(S), MB90356TA(S), MB90357TA(S))

[External impedance = 0 kΩ to 100 kΩ]

[External impedance = 0 kΩ to 20kΩ]

4.5 V AV_CC5.5 V

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

4.0 V AV_CC4.5 V

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [μs]

• About the error

Values of relative errors grow larger, as |AVRH − AV^SS| becomes smaller.

DS07-13737-6E

77

MB90350 Series

6. Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Non linearity

error

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differential

linearity error

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error

: Difference between an actual value and a theoretical value. A total error includes zero tran-

sition error, full-scale transition error, and linear error.

Total error

3FFH

1.5 LSB

3FEH

3FDH

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

V^NT

(Actual measurement value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVRH − AV^SS

1 LSB = (Ideal value)

[V]

1024

N : A/D converter digital output value

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

VNT : A voltage at which digital output transits from (N − 1) to N.

(Continued)

78

DS07-13737-6E

MB90350 Series

(Continued)

Non linearity error

Differential linearity error

Ideal

characteristics

3FF

3FE

3FD

H

Actual conversion

characteristics

N + 1

Actual conversion

characteristics

{1 LSB × (N − 1)

+ VOT

}

V

FST (actual

measurement

value)

N

V

NT (actual

measurement value)

004

003

002

001

H

V

(N + 1) T

(actual measurement

Actual conversion

characteristics

N − 1

N − 2

value)

V

NT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

V

OT (actual measurement value)

AVSS

AVRH

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

[LSB]

Non linearity error of digital output N =

1 LSB

V (^N+1) T − VNT

−1 LSB [LSB]

1 LSB

Differential linearity error of digital output N =

VFST − VOT

[V]

1 LSB =

1022

N : A/D converter digital output value

V^OT: Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

DS07-13737-6E

79

MB90350 Series

7. Flash Memory Program/Erase Characteristics

Flash Memory

Value

Typ

Parameter

Conditions

Unit

Remarks

Min

Max

Excludes programming

prior to erasure

Sector erase time

Chip erase time

⎯

1

9

15

s

T^A= +25 °C

VCC = 5.0 V

Excludes programming

prior to erasure

⎯

Word (16-bit width)

programming time

Except for the overhead

time of the system level

⎯

10,000

20

16

⎯

3,600

⎯

μs

Program/Erase cycle

⎯

cycle

year

Flash Memory Data

Retention Time

Average

T^A= +85 °C

⎯

*

* : This value comes from the technology qualification.

(Using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C)

Dual Operation Flash Memory

Value

Parameter

Conditions

Unit

Remarks

Min

Typ

Max

Sector erase time

(4 Kbytes sector)

Excludes programming

prior to erasure

⎯

0.2

0.5

s

Sector erase time

(16 Kbytes sector)

Excludes programming

prior to erasure

⎯

0.5

4.6

7.5

T^A= +25 °C

VCC = 5.0 V

Excludes programming

prior to erasure

Chip erase time

⎯

Word (16-bit width)

programming time

Except for the overhead

time of the system level

⎯

10,000

20

64

⎯

3,600

⎯

μs

Program/Erase cycle

⎯

cycle

year

Flash Memory Data

Retention Time

Average

T^A= +85 °C

⎯

*

* : This value comes from the technology qualification.

(Using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C)

80

DS07-13737-6E

MB90350 Series

■ ORDERING INFORMATION

Part number

MB90F351PMC

Package

Remarks

Flash memory products

(64 Kbytes)

64-pin plastic LQFP

FPT-64P-M23

12mm , 0.65mm pitch

MB90F351SPMC

MB90F352PMC

Flash memory products

(128 Kbytes)

MB90F352SPMC

MB90F351APMC

MB90F351ASPMC

MB90F351TAPMC

MB90F351TASPMC

MB90F356APMC

MB90F356ASPMC

MB90F356TAPMC

MB90F356TASPMC

MB90F352APMC

MB90F352ASPMC

MB90F352TAPMC

MB90F352TASPMC

MB90F357APMC

MB90F357ASPMC

MB90F357TAPMC

MB90F357TASPMC

MB90351APMC

64-pin plastic LQFP

FPT-64P-M23

12mm , 0.65mm pitch

Dual operation

Flash memory products

(64 Kbytes)

64-pin plastic LQFP

FPT-64P-M23

12mm , 0.65mm pitch

Dual operation

Flash memory products

(128 Kbytes)

MB90351ASPMC

MB90351TAPMC

MB90351TASPMC

MB90356APMC

64-pin plastic LQFP

FPT-64P-M23

12mm , 0.65mm pitch

MASK ROM products

(64 Kbytes)

MB90356ASPMC

MB90356TAPMC

MB90356TASPMC

MB90352APMC

MB90352ASPMC

MB90352TAPMC

MB90352TASPMC

MB90357APMC

64-pin plastic LQFP

FPT-64P-M23

12mm , 0.65mm pitch

MASK ROM products

(128 Kbytes)

MB90357ASPMC

MB90357TAPMC

MB90357TASPMC

(Continued)

DS07-13737-6E

81

MB90350 Series

(Continued)

Part number

Package

Remarks

MB90F351APMC1

MB90F351ASPMC1

MB90F351TAPMC1

MB90F351TASPMC1

MB90F356APMC1

MB90F356ASPMC1

MB90F356TAPMC1

MB90F356TASPMC1

MB90F352APMC1

MB90F352ASPMC1

MB90F352TAPMC1

MB90F352TASPMC1

MB90F357APMC1

MB90F357ASPMC1

MB90F357TAPMC1

MB90F357TASPMC1

MB90351APMC1

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

Dual operation

Flash memory products*

(64 Kbytes)

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

Dual operation

Flash memory products*

(128 Kbytes)

MB90351ASPMC1

MB90351TAPMC1

MB90351TASPMC1

MB90356APMC1

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

MASK ROM products*

(64 Kbytes)

MB90356ASPMC1

MB90356TAPMC1

MB90356TASPMC1

MB90352APMC1

MB90352ASPMC1

MB90352TAPMC1

MB90352TASPMC1

MB90357APMC1

64-pin plastic LQFP

FPT-64P-M24

10 mm , 0.50 mm pitch

MASK ROM products*

(128 Kbytes)

MB90357ASPMC1

MB90357TAPMC1

MB90357TASPMC1

MB90V340A-101

MB90V340A-102

299-pin ceramic PGA

PGA-299C-A01

Device for evaluation

MB90V340A-103

MB90V340A-104

* : These devices are under development.

82

DS07-13737-6E

MB90350 Series

■ PACKAGE DIMENSIONS

64-pin plastic LQFP

Lead pitch

0.65 mm

Package width ×

package length

12.0 × 12.0 mm

Gullwing

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.47 g

Code

(Reference)

P-LQFP64-12×12-0.65

(FPT-64P-M23)

64-pin plastic LQFP

(FPT-64P-M23)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00 0.20(.551 .008)SQ

*12.00 0.10(.472 .004)SQ

0.145 0.055

(.006 .002)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 ^+0.20

–

0.10

(Mounting height)

.059 ^+.008

–.004

0.25(.010)

INDEX

0~8°

64

17

0.50 0.20

0.10 0.10

(.020 .008)

(.004 .004)

(Stand off)

"A"

1

16

0.60 0.15

(.024 .006)

0.65(.026)

0.32 0.05

(.013 .002)

M

0.13(.005)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

DS07-13737-6E

83

MB90350 Series

(Continued)

64-pin plastic LQFP

Lead pitch

0.50 mm

10.0 mm × 10.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Plastic mold

Code

(Reference)

P-LFQFP64-10×10-0.50

(FPT-64P-M24)

64-pin plastic LQFP

(FPT-64P-M24)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

12.00 0.20(.472 .008)SQ

Details of "A" part

*10.00 0.10(.394 .004)SQ

0.145 0.055

(.006 .002)

48

33

0.15(.006)

MAX

49

32

0.40(.016)

MAX

0.08(.003)

Details of "B" part

1.50 ^+0.20

11.00(.433)

NOM.

–

0.10

.004

(Mounting height)

.059 ^+.008

–

0.25(.010)

INDEX

0~8°

"A"

64

17

0.50 0.20

0.10 0.10

(.020 .008)

(.004 .004)

(Stand off)

"B"

1

16

LEAD No.

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2006-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-1c(D)-1-3

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

84

DS07-13737-6E

MB90350 Series

■ MAJOR CHANGES IN THIS EDITION

Page

Section

Change Results

Deleted the following package.

FPT-64P-M09

⎯

■ PACKAGES AND PRODUCT Changed the correspondence package for MB90F351,

13

26

CORRESPONDENCE

MB90F351S, MB90F352 and MB90F352S.

FPT-64P-M09 → FPT-64P-M23

■ HANDLING DEVICES

Corrected a typo in number 10.

“is used”→ “is not used”

■ ELECTRICAL CHARACTER- Changed the Minimum value of cycle time.

ISTICS

4. AC Characteristics

(4) Clock Output Timing

41.76 → 41.67

64

75

5. A/D Converter

Changed the notation of “Zero reading voltage” and “Full scale

reading voltage”.

■ ORDERING INFORMATION

Changed the part numbers and the package.

MB90F351PFM → MB90F351PMC

MB90F351SPFM → MB90F351SPMC

MB90F352PFM → MB90F352PMC

MB90F352SPFM → MB90F352SPMC

FPT-64P-M09 → FPT-64P-M23

81

The vertical lines marked in the left side of the page show the changes.

DS07-13737-6E

85

MB90350 Series

MEMO

86

DS07-13737-6E

MB90350 Series

MEMO

DS07-13737-6E

87

MB90350 Series

FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,

Kohoku-ku Yokohama Kanagawa 222-0033, Japan

Tel: +81-45-415-5858

http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU SEMICONDUCTOR AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://us.fujitsu.com/micro/

FUJITSU SEMICONDUCTOR ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

Europe

FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU SEMICONDUCTOR EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/semiconductor/

Korea

FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU SEMICONDUCTOR KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not

warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device

based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or

any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other

right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property

rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in

connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB90351ASPMC
厂家：	CYPRESS
描述：	Microcontroller, CMOS, 时钟微控制器外围集成电路装置
文件：	总88页 (文件大小：1802K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90351ASPMC [CYPRESS]

相关型号：

MB90351ASPMC1

MB90351EPMC

MB90351EPMC

MB90351EPMC1

MB90351EPMC1

MB90351EPMC1

MB90351ES

MB90351ESPMC

MB90351ESPMC1

MB90351ESPMC1

MB90351TAPMC

MB90351TAPMC1