MB90356ESPMC_技术文档

MB90350E Series

F²MC-16LX16-bit Microcontrollers

The MB90350E series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose Cypress 16-bit microcontroller

designing for automotive and industrial applications. Its main feature is the on-board CAN interface, which conforms to CAN standard

Version2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal

full CAN approach.

The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI

and power consumption.

The PLL clock multiplication circuit provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also, the clock

supervisor function can monitor main clock and sub clock independently.

As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit, 2 separate 16-bit

free-run timers, 2-channel LIN-UART and 15-channel 8/10-bit A/D converter built-in.

: Controller Area Network (CAN) - License of Robert Bosch GmbH

Features

Clock

Powerful interrupt function

■ Built-in PLL clock frequency multiplication circuit

■ Powerful 8-level, 34-condition interrupt feature

■ Up to 8 channels external interrupts are supported.

■ Selection of machine clocks (PLL clocks) is allowed among

frequency division by two on oscillation clock, and multipli-

cation of 1 to 6 times of oscillation clock (for 4 MHz oscillation

clock, 4 MHz to 24 MHz).

Automatic data transfer function independent of

CPU

■ Extended intelligent I/O service function (EI²OS): up to 16

channels

■ Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock

divided by two) is allowed (devices without S-suffix only) .

■ DMA: up to 16 channels

■ Minimum execution time of instruction : 42 ns (when operating

with 4-MHz oscillation clock, and 6-time

multiplied PLL clock).

Low power consumption (standby) mode

■ Sleep mode (a mode that stops CPU operating clock)

■ Built-in clock modulation circuit

■ Main timer mode (a timebase timer mode switched from the

main clock mode)

16 Mbytes CPU memory space

24-bit internal addressing

■ PLLtimermode(atimebasetimermodeswitchedfromthePLL

clock mode)

Instruction system best suited to controller

■ Wide choice of data types (bit, byte, word, and long word)

■ Wide choice of addressing modes (23 types)

■ Watch mode (a mode that operates sub clock and watch timer

only)

■ Stop mode (a mode that stops oscillation clock and sub clock)

■ Enhanced multiply-divide instructions with sign and RETI

instructions

■ CPU intermittent operation mode

Process

Clock supervisor (MB90x356x and MB90x357x

only)

CMOS technology

Main clock or sub clock is monitored independently.

I/O port

Enhanced high-precision computing with 32-bit

accumulator

■ General-purpose input/output port (CMOS output)

49 ports (devices without S-suffix : devices that correspond to

sub clock)

51 ports (devices with S-suffix : devices that do not correspond

to sub clock)

Instruction system compatible with high-level

language (C language) and multitask

■ Employing system stack pointer

■ Enhanced various pointer indirect instructions

■ Barrel shift instructions

Sub clock pin (X0A, X1A)

■ Yes (using the external oscillation) : devices without S-suffix

■ No (using the sub clock mode at internal CR oscillation) :

devices with S-suffix

Increased processing speed

4-byte instruction queue

Timer

■ Timebase timer, watch timer, watchdog timer : 1 channel

Cypress Semiconductor Corporation

Document Number: 002-04493 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 7, 2016

MB90350E Series

■ 8/16-bit PPG timer : 8-bit  10 channels or 16-bit 6 channels

■ 16-bit reload timer : 2 channels (only Evaluation products has

Address matching detection (Program patch)

function

4 channels)

■ Address matching detection for 6 address pointers.

■ 16- bit input/output timer

- 16-bit free-run timer : 2 channels (FRT0 : ICU0/1, FRT1 :

Capable of changing input voltage level for port

ICU4/5/6/7, OCU4/5/6/7)

- 16- bit input capture: (ICU) : 6 channels

- 16-bit output compare : (OCU) : 4 channels

■ Automotive/CMOS-Schmitt (initial level is Automotive in single

chip mode)

■ TTL level (corresponds to external bus pins only, initial level of

FULL-CAN interface: 1 channel

■ Compliant with CAN standard Version2.0 Part A and Part B

■ 16 message buffers are built-in

these pins is TTL in external bus mode)

Low voltage/CPU operation detection reset

(devices with T-suffix)

■ Detects low voltage (4.0 V  0.3 V) and resets automatically

■ CAN wake-up function

■ Resets automatically when program is runaway and counter is

not cleared within interval time

LIN-UART: 2 channels

■ Equipped with full-duplex double buffer

(approx. 262 ms : external 4 MHz)

Dual operation Flash memory (only devices 128

Kbytes Flash memory)

■ Clock-asynchronous or clock-synchronous serial transmission

is available.

I²C interface: 1 channel

■ Erase/write and read can be executed in the different bank

(Upper Bank/Lower Bank) at the same time.

Up to 400 kbps transfer rate

Supported T_A  125C

DTP/External interrupt:

wakeup: 1 channel

8

channels, CAN

The maximum operating frequency is 24 MHz* : (at T_A

125C) .

Module for activation of extended intelligent I/O service (EI²OS),

DMA, and generation of external interrupt by external input.

Flash security function

Delay interrupt generator module

Generates interrupt request for task switching.

8/10-bit A/D converter: 15 channels

■ Protects the content of Flash memory

(MB90F352x, MB90F357x only)

External bus interface

■ 4 Mbytes external memory space

■ Resolution is selectable between 8-bit and 10-bit.

■ Activation by external trigger input is allowed.

MB90F351E(S), MB90F351TE(S), MB90F352E(S),

MB90F352TE(S) : External bus Interface can not be used in

internal vector mode. It can be used only in external vector

mode.

■ Conversion time : 3 s (at 24 MHz machine clock, including

sampling time)

* : If used exceeding T_A  105 C, be sure to contact Cypress

for reliability limitations.

Document Number: 002-04493 Rev. *A

Page 2 of 84

MB90350E Series

Contents

Product Lineup1 (Without Clock supervisor function) 4

Product Lineup 2 (With Clock supervisor function) .....7

Packages and Product Correspondence .....................12

Pin Assignments ............................................................13

Pin Description ...............................................................14

I/O Circuit Type ...............................................................19

Handling Devices ............................................................22

Block Diagrams ..............................................................27

Memory Map ....................................................................33

I/O Map ............................................................................34

CAN Controllers ..............................................................42

Interrupt Factors, Interrupt Vectors, Interrupt

Control Register .............................................................50

Electrical Characteristics ...............................................51

Absolute Maximum Ratings .......................................51

Recommended Operating Conditions .......................53

DC Characteristics ....................................................54

AC Characteristics .....................................................59

Clock Timing ..............................................................59

Reset Standby Input ..................................................62

Power On Reset ........................................................63

Clock Output Timing ..................................................63

Bus Timing (Read) ....................................................64

Bus Timing (Write) .....................................................66

Ready Input Timing ...................................................67

Hold Timing ...............................................................68

LIN-UART2/3 .............................................................69

Trigger Input Timing ..................................................73

Timer Related Resource Input Timing .......................74

Timer Related Resource Output Timing ....................74

I2C Timing .................................................................75

A/D Converter ............................................................76

Definition of A/D Converter Terms ...........................80

Flash Memory Program/Erase Characteristics ..........82

Ordering Information .....................................................83

Package Dimensions ......................................................85

Major Changes ...............................................................87

Document Number: 002-04493 Rev. *A

Page 3 of 84

MB90350E Series

1. Product Lineup1 (Without Clock supervisor function)

■ Flash memory products

Part Number

MB90F351E

MB90F352E

MB90F351TE

MB90F352TE

MB90F351ES

MB90F352ES

MB90F351TES

MB90F352TES

Parameter

Type

Flash memory products

F²MC-16LX CPU

CPU

PLL clock multiplication circuit ( 1,  2,  3,  4,  6, 1/2 when PLL stops)

^{Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL} 6)

System clock

64 Kbytes Flash memory : MB90F351E(S), MB90F351TE(S)

ROM

RAM

128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the same time) :

MB90F352E(S), MB90F352TE(S)

4 Kbytes

Emulator-specific power

supply*



Sub clock pin

(X0A, X1A)

Yes

No

(Max 100 kHz)

Clock supervisor

No

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter/Flash programming

4.5 V to 5.5 V : at using external bus

Operating voltage

Operating

temperature

40C to 125C

Package

LQFP-64

2 channels

Wide range of baud rate settings using a dedicated baud rate generator (reload timer)

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

LIN-UART

I²C (400 kbps)

A/D converter

1 channel

15 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

16-bit reload timer

(2 channels)

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

Supports External Event Count function.

Free-run Timer 0 (clock input FRCK0) corresponds to ICU0/1.

Free-run Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU4/5/6/7.

16-bit Free-run timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when it matches Output Compare (ch.0, ch.4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

4 channels

16-bit output

compare

Signals an interrupt when 16-bit free-run Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

(Continued)

Document Number: 002-04493 Rev. *A

Page 4 of 84

MB90350E Series

(Continued)

Part Number

MB90F351E

MB90F352E

MB90F351TE

MB90F352TE

MB90F351ES

MB90F352ES

MB90F351TES

MB90F352TES

Parameter

6 channels

16-bit Input capture

Retains 16-bit free-run timer value by (rising edge, falling edge or rising & falling edge) , signals an interrupt.

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters  12

8-bit reload registers for L pulse width  12

8-bit reload registers for H pulse width12

8/16-bit

programmable pulse gen-

erator

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler  8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 s@fosc  4 MHz

(fsys  Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

Compliant with CAN standard Version2.0 Part A and Part B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

16 prioritized message buffers for data and ID

Supports multiple messages.

CAN interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

External interrupt

D/A converter

Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.



Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O ports

Bit-wise settable as input/output or peripheral signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10000 times

Flash memory

Data retention time : 20 years

Boot block configuration

Erase can be performed on each block.

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash (MB90F352E(S) and MB90F352TE(S) only)

Corresponding

evaluation name

MB90V340E-102

MB90V340E-101

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-04493 Rev. *A

Page 5 of 84

MB90350E Series

■ MASK ROM products/Evaluation products

Part Number

MB90351E

MB90351TE

MB90352TE

MB90351ES MB90351TES MB90V340E-1 MB90V340E-1

MB90352E

Parameter

MB90352ES MB90352TES

01

02

Type

CPU

MASK ROM products

F²MC-16LX CPU

Evaluation products

PLL clock multiplication circuit (1, 2, 3, 4, 6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)

System clock

MASK ROM

ROM

RAM

64 Kbytes :

128 Kbytes :

MB90351E(S), MB90351TE(S)

MB90352E(S), MB90352TE(S)

External

4 Kbytes

30 Kbytes

Yes

Emulator-specific power

supply*



Sub clock pin

(X0A, X1A)

(Max 100 kHz)

Yes

No

Yes

Clock supervisor

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

No

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter

4.5 V to 5.5 V : at using external bus

Operating

voltage range

5 V  10

Operating

temperature range

40C to 125C



Package

LQFP-64

PGA-299

2 channels

5 channels

Wide range of baud rate settings using a dedicated baud rate generator (reload timer)

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

LIN-UART

I²C (400 kbps)

A/D converter

1 channel

2 channels

15 channels

24 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

2 channels

4 channels

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

16-bit reload timer

Supports External Event Count function.

Free-run Timer 0

corresponds to ICU0/1/2/3,

OCU0/1/2/3.

Free-run Timer 0 (clock input FRCK0) corresponds to

ICU0/1.

Free-run Timer 1

Free-run Timer 1 (clock input FRCK1) corresponds to

ICU4/5/6/7, OCU4/5/6/7.

corresponds to ICU4/5/6/7,

OCU4/5/6/7.

16-bit free-run timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when it matches Output Compare (ch.0, ch.4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

(Continued)

Document Number: 002-04493 Rev. *A

Page 6 of 84

MB90350E Series

(Continued)

Part Number

MB90351E

MB90352E

MB90351TE

MB90352TE

MB90351ES MB90351TES MB90V340E-1 MB90V340E-1

MB90352ES MB90352TES

01

02

Parameter

4 channels

8 channels

16-bit output

compare

Signals an interrupt when 16-bit free-run Timer matches output compare registers.

A pair of compare registers can be used to generate an output signal.

6 channels

8 channels

16-bit input capture

Retains 16-bit free-run timer value by (rising edge, falling edge, or the both edges), signals an interrupt.

8 channels (16-bit)/

16 channels (8-bit)

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters 16

8-bit reload counters  12

8-bit reload registers for L pulse width12

8-bit reload registers for H pulse width12

8-bit reload registers for

L pulse width 16

8/16-bit

programmable pulse gen-

erator

H pulse width 16

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler  8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 s@fosc  4 MHz

(fsys  Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

3 channels

Compliant with CAN standard Version 2.0 Part A and Part B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

16 prioritized message buffers for data and ID

Supports multiple messages.

CAN interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

16 channels

External interrupt

D/A converter

Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.



2 channels

Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O ports

Bit-wise settable as input/output or peripheral signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Flash memory



Corresponding

evaluation name

MB90V340E-102

MB90V340E-101



* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-04493 Rev. *A

Page 7 of 84

MB90350E Series

2. Product Lineup 2 (With Clock supervisor function)

■ Flash memory products

Part Number

MB90F356E

MB90F357E

MB90F356TE

MB90F357TE

MB90F356ES

MB90F357ES

MB90F356TES

MB90F357TES

Parameter

Type

Flash memory products

F²MC-16LX CPU

CPU

On-chip PLL clock multiplier (1, 2, 3, 4, 6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)

System clock

64 Kbytes Flash memory : MB90F356E(S), MB90F356TE(S)

128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the

same time) : MB90F357E(S), MB90F357TE(S)

ROM

RAM

4 Kbytes

Emulator-specific power

supply*



Sub clock pin

(X0A, X1A)

Yes

No

Clock supervisor

Yes

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

3.5 V to 5.5 V : at normal operating (not using A/D converter)

3.5 V to 5.5 V : at using A/D converter/Flash programming

3.5 V to 5.5 V : at using external bus

Operating

voltage range

Operating

temperature range

40C to 125C

Package

LQFP-64

2 channels

Wide range of baud rate settings using a dedicated baud rate generator (reload timer)

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

LIN-UART

I²C (400 kbps)

A/D converter

1 channel

15 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

16-bit reload timer

(4 channels)

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

Supports External Event Count function.

Free-run Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

Free-run Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.

16-bit free-run timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

4 channels

16-bit output

compare

Signals an interrupt when 16-bit free-run Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

Document Number: 002-04493 Rev. *A

Page 8 of 84

MB90350E Series

(Continued)

Part Number

MB90F356E

MB90F357E

MB90F356TE

MB90F357TE

MB90F356ES

MB90F357ES

MB90F356TES

MB90F357TES

Parameter

6 channels

16-bit input capture

Retains 16-bit free-run timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters 12

8-bit reload registers for L pulse width12

8-bit reload registers for H pulse width12

8/16-bit

programmable pulse gen-

erator

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler  8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 s@fosc  4 MHz

(fsys  Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

External interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.



Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O ports

Bit-wise settable as input/output or peripheral module signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Supports automatic programming, Embedded Algorithm

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10000 times

Flash memory

Data retention time : 20 years

Boot block configuration

Erase can be performed on each block.

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash (MB90F357x only)

Corresponding EVA name

MB90V340E-104

MB90V340E-103

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-04493 Rev. *A

Page 9 of 84

MB90350E Series

■ MASK ROM products/Evaluation products

Part Number

MB90356E

MB90356TE

MB90357TE

MB90356ES MB90356TES MB90V340E-1 MB90V340E-1

MB90357E

Parameter

MB90357ES MB90357TES

03

04

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (1, 2, 3, 4, 6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)

System clock

MASK ROM

ROM

RAM

64 Kbytes

128 Kbytes

:MB90356E(S), MB90356TE(S)

:MB90357E(S), MB90357TE(S)

External

4 Kbytes

30 Kbytes

Yes

Emulator-specific power

supply*



Sub clock pin

(X0A, X1A)

Yes

No

Yes

Clock supervisor

Yes

Low voltage/CPU

operation detection

reset

No

Yes

No

Yes

No

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter

4.5 V to 5.5 V : at using external bus

Operating

voltage range

5 V  10%

Operating

temperature range

40C to 125C



Package

LQFP-64

PGA-299

2 channels

5 channels

Wide range of baud rate settings using a dedicated baud rate generator (reload timer)

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

LIN-UART

I²C (400 kbps)

A/D converter

1 channel

2 channels

15 channels

24 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

16-bit reload timer

(4 channels)

Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys  Machine clock frequency)

Supports External Event Count function.

Free-run Timer 0

corresponds to ICU 0/1/2/3,

OCU 0/1/2/3.

Free-run Timer 0 (clock input FRCK0) corresponds to

ICU 0/1.

Free-run Timer 1

Free-run Timer 1 (clock input FRCK1) corresponds to

ICU 4/5/6/7, OCU 4/5/6/7.

corresponds to ICU 4/5/6/7,

OCU 4/5/6/7.

16-bit free-run timer

(2 channels)

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys  Machine clock frequency)

(Continued)

Document Number: 002-04493 Rev. *A

Page 10 of 84

MB90350E Series

(Continued)

Part Number

MB90356E

MB90357E

MB90356TE

MB90357TE

MB90356ES MB90356TES MB90V340E-1 MB90V340E-1

MB90357ES MB90357TES

03

04

Parameter

4 channels

8 channels

16-bit output

compare

Signals an interrupt when 16-bit free-run Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

6 channels

16-bit input capture

Retains 16-bit free-run timer value by (rising edge, falling edge or rising & falling edge),

signals an interrupt.

8 channels (16-bit)/

16 channels (8-bit)

8-bit reload counters16

8-bit reload registers for

L pulse width16

6 channels (16-bit)/10 channels (8-bit)

8-bit reload counters12

8-bit reload registers for L pulse width 12

8-bit reload registers for H pulse width 12

8/16-bit

8-bit reload registers for

programmable pulse gen-

erator

H pulse width16

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler  8-bit reload counter.

Operation clock frequency : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 s@fosc  4 MHz

(fsys  Machine clock frequency, fosc  Oscillation clock frequency)

1 channel

3 channels

Conforms to CAN Specification Version 2.0 Part A and B.

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID

Supports multiple messages.

CAN interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps.

8 channels

16 channels

2 channels

External interrupt

D/A converter

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA.



Virtually all external pins can be used as general purpose I/O port.

All push-pull outputs

I/O ports

Bit-wise settable as input/output or peripheral module signal

Settable as CMOS schmitt trigger/ automotive inputs

TTL input level settable for external bus (only for external bus pin)

Flash memory



Corresponding EVA name

MB90V340E-104

MB90V340E-103



* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

Document Number: 002-04493 Rev. *A

Page 11 of 84

MB90350E Series

3. Packages and Product Correspondence

MB90351E (S) , MB90351TE (S)

MB90F351E (S) , MB90F351TE (S)

MB90352E (S) , MB90352TE (S)

MB90F352E (S) , MB90F352TE (S)

MB90356E (S) , MB90356TE (S)

MB90F356E (S) , MB90F356TE (S)

MB90357E (S) , MB90357TE (S)

MB90F357E (S) , MB90F357TE (S)

MB90V340E-101

MB90V340E-102

Package

MB90V340E-103

MB90V340E-104

PGA-299C-A01



FPT-64P-M23



(12.0 mm

, 0.65 mm pitch)

, 0.50 mm pitch)

FPT-64P-M24

(10.0 mm



: Yes,  : No

Note : Refer to “Package Dimensions” for detail of each package.

Document Number: 002-04493 Rev. *A

Page 12 of 84

MB90350E Series

4. Pin Assignments

■ MB90351E (S) , MB90351TE (S) , MB90F351E (S) , MB90F351TE (S) , MB90352E (S) , MB90352TE (S) ,

MB90F352E (S) , MB90F352TE (S) , MB90356E (S) , MB90356TE (S) , MB90F356E (S) , MB90F356TE (S) ,

MB90357E (S) , MB90357TE (S) , MB90F357E (S) , MB90F357TE (S)

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P10/AD08/TIN1

P07/AD07/INT15

Vcc

C

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

P25/A21/IN1/ADTG

P44/SDA0/FRCK0

P45/SCL0/FRCK1

P30/ALE/IN4

P31/RD/IN5

P06/AD06/INT14

P05/AD05/INT13

P04/AD04/INT12

P03/AD03/INT11

P02/AD02/INT10

P01/AD01/INT9

P00/AD00/INT8

MD0

P32/WRL/WR/INT10R

P33/WRH

P34/HRQ/OUT4

P35/HAK/OUT5

P36/RDY/OUT6

P37/CLK/OUT7

P60/AN0

MD1

MD2

P41/X1A*

P40/X0A*

P61/AN1

Vss

AVcc

P43/IN7/TX1

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(FPT-64P-M23, FPT-64P-M24)

* : Devices without S-suffix : X0A, X1A

Devices with S-suffix : P40, P41

Document Number: 002-04493 Rev. *A

Page 13 of 84

MB90350E Series

5. Pin Description

I/O

Circuit

type*

Pin No.

Pin name

Function

46

47

45

X1

X0

Oscillation output pin

A

E

Oscillation input pin

RST

Reset input pin

P62 to P67

AN2 to AN7

General purpose I/O ports

Analog input pins for A/D converter

3 to 8

I

PPG4 (5) , 6 (7) , 8

(9) , A (B) ,

Output pins for PPGs

C (D) , E (F)

P50

AN8

General purpose I/O port

9

O

I

Analog input pin for A/D converter

Serial data input pin for UART2

General purpose I/O port

SIN2

P51

10

11

12

AN9

Analog input pin for A/D converter

Serial data output pin for UART2

General purpose I/O port

SOT2

P52

AN10

SCK2

P53

I

Analog input pin for A/D converter

Serial clock I/O pin for UART2

General purpose I/O port

AN11

TIN3

I

Analog input pin for A/D converter

Event input pin for reload timer3

General purpose I/O port

P54

13

AN12

TOT3

P55, P56

AN13, AN14

P42

I

Analog input pin for A/D converter

Output pin for reload timer3

General purpose I/O ports

14, 15

Analog input pins for A/D converter

General purpose I/O port

IN6

Data sample input pin for input capture ICU6

RX input pin for CAN1

16

17

F

RX1

INT9R

P43

External interrupt request input pin for INT9

General purpose I/O port

IN7

Data sample input pin for input capture ICU7

TX output pin for CAN1

TX1

General purpose I/O ports

(devices with S-suffix and MB90V340E-101/103)

P40, P41

X0A, X1A

F

B

19, 20

X0A : Oscillation input pin for sub clock

X1A : Oscillation output pin for sub clock

(devices without S-suffix and MB90V340E-102/104)

(Continued)

Document Number: 002-04493 Rev. *A

Page 14 of 84

MB90350E Series

I/O

Circuit

type*

Pin No.

Pin name

Function

General purpose I/O ports. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

P00 to P07

24 to 31

G

Input/output pins of external address data bus lower 8 bits. This function is enabled when the

external bus is enabled.

AD00 to AD07

INT8 to INT15

P10

External interrupt request input pins for INT8 to INT15

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

32

33

Input/output pin for external bus address data bus bit 8.

This function is enabled when external bus is enabled.

AD08

TIN1

P11

Event input pin for reload timer1

General purpose I/O port. The register can be set to select whether to use a

pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 9. This function is

enabled when external bus is enabled.

AD09

TOT1

P12

Output pin for reload timer1

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 10. This function is enabled when exter-

nal bus is enabled.

AD10

34

N

SIN3

Serial data input pin for UART3

INT11R

External interrupt request input pin for INT11

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

P13

35

36

G

Input/output pin for external bus address data bus bit 11.

This function is enabled when external bus is enabled.

AD11

SOT3

P14

Serial data output pin for UART3

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 12.

This function is enabled when external bus is enabled.

AD12

SCK3

P15

Clock input/output pin for UART3

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

37

38

N

G

Input/output pin for external bus address data bus bit 13.

This function is enabled when external bus is enabled.

AD13

P16

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 14.

This function is enabled when external bus is enabled.

AD14

(Continued)

Document Number: 002-04493 Rev. *A

Page 15 of 84

MB90350E Series

I/O

Circuit

type*

Pin No.

Pin name

Function

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

P17

39

G

Input/output pin for external bus address data bus bit 15.

This function is enabled when external bus is enabled.

AD15

General purpose I/O ports. The register can be set to select whether to use a pull-up resistor.

In external bus mode, the pins are enabled as a general-

purpose I/O port when the corresponding bit in the external address output control register

(HACR) is 1.

P20 to P23

A16 to A19

Output pins for A16 to A19 of the external address data bus.

When the corresponding bit in the external address output control register (HACR) is 0, the pins

are enabled as high address output pins A16 to A19.

40 to 43

G

PPG9 (8)

PPGB (A)

PPGD (C)

PPGF (E)

Output pins for PPGs

General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In

external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output control register

(HACR) is 1.

P24

44

G

Output pin for A20 of the external address data bus. When the corresponding bit in the external

address output control register (HACR) is 0, the pin is

enabled as high address output pin A20.

A20

IN0

Data sample input pin for input capture ICU0

General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In

external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output control register

(HACR) is 1.

P25

51

G

Output pin for A21 of the external address data bus. When the corresponding bit in the external

address output control register (HACR) is 0, the pin is enabled as high address output pin A21.

A21

IN1

ADTG

P44

Data sample input pin for input capture ICU1

Trigger input pin for A/D converter

General purpose I/O port

52

53

SDA0

FRCK0

P45

H

Serial data I/O pin for I²C 0

Input pin for the 16-bit Free-run Timer 0

General purpose I/O port

SCL0

FRCK1

Serial clock I/O pin for I²C 0

Input pin for the 16-bit Free-run Timer 1

(Continued)

Document Number: 002-04493 Rev. *A

Page 16 of 84

MB90350E Series

I/O

Circuit

type*

Pin No.

Pin name

Function

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

P30

54

G

ALE

IN4

Address latch enable output pin. This function is enabled when external bus is enabled.

Data sample input pin for input capture ICU4

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

P31

55

56

RD

IN5

Read strobe output pin for data bus. This function is enabled when external bus is enabled.

Data sample input pin for input capture ICU5

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled either in single-chip mode or with the WR/WRL pin output disabled.

P32

Write strobe output pin for the data bus. This function is enabled when both the external bus

and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data

bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit access.

G

WR/WRL

INT10R

P33

External interrupt request input pin for INT10

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled either in single-chip mode, in

external bus 8-bit mode or with the WRH pin output disabled.

57

Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the

external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH

output pin is enabled.

WRH

P34

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled either in single-chip mode or with the hold function disabled.

58

59

60

G

Hold request input pin. This function is enabled when both the external bus and the hold func-

tion are enabled.

HRQ

OUT4

P35

Wave form output pin for output compare OCU4

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled either in single-chip mode or with the hold function disabled.

Hold acknowledge output pin. This function is enabled when both the

external bus and the hold function are enabled.

HAK

OUT5

P36

Wave form output pin for output compare OCU5

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled either in single-chip mode or with the external ready function disabled.

Ready input pin. This function is enabled when both the external bus and the external ready

function are enabled.

RDY

OUT6

Wave form output pin for output compare OCU6

(Continued)

Document Number: 002-04493 Rev. *A

Page 17 of 84

MB90350E Series

(Continued)

I/O

Circuit

type*

Pin No.

Pin name

Function

General purpose I/O port. The register can be set to select whether to use a pull-up resistor.

This function is enabled either in single-chip mode or with the CLK output disabled.

P37

CLK

61

G

CLK output pin. This function is enabled when both the external bus and CLK output are en-

abled.

OUT7

P60, P61

AN0, AN1

AV_CC

Wave form output pin for output compare OCU7

General purpose I/O ports

62, 63

I

Analog input pins for A/D converter

64

2

K

L

V_CCpower input pin for analog circuits

Reference voltage input for the A/D converter. This power supply must be turned on or off

AVRH

while a voltage higher than or equal to AVRH is applied to AV_CC

V_SSpower input pin for analog circuits

Input pins for specifying the operating mode

Input pin for specifying the operating mode

Power (3.5 V to 5.5 V) input pin

.

1

AV_SS

MD1, MD0

MD2

K

C

D



22, 23

21

49

V_CC

18, 48

V_SS

Power (0 V) input pins

This is the power supply stabilization capacitor pin. It should be connected to a higher than or

equal to 0.1 F ceramic capacitor.

50

C

K

* : For the I/O circuit type, refer to “I/O Circuit Type”.

Document Number: 002-04493 Rev. *A

Page 18 of 84

MB90350E Series

6. I/O Circuit Type

Type

Circuit

Remarks

Oscillation circuit

High-speed oscillation feedback

resistor = approx. 1 M

X1

Xout

A

X0

Standby control signal

Oscillation circuit

Low-speed oscillation feedback

resistor = approx. 10 M

X1A

Xout

B

X0A

Standby control signal

■ MASK ROM device

CMOS hysteresis input pin

R

CMOS

C

■ Flash memory device

hysteresis

CMOS input pin

inputs

■ MASK ROM device

CMOS hysteresis input pin

Pull-down resistor value: approx. 50 k

R

CMOS

hysteresis

inputs

■ Flash memory device

CMOS input pin

No Pull-down

D

Pull-down

resistor

CMOS hysteresis input pin

Pull-up resistor value: approx. 50 k

Pull-up

E

resistor

R

CMOS

hysteresis

inputs

(Continued)

Document Number: 002-04493 Rev. *A

Page 19 of 84

MB90350E Series

Type

Circuit

Remarks

^■(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

■ CMOS hysteresis inputs (With input

P-ch

N-ch

Pout

shutdown function when is standby)

■ Automotive input (With the standby-time input

shutdown function)

Nout

R

F

CMOS

hysteresis inputs

Automotive input

Standby control for

input shutdown

^■(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

■ CMOS hysteresis inputs (With the standby-time

Pull-up control

Pout

Pull-up

resistor

P-ch

input shutdown function)

■ Automotive input (With the standby-time input

shutdown function)

N-ch

Nout

■ TTL input (With the standby-time input shutdown

function)

R

G

■ Programmable pull-up resistor:

approx. 50 k

CMOS

hysteresis inputs

Automotive input

TTL input

Standby control for

input shutdown

^■(^CI_O^M_L^O=^S3^lem^vA^el, ^oI_O^u_H^tp^ut3 mA)

■ CMOS hysteresis inputs (With the standby-time

P-ch

N-ch

Pout

Nout

input shutdown function)

■ Automotive input (With the standby-time input

shutdown function)

H

R

CMOS

hysteresis inputs

Automotive input

Standby control for

input shutdown

(Continued)

Document Number: 002-04493 Rev. *A

Page 20 of 84

MB90350E Series

Type

Circuit

Remarks

■ CMOS level output

(I_OL= 4 mA, I_OH= 4 mA)

■ CMOS hysteresis inputs (With the standby-time

P-ch

N-ch

Pout

input shutdown function)

■ Automotive input (With the standby-time input

shutdown function)

Nout

R

■ Analog input for A/D converter

I

CMOS

hysteresis inputs

Automotive input

Standby control for

input shutdown

Analog input

Protection circuit for power supply input

P-ch

N-ch

K

■ With the protection circuit of A/D

converter reference voltage power

input pin

ANE

AVR

P-ch

N-ch

■ Flash memory devices do not have a

protection circuit against V_CCfor pin

AVRH.

L

ANE

(Continued)

Document Number: 002-04493 Rev. *A

Page 21 of 84

MB90350E Series

(Continued)

Type

Circuit

Pull-up control

Remarks

^■(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

■ CMOS inputs (With the standby-time

Pull-up

resistor

P-ch

N-ch

P-ch

input shutdown function)

Pout

Nout

■ Automotive input (With the standby-time input

shutdown function)

■ TTL input (With the standby-time input shutdown

function)

R

N

■ Programmable pull-up resistor:

approx. 50 k

CMOS inputs

Automotive input

TTL input

Standby control for

input shutdown

^■(^CI_O^M_L^O=^S4^lem^vA^el, ^oI_O^u_H^tp^ut4 mA)

■ CMOS inputs (With the standby-time

P-ch

N-ch

Pout

input shutdown function)

■ Automotive input (With the standby-time input

shutdown function)

Nout

R

■ Analog input for A/D converter

O

CMOS inputs

Automotive input

Standby control for

input shutdown

Analog input

7. Handling Devices

1. Preventing latch-up

CMOS IC may suffer latch-up under the following conditions :

■A voltage higher than V_CCor lower than V_SSis applied to an input or output pin.

■A voltage higher than the rated voltage is applied between V_CCand V_SSpins.

■The AV_CCpower supply is applied before the V_CCvoltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, also be careful not to let the analog power-supply voltage (AV_CC, AVRH) exceed the digital power-supply

voltage (V_CC) .

2. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore

they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k.

Unused I/O pins should be set to the output state and can be left open, or the input state with the above described connection.

Document Number: 002-04493 Rev. *A

Page 22 of 84

MB90350E Series

3. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90350E Series

X0

X1

Open

4. Precautions for when not using a sub clock signal

X0A and X1A are oscillation pins for sub clock. If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on

the X0A pin, and leave the X1A pin open.

5. Notes on during operation of PLL clock mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode

is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Cypress

will not guarantee results of operations if such failure occurs.

6. Treatment of Power Supply Pins (V_CC/V_SS

)

■ If there are multiple V_CCand V_SSpins, from the point of view of device design, pins to be of the same potential are connected inside

of the device to prevent malfunction such as latch-up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard

for total output current, be sure to connect the V_CCand V_SSpins to the power supply and ground externally.

Connect V_CCand V_SSpins to the device from the current supply source at a possibly low impedance.

■ As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 F as a bypass capacitor between

V_CCand V_SSpins in the vicinity of V_CCand V_SSpins of the device.

Vcc

Vss

Vcc

Vss

Vcc

MB90350E

Series

Vcc

Vss

Vcc

Vss

7. Pull-up/down resistors

The MB90350E series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external

components where needed.

8. Crystal oscillator circuit

Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly

recommended that printed circuit artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal

oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits.

Document Number: 002-04493 Rev. *A

Page 23 of 84

MB90350E Series

Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.

9. Turning-on sequence of power supply to A/D converter and analog inputs

Make sure to turn on the A/D converter power supply (AV_CC, AVRH) and analog inputs (AN0 to AN14) after turning-on the digital power

supply (V_CC) .Turn-off the digital power after turning off the A/D converter power

supply and analog inputs. In this case, make sure that the power supply voltage does not exceed the rated voltage of the A/D converter

(turning on/of the analog and digital power supplies simultaneously is acceptable).

10. Connection of unused pins of A/D converter if A/D converter is not used

Connect unused pins of A/D converter to AV_CC V_CC, AV_SS AVRH  V_SS

.

11. Notes on energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at

⁵⁰s or more (0.2 V to 2.7 V) .

12. Stabilization of power supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the V_CCsupply voltage operating range.

Therefore, the V_CCsupply voltage should be stabilized. For reference, the supply voltage should be controlled so that V_CCripple

variations (peak- to-peak values) at commercial frequencies (50 MHz/

60 MHz) fall below 10 of the standard V_CCsupply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instanta-

neous power switching.

Document Number: 002-04493 Rev. *A

Page 24 of 84

MB90350E Series

13. Serial Communication

There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed

circuit board so as to avoid noise.

Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data due

to the noise.

14. Port 0 to port 3 output during power-on (External-bus mode)

As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of

Port 0 to Port 3 might be unstable regardless of reset inputs.

1/2 VCC

VCC

Port 0 to Port 3

Port 0 to Port 3 outputs Port 0 to Port 3 outputs = Hi-Z

might be unstable.

15. Setting using CAN function

To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR).

16. Flash security function

The security byte is located in the area of the Flash memory. If protection code 01_His written in the security byte, the Flash memory

is in the protected state by security.

Therefore please do not write 01_Hin this address if you do not use the security function.

Please refer to following table for the address of the security byte.

Product name

Flash memory size

Address for security bit

MB90F352E(S)

MB90F352TE(S)

MB90F357E(S)

MB90F357TE(S)

Embedded 1 Mbit Flash memory

FE0001_H

17. Operation with T_A 105C or more

^{If used exceeding T}_A 105C, please contact Cypress sales representatives for reliability limitations.

18. Low voltage/CPU operation reset circuit

The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below

a given voltage level. When a low voltage condition is detected, an internal reset signal is generated.

The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset

signal if not cleared within a given time after startup.

(1) Low voltage detection reset circuit

Detection voltage

4.0 V  0.3 V

When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an internal reset signal is

output.

Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage condition generates

an internal reset and releases stop mode.

Document Number: 002-04493 Rev. *A

Page 25 of 84

MB90350E Series

During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the output of this internal

reset, the reset output from the low voltage detection reset circuit is suppressed.

(2) CPU operation detection reset circuit

The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts automatically after a

power-on reset, and must be continually and regularly cleared within a given time. If the given time interval elapses and the counter

has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal

reset generated from the CPU operation detection circuit has a width of 5 machine cycles.

Interval time

20

2 /F (approx. 262 ms*)

C

* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.

During recovery from standby mode, the detection period is the maximum interval plus 20 s.

This circuit does not operate in modes where CPU operation is stopped.

The CPU operation detection reset circuit counter is cleared under any of the following conditions.

■“0” writing to CL bit of LVRC register

■Internal reset

■Main oscillation clock stop

■Transit to sleep mode

■Transit to timebase timer mode and watch mode

19. Internal CR oscillation circuit

Value

Parameter

Symbol

Unit

Min

50

Typ

100



Max

200

Oscillation frequency

f_RC

kHz

Oscillation stabilization wait time

tstab



100

s

Document Number: 002-04493 Rev. *A

Page 26 of 84

MB90350E Series

8. Block Diagrams

■ MB90V340E-101/102

X0

X0A*

Clock

controller

2

F MC-16LX

RST

X1

CPU

X1A*

Free-run

timer 0

RAM

30 Kbytes

FRCK0

Input

capture

IN7 to IN0

8 channels

Output

compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

5 channels

Free-run

timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

controller

3 channels

LIN-UART

5 channels

RX2 to RX0

TX2 to TX0

16-bit

reload timer

4 channels

AVCC

AVSS

TIN3 to TIN0

8/10-bit

A/D

converter

24 channels

TOT3 to TOT0

AN23 to AN0

AVRH

AD15 to AD00

A21 to A16

ALE

AVRL

ADTG

10-bit

D/A

converter

2 channels

RD

External

bus

interface

WR/WRL

WRH

DA00,DA01

HRQ

HAK

8/16-bit

PPG

PPGF to PPG0

RDY

16/8 channels

CLK

2

SDA0,SDA1

SCL0,SCL1

I C interface

INT7 to INT0

DTP/

External

interrupt

2 channels

INT15 to INT8

(INT11R to INT9R)

DMAC

Clock

CKOT

monitor

* : MB90V340E-102 only

Document Number: 002-04493 Rev. *A

Page 27 of 84

MB90350E Series

■ MB90V340E-103/104

X0

X0A*

RST

X1

X1A*

Clock

control-

ler/Monitor

2

F MC-16LX

CPU

Free-run

timer 0

FRCK0

CRoscillation

circuit

Input

capture

IN7 to IN0

8 channels

RAM

30 Kbytes

Output

compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

5 channels

Free-run

timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

controller

3 channels

LIN-UART

5 channels

RX2 to RX0

TX2 to TX0

16-bit

reload

AVCC

AVSS

AN23 to AN0

AVRH

TIN3 to TIN0

TOT3 to TOT0

8/10-bit

A/D

converter

24 channels

timer

4 channels

AVRL

ADTG

AD15 to AD00

A23 to A16

ALE

RD

WRL

10-bit

D/A

converter

2 channels

External

bus

interface

DA01, DA00

WRH

HRQ

HAK

RDY

CLK

8/16-bit

PPG

16/8 channels

PPGF to PPG0

2

SDA1, SDA0

SCL1, SCL0

I C interface

INT15 to INT8

(INT15R to INT8R)

INT7 to INT0

DTP/External

interrupt

2 channels

DMA

Clock

monitor

CKOT

* : MB90V340E-104 only

Document Number: 002-04493 Rev. *A

Page 28 of 84

MB90350E Series

■ MB90351E (S) , MB90351TE (S) , MB90F351E (S) , MB90F351TE (S) , MB90352E (S) , MB90352TE (S) , MB90F352E (S)

MB90F352TE (S)

X0

X0A *¹

Clock

controller

2

F MC-16LX

RST

X1

CPU

X1A*¹

Low voltage/

CPU operation

detection

Free-run

timer 0

FRCK0

reset*²

Input

capture

6 channels

RAM

4 Kbytes

IN7 to IN4,

IN1, IN0

ROM/Flash

128 Kbytes/

64 Kbytes

Output

compare

4 channels

OUT7 to OUT4

FRCK1

Prescaler

2 channels

Free-run

timer 1

SOT3, SOT2

SCK3, SCK2

SIN3, SIN2

CAN

controller

1 channel

RX1

TX1

LIN-UART

2 channels

AVCC

AVSS

TIN3, TIN1

16-bit

reload timer

2 channels

TOT3, TOT1

AN14 to AN0

8/10-bit

A/D

AVRH

ADTG

AD15 to AD00

A21 to A16

converter

15 channels

ALE

RD

WR/WRL

External

bus

interface

WRH

HRQ

PPGF to PPG8

PPG6, PPG4

8/16-bit

PPG

HAK

RDY

CLK

10/6 channels

2

SDA0

SCL0

I C interface

1 channel

INT15 to INT8

DTP/

External

interrupt

(INT11R to INT9

DMAC

*1 : Only for devices without “S”-suffix

*2 : Only for devices with “T”-suffix

Document Number: 002-04493 Rev. *A

Page 29 of 84

MB90350E Series

■ MB90356E (S) , MB90356TE (S) , MB90F356E (S) , MB90F356TE (S) , MB90357E (S) , MB90357TE (S) , MB90F357E (S) ,

MB90F357TE (S)

X0

Clock

control-

ler/Monitor

X0A*¹

RST

X1

2

F MC-16LX

CPU

X1A*¹

CR

oscillation

circuit

Free-run

timer 0

FRCK0

Input

capture

6 channels

Low voltage/

IN7 to IN4,

IN1, IN0

CPU operation

detector reset*²

Output

compare

4 channels

OUT7 to OUT4

FRCK1

RAM

4 Kbytes

Free-run

timer 1

ROM/Flash

128 Kbytes/

64 Kbytes

CAN

controller

1 channel

RX1

TX1

Prescaler

2 channels

16-bit

reload timer

4 channels

TIN3, TIN1

SOT3, SOT2

SCK3, SCK2

SIN3, SIN2

LIN-UART

2 channels

TOT3, TOT1

AVCC

AVSS

AD15 to AD00

A21 to A16

ALE

8/10-bit

A/D

AN14 to AN0

converter

15 channels

RD

AVRH

ADTG

WR/WRL

WRH

External

bus

interface

HRQ

HAK

8/16-bit

PPG

10/6 channels

PPGF to PPG8

PPG6, PPG4

RDY

CLK

2

SDA0

SCL0

I C interface

External

interrupt

1 channel

INT15 to INT8

(INT11R to INT9R)

DMAC

*1 : Only for devices without “S”-suffix

*2 : Only for devices with “T”-suffix

Document Number: 002-04493 Rev. *A

Page 30 of 84

MB90350E Series

9. Memory Map

MB90352E (S)

MB90352TE (S)

MB90F352E (S)

MB90F352TE (S)

MB90357E (S)

MB90357TE (S)

MB90F357E (S)

MB90F357TE (S)

MB90351E (S)

MB90351TE (S)

MB90F351E (S)

MB90F351TE (S)

MB90356E (S)

MB90356TE (S)

MB90F356E (S)

MB90F356TE (S)

MB90V340E-101

MB90V340E-102

MB90V340E-103

MB90V340E-104

FFFFFFH

FF0000H

FFFFFFH

ROM (FF bank)

ROM (FE bank)

FF0000H

FEFFFFH

FF0000H

FEFFFFH

ROM (FE bank)

ROM (FD bank)

FE0000H

FDFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (F8 bank)

External access

area

External access

area

FC0000H

FBFFFFH

FB0000H

FAFFFFH

C00100H

00FFFFH

C00100H

00FFFFH

FA0000H

F9FFFFH

F90000H

F8FFFFH

ROM

(image of FF bank)

ROM

(image of FF bank)

F80000H

00FFFFH

008000H

007FFFH

External access area

008000H

007FFFH

ROM

(image of FF bank)

Peripheral

008000H

007FFFH

007900H

Peripheral

007900H

0078FFH

RAM 30 Kbytes

001100H

0010FFH

001100H

0010FFH

RAM 4 Kbytes

External access area

Peripheral

RAM 4 Kbytes

000100H

External access area

0000EFH

000000H

0000EFH

000000H

0000EFH

000000H

Peripheral

: No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.

Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer

declaration.

For example, an attempt to access 00C000_Hpractically accesses the value at FFC000_Hin ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000_Hand FFFFFF_His visible in bank 00, while the image between FF0000_Hand FF7FFF_His visible

only in bank FF.

Document Number: 002-04493 Rev. *A

Page 31 of 84

MB90350E Series

10. I/O Map

Address

Register

Abbreviation Access

Resource name

Initial value

XXXXXXXX_B

000000_H

000001_H

000002_H

000003_H

000004_H

000005_H

000006_H

Port 0 Data Register

Port 1 Data Register

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 2 Data Register

Port 3 Data Register

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

000007_Hto

00000A_H

Reserved

00000B_H

00000C_H

00000D_H

00000E_H

00000F_H

000010_H

000011_H

000012_H

000013_H

000014_H

000015_H

000016_H

Port 5 Analog Input Enable Register

Port 6 Analog Input Enable Register

ADER5

ADER6

R/W

Port 5, A/D

Port 6, A/D

11111111_B

Reserved

Input Level Select Register 0

Input Level Select Register 1

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

Port 3 Direction Register

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

ILSR0

ILSR1

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

R/W

Ports

00000000_B

XX000000_B

00000000_B

XX000000_B

X0000000_B

00000000_B

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

000017_Hto

000019_H

Reserved

00001A_H

00001B_H

00001C_H

00001D_H

00001E_H

00001F_H

SIN input Level Setting Register

DDRA

Reserved

W

UART2, UART3

X00XXXXX_B

Port 0 Pull-up Control Register

Port 1 Pull-up Control Register

Port 2 Pull-up Control Register

Port 3 Pull-up Control Register

PUCR0

PUCR1

PUCR2

PUCR3

R/W

Port 0

Port 1

Port 2

Port 3

00000000_B

000020_Hto

000037_H

Reserved

(Continued)

Document Number: 002-04493 Rev. *A

Page 32 of 84

MB90350E Series

Address

Register

Abbreviation Access

Resource name

Initial value

0X000XX1_B

0X000001_B

000000X0_B

000038_HPPG 4 Operation Mode Control Register

000039_HPPG 5 Operation Mode Control Register

00003A_HPPG 4/5 Count Clock Select Register

PPGC4

PPGC5

PPG45

W, R/W

R/W

16-bitProgrammablePulse

Generator 4/5

Address Match

Detection 1

00003B_HAddress Detect Control Register 1

PACSR1

R/W

00000000_B

00003C_HPPG 6 Operation Mode Control Register

00003D_HPPG 7 Operation Mode Control Register

00003E_HPPG 6/7 Count Clock Select Register

00003F_H

PPGC6

PPGC7

PPG67

W, R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bitProgrammablePulse

Generator 6/7

Reserved

000040_HPPG 8 Operation Mode Control Register

000041_HPPG 9 Operation Mode Control Register

000042_HPPG 8/9 Count Clock Select Register

000043_H

PPGC8

PPGC9

PPG89

W, R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bitProgrammablePulse

Generator 8/9

Reserved

000044_HPPG A Operation Mode Control Register

000045_HPPG B Operation Mode Control Register

000046_HPPG A/B Count Clock Select Register

000047_H

PPGCA

PPGCB

PPGAB

W, R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bitProgrammablePulse

Generator A/B

Reserved

000048_HPPG C Operation Mode Control Register

000049_HPPG D Operation Mode Control Register

00004A_HPPG C/D Count Clock Select Register

00004B_H

PPGCC

PPGCD

W,R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bitProgrammablePulse

Generator C/D

Reserved

00004C_HPPG E Operation Mode Control Register

00004D_HPPG F Operation Mode Control Register

00004E_HPPG E/F Count Clock Select Register

00004F_H

PPGCE

PPGCF

PPGEF

W,R/W

R/W

0X000XX1_B

0X000001_B

000000X0_B

16-bitProgrammablePulse

Generator E/F

Reserved

Input Capture Control Status

Register 0/1

000050_H

ICS01

ICE01

R/W

00000000_B

Input Capture 0/1

000051_HInput Capture Edge Register 0/1

R/W, R

XXX0X0XX_B

000052_H,

000053_H

Reserved

Input Capture Control Status

Register 4/5

000054_H

ICS45

ICE45

ICS67

ICE67

R/W

R

00000000_B

XXXXXXXX_B

00000000_B

XXX000XX_B

Input Capture 4/5

Input Capture 6/7

000055_HInput Capture Edge Register 4/5

Input Capture Control Status

Register 6/7

000056_H

R/W

R/W, R

000057_HInput Capture Edge Register 6/7

(Continued)

Document Number: 002-04493 Rev. *A

Page 33 of 84

MB90350E Series

Address

Register

Abbreviation Access

Resource name

Initial value

000058_H

to

Reserved

00005B_H

Output Compare Control Status

Register 4

00005C_H

00005D_H

00005E_H

00005F_H

OCS4

OCS5

OCS6

OCS7

R/W

0000XX00_B

0XX00000_B

0000XX00_B

0XX00000_B

Output Compare 4/5

Output Compare 6/7

Output Compare Control Status

Register 5

Output Compare Control Status

Register 6

Output Compare Control Status

Register 7

000060_HTimer Control Status Register 0

000061_HTimer Control Status Register 0

000062_HTimer Control Status Register 1

000063_HTimer Control Status Register 1

000064_HTimer Control Status Register 2

000065_HTimer Control Status Register 2

000066_HTimer Control Status Register 3

000067_HTimer Control Status Register 3

000068_HA/D Control Status Register 0

000069_HA/D Control Status Register 1

00006A_HA/D Data Register 0

TMCSR0

TMCSR1

TMCSR2

TMCSR3

ADCS0

R/W

R

00000000_B

XXXX0000_B

00000000_B

XXXX0000_B

00000000_B

XXXX0000_B

00000000_B

XXXX0000_B

000XXXX0_B

0000000X_B

00000000_B

XXXXXX00_B

00000000_B

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

ADCS1

ADCR0

A/D Converter

00006B_HA/D Data Register 1

ADCR1

R

00006C_HADC Setting Register 0

ADSR0

R/W

00006D_HADC Setting Register 1

ADSR1

Low Voltage/CPU Operation Detection Reset

Control Register

Low Voltage/CPU

Operation Detection Reset

00006E_H

LVRC

R/W, W

W

00111000_B

00006F_HROM Mirror Function Select Register

ROMM

ROM Mirror

XXXXXXX1_B

000070_H

to

Reserved

00007F_H

000080_H

to

Reserved for CAN controller 1. Refer to “CAN Controllers”

00008F_H

000090_H

to

Reserved

00009A_H

(Continued)

Document Number: 002-04493 Rev. *A

Page 34 of 84

MB90350E Series

Address

Register

Abbreviation

DCSR

Access

R/W

Resource name

Initial value

00000000_B

00009B_HDMA Descriptor Channel Specification Register

00009C_HDMA Status Register L Register

DSRL

R/W

DMA

00009D_HDMA Status Register H Register

DSRH

R/W

Address Match

Detection 0

00009E_HAddress Detect Control Register 0

00009F_HDelayed Interrupt/Release Register

PACSR0

DIRR

R/W

00000000_B

Delayed Interrupt

XXXXXXX0_B

Low Power

Consumption

Control Circuit

Low-power Consumption Mode

0000A0_H

LPMCR

CKSCR

W,R/W

R,R/W

00011000_B

11111100_B

Control Register

Low Power

Consumption

Control Circuit

0000A1_HClock Selection Register

0000A2_H,

0000A3_H

Reserved

DSSR

0000A4_HDMA Stop Status Register

R/W

W

DMA

00000000_B

0011XX00_B

Automatic Ready Function Selection

0000A5_H

Register

ARSR

External Memory

Access

0000A6_HExternal Address Output Control Register

0000A7_HBus Control Signal Selection Register

0000A8_HWatchdog Control Register

0000A9_HTimebase Timer Control Register

0000AA_HWatch Timer Control Register

0000AB_H

HACR

ECSR

WDTC

TBTC

W

00000000_B

0000000X_B

XXXXX111_B

1XX00100_B

1X001000_B

R,W

Watchdog Timer

Timebase timer

Watch Timer

W,R/W

R,R/W

WTC

Reserved

DERL

0000AC_HDMA Enable Register L Register

0000AD_HDMA Enable Register H Register

R/W

00000000_B

DMA

DERH

Flash Control Status Register

0000AE_H(Flash Devices only. Otherwise

reserved)

FMCS

R,R/W

Flash memory

000X0000_B

0000AF_H

Reserved

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

0000B0_HInterrupt Control Register 00

0000B1_HInterrupt Control Register 01

0000B2_HInterrupt Control Register 02

0000B3_HInterrupt Control Register 03

0000B4_HInterrupt Control Register 04

0000B5_HInterrupt Control Register 05

0000B6_HInterrupt Control Register 06

0000B7_HInterrupt Control Register 07

0000B8_HInterrupt Control Register 08

W,R/W

00000111_B

Interrupt Control

(Continued)

Document Number: 002-04493 Rev. *A

Page 35 of 84

MB90350E Series

Address

Register

Abbreviation

ICR09

Access

W,R/W

Resource name

Initial value

00000111_B

0000B9_HInterrupt Control Register 09

0000BA_HInterrupt Control Register 10

0000BB_HInterrupt Control Register 11

0000BC_HInterrupt Control Register 12

0000BD_HInterrupt Control Register 13

0000BE_HInterrupt Control Register 14

0000BF_HInterrupt Control Register 15

ICR10

ICR11

ICR12

Interrupt Control

ICR13

ICR14

ICR15

0000C0_H

to 0000C9_H

Reserved

0000CA_HExternal Interrupt Enable Register 1

0000CB_HExternal Interrupt Source Register 1

0000CC_HExternal Interrupt Level Register 1

0000CD_HExternal Interrupt Level Register 1

ENIR1

EIRR1

ELVR1

R/W

00000000_B

XXXXXXXX_B

00000000_B

External Interrupt 1

External Interrupt Source Select

0000CE_H

Register

EISSR

PSCCR

BAPL

R/W

W

00000000_B

XXXX0000_B

XXXXXXXX_B

0000CF_HPLL/Sub clock Control register

PLL

DMA Buffer Address Pointer L

0000D0_H

Register

R/W

DMA Buffer Address Pointer M

0000D1_H

Register

BAPM

R/W

XXXXXXXX_B

DMA Buffer Address Pointer H

0000D2_H

Register

BAPH

DMACS

IOAL

R/W

XXXXXXXX_B

0000D3_HDMA Control Register

DMA

I/O Register Address Pointer L

0000D4_H

Register

I/O Register Address Pointer H

0000D5_H

Register

IOAH

R/W

XXXXXXXX_B

0000D6_HData Counter L Register

0000D7_HData Counter H Register

0000D8_HSerial Mode Register 2

0000D9_HSerial Control Register 2

DCTL

DCTH

SMR2

SCR2

R/W

XXXXXXXX_B

00000000_B

W,R/W

Reception/Transmission Data

0000DA_H

Register 2

RDR2/TDR2

SSR2

R/W

00000000_B

00001000_B

000000XX_B

0000DB_HSerial Status Register 2

R,R/W

UART2

R,W,

R/W

0000DC_HExtended Communication Control Register 2

ECCR2

0000DD_HExtended Status/Control Register 2

0000DE_HBaud Rate Generator Register 20

ESCR2

BGR20

R/W

00000100_B

00000000_B

(Continued)

Document Number: 002-04493 Rev. *A

Page 36 of 84

MB90350E Series

Address

Register

Abbreviation

Access

Resource name

Initial value

0000DF_H

Baud Rate Generator Register 21

BGR21

R/W

UART2

00000000_B

0000E0_H

to 0000EF_H

Reserved

0000F0_H

to 0000FF_H

External area

Reserved

007900_H

to

007907_H

007908_H

007909_H

00790A_H

00790B_H

00790C_H

00790D_H

00790E_H

00790F_H

007910_H

007911_H

007912_H

007913_H

007914_H

007915_H

007916_H

007917_H

007918_H

007919_H

00791A_H

00791B_H

00791C_H

00791D_H

00791E_H

00791F_H

007920_H

007921_H

007922_H

007923_H

Reload Register L4

Reload Register H4

Reload Register L5

Reload Register H5

Reload Register L6

Reload Register H6

Reload Register L7

Reload Register H7

Reload Register L8

Reload Register H8

Reload Register L9

Reload Register H9

Reload Register LA

Reload Register HA

Reload Register LB

Reload Register HB

Reload Register LC

Reload Register HC

Reload Register LD

Reload Register HD

Reload Register LE

Reload Register HE

Reload Register LF

Reload Register HF

Input Capture Register 0

Input Capture Register 1

PRLL4

R/W

R

XXXXXXXX_B

16-bit Programmable

Pulse

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

PRLLC

PRLHC

PRLLD

PRLHD

PRLLE

PRLHE

PRLLF

PRLHF

IPCP0

IPCP1

Generator 4/5

16-bit Programmable

Pulse

Generator 6/7

16-bit Programmable

Pulse

Generator 8/9

16-bit Programmable

Pulse

Generator A/B

16-bit Programmable

Pulse

Generator C/D

16-bit Programmable

Pulse

Generator E/F

R

Input Capture 0/1

R

(Continued)

Document Number: 002-04493 Rev. *A

Page 37 of 84

MB90350E Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

007924_H

to

Reserved

007927_H

007928_H

007929_H

00792A_H

00792B_H

00792C_H

00792D_H

00792E_H

00792F_H

Input Capture Register 4

IPCP4

IPCP5

IPCP6

IPCP7

R

XXXXXXXX_B

Input Capture Register 4

Input Capture Register 5

Input Capture Register 6

Input Capture Register 7

Input Capture 4/5

Input Capture 6/7

007930_H

to

Reserved

007937_H

007938_H

007939_H

00793A_H

00793B_H

00793C_H

00793D_H

00793E_H

00793F_H

007940_H

007941_H

007942_H

007943_H

007944_H

007945_H

007946_H

007947_H

007948_H

007949_H

00794A_H

00794B_H

00794C_H

00794D_H

00794E_H

00794F_H

Output Compare Register 4

Output Compare Register 5

Output Compare Register 6

Output Compare Register 7

Timer Data Register 0

OCCP4

OCCP5

OCCP6

OCCP7

TCDT0

TCCSL0

TCCSH0

TCDT1

TCCSL1

TCCSH1

R/W

XXXXXXXX_B

00000000_B

Output Compare 4/5

Output Compare 6/7

Free-run Timer 0

Timer Data Register 0

00000000_B

Timer Control Status Register 0

Timer Data Register 1

00000000_B

0XXXXXXX_B

00000000_B

Timer Data Register 1

00000000_B

Free-run Timer 1

Timer Control Status Register 1

00000000_B

0XXXXXXX_B

XXXXXXXX_B

TMR0/TMRL

R0

16-bit Reload

Timer 0

Timer Register 0/Reload Register 0

Timer Register 1/Reload Register 1

Timer Register 2/Reload Register 2

Timer Register 3/Reload Register 3

TMR1/TMRL

R1

16-bit Reload

Timer 1

TMR2/TMRL

R2

16-bit Reload

Timer 2

TMR3/TMRL

R3

16-bit Reload

Timer 3

(Continued)

Document Number: 002-04493 Rev. *A

Page 38 of 84

MB90350E Series

Address

Register

Abbreviation Access

Resource name

Initial value

00000000_B

007950_HSerial Mode Register 3

007951_HSerial Control Register 3

SMR3

SCR3

W, R/W

Reception/Transmission Data

Register 3

007952_H

RDR3/TDR3

SSR3

R/W

00000000_B

00001000_B

000000XX_B

007953_HSerial Status Register 3

R,R/W

UART3

Extended Communication Control

Register 3

R,W,

R/W

007954_H

ECCR3

007955_HExtended Status Control Register 3

007956_HBaud Rate Generator Register 30

007957_HBaud Rate Generator Register 31

ESCR3

BGR30

BGR31

R/W

00000100_B

00000000_B

007958_H,

007959_H

Reserved

CSVCR

007960_HClock supervisor Control Register

R, R/W

Clock Supervisor

CAN Clock Sync

00011100_B

007961_H

to

Reserved

00796D_H

00796E_HCAN Direct Mode Register

CDMR

Reserved

IBSR0

R/W

XXXXXXX0_B

00796F_H

007970_HI²C Bus Status Register 0

007971_HI²C Bus Control Register 0

R

W,R/W

R/W

00000000_B

11111111_B

00111111_B

00000000_B

01111111_B

00000000_B

IBCR0

007972_H

ITBAL0

ITBAH0

ITMKL0

ITMKH0

ISBA0

I²C 10-bit Slave Address Register 0

007973_H

007974_H

I²C Interface 0

I²C 10-bit Slave Address Mask

Register 0

007975_H

007976_HI²C 7-bit Slave Address Register 0

007977_HI²C 7-bit Slave Address Mask Register 0

007978_HI²C data register 0

ISMK0

IDAR0

007979_H,

00797A_H

Reserved

ICCR0

00797B_HI²C Clock Control Register 0

R/W

I²C Interface 0

00011111_B

00797C_H

to 0079A1_H

Reserved

0079A2_HFlash Write Control Register 0

0079A3_HFlash Write Control Register 1

0079A4_HSector Change Setting Register 0

FWR0

FWR1

SSR0

R/W

00000000_B

00XXXXX0_B

Dual Operation

Flash

0079A5_H

to

0079C1_H

Reserved

CMCR

0079C2_HClock modulator Control Register

R, R/W

Clock Modulator

0001X000_B

(Continued)

Document Number: 002-04493 Rev. *A

Page 39 of 84

MB90350E Series

(Continued)

Address

Register

Abbreviation

Access

Resource name

Initial value

0079C3_Hto

0079DF_H

Reserved

0079E0_H

0079E1_H

0079E2_H

0079E3_H

0079E4_H

0079E5_H

0079E6_H

0079E7_H

0079E8_H

Detect Address Setting Register 0

Detect Address Setting Register 1

Detect Address Setting Register 2

PADR0

PADR1

PADR2

R/W

XXXXXXXX_B

Address Match

Detection 0

0079E9_H

to

Reserved

0079EF_H

0079F0_H

0079F1_H

0079F2_H

0079F3_H

0079F4_H

0079F5_H

0079F6_H

0079F7_H

0079F8_H

Detect Address Setting Register 3

Detect Address Setting Register 4

Detect Address Setting Register 5

PADR3

PADR4

PADR5

R/W

XXXXXXXX_B

Address Match

Detection 1

0079F9_H

to

Reserved

007BFF_H

007C00_Hto

007DFF_H

Reserved for CAN controller 1. Refer to “CAN Controllers”

Reserved

007E00_H

to 007FFF_H

Notes :  Initial value of “X” represents unknown value.

 Any write access to reserved addresses in I/O map should not be performed. A read access to reserved

addresses results reading unknown value.

11. CAN Controllers

■ Compliant with CAN standard Version2.0 Part A and Part B

- Supports tr12ansmission/reception in standard frame and extended frame formats

■ Supports transmitting of data frames by receiving remote frames

■ 16 transmitting/receiving message buffers

- 29-bit ID and 8-byte data

- Multi-level message buffer configuration

■ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message

buffer as ID acceptance mask

- Two acceptance mask registers in either standard frame format or extended frame formats

■ Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)

Document Number: 002-04493 Rev. *A

Page 40 of 84

MB90350E Series

List of Control Registers

Abbreviation

Address

CAN1

Register

Access

R/W

W

Initial Value

000080_H

000081_H

000082_H

000083_H

000084_H

000085_H

000086_H

000087_H

000088_H

000089_H

00008A_H

00008B_H

00008C_H

00008D_H

00008E_H

00008F_H

00000000_B

Message buffer enable register

Transmit request register

Transmit cancel register

BVALR

TREQR

TCANR

TCR

00000000_B

Transmission complete register

Receive complete register

Remote request receiving register

Receive overrun register

R/W

00000000_B

RCR

00000000_B

RRTRR

ROVRR

RIER

00000000_B

Reception interrupt

enable register

00000000_B

(Continued)

Document Number: 002-04493 Rev. *A

Page 41 of 84

MB90350E Series

(Continued)

Address

Register

Control status register

Last event indicator register

Receive/transmit error counter

Bit timing register

Abbreviation

CSR

Access

Initial Value

CAN1

007D00_H

007D01_H

007D02_H

007D03_H

007D04_H

007D05_H

007D06_H

007D07_H

007D08_H

007D09_H

007D0A_H

007D0B_H

007D0C_H

007D0D_H

007D0E_H

007D0F_H

007D10_H

007D11_H

007D12_H

007D13_H

007D14_H

007D15_H

007D16_H

007D17_H

007D18_H

007D19_H

007D1A_H

007D1B_H

R/W, W

R/W, R

0XXXX0X1_B

00XXX000_B

000X0000_B

XXXXXXXX_B

LEIR

R/W

R

00000000_B

RTEC

11111111_B

X1111111_B

BTR

R/W

XXXXXXXX_B

IDE register

IDER

00000000_B

Transmit RTR register

TRTRR

RFWTR

TIER

Remote frame receive waiting

register

XXXXXXXX_B

Transmit interrupt

enable register

00000000_B

XXXXXXXX_B

Acceptance mask

select register

AMSR

AMR0

AMR1

R/W

XXXXXXXX_B

Acceptance mask register 0

Acceptance mask register 1

XXXXXXXX_B

Document Number: 002-04493 Rev. *A

Page 42 of 84

MB90350E Series

List of Message Buffers (ID Registers)

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C00_H

to

007C1F_H

XXXXXXXX_B

to

XXXXXXXX_B

General-purpose RAM



R/W

007C20_H

007C21_H

007C22_H

007C23_H

007C24_H

007C25_H

007C26_H

007C27_H

007C28_H

007C29_H

007C2A_H

007C2B_H

007C2C_H

007C2D_H

007C2E_H

007C2F_H

007C30_H

007C31_H

007C32_H

007C33_H

007C34_H

007C35_H

007C36_H

007C37_H

007C38_H

007C39_H

007C3A_H

007C3B_H

007C3C_H

007C3D_H

007C3E_H

007C3F_H

XXXXXXXX_B

ID register 0

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

XXXXXXXX_B

R/W

XXXXXXXX_B

(Continued)

Document Number: 002-04493 Rev. *A

Page 43 of 84

MB90350E Series

(Continued)

Address

Register

Abbreviation

Access

Initial Value

CAN1

007C40_H

007C41_H

007C42_H

007C43_H

007C44_H

007C45_H

007C46_H

007C47_H

007C48_H

007C49_H

007C4A_H

007C4B_H

007C4C_H

007C4D_H

007C4E_H

007C4F_H

007C50_H

007C51_H

007C52_H

007C53_H

007C54_H

007C55_H

007C56_H

007C57_H

007C58_H

007C59_H

007C5A_H

007C5B_H

007C5C_H

007C5D_H

007C5E_H

007C5F_H

XXXXXXXX_B

ID register 8

IDR8

R/W

XXXXXXXX_B

ID register 9

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

IDR9

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

R/W

XXXXXXXX_B

Document Number: 002-04493 Rev. *A

Page 44 of 84

MB90350E Series

List of Message Buffers (DLC Registers and Data Registers)

Address

CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

XXXXXXXX_B

007C60_H

007C61_H

007C62_H

007C63_H

007C64_H

007C65_H

007C66_H

007C67_H

007C68_H

007C69_H

007C6A_H

007C6B_H

007C6C_H

007C6D_H

007C6E_H

007C6F_H

007C70_H

007C71_H

007C72_H

007C73_H

007C74_H

007C75_H

007C76_H

007C77_H

007C78_H

007C79_H

007C7A_H

007C7B_H

007C7C_H

007C7D_H

007C7E_H

007C7F_H

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

XXXXXXXX_B

(Continued)

Document Number: 002-04493 Rev. *A

Page 45 of 84

MB90350E Series

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C80_H

to

007C87_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 0

(8 bytes)

DTR0

R/W

007C88_H

to

007C8F_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 1

(8 bytes)

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

R/W

007C90_H

to

007C97_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 2

(8 bytes)

007C98_H

to

007C9F_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 3

(8 bytes)

007CA0_H

to

007CA7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 4

(8 bytes)

007CA8_H

to

007CAF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 5

(8 bytes)

007CB0_H

to

007CB7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 6

(8 bytes)

007CB8_H

to

007CBF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 7

(8 bytes)

007CC0_H

to

007CC7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 8

(8 bytes)

007CC8_H

to

007CCF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 9

(8 bytes)

007CD0_H

to

007CD7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 10

(8 bytes)

007CD8_H

to

007CDF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 11

(8 bytes)

007CE0_H

to

007CE7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 12

(8 bytes)

007CE8_H

to

007CEF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 13

(8 bytes)

(Continued)

Document Number: 002-04493 Rev. *A

Page 46 of 84

MB90350E Series

(Continued)

Address

Register

Abbreviation

Access

Initial Value

CAN1

007CF0_H

to

007CF7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 14

(8 bytes)

DTR14

R/W

007CF8_H

to

007CFF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 15

(8 bytes)

DTR15

R/W

Document Number: 002-04493 Rev. *A

Page 47 of 84

MB90350E Series

12. Interrupt Factors, Interrupt Vectors, Interrupt Control Register

Interrupt control

register

Interrupt vector

EI²OS

corresponding

DMA ch

number

Interrupt cause

Number

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

Address

FFFFDC_H

FFFFD8_H

FFFFD4_H

FFFFD0_H

FFFFCC_H

FFFFC8_H

FFFFC4_H

FFFFC0_H

FFFFBC_H

FFFFB8_H

FFFFB4_H

FFFFB0_H

FFFFAC_H

FFFFA8_H

FFFFA4_H

FFFFA0_H

FFFF9C_H

FFFF98_H

FFFF94_H

FFFF90_H

FFFF8C_H

FFFF88_H

Number

Address

Reset

N



0



INT9 instruction

Exception

N

Reserved

N

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

0000B0_H

0000B1_H

0000B2_H

0000B3_H

0000B4_H

0000B5_H

0000B6_H

0000B7_H

0000B8_H

Reserved

N

CAN 1 RX / Input Capture 6

CAN 1 TX/NS / Input Capture 7

I²C

Y1

N

Reserved

N

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

PPG 4/5

Y1

N

1

2



3

PPG 6/7

N

PPG 8/9/C/D

N

PPG A/B/E/F

N

Timebase Timer

External Interrupt 8 to 11

Watch Timer

N

Y1

N



4

External Interrupt 12 to 15

A/D Converter

Y1

5

ICR09

0000B9_H

Free-run Timer 0 /

free-run Timer 1

N



#30

FFFF84_H

Input Capture 4/5

Output Compare 4/5

Input Capture 0/1

Output Compare 6/7

Reserved

Y1

N

6

7

#31

#32

#33

#34

#35

#36

#37

#38

FFFF80_H

FFFF7C_H

FFFF78_H

FFFF74_H

FFFF70_H

FFFF6C_H

FFFF68_H

FFFF64_H

ICR10

ICR11

ICR12

ICR13

0000BA_H

0000BB_H

0000BC_H

0000BD_H

8

9

10

11

12

13

Reserved

N

UART 3 RX

Y2

Y1

UART 3 TX

(Continued)

Document Number: 002-04493 Rev. *A

Page 48 of 84

MB90350E Series

(Continued)

Interrupt cause

Interrupt control

register

Interrupt vector

Number Address

EI²OS

corresponding

DMA ch

number

Number

Address

UART 2 RX

Y2

Y1

N

14

15



#39

#40

#41

#42

FFFF60_H

FFFF5C_H

FFFF58_H

FFFF54_H

ICR14

0000BE_H

UART 2 TX

Flash Memory

Delayed Interrupt

Y1 : Usable

ICR15

0000BF_H

N



Y2 : Usable, with EI²OS stop function

: Unusable

Notes : The peripheral resources sharing the ICR register have the same interrupt level.

N

When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one

can use EI²OS at a time.

When either of the two peripheral resources sharing the ICR register specifies EI²OS, the other one

cannot use interrupts.

13. Electrical Characteristics

13.1 Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V_SS 6.0

4.0

V_CC

AV_CC

AVRH

V_I

V_SS 0.3

V

Power supply voltage*¹

V_SS 0.3

V_CC AV_CC*

2

V_SS 0.3

AV_CCAVRH*²

Input voltage*¹

V_SS 0.3

*3

Output voltage*¹

V_O

V_SS 0.3

Maximum Clamp Current

I_CLAMP

4.0



mA *5

mA *4

mW

Total Maximum Clamp Current

“L” level maximum output current

“L” level average output current

“L” level maximum overall output current

“L” level average overall output current

“H” level maximum output current

“H” level average output current

“H” level maximum overall output current

“H” level average overall output current

Power consumption

|I_CLAMP

I_OL

I_OLAV

I_OL

I_OLAV

I_OH

I_OHAV

I_OH

I_OHAV

P_D

|

40

15

4

100

50

15

4

100

50



454

40

55

105

125

150

C

Operating temperature

Storage temperature

T_A

C

*6

T_STG

(Continued)

Document Number: 002-04493 Rev. *A

Page 49 of 84

MB90350E Series

(Continued)

*1: This parameter is based on V_SS AV_SS 0 V

*2: Set AV_CCand V_CCto the same voltage. Make sure that AV_CCdoes not exceed V_CCand that the voltage at the analog inputs does

not exceed AV_CCwhen the power is switched on.

*3: V_Iand V_Oshould not exceed V_CC 0.3 V. V_Ishould not exceed the specified ratings. However if the maximum current to/from an

input is limited by some means with external components, the I_CLAMPrating supersedes the

V_Irating.

*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67

*5: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,

P50 to P56 (for evaluation device : P50 to P55) , P60 to P67

 Use within recommended operating conditions.

 Use at DC voltage (current)

 The B signal should always be applied a connecting limit resistance between the B signal and the

microcontroller.

 The value of the limiting resistance should be set so that when the B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

 Note that when the microcontroller drive current is low, such as in the power saving modes, the B input

potential may pass through the protective diode and increase the potential at the V_CCpin, and this may affect

other devices.

 Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

 Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting

power supply voltage may not be sufficient to operate the power-on reset.

 Care must be taken not to leave the B input pin open.

 Recommended circuit sample:

• Input/output equivalent circuits

Protective diode

VCC

Limiting

resistance

P-ch

N-ch

B input (0 V to 16 V)

R

*6 : If used exceeding T_A 105C, be sure to contact Cypress for reliability limitations.

WARNING:

Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Document Number: 002-04493 Rev. *A

Page 50 of 84

MB90350E Series

13.2 Recommended Operating Conditions

(V_SS AV_SS 0 V)

Value

Typ

5.0

Parameter

Symbol

Unit

Remarks

Min

Max

4.0

5.5

V

Under normal operation

Under normal operation, when not using the A/D con-

verter and not Flash programming.

3.5

5.0

5.5

V_CC

,

Power supply voltage

AV_CC

4.5

3.0

5.0

5.5

V

When External bus is used.



Maintains RAM data in stop mode

Use a ceramic capacitor or comparable

Smoothing capacitor

C_S

T_A

0.1



1.0

F capacitor of the AC characteristics. Bypass capacitor at

the V_CCpin should be greater than this capacitor.

Operating temperature

40

125

C

*

* : If used exceeding T_A 105C, be sure to contact Cypress for reliability limitations.

 C Pin Connection Diagram

C

CS

WARNING:

The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Document Number: 002-04493 Rev. *A

Page 51 of 84

MB90350E Series

13.3 DC Characteristics

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Typ

Max

Pin inputs if CMOS

hysteresis input levels are se-

lected (except P12, P15, P44,

P45, P50)

V_IHS



0.8 V_CC



V_CC 0.3

V

Pin inputs if

V_IHA



0.8 V_CC



V_CC 0.3

V

Automotive input

levels are selected

“H” level

input

voltage

(At V_CC

Pin inputs if TTL input levels

are selected

V_IHT

V_IHS

V_IHI



2.0



V_CC 0.3

V



P12, P15, P50 inputs if CMOS

input levels are selected

5 V  10)

0.7 V_CC

P44, P45 inputs if CMOS hys-

teresis input levels are selected

RST input pin (CMOS hystere-

sis)

V_IHR

V_IHM



0.8 V_CC



V_CC 0.3

V

V_CC 0.3

MD input pin

Pin inputs if CMOS

hysteresis input levels are se-

lected (except P12, P15, P44,

P45, P50)

V_ILS



V_SS 0.3



0.2 V_CC

0.5 V_CC

V

Pin inputs if

Automotive input

levels are selected

V_ILA

“L” level

input

voltage

(At V_CC

5 V  10)

Pin inputs if TTL

input levels are selected

V_ILT

V_ILS

V_ILI



V_SS 0.3



0.8

V



P12, P15, P50 inputs if CMOS

input levels are selected

0.3 V_CC

P44, P45 inputs if CMOS hys-

teresis input levels are selected

RST input pin (CMOS hystere-

sis)

V_ILR

V_ILM

V_OH



V_SS 0.3

V_CC 0.5



0.2 V_CC

V_SS 0.3



V

MD input pin

Output “H”

voltage

Normal out- V_CC 4.5 V,

puts

I_OH 4.0 mA

Output “H”

voltage

I²C current

outputs

V_CC 4.5 V,

I_OH 3.0 mA

V_OHI

V_CC 0.5



V

(Continued)

Document Number: 002-04493 Rev. *A

Page 52 of 84

MB90350E Series

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

Output “L”

voltage

Normal

outputs

I²C current

outputs

V_CC 4.5 V,

I_OL 4.0 mA

V_OL

V_OLI

I_IL



0.4

V

Output “L”

voltage

V_CC 4.5 V,

I_OL 3.0 mA



0.4

Input leak

current

V_CC 5.5 V,



 1

 1

µA

V

_SS< V_I< V_CC

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P37,

Pull-up

resistance

R_UP



25

50

100

k

RST

Pull-down

resistance

Except Flash

memory devices

R_DOWN

MD2

25

50

48

100

60

k

V_CC 5.0 V,

Internal frequency : 24 MHz,

At normal operation.



mA

V_CC 5.0 V,

Internal frequency : 24 MHz,

At writing Flash memory.

Flash memory

devices

I_CC



53

58

25

65

70

35

mA

V_CC 5.0 V,

Internal frequency : 24 MHz,

At erasing Flash memory.

Flash memory

devices

V_CC 5.0 V,

Internal frequency : 24 MHz,

At Sleep mode.

Power supply

current

I_CCS

V_CC

Devices



0.3

0.4

0.8

1.0

mA without

“T”-suffix

V_CC 5.0 V,

Internal frequency : 2 MHz,

At Main Timer mode

I_CTS

Devices

mA

with “T”-suffix

V_CC 5.0 V,

I_CTSPLL

Internal frequency : 24 MHz,

At PLL Timer mode,



4

7

mA

6

external frequency  4 MHz

(Continued)

Document Number: 002-04493 Rev. *A

Page 53 of 84

MB90350E Series

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

MB90351E

V_CC= 5.0 V,

MB90F351E

MB90352E

MB90F352E

MB90356E

MB90F356E

MB90357E

MB90F357E

Internal frequency: 8 kHz,

During stopping clock

supervisor,



70

140

A

At sub clock operation

T_A= 25C

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock

supervisor,

MB90356E

MB90F356E

MB90357E

MB90F357E



100

200

µA

At sub clock operation

T_A= 25C

V

_CC= 5.0 V,

MB90356ES

MB90F356ES

MB90357ES

MB90F357ES

Internal CR oscillation/

4 division,

At sub clock operation

T_A= 25C

Power supply

current

I_CCL

V_CC

MB90351TE

MB90F351TE

MB90352TE

MB90F352TE

MB90356TE

MB90F356TE

MB90357TE

MB90F357TE

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During stopping clock

supervisor,



120

240

µA

At sub clock operation

T_A= 25C

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock

supervisor,

MB90356TE

MB90F356TE

MB90357TE

MB90F357TE



150

300

µA

At sub clock operation

T_A= 25C

V

_CC= 5.0 V,

MB90356TES

MB90F356TES

MB90357TES

MB90F357TES

Internal CR oscillation/

4 division,

At sub clock operation

T_A= 25C

(Continued)

Document Number: 002-04493 Rev. *A

Page 54 of 84

MB90350E Series

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

MB90351E

V_CC= 5.0 V,

MB90F351E

MB90352E

MB90F352E

MB90356E

MB90F356E

MB90357E

MB90F357E

Internal frequency: 8 kHz,

During stopping clock

supervisor,



20

50

A

At sub sleep

T_A= 25C

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock

supervisor,

MB90356E

MB90F356E

MB90357E

MB90F357E



60

200

A

At sub sleep

T_A= 25C

V

_CC= 5.0 V,

MB90356ES

MB90F356ES

MB90357ES

MB90F357ES

Internal CR oscillation/

4 division,

At sub sleep

T_A= 25C

Power supply

current

I_CCLS

V_CC

MB90351TE

MB90F351TE

MB90352TE

MB90F352TE

MB90356TE

MB90F356TE

MB90357TE

MB90F357TE

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

At sub sleep



70

150

A

T_A= 25C

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock

supervisor,

MB90356TE

MB90F356TE

MB90357TE

MB90F357TE



110

300

A

At sub sleep

T_A= 25C

V

_CC= 5.0 V,

MB90356TES

MB90F356TES

MB90357TES

MB90F357TES

Internal CR oscillation/

4 division,

At sub sleep

T_A= 25C

(Continued)

Document Number: 002-04493 Rev. *A

Page 55 of 84

MB90350E Series

(Continued)

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

MB90351E

V_CC= 5.0 V,

MB90F351E

MB90352E

MB90F352E

MB90356E

MB90F356E

MB90357E

MB90F357E

Internal frequency: 8 kHz,

During stopping clock

supervisor,



10

35

A

At watch mode

T_A= 25C

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock supervi-

sor,

MB90356E

MB90F356E

MB90357E

MB90F357E



25

150

A

At watch mode

T_A= 25C

V

_CC= 5.0 V,

MB90356ES

MB90F356ES

MB90357ES

MB90F357ES

Internal CR oscillation/

4 division,

At watch mode

T_A= 25C

I_CCT

MB90351TE

MB90F351TE

MB90352TE

MB90F352TE

MB90356TE

MB90F356TE

MB90357TE

MB90F357TE

V

_CC= 5.0 V,

Power supply

current

V_CC

Internal frequency: 8 kHz,

During stopping clock

supervisor,



60

140

A

At watch mode

T_A= 25C

V

_CC= 5.0 V,

Internal frequency: 8 kHz,

During operating clock

supervisor,

MB90356TE

MB90F356TE

MB90357TE

MB90F357TE



80

250

A

At watch mode

T_A= 25C

V

_CC= 5.0 V,

MB90356TES

MB90F356TES

MB90357TES

MB90F357TES

Internal CR oscillation/

4 division,

At watch mode

T_A= 25C

Devices without

“T”-suffix



7

25

A

V_CC 5.0 V,

At stop mode,

T_A 25C

I_CCH

Devices with

“T”-suffix

60

130

Other than

Input capacity

C_IN

C, AV_CC, AV_SS

AVRH, V_CC, V_SS

,



5

15

pF

Document Number: 002-04493 Rev. *A

Page 56 of 84

MB90350E Series

13.4 AC Characteristics

13.4.1 Clock Timing

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

1/2 (at PLL stop)

When using an oscillation circuit

3



16

MHz

1 multiplied PLL

When using an oscillation circuit

4



3

4



16

12

8

2 multiplied PLL

When using an oscillation circuit

X0, X1

3 multiplied PLL

When using an oscillation circuit

4 multiplied PLL

When using an oscillation circuit

6

6 multiplied PLL

When using an oscillation circuit

4

f_C

Clock frequency

1/2 (at PLL stop),

When using an external clock

24

12

8

1 multiplied PLL

When using an external clock

2 multiplied PLL

When using an external clock

X0

3 multiplied PLL

When using an external clock

4 multiplied PLL

When using an external clock

6

6 multiplied PLL

When using an external clock

4

fCL

X0A, X1A

X0, X1

X0

—

62.5

41.67

10

32.768



100

333

—

kHz

ns

s

ns

s

ns

When using sub clock

When using an oscillation circuit

When using an external clock

t_CYL

Clock cycle time

tCYLL

X0A, X1A

X0

30.5

P_WH, P_WL

10



15.2



Duty ratio should be about

30 to 70.

Input clock pulse width

P_WHL, P_WLL

_CR, t_CF

X0A

5

Input clock rise and fall time

t

X0



5

When using an external clock

(Continued)

Document Number: 002-04493 Rev. *A

Page 57 of 84

MB90350E Series

(Continued)

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

Internal operating clock fre-

quency

(machine clock)

f_CP

f_CPL

t_CP



1.5



24

MHz

kHz

ns

When using main clock

When using sub clock

When using main clock

When using sub clock



41.67

20

8.192

50

666



Internal operating clock cy-

cle time

(machine clock)



t_CPL

122.1

s

*: The limitation is in the range of the clock frequency when PLL is used. Use within the range in graph of “· PLL guaranteed

operation range External clock frequency and internal operation clock frequency“.

 Clock Timing

t

CYL

0.8 VCC

0.2 VCC

X0

P

WH

PWL

t

CF

tCR

t

CYLL

0.8 VCC

X0A

0.2 VCC

P

WHL

PWLL

t

CF

tCR

Document Number: 002-04493 Rev. *A

Page 58 of 84

MB90350E Series

 PLL guaranteed operation range

Guaranteed operation range

5.5

4.0

Guaranteed A/D converter

operation range

3.5

Guaranteed PLL operation range

1.5

4

24

Main clock f (MHz)

CP

Guaranteed operation range of MB90350E series

Guaranteed A/D converter operation range

× 6 × 4 × 3

× 2

× 1

24

16

12

8

× 1/2

(PLL off)

4.0

1.5

3

4

8

12

24

16

External clock f (MHz) *

C

* : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz.

External clock frequency and internal operation clock frequency

13.4.2 Reset Standby Input

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Min

Parameter

Symbol

Unit

Remarks

Max

500



ns

Under normal operation

In Stop mode, Sub Clock mode,

Sub Sleep mode and Watch

mode

Reset input

time

Oscillation time of oscillator*  100 s



s

t_RSTL

RST

In Main timer mode and PLL

timer mode

100

Document Number: 002-04493 Rev. *A

Page 59 of 84

MB90350E Series

* : Oscillation time of oscillator is the time that the amplitude reaches 90. In the crystal oscillator, the oscillation

time is between several ms to tens of ms. In ceramic oscillators, the oscillation time is between hundreds

of s to several ms. With an external clock, the oscillation time is 0 ms.

Under normal operation:

tRSTL

RST

0.2 VCC

In Stop mode, Sub Clock mode, Sub Sleep mode and, Watch mode:

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

100 μs

Oscillation time

of oscillator

Oscillation stabilization

waiting time

Instruction execution

Internal reset

13.4.3 Power On Reset

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

30

Power on rise time

Power off time

t_R

V_CC

ms



t_OFF



Waiting time until power-on

t

R

2.7 V

VCC

0.2 V

t

OFF

Document Number: 002-04493 Rev. *A

Page 60 of 84

MB90350E Series

Note : If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you start up smoothly by

restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while

not using the PLL clock. However, if voltage drops are within

1 V/s, you can operate while using the PLL clock.

VCC

We recommend the slope for

a rise of 50 mV/ms maximum.

3 V

Holds RAM data

VSS

13.4.4 Clock Output Timing

(T_A 40C to 105C, V_CC 5.0 V  10, V_SS 0.0 V, f_CP 24 MHz)

Value

Parameter

Symbol

t_CYC

CLK

Condition

Unit

Remarks

Min

62.5

41.67

20

Max



ns

f_CP 16 MHz

Cycle time



f_CP 24 MHz

f_CP 16 MHz

f_CP 24 MHz

CLK CLK 

t_CHCL

13

tCYC

tCHCL

2.4 V

CLK

0.8 V

Document Number: 002-04493 Rev. *A

Page 61 of 84

MB90350E Series

13.4.5 Bus Timing (Read)

(T_A= –40C to +105C, V_CC= 5.0 V  10 , V_SS= 0.0 V, f_CP 24 MHz)

Value

Sym-

bol

Parameter

Condition

Unit

Min

Max

ALE pulse width

t_LHLL

t_AVLL

t_LLAX

t_AVRL

ALE

t_CP/2  10



ns

ALE, A21 to A16, AD15 to

AD00

Valid address  ALE  time

ALE   Address valid time

Valid address  RD  time

t

_CP/2  20



ALE, AD15 to AD00

t_CP/2  15

t_CP 15

A21 to A16,

AD15 to AD00, RD

A21 to A16,

AD15 to AD00

Valid address  Valid data input

t_AVDV



5 t_CP/2  60

ns

RD pulse width

t_RLRHRD

(n*+3/2) t_CP 20



ns



RD   Valid data input

RD   Data hold time

RD   ALE  time

t_RLDV

RD, AD15 to AD00



0

(n*+3/2) t_CP 50

t_RHDXRD, AD15 to AD00

t_RHLHRD, ALE

t_RHAXRD, A21 to A16



t_CP/2  15

t_CP/2  10

RD   Address valid time

A21 to A16,

t_AVCHAD15 to AD00,

CLK

Valid address  CLK  time

t

_CP/2  16



ns

RD   CLK  time

ALE   RD  time

t_RLCHRD, CLK

t_CP/2  15



ns

t_LLRL

ALE, RD

* : Number of ready cycles

Document Number: 002-04493 Rev. *A

Page 62 of 84

MB90350E Series

For 1 cycle of auto-ready

CLK

tRLCH

tAVCH

2.4 V

tLLAX

tAVLL

tLHLL

tRHLH

2.4 V

0.8 V

2.4 V

ALE

RD

tAVRL

tRLRH

2.4 V

0.8 V

tLLRL

tRHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

tRLDV

tRHDX

tAVDV

2.4 V

0.8 V

V_IH

2.4 V

0.8 V

V_IH

V_IL

AD15 to AD00

Address

Read data

V_IL

Document Number: 002-04493 Rev. *A

Page 63 of 84

MB90350E Series

13.4.6 Bus Timing (Write)

(T_A= –40C to +105C, V_CC= 5.0 V  10 , V_SS= 0.0 V, f_CP 24 MHz)

Value

Parameter

Symbol

Condition

Unit

Min

Max

A21 to A16, AD15

to AD00, WR

Valid address  WR  time

t_AVWL

t_CP15



ns

WR pulse width

t_WLWH

t_DVWH

t_WHDX

t_WHAX

t_WHLH

t_WLCH

WR

(n*+3/2)t_CP 20

15



ns

Valid data output  WR  time

WR   Data hold time

WR   Address valid time

WR   ALE  time

AD15 to AD00, WR

A21 to A16, WR

WR, ALE



t_CP/2  10

t_CP/2  15

WR   CLK  time

WR, CLK

* : Number of ready cycles

For 1 cycle of auto-ready

tWLCH

2.4 V

CLK

tWHLH

2.4 V

ALE

tAVWL

tWLWH

2.4 V

WR (WRL, WRH)

0.8 V

tWHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

tDVWH

tWHDX

2.4 V

0.8 V

2.4 V

AD15 to AD00

Address

Write data

0.8 V

Document Number: 002-04493 Rev. *A

Page 64 of 84

MB90350E Series

13.4.7 Ready Input Timing

(T_A= –40C to +105C, V_CC= 5.0 V  10 , V_SS= 0.0 V, f_CP 24 MHz)

Value

Parameter

Symbol

Condition

Units

Remarks

Min

45

32

0

Max



ns

f_CP 16 MHz

f_CP 24 MHz

RDY set-up time

RDY hold time

t_RYHS

t_RYHH

RDY



Note : If the RDY set-up time is insufficient, use the auto-ready function.

2.4 V

CLK

ALE

RD/WR

tRYHS

tRYHH

V_IH

RDY

(When WAIT is not used.)

RDY

(When WAIT is used.)

V_IL

Document Number: 002-04493 Rev. *A

Page 65 of 84

MB90350E Series

13.4.8 Hold Timing

(T_A= –40C to +105C, V_CC= 5.0 V  10 , V_SS= 0.0 V, f_CP 24 MHz)

Value

Parameter

Symbol

Condition

Units

Min

30

Max

t_CP

Pin floating  HAK  time

HAK  time  Pin valid time

t_XHAL

t_HAHV

HAK

ns



t_CP

2 t_CP

Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.

2.4 V

HAK

0.8 V

tHAHV

tXHAL

Hi-Z

2.4 V

0.8 V

Each pin

0.8 V

Document Number: 002-04493 Rev. *A

Page 66 of 84

MB90350E Series

13.4.9 LIN-UART2/3

■ Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

t_SLOVI

t_IVSHI

t_SHIXI

SCK2, SCK3

5 t_CP



ns

SCK2, SCK3

SOT2, SOT3

SCK   SOT delay time

Valid SIN  SCK 

50

_CP+ 80

0

50

Internal shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK2, SCK3

SIN2, SIN3

t



ns

SCK2, SCK3

SIN2, SIN3

SCK   Valid SIN hold time



Serial clock “L” pulse width

Serial clock “H” pulse width

t_SHSL

t_SLSH

SCK2, SCK3

3 t_CP- t_R

t_CP+ 10



ns

SCK2, SCK3

SOT2, SOT3

SCK   SOT delay time

Valid SIN  SCK 

t_SLOVE

t_IVSHE

t_SHIXE



2 t_CP+ 60

ns

External shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK2, SCK3

SIN2, SIN3

30



SCK2, SCK3

SIN2, SIN3

SCK   Valid SIN hold time

t

_CP+ 30

SCK fall time

SCK rise time

t_F

SCK2, SCK3



10

ns

t_R

Notes :  AC characteristic in CLK synchronized mode.

 C_Lis load capacity value of pins when testing.

 t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

 Internal Shift Clock Mode

tSCYC

2.4 V

SCK2, SCK3

0.8 V

tSLOVI

2.4 V

SOT2, SOT3

0.8 V

tIVSHI

tSHIXI

VIH

VIL

VIH

VIL

SIN2, SIN3

Document Number: 002-04493 Rev. *A

Page 67 of 84

MB90350E Series

External Shift Clock Mode

t

SLSH

t

SHSL

V

IH

VIH

SCK2, SCK3

V

IL

VIL

t

SLOVE

t

F

t

R

2.4 V

0.8 V

SOT2, SOT3

SIN2, SIN3

t

IVSHE

t

SHIXE

V

IH

IL

V

IH

IL

■ Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

SCK2, SCK3

5 t_CP



ns

SCK2, SCK3

SOT2, SOT3

SCK   SOT delay time

Valid SIN  SCK 

t_SHOVI

50

_CP+ 80

0

50



Internal shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK2, SCK3

SIN2, SIN3

t_IVSLI

t_SLIXI

t

ns

SCK2, SCK3

SIN2, SIN3

SCK   Valid SIN hold time



Serial clock “H” pulse width

Serial clock “L” pulse width

t_SHSL

t_SLSH

SCK2, SCK3

3 t_CP- t_R

t_CP+ 10



ns

SCK2, SCK3

SOT2, SOT3

SCK   SOT delay time

Valid SIN  SCK 

t_SHOVE

t_IVSLE

t_SLIXE



2 t_CP+ 60

ns

External shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK2, SCK3

SIN2, SIN3

30



SCK2, SCK3

SIN2, SIN3

SCK   Valid SIN hold time

t

_CP+ 30

SCK fall time

SCK rise time

t_F

SCK2, SCK3



10

ns

t_R

Notes :  C_Lis load capacity value of pins when testing.

 t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Document Number: 002-04493 Rev. *A

Page 68 of 84

MB90350E Series

 Internal Shift Clock Mode

tSCYC

2.4 V

SCK2, SCK3

0.8 V

t^SHOVI

2.4 V

0.8 V

SOT2, SOT3

SIN2, SIN3

tIVSLI

tSLIXI

VIH

VIL

VIH

VIL

 External Shift Clock Mode

tSHSL

tSLSH

VIH

SCK2, SCK3

VIL

tF

VIL

t^SHOVE

tR

2.4 V

0.8 V

SOT2, SOT3

SIN2, SIN3

tIVSLE

tSLIXE

VIH

VIL

VIH

VIL

■ Bit setting: ESCR:SCES = 0, ECCR:SCDE = 1

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

SCK2, SCK3

5 t_CP



ns

SCK2, SCK3

SOT2, SOT3

SCK   SOT delay time

t_SHOVI

50

t_CP 80

0

50

SCK2, SCK3

SIN2, SIN3

Internal clock operation output

pins are

CL  80 pF  1 TTL.

Valid SIN  SCK 

t_IVSLI

t_SLIXI

t_SOVLI



ns

SCK2, SCK3

SIN2, SIN3

SCK   Valid SIN hold time

SOT  SCK  delay time



SCK2, SCK3

SOT2, SOT3

3 t_CP 70



Notes :  C_Lis load capacity value of pins when testing.

 t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Document Number: 002-04493 Rev. *A

Page 69 of 84

MB90350E Series

t

SCYC

2.4 V

SCK2, SCK3

SOT2, SOT3

0.8 V

t

SHOVI

t

SOVLI

2.4 V

0.8 V

2.4 V

0.8 V

t

IVSLI

tSLIXI

V

IH

IL

V

IH

IL

SIN2, SIN3

■ Bit setting: ESCR:SCES = 1, ECCR:SCDE = 1

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

t_SLOVI

SCK2, SCK3

5 t_CP



ns

SCK2, SCK3

SOT2, SOT3

SCK   SOT delay time

50

t_CP 80

0

50

SCK2, SCK3

SIN2, SIN3

Internal clock operation out-

put pins are

CL  80 pF  1 TTL.

Valid SIN  SCK 

t_IVSHI

t_SHIXI

t_SOVHI



ns

SCK2, SCK3

SIN2, SIN3

SCK   Valid SIN hold time

SOT  SCK  delay time



SCK2, SCK3

SOT2, SOT3

3 t_CP 70



Notes :  C_Lis load capacity value of pins when testing.

t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

tSCYC

2.4 V

SCK2, SCK3

0.8 V

tSLOVI

tSOVHI

2.4 V

0.8 V

2.4 V

0.8 V

SOT2, SOT3

SIN2, SIN3

tIVSHI

tSHIXI

VIH

VIL

VIH

VIL

Document Number: 002-04493 Rev. *A

Page 70 of 84

MB90350E Series

13.4.10 Trigger Input Timing

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

t_TRGH

t_TRGL

INT8 to INT15,

INT9R to INT11R, ADTG

Input pulse width



5 t_CP



ns

V_IH

INT8 to INT15,

V_IL

INT9R to INT11R,

ADTG

tTRGH

tTRGL

13.4.11 Timer Related Resource Input Timing

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

t_TIWH

t_TIWL

TIN1, TIN3,IN0, IN1,

IN4 to IN7

Input pulse width



4 t_CP



ns

V_IH

TIN1, TIN3,

IN0, IN1,

V_IL

tTIWH

IN4 to IN7

tTIWL

13.4.12 Timer Related Resource Output Timing

(T_A 40C to 125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

TOT1, TOT3, PPG4, PPG6,

PPG8 to PPGF

CLK   T_OUTchange time

t_TO



30



ns

Document Number: 002-04493 Rev. *A

Page 71 of 84

MB90350E Series

2.4 V

CLK

2.4 V

0.8 V

TOT1, TOT3,

PPG4, PPG6

PPG8 to PPGF

tTO

13.4.13 I²C Timing

(T_A 40C to 125C, V_CC AV_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Fast-mode*⁴

Standard-mode

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

SCL clock frequency

f_SCL

0

100

0

400

kHz

Hold time for (repeated) START condition

SDA   SCL 

t_HDSTA

4.0



0.6



s

“L” width of the SCL clock

“H” width of the SCL clock

t_LOW

t_HIGH

4.7

4.0



1.3

0.6



s

Set-up time for a repeated START condition

SCL   SDA 

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTO

t_BUS

4.7

0



3.45*²



0.6

0



0.9*³



s

ns

s

R  1.7 k,

C  50 pF*¹

Data hold time

SCL   SDA  

Data set-up time

SDA    SCL 

250*⁵

4.0

100*⁵

0.6

Set-up time for STOP condition

SCL   SDA 



Bus free time between STOP condition and START

condition

4.7



1.3



*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t_HDDAThas to meet at least that the device does not exceed the “L” width (t_LOW) of the SCL signal.

*3 : A Fast-mode I²C -bus device can be used in a Standard-mode I²C-bus system, but the requirement

t_SUDAT250 ns must be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

*5 : Refer to “ Note of SDA, SCL set-up time”.

Document Number: 002-04493 Rev. *A

Page 72 of 84

MB90350E Series

• Note of SDA, SCL set-up time

SDA

Input data set-up time

SCL

6 tCP

Note : Theratingoftheinputdataset-uptimeinthedeviceconnectedtothebuscannotbesatisfieddependingontheloadcapacitance

or pull-up resistor.

Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied.

• Timing definition

SDA

tBUS

tHDSTA

tSUDAT

tLOW

SCL

tHDSTA

tSUSTA

tHIGH

tSUSTO

tHDDAT

fSCL

Document Number: 002-04493 Rev. *A

Page 73 of 84

MB90350E Series

13.5 A/D Converter

Parameter

(

T_A



40C to



125C, 3.0 V



AVRH, V_CC AV_CC 5.0 V



10



,

f

_CP 24 MHz, V_SS AV_SS 0 V

)

Value

Symbol

Unit

Remarks

Min



Typ



Max

10

Resolution



bit

Total error



3.0

2.5

LSB

Nonlinearity error



Differential

nonlinearity error



1.9

LSB

V

Zero reading

voltage

AV_SS

1.5LSB



AV_SS

0.5LSB



AV_SS

2.5LSB



V_OT

V_FST

AN0 to AN14

Full scale reading

voltage

^AVRH

AVRH 

1.5LSB

AVRH 

0.5LSB

V

3.5LSB

1.0

2.0

0.5

1.2

^{4.5 V} AV_CC 5.5 V

4.0 V  AV_CC< 4.5 V

^{4.5 V} AV_CC 5.5 V

4.0 V  AV_CC< 4.5 V

Compare time

Sampling time



16500

s



Analog port input

current

I_AIN

V_AIN



AN0 to AN14

AVRH

 0.3



 0.3

AVRH

AV_CC

A

V

Analog input

voltage range

AV_SS

Reference

voltage range

AV_SS 2.7

V

I_A

AV_CC



3.5

7.5

5

mA

Power supply

current

I_AH



A

*

I_R

I_RH



AVRH



600

900

5

A

Reference

voltage supply current



Offset between

channels

AN0 to AN14



4

LSB

* : If A/D converter is not operating, a current when CPU is stopped is applicable (V_CC AV_CC AVRH  5.0 V) .

Notes on A/D Converter Section

■ About the external impedance of the analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage

charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external

impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external

impedance so that the sampling time is longer than the minimum value. Also if the sampling time cannot be sufficient, connect a

capacitor of about 0.1 F to the analog input pin.

Document Number: 002-04493 Rev. *A

Page 74 of 84

MB90350E Series

· Analog input equivalence circuit

Analog input

R

Comparator

C

ON at sampling

MB90F351E(S),MB90F351TE(S),MB90F352E(S),MB90F352TE(S),

MB90F356E(S),MB90F356TE(S),MB90F357E(S),MB90F357TE(S)

R

C

4.5 V ≤ AV_CC≤ 5.5 V 2.0 kΩ (Max) 16.0 pF (Max)

4.0 V ≤ AV_CC≤ 4.5 V 8.2 kΩ (Max) 16.0 pF (Max)

MB90351E(S),MB90351TE(S),MB90352E(S),MB90352TE(S),

MB90356E(S),MB90356TE(S),MB90357E(S),MB90357TE(S),

MB90V340E-101/102/103/104

R

C

4.5 V ≤ AV_CC≤ 5.5 V 2.0 kΩ (Max) 14.4 pF (Max)

4.0 V ≤ AV_CC≤ 4.5 V 8.2 kΩ (Max) 14.4 pF (Max)

Note : The value is reference value.

■ Flash memory device

· Relation between External impedance and minimum sampling time

(MB90F351E(S),MB90F351TE(S),MB90F352E(S),MB90F352TE(S),

MB90F356E(S),MB90F356TE(S),MB90F357E(S),MB90F357TE(S))

[External impedance = 0 kΩ to 100 kΩ]

4.5 V ≤ AV_CC≤ 5.5 V

[External impedance = 0 kΩ to 20 kΩ]

4.5 V ≤ AV_CC≤ 5.5 V

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

4.0 V ≤ AV_CC≤ 4.5 V

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [μs]

Document Number: 002-04493 Rev. *A

Page 75 of 84

MB90350E Series

■ MASK ROM device

· Relation between External impedance and minimum sampling time

( MB90351E(S),MB90351TE(S),MB90352E(S),MB90352TE(S),MB90356E(S),

MB90356TE(S),MB90357E(S),MB90357TE(S),MB90V340E-101/102/103/104)

[External impedance = 0 kΩ to 100 kΩ]

4.5 V ≤ AV_CC≤ 5.5 V

[External impedance = 0 kΩ to 20kΩ]

4.5 V ≤ AV_CC≤ 5.5 V

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

4.0 V ≤ AV_CC≤ 4.5 V

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [μs]

■ About the error

^{Values of relative errors grow larger, as |AVRH} AV_SS| becomes smaller.

Document Number: 002-04493 Rev. *A

Page 76 of 84

MB90350E Series

13.6 Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Non linearity

error

:

^{Deviation between a line across zero-transition line ( “00 0000 0000”}  “00 0000 0001” ) and

full-scale transition line ( “11 1111 1110”   “11 1111 1111” ) and actual conversion characteristics.

Differential

linearity error

:

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Total error

: Difference between an actual value and a theoretical value. A total error includes zero

transition error, full-scale transition error, and linear error.

Total error

3FFH

1.5 LSB

3FEH

3FDH

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

V^NT

(Actual measurement value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVRH

Analog input

V

_NT {1 LSB (N  1)  0.5 LSB}

[LSB]

Total error of digital output “N” 

1 LSB (Ideal value) 

1 LSB

AVRH  AV

SS

[V]

1024

N

V

: A/D converter digital output value

(Ideal value)  AV_SS 0.5 LSB [V]

(Ideal value)  AVRH  1.5 LSB [V]

: A voltage at which digital output transits from (N  1) to N .

OT

V

FST

NT

H

(Continued)

Document Number: 002-04493 Rev. *A

Page 77 of 84

MB90350E Series

(Continued)

Non linearity error

Differential linearity error

Ideal

characteristics

3FFH

Actual conversion

characteristics

3FEH

3FDH

(N + 1)^H

Actual conversion

characteristics

{1 LSB × (N − 1)

+ V^OT}

V^FST(actual

measurement

value)

NH

V^NT(actual

measurement value)

004H

003H

002H

001H

V (N + 1) T

(actual measurement

value)

Actual conversion

characteristics

(N − 1)H

(N − 2)H

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

VOT (actual measurement value)

Analog input

AVSS

AVRH

AVSS

AVRH

Analog input

V

_NT {1 LSB (N  1)  V

}

OT

[LSB]

Non linearity error of digital output N 

1 LSB

V ( )  V

N+1 T

1 LSB

NT

Differential linearity error of digital output N 

1 LSB 

1 LSB [LSB]

V

_FST V

OT

[V]

1022

N

: A/D converter digital output value

: Voltage at which digital output transits from “000 ” to “001 ”.

V

OT

H

: Voltage at which digital output transits from “3FE ” to “3FF ”.

FST

H

13.7 Flash Memory Program/Erase Characteristics

■ Dual Operation Flash Memory

Value

Typ

Parameter

Conditions

Unit

Remarks

Min

Max

Sector erase time

(4 Kbytes sector)

Excludes programming prior to

erasure



0.2

0.5

4.6

0.5

s

Sector erase time

(16 Kbytes sector)

Excludes programming prior to

erasure



7.5

T_A 25C

V_CC 5.0 V

Excludes programming prior to

erasure

Chip erase time



Word (16-bit width)

programming time

Except for the overhead time of

the system level



64

3600

s

Program/Erase cycle



10000



cycle

Document Number: 002-04493 Rev. *A

Page 78 of 84

MB90350E Series

Value

Typ

Parameter

Conditions

Unit

Remarks

Min

Max

Flash memory Data

Retention Time

Average

T_A 85C

20



year

*

* : Corresponding value comes from the technology reliability evaluation result.

(Using Arrhenius equation to translate high temperature measurements test result into normalized value at 85C)

14. Ordering Information

Part number

Package

Remarks

MB90F351EPMC

MB90F351ESPMC

MB90F351TEPMC

MB90F351TESPMC

MB90F356EPMC

MB90F356ESPMC

MB90F356TEPMC

MB90F356TESPMC

MB90F352EPMC

MB90F352ESPMC

MB90F352TEPMC

MB90F352TESPMC

MB90F357EPMC

MB90F357ESPMC

MB90F357TEPMC

MB90F357TESPMC

MB90351EPMC

64-pin plastic LQFP

FPT-64P-M23

12.0 mm , 0.65 mm pitch

Flash memory products

(64 Kbytes)

64-pin plastic LQFP

FPT-64P-M23

12.0 mm , 0.65 mm pitch

Dual operation

Flash memory products

(128 Kbytes)

MB90351ESPMC

MB90351TEPMC

MB90351TESPMC

MB90356EPMC

64-pin plastic LQFP

FPT-64P-M23

12.0 mm , 0.65 mm pitch

MASK ROM products

(64 Kbytes)

MB90356ESPMC

MB90356TEPMC

MB90356TESPMC

MB90352EPMC

MB90352ESPMC

MB90352TEPMC

MB90352TESPMC

MB90357EPMC

64-pin plastic LQFP

FPT-64P-M23

12.0 mm , 0.65 mm pitch

MASK ROM products

(128 Kbytes)

MB90357ESPMC

MB90357TEPMC

MB90357TESPMC

(Continued)

Document Number: 002-04493 Rev. *A

Page 79 of 84

MB90350E Series

(Continued)

Part number

Package

Remarks

MB90F351EPMC1

MB90F351ESPMC1

MB90F351TEPMC1

MB90F351TESPMC1

MB90F356EPMC1

MB90F356ESPMC1

MB90F356TEPMC1

MB90F356TESPMC1

MB90F352EPMC1

MB90F352ESPMC1

MB90F352TEPMC1

MB90F352TESPMC1

MB90F357EPMC1

MB90F357ESPMC1

MB90F357TEPMC1

MB90F357TESPMC1

MB90351EPMC1

64-pin plastic LQFP

FPT-64P-M24

10.0 mm , 0.50 mm pitch

Flash memory products

(64 Kbytes)

64-pin plastic LQFP

FPT-64P-M24

10.0 mm , 0.50 mm pitch

Dual operation

Flash memory products

(128 Kbytes)

MB90351ESPMC1

MB90351TEPMC1

MB90351TESPMC1

MB90356EPMC1

64-pin plastic LQFP

FPT-64P-M24

10.0 mm , 0.50 mm pitch

MASK ROM products

(64 Kbytes)

MB90356ESPMC1

MB90356TEPMC1

MB90356TESPMC1

MB90352EPMC1

MB90352ESPMC1

MB90352TEPMC1

MB90352TESPMC1

MB90357EPMC1

64-pin plastic LQFP

FPT-64P-M24

10.0 mm , 0.50 mm pitch

MASK ROM products

(128 Kbytes)

MB90357ESPMC1

MB90357TEPMC1

MB90357TESPMC1

MB90V340E-101CR

MB90V340E-102CR

MB90V340E-103CR

MB90V340E-104CR

299-pin ceramic PGA

PGA-299C-A01

Device for evaluation

Document Number: 002-04493 Rev. *A

Page 80 of 84

MB90350E Series

14.1 Package Dimensions

64-pin plastic LQFP

Lead pitch

0.65 mm

12.0 × 12.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Plastic mold

1.70 mm MAX

P-LFQFP64-12×12-0.65

Code

(Reference)

(FPT-64P-M23)

64-pin plastic LQFP

(FPT-64P-M23)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00 0.20(.551 .008)SQ

*12.00 0.10(.472 .004)SQ

0.145 0.055

(.0057 .0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 ^+0.20

–

0.10

.004

(Mounting height)

.059 ^+.008

–

0.25(.010)

INDEX

0~8˚

64

17

0.50 0.20

0.10 0.10

(.020 .008)

(.004 .004)

(Stand off)

"A"

1

16

0.60 0.15

(.024 .006)

0.65(.026)

0.32 0.05

(.013 .002)

M

0.13(.005)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2003 FUJITSU LIMITED F64034S-c-1-1

(Continued)

Document Number: 002-04493 Rev. *A

Page 81 of 84

MB90350E Series

(Continued)

64-pin plastic LQFP

Lead pitch

0.50 mm

10.0 × 10.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.32 g

Code

(Reference)

(FPT-64P-M24)

P-LFQFP64-10×10-0.50

64-pin plastic LQFP

(FPT-64P-M24)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

12.00 0.20(.472 .008)SQ

*

10.00 0.10(.394 .004)SQ

0.145 0.055

(.006 .002)

48

33

49

32

Details of "A" part

0.08(.003)

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

INDEX

0.10 0.10

(.004 .004)

(Stand off)

0˚~8˚

64

17

"A"

0.25(.010)

0.50 0.20

(.020 .008)

1

16

LEAD No.

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2005 FUJITSU LIMITED F64036S-c-1-1

Document Number: 002-04493 Rev. *A

Page 82 of 84

MB90350E Series

15. Major Changes

Page

Section

Change Results

The following names are changed.



^UART LIN-UART

^{16-bit I/O timer} 16-bit free-run timer

26

51

Handling Devices

Added the section ”13. Serial Communication”.

Electrical Characteristics

Changed the maximum value of power consumption.

Absolute Maximum Ratings

63

Electrical Characteristics

AC Characteristics

Changed the "(4) Clock Output Timing".

Changed the Minimum value of cycle time.

^(41.76 41.67)

69 to 73

78

Changed the notation of “(9) LIN-UART”.

A/D Converter

Changed the notation of “Zero reading voltage” and “full scale reading voltage”.

85

Ordering Information

Changed the part number;

^{MB90V340E-101} MB90V340E-101CR

^{MB90V340E-102} MB90V340E-102CR

^{MB90V340E-103} MB90V340E-103CR

^{MB90V340E-104} MB90V340E-104CR

NOTE: Please see “Document History” about later revised information.

Document History

Document Title: MB90350E Series F²MC-16LX 16-bit Microcontrollers

Document Number: 002-04493

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**



AKIH

10/12/2006 Migrated to Cypress and assigned document number 002-04993.

No change to document contents or format.

*A

5193077

AKIH

04/07/2016 Updated to Cypress template

Document Number: 002-04493 Rev. *A

Page 83 of 84

MB90350E Series

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

Automotive

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Community | Forums | Blogs | Video | Training

Lighting & Power Control

Memory

Technical Support

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then

Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code

form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to

end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the

Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation,

or compilation of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be

reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from

any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages,

and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United

States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-04493 Rev. *A

Revised April 7, 2016

Page 84 of 84


型号：	MB90356ESPMC
厂家：	CYPRESS
描述：	Microcontroller, 16-Bit, FLASH, F2MC-16LX CPU, 24MHz, CMOS, PQFP64, 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LFQFP-64 时钟微控制器外围集成电路
文件：	总84页 (文件大小：1821K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90356ESPMC [CYPRESS]

相关型号：

MB90356ESPMC1

MB90356ESPMC1

MB90356TAPMC

MB90356TAPMC1

MB90356TASPMC

MB90356TASPMC1

MB90356TE

MB90356TEPMC

MB90356TEPMC

MB90356TEPMC1

MB90356TES

MB90356TESPMC