MB90362ESPMT_技术文档

MB90360E Series

F²MC-16LX 16-bit Microcontroller

Datasheet

The MB90360E-series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose Cypress 16-bit microcontroller

designing for automotive and industrial applications. Its main feature is the on-board CAN Interfaces, which conform to Ver 2.0 Part

A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN

approach. With the new 0.35m CMOS technology, Cypress now offers on-chip Flash ROM program memory up to 64 Kbytes.

The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI

and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also,

main and sub clock can be monitored independently using the clock supervisor function.

The unit features a 4-channel input capture unit 1 channel 16-bit free running timer, 2-channel LIN-UART, and 16-channel 8/10-bit

A/D converter as the peripheral resource.

*: Controller Area Network (CAN) - License of Robert Bosch GmbH

Features

Clock

Powerful interrupt function

■ Built-in PLL clock frequency multiplication circuit

■ Powerful 8-level, 34-condition interrupt feature

■ Up to 8 channels external interrupts are supported

■ Selection of machine clocks (PLL clocks) is allowed among

frequency division by 2 on oscillation clock and multiplication

of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock,

4 MHz to 24 MHz)

Automatic data transfer function independent of

CPU

Expanded intelligent I/O service function (EI²OS) : up to 16

channels

■ Operation by sub clock : internal operating clock frequency: up

to 50 kHz (for operating with 100 kHz oscillation clock divided

two and devices without S-suffix only) is available

Low power consumption (standby) mode

■ Minimum execution time of instruction: 42 ns (when operating

with 4-MHz oscillation clock and 6-time multiplied PLL clock)

■ Sleep mode (a mode that halts CPU operating clock)

■ Main timer mode (timebase timer mode that is transferred from

main clock mode)

Clock supervisor (MB90x367x only)

■ Main clock or sub clock is monitored independently

Instruction system best suited to controller

■ PLL timer mode (timebase timer mode that is transferred from

PLL clock mode)

■ Watch mode (a mode that operates sub clock and watch timer

only, devices without S-suffix)

■ 16 Mbytes CPU memory space

■ 24-bit internal addressing

■ Stop mode (a mode that stops oscillation clock and sub clock)

■ Wide choice of data types (bit, byte, word, and long word)

■ Wide choice of addressing modes (23 types)

■ CPU blocking operation mode

Process

■ Enhanced multiply-divide instructions with sign and RETI

instructions

CMOS technology

I/O port

■ Enhanced high-precision computing with 32-bit accumulator

General purpose input/output port (CMOS output) :

- 34 ports (devices without S-suffix)

- 36 ports (devices with S-suffix)

Instruction system compatible with high-level

language (C language) and multitask

■ Employing system stack pointer

■ Enhanced various pointer indirect instructions

■ Barrel shift instructions

Sub clock pin (X0A and X1A)

■ Provided(usedforexternaloscillation), deviceswithoutS-suffix

■ Not provided, devices with S-suffix

Timer

Increased processing speed

4-byte instruction queue

■ Timebase timer, watch timer (device without S-suffix) ,

watchdog timer: 1 channel

Cypress Semiconductor Corporation

Document Number: 002-04496 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 19, 2016

MB90360E Series

■ 8/16-bit PPG timer: 8-bit  4 channels or 16-bit  2 channels

■ 16-bit reload timer: 2 channels

8/10-bit A/D converter: 16 channels

■ Resolution is selectable between 8-bit and 10-bit

■ Activation by external trigger input is allowed

■ 16- bit input/output timer

❐ 16-bit free-run timer: 1 channel (FRT0: ICU 0/1/2/3)

❐ 16- bit input capture: (ICU) : 4 channels

■ Conversion time: 3 s (at 24-MHz machine clock, including

sampling time)

FULL-CAN interface: 1 channel

Address matching detection (program patch)

function

■ Compliant with CAN specifications Version 2.0 Part A and B

■ 16 message buffers are built in

Address matching detection for 6 address pointers

■ CAN wake-up function

Low voltage/CPU operation detection reset (de-

vices with T-suffix)

LIN-UART: 2 channels

■ Detects low voltage (4.0 V  0.3 V) and resets automatically

■ Equipped with full-duplex double buffer

■ Resets automatically when program is runaway and counter is

not cleared within interval time

■ Clock-asynchronous or clock-synchronous serial transmission

is available

(approx. 262 ms: external 4 MHz)

DTP/External interrupt: up to 8 channels, CAN

wakeup: up to 1 channel

Capable of changing input voltage for port

Automotive/CMOS-Schmitt input level (initial level is Automotive

in single-chip mode)

Module for activation of expanded intelligent I/O service (EI²OS)

and generation of external interrupt by external input

Flash memory security function

Delay interrupt generator module

Protects the content of Flash memory (MB90F362x, MB90F367x

only)

Generates interrupt request for task switching

Document Number: 002-04496 Rev. *A

Page 2 of 63

MB90360E Series

Contents

Product Lineup .................................................................3

Pin Assignment ................................................................6

Pin Description .................................................................7

I/O Circuit Type ...............................................................10

Handling Devices ............................................................13

Block Diagrams ..............................................................16

Memory Map ....................................................................20

I/O Map .............................................................................21

CAN Controllers ..............................................................28

Interrupt Factors, Interrupt Vectors,

Interrupt Control Register ..............................................35

Electrical Characteristics ...............................................37

Absolute Maximum Ratings .......................................37

Recommended Conditions ........................................39

DC Characteristics ....................................................40

AC Characteristics .....................................................43

Clock Timing ..............................................................43

Reset Standby Input ..................................................46

Power-on Reset .........................................................47

LIN-UART0/1 .............................................................48

Trigger Input Timing ..................................................52

Timer Related Resource Input Timing .......................53

Timer Related Resource Output Timing ....................53

A/D Converter ............................................................54

Definition of A/D Converter Terms ...........................57

Flash Memory Program/Erase Characteristics .........58

Ordering Information ......................................................59

Package Dimension ........................................................60

Major Changes ................................................................61

Document Number: 002-04496 Rev. *A

Page 3 of 63

MB90360E Series

1. Product Lineup

MB90V340E-1 MB90V340E-1

Features

MB90362E

MB90362TE

MB90362ES

MB90362TES

01

02

Type

CPU

MASK ROM product

Evaluation product

F²MC-16LX CPU

^{PLL clock multiplier (} 1,  2,  3,  4,  6, 1/2 when PLL stops)

System clock

^{Minimum instruction execution time: 42 ns (4 MHz oscillation clock, PLL} 6)

Sub clock pin

(X0A, X1A)

Yes

No

Yes

Clock supervisor

ROM

No

MASK ROM, 64 Kbytes

3 Kbytes

External

30 Kbytes

3 channels

RAM capacitance

CAN interface

LIN-UART

1 channel

2 channels

Low voltage/CPU oper-

ation

No

Yes

No

Yes

No

detection reset

Package

LQFP-48P

PGA-299C

Yes

Emulator-specific pow-

er supply *



Corresponding evalua-

tion product

MB90V340E-102

MB90V340E-101



*: It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual

for the details.

Document Number: 002-04496 Rev. *A

Page 4 of 63

MB90360E Series

Features

MB90F362E

MB90F362TE

MB90F362ES

MB90F362TES

Type

CPU

Flash memory product

F²MC-16LX CPU

PLL clock multiplier

(  1,  2,  3,  4,  6, 1/2 when PLL stops)

Minimum instruction execution time: 42 ns

(4 MHz oscillation clock, PLL  6)

System clock

Sub clock pin

(X0A, X1A)

Yes

No

Clock supervisor

ROM

No

Flash memory, 64 Kbytes

3 Kbytes

RAM capacitance

CAN interface

LIN-UART

1 channel

2 channels

Low voltage/CPU operation de-

tection reset

No

Yes

No

Yes

Package

LQFP-48P

Corresponding

evaluation product

MB90V340E-102

MB90V340E-101

Document Number: 002-04496 Rev. *A

Page 5 of 63

MB90360E Series

MB90V340E-1 MB90V340E-1

Features

MB90367E

MB90367TE

MB90367ES

MB90367TES

03

04

Type

CPU

MASK ROM product

F²MC-16LX CPU

Evaluation product

PLL clock multiplier (  1,  2,  3,  4,  6, 1/2 when PLL stops)

Minimum instruction execution time: 42 ns (4 MHz oscillation clock, PLL  6)

System clock

Sub clock pin

(X0A, X1A)

Yes

No

Yes

Clock supervisor

ROM

Yes

MASK ROM, 64 Kbytes

3 Kbytes

External

RAM capacitance

CAN interface

LIN-UART

30 Kbytes

3 channels

1 channel

2 channels

Low voltage/CPU op-

eration

detection reset

No

Yes

No

LQFP-48P

Yes

No

Package

PGA-299C

Yes

Emulator-specific

power supply *



Corresponding EVA

product

MB90V340E-104

MB90V340E-103



*: It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual

for the details.

Features

MB90F367E

MB90F367TE

MB90F367ES

MB90F367TES

Type

CPU

Flash memory product

F²MC-16LX CPU

PLL clock multiplier

(  1,  2,  3,  4,  6, 1/2 when PLL stops)

Minimum instruction execution time: 42 ns

(4 MHz oscillation clock, PLL  6)

System clock

Sub clock pin

(X0A, X1A)

Yes

No

Clock supervisor

ROM

Yes

Flash memory, 64 Kbytes

3 Kbytes

RAM capacitance

CAN interface

LIN-UART

1 channel

2 channels

Low voltage/CPU

operation detection reset

No

Yes

No

Yes

Package

LQFP-48P

Corresponding EVA product

MB90V340E-104

MB90V340E-103

Document Number: 002-04496 Rev. *A

Page 6 of 63

MB90360E Series

2. Pin Assignment

■ MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES, MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES

(TOP VIEW)

P20 *²

P21 *²

1

2

36

35

34

33

32

31

30

29

28

27

26

25

AVcc

AVR

P22/PPGD(C) *²

P60/AN0

3

P61/AN1

4

P23/PPGF(E) *²

P24/IN0

P25/IN1

P26/IN2

P27/IN3

X1

P62/AN2

5

P63/AN3

6

7

P64/AN4

8

P65/AN5

9

P66/AN6/PPGC(D)

P67/AN7/PPGE(F)

P80/ADTG/INT12R

P50/AN8

10

11

12

X0

C

Vss

(FPT-48P-M26)

*1 : MB90F362E/TE, MB90362E/TE, MB90F367E/TE, MB90367E/TE

: X0A, X1A

MB90F362ES/TES, MB90362ES/TES, MB90F367ES/TES, MB90367ES/TES : P40, P41

*2 : High current output port

Document Number: 002-04496 Rev. *A

Page 7 of 63

MB90360E Series

3. Pin Description

Pin No.

Pin name

I/O circuit type*

Function

1

AV_CC

I

V_CCpower input pin for analog circuit.

Power (Vref) input pin for A/D converter.

It should be below V_CC

2

AVR



.

P60 to P65

AN0 to AN5

P66, P67

General-purpose I/O port.

3 to 8

H

Analog input pins for A/D converter.

General-purpose I/O port.

AN6, AN7

Analog input pins for A/D converter.

9, 10

H

PPGC (D) , PPGE

(F)

Output pins for PPG.

P80

ADTG

General-purpose I/O port.

11

12 to 14

15

F

H

Trigger input pin for A/D converter.

External interrupt request input pin for INT12.

INT12R

P50 to P52

AN8 to AN10

P53

General-purpose I/O port (P50 has different I/O circuit type from MB90V340E) .

Analog input pins for A/D converter.

General-purpose I/O port.

AN11

Analog input pin for A/D converter.

Event input pin for reload timer 3.

General-purpose I/O port.

TIN3

P54

AN12

Analog input pin for A/D converter.

Output pin for reload timer 3

16

H

TOT3

INT8

External interrupt request input pin for INT8.

General-purpose I/O port.

P55 to P57

AN13 to AN15

Analog input pins for A/D converter.

17 to 19

INT10, INT11,

INT13

External interrupt request input pins for INT10, INT11, INT13.

Input pin for operation mode specification.

20

MD2

D

C

MD1,

MD0

21, 22

Input pins for operation mode specification.

23

24

25

RST

V_CC

V_SS

E



Reset input pin.

Power input pin (3.5 V to 5.5 V) .

Power input pin (0 V) .

Power supply stabilization capacitor pin. It should be connected to a higher than

or equal to 0.1 F ceramic condenser.

26

C

I

(Continued)

Document Number: 002-04496 Rev. *A

Page 8 of 63

MB90360E Series

I/O circuit

type*

Pin No.

Pin name

Function

27

28

X0

X1

Oscillation input pin.

A

Oscillation output pin.

General-purpose I/O port.

P27 to P24

IN3 to IN0

The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

29 to 32

G

Event input pins for input capture 0 to 3.

General-purpose I/O port.

The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

High current output port.

P23, P22

33, 34

35, 36

J

PPGF (E) ,

PPGD (C)

Output pins for PPG.

General-purpose I/O port.

The register can be set to select whether to use a pull-up

resistor. This function is enabled in single-chip mode.

High current output port.

P21, P20

P85

SIN1

P87

General-purpose I/O port.

37

38

39

40

K

F

Serial data input pin for LIN-UART1.

General-purpose I/O port.

SCK1

P86

Clock I/O pin for LIN-UART1.

General-purpose I/O port.

SOT1

P43

Serial data output pin for LIN-UART1.

General-purpose I/O port.

TX1

TX output pin for CAN1 interface.

General-purpose I/O port.

P42

41

42

43

RX1

F

RX input pin for CAN1 interface.

External interrupt request input pin for INT9 (Sub) .

General-purpose I/O port.

INT9R

P83

SOT0

TOT2

P84

Serial data output pin for LIN-UART0.

Output pin for reload timer 2.

General-purpose I/O port.

SCK0

INT15R

Clock I/O pin for LIN-UART0.

External interrupt request input pin for INT15.

(Continued)

Document Number: 002-04496 Rev. *A

Page 9 of 63

MB90360E Series

(Continued)

I/O circuit

type*

Pin No.

Pin name

Function

P82

SIN0

General-purpose I/O port.

Serial data input pin for LIN-UART0.

External interrupt request input pin for INT14.

Event input pin for reload timer 2.

44

45

K

INT14R

TIN2

General-purpose I/O port

(Different I/O circuit type from MB90V340E) .

P44

F

FRCK0

P40, P41

Free-run timer 0 clock pin.

General-purpose I/O port

(Devices with S-suffix and MB90V340E-101/103 only) .

46, 47

48

Oscillation pins for sub clock

(Devices without S-suffix and MB90V340E-102/104 only) .

X0A, X1A

AV_SS

B

I

V_SSpower input pin for analog circuit.

*: For the I/O circuit type, refer to “I/O Circuit Type”

Document Number: 002-04496 Rev. *A

Page 10 of 63

MB90360E Series

4. I/O Circuit Type

Type

Circuit

Remarks

Oscillation circuit:

High-speed oscillation feedback resistor 

approx. 1 M

X1

Xout

A

X0

Standby control signal

Oscillation circuit:

Low-speed oscillation feedback resistor 

approx. 10 M

X1A

Xout

B

X0A

Standby control signal

■ MASK ROM product:

CMOS hysteresis input pin

R

■ Flash memory product:

CMOS input pin

C

CMOS hysteresis

inputs

■ MASK ROM product:

CMOS hysteresis input pin

R

■ Flash memory product:

- CMOS input pin

- No Pull-down

CMOS hysteresis

inputs

D

Pull-down

resistor

CMOS hysteresis input pin

Pull-up

resistor

E

R

CMOS hysteresis

inputs

(Continued)

Document Number: 002-04496 Rev. *A

Page 11 of 63

MB90360E Series

Type

Circuit

Remarks

■ CMOS level output

■ CMOS hysteresis inputs (With the standby-time input

P-ch

N-ch

shutdown function)

Pout

Nout

■ Automotive input (With the standby-time input

shutdown function)

F

R

CMOS hysteresis inputs

Automotive inputs

Standby control for

input shutdown

■ CMOS level output

■ CMOS hysteresis inputs (With the standby-time input

Pull-up control

Pout

shutdown function)

Pull-up

resistor

■ Automotive input (With the standby-time input

shutdown function)

P-ch

N-ch

Nout

G

R

CMOS hysteresis inputs

Automotive inputs

Standby control for

input shutdown

■ CMOS level output

■ CMOS hysteresis inputs (With the standby-time input

P-ch

N-ch

shutdown function)

Pout

Nout

■ Automotive input (With the standby-time input

shutdown function)

■ A/D analog input

R

H

CMOS hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Analog input

(Continued)

Document Number: 002-04496 Rev. *A

Page 12 of 63

MB90360E Series

(Continued)

Type

Circuit

Remarks

Protection circuit for power supply input

P-ch

N-ch

I

■ CMOS level output

■ CMOS hysteresis inputs (With the standby-time input

shutdown function)

Pull-up control

Pull-up

resistor

■ Automotive input (With the standby-time input

shutdown function)

P-ch

Pout high current output

Nout high current output

N-ch

J

R

CMOS hysteresis inputs

Automotive inputs

Standby control for

input shutdown

■ CMOS level output

■ CMOS input (With standby-time input shutdown

P-ch

N-ch

function)

Pout

Nout

■ Automotive input (With standby-time input shutdown

function)

K

R

CMOS inputs

Automotive inputs

Standby control for

input shutdown

Document Number: 002-04496 Rev. *A

Page 13 of 63

MB90360E Series

5. Handling Devices

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions:

■ A voltage higher than V_CCpin or lower than V_SSpin is applied to an input or output pin.

■ A voltage higher than the rated voltage is applied between V_CCpin and V_SSpin.

■ The AV_CCpower supply is applied before the V_CCvoltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

Use meticulous care not to exceed the rating.

For the same reason, also be careful not to let the analog power-supply voltage (AV_CC, AVR) exceed the digital power-supply voltage.

2. Treatment of unused pins

Leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up. Therefore, they must

be pulled up or pulled down through resistors. In this case, those resistors should be more than 2 k .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.

3. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90360E Series

X0

X1

Open

4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin and leave the X1A pin open.

5. Notes on during operation of PLL clock mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode

is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will

not guarantee results of operations if such failure occurs.

6. Power supply pins (V_CC/V_SS

)

■ If there are multiple V_CCand V_SSpins, from the point of view of device design, pins to be of the same potential are connected the

inside of the device to prevent malfunction such as latch-up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard

for total output current, be sure to connect the V_CCand V_SSpins to the power supply and ground externally.

■ Connect V_CCand V_SSpins to the device from the current supply source at a low impedance.

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Page 14 of 63

MB90360E Series

■ As a measure against power supply noise, connect a capacitor of about 0.1 F as a bypass capacitor between V_CCpin and V_SS

pin in the vicinity of V_CCand V_SSpins of the device.

V

CC

SS

V

CC

VSS

V

SS

CC

MB90360E

Series

V

CC

V

SS

V

CC

VSS

7. Pull-up/down resistors

The MB90360E Series does not support internal pull-up/down resistors (Port 2: built-in pull-up resistors) . Use external components

where needed.

8. Crystal oscillator circuit

Noises around X0 or X1 pin may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest

distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of

oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the

operation. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

9. Turning-on sequence of power supply to A/D converter and analog inputs

Make sure to turn on the A/D converter power supply (AV_CCand AVR) and analog inputs (AN0 to AN15) after turning-on the digital

power supply (V_CC) .

Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage

does not exceed AVRH or AV_CC(turning on/off the analog and digital power supplies simultaneously is acceptable).

10. Connection of unused pins of A/D converter if A/D converter is not used

Connect unused pins of A/D converter to AV_CC V_CC, AV_SS AVR  V_SS

.

11. Notes on energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at

⁵⁰s or more (0.2 V to 2.7 V) .

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Page 15 of 63

MB90360E Series

12. Stabilization of power supply voltage

A sudden change in the power supply voltage may cause the device to malfunction even within the specified V_CCpower supply voltage

operating guarantee range. Therefore, the V_CCpower supply voltage should be

stabilized.

For reference, the power supply voltage should be controlled so that V_CCripple variations (peak-to-peak value) at commercial

^{frequencies (50 Hz/60 Hz) fall below 10} of the standard V_CCpower supply voltage and the coefficient of transient fluctuation does

not exceed 0.1 V/ms at instantaneous power switching.

13. Initialization

In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power

again.

14. Notes on using CAN function

To use CAN function, please set ’1’ to DIRECT bit of CAN direct mode register (CDMR) .

If DIRECT bit is set to ’0’ (initial value) , wait states will be performed when accessing CAN registers.

Note: Please refer to Hardware Manual of “MB90360E series for detail of CAN Direct Mode Register”.

15. Flash security function

The security bit is located in the area of the Flash memory.

If protection code 01_His written in the security bit, the Flash memory is in the protected state by security.

Therefore, please do not write 01_Hin this address if you do not use the security function.

Please refer to following table for the address of the security bit.

Flash memory size

Address for security bit

MB90F362E

MB90F362ES

MB90F362TE

MB90F362TES

MB90F367E

Embedded 512 Kbits Flash Memory

FF0001_H

MB90F367ES

MB90F367TE

MB90F367TES

16. Correspondence with T_A 105 °C or more

^{There is a restriction of reliability if the product is used exceeding T}_A 105 °C.

Contact the sales or support representative.

It is ensured to write/erase data to the Flash memory between T_A  40 °C and 105 °C.

17. Serial communication

There is a possibility to receive wrong data due to the noise or other causes on the serial communication.

Therefore, design a printed circuit board so as to avoid noise.

Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data due

to the noise.

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Page 16 of 63

MB90360E Series

6. Block Diagrams

■ MB90V340E-101/102

X0, X1

X0A, X1A

RST

F²MC-16LX

core

Clock

controller

∗

16-bit

Free-run

timer 0

FRCK0

Input

capture

IN7 to IN0

8 channels

RAM

30 Kbytes

Output

compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

(5 channels)

16-bit

free-run

timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

controller

3 channels

RX2 to RX0

TX2 to TX0

LIN-UART

5 channels

16-bit

reload timer

4 channels

AV^CC

AVSS

AN23 to AN0

TIN3 to TIN0

TOT3 to TOT0

8/10-bit

A/D

converter

24 channels

AVRH

AVRL

ADTG

AD15 to AD00

A23 to A16

ALE

RD

WRL

WRH

HRQ

10-bit

D/A converter

2 channels

External

bus

DA01, DA00

8/16-bit

PPG

16/8 channels

HAK

RDY

CLK

PPGF to PPG0

I²C

interface

2 channels

SDA1, SDA0

SCL1, SCL0

INT15 to INT8

(INT15R to INT8R)

INT7 to INT0

DTP/

External

interrupt

DMA

Clock

monitor

CKOT

*: Only for MB90V340E-102

Document Number: 002-04496 Rev. *A

Page 17 of 63

MB90360E Series

■ MB90V340E-103/104

X0, X1

X0A, X1A*

Clock

controller/

monitor

F²MC-16LX

Core

RST

16-bit

Free-run

timer 0

FRCK0

CR

oscillator

circuit

Input

capture

IN7 to IN0

8 channels

RAM

30 Kbytes

Output

compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

(5 channels)

16-bit

free-run

timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

controller

3 channels

RX2 to RX0

TX2 to TX0

LIN-UART

5 channels

16-bit

reload timer

4 channels

AV^CC

AVSS

AN23 to AN0

TIN3 to TIN0

TOT3 to TOT0

8/10-bit

A/D

converter

24 channels

AVRH

AVRL

ADTG

AD15 to AD00

A23 to A16

ALE

RD

WRL

WRH

HRQ

10-bit

D/A converter

2 channels

External

bus

DA01, DA00

8/16-bit

PPG

16/8 channels

HAK

RDY

CLK

PPGF to PPG0

I²C

interface

2 channels

SDA1, SDA0

SCL1, SCL0

INT15 to INT8

(INT15R to INT8R)

INT7 to INT0

DTP/

External

interrupt

DMA

Clock

monitor

CKOT

*: Only for MB90V340E-104

Document Number: 002-04496 Rev. *A

Page 18 of 63

MB90360E Series

■ MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES

X0, X1

F²MC-16LX

core

Clock

controller

1

∗

X0A, X1A

RST

Input

capture

4 channels

IN0 to IN3

FRCK0

Low voltage/CPU

operation detection *²

16-bit

free-run

timer 0

RAM

3 Kbytes

CAN

RX1

TX1

controller

1 channel

ROM

64 Kbytes

16-bit

reload

TIN2, TIN3

TOT2, TOT3

timer

2 channels

Prescaler

(2 channels)

SOT0, SOT1

SCK0, SCK1

SIN0, SIN1

LIN-UART

2 channels

AV^CC

AVSS

AN15 to AN0

8/10-bit

A/D

converter

16 channels

AVR

ADTG

INT8, INT9R

DTP/

External

interrupt

INT10, INT11

INT12R, INT13

INT14R, INT15R

8/16-bit

PPG

4/2 channels

PPGF(E), PPGD(C),

PPGC(D), PPGE(F)

*1: Only for devices without S-suffix

*2: Only for devices with T-suffix

Document Number: 002-04496 Rev. *A

Page 19 of 63

MB90360E Series

■ MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES

X0, X1

Clock

controller/

monitor

F²MC-16LX

Core

X0A, X1A*¹

RST

CR

oscillator

circuit

Input

capture

4 channels

IN0 to IN3

FRCK0

16-bit

free-run

timer 0

Low voltage/CPU

operation detection *²

RAM

3 Kbytes

CAN

RX1

TX1

controller

1 channel

ROM

64 Kbytes

16-bit

reload

TIN2, TIN3

TOT2, TOT3

timer

2 channels

Prescaler

(2 channels)

SOT0, SOT1

SCK0, SCK1

SIN0, SIN1

LIN-UART

2 channels

AV^CC

AVSS

AN15 to AN0

8/10-bit

A/D

converter

16 channels

AVR

ADTG

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

DTP/

External

interrupt

8/16-bit

PPG

4/2 channels

PPGF(E), PPGD(C),

PPGC(D), PPGE(F)

*1: Only for devices without S-suffix

*2: Only for devices with T-suffix

Document Number: 002-04496 Rev. *A

Page 20 of 63

MB90360E Series

7. Memory Map

MB90F362E/TE/ES/TES

MB90362E/TE/ES/TES

MB90F367E/TE/ES/TES

MB90367E/TE/ES/TES

MB90V340E-101/102

MB90V340E-103/104

FFFFFF^H

FFFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (FF bank)

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

F90000H

F8FFFFH

ROM (F8 bank)

F80000H

010000^H

00FFFFH

External access area

00FFFFH

ROM (image

of FF bank)

008000H

007FFFH

Peripheral

007900H

0078FFH

RAM 30 Kbytes

000CFFH

000100H

RAM 3 Kbytes

000100H

0000FFH

External access area

Peripheral

0000F0H

0000EFH

000000H

0000EFH

000000H

Peripheral

: No access

Note: The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.

Since the low-order 16 bits are the same, the table in ROM can be referred without using the far specification in the pointer

declaration.

For example, an attempt to access 00C000_Hpractically accesses the value at FFC000_Hin ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000_Hand FFFFFF_His visible in bank 00, while the image between FF0000_Hand FF7FFF_His visible

only in bank FF.

Document Number: 002-04496 Rev. *A

Page 21 of 63

MB90360E Series

8. I/O Map

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

000000_H,00

0001_H

Reserved

000002_H

000003_H

000004_H

000005_H

000006_H

000007_H

000008_H

Port 2 Data Register

PDR2

R/W

Port 2

XXXXXXXX_B

Reserved

PDR4

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

R/W

Port 4

Port 5

Port 6

XXXXXXXX_B

PDR5

PDR6

Reserved

PDR8

Port 8 Data Register

R/W

Port 8

XXXXXXXX_B

000009_H,00

000A_H

Reserved

00000B_HPort 5 Analog Input Enable Register

00000C_HPort 6 Analog Input Enable Register

00000D_H

ADER5

ADER6

Reserved

ILSR0

R/W

Port 5, A/D

Port 6, A/D

11111111_B

00000E_HInput Level Select Register

00000F_HInput Level Select Register

R/W

Ports

XXXX0XXX_B

XXXXXXXX_B

ILSR1

000010_H,00

0011_H

Reserved

000012_H

000013_H

000014_H

000015_H

000016_H

000017_H

000018_H

000019_H

Port 2 Direction Register

DDR2

R/W

Port 2

00000000_B

Reserved

DDR4

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

R/W

Port 4

Port 5

Port 6

XXX00000_B

00000000_B

DDR5

DDR6

Reserved

DDR8

Port 8 Direction Register

R/W

W

Port 8

Port A

000000X0_B

Reserved

DDRA

00001A_HPort A Direction Register

XXX00XXX_B

00001B_Hto

00001D_H

Reserved

00001E_HPort 2 Pull-up Control Register

00001F_H

PUCR2

R/W

Port 2

00000000_B

Reserved

Document Number: 002-04496 Rev. *A

Page 22 of 63

MB90360E Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

000020_H

000021_H

000022_H

000023_H

Serial Mode Register 0

SMR0

SCR0

W, R/W

R/W

00000000_B

00001000_B

Serial Control Register 0

Reception/Transmission Data Register 0

Serial Status Register 0

RDR0/TDR0

SSR0

R, R/W

LIN-UART0

Extended Communication Control

Register 0

R, W,

R/W

000024_H

ECCR0

000000XX_B

000025_H

000026_H

000027_H

000028_H

000029_H

Extended Status/Control Register 0

Baud Rate Generator Register 00

Baud Rate Generator Register 01

Serial Mode Register 1

ESCR0

BGR00

BGR01

SMR1

R/W

00000100_B

00000000_B

00001000_B

R/W, R

W, R/W

R/W

Serial Control Register 1

SCR1

00002A_HReception/Transmission Data Register 1

00002B_HSerial Status Register 1

RDR1/TDR1

SSR1

R, R/W

LIN-UART1

Extended Communication Control

Register 1

R, W,

R/W

00002C_H

ECCR1

000000XX_B

00002D_HExtended Status/Control Register 1

00002E_HBaud Rate Generator Register 10

00002F_HBaud Rate Generator Register 11

ESCR1

BGR10

BGR11

R/W

00000100_B

00000000_B

R/W, R

000030_Hto

00003A_H

Reserved

PACSR1

Address Match

Detection 1

00003B_HAddress Detect Control Register 1

R/W

00000000_B

00003C_Hto

000047_H

Reserved

000048_H

000049_H

PPG C Operation Mode Control Register

PPG D Operation Mode Control Register

PPGCC

PPGCD

W, R/W

0X000XX1_B

0X000001_B

16-bit PPG C/D

16-bit PPG E/F

PPG C/PPG D Count Clock Select

Register

00004A_H

00004B_H

PPGCD

R/W

000000X0_B

Reserved

PPGCE

00004C_HPPG E Operation Mode Control Register

00004D_HPPG F Operation Mode Control Register

W, R/W

0X000XX1_B

0X000001_B

PPGCF

PPG E/PPG F Count Clock Select

00004E_H

Register

PPGEF

R/W

000000X0_B

00004F_H

Reserved

(Continued)

Document Number: 002-04496 Rev. *A

Page 23 of 63

MB90360E Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

000050_H

000051_H

000052_H

000053_H

Input Capture Control Status 0/1

Input Capture Edge 0/1

ICS01

ICE01

ICS23

ICE23

R/W

R/W, R

R/W

R

00000000_B

XXX0X0XX_B

00000000_B

XXXXXXXX_B

Input Capture 0/1

Input Capture 2/3

Input Capture Control Status 2/3

Input Capture Edge 2/3

000054_Hto

000063_H

Reserved

000064_H

000065_H

000066_H

000067_H

000068_H

000069_H

Timer Control Status 2

Timer Control Status 3

A/D Control Status 0

A/D Control Status 1

TMCSR2

TMCSR3

ADCS0

ADCS1

ADCR0

ADCR1

ADSR0

ADSR1

R/W

R/W, W

R

00000000_B

XXXX0000_B

00000000_B

XXXX0000_B

000XXXX0_B

0000000X_B

00000000_B

XXXXXX00_B

00000000_B

16-bit Reload Timer 2

16-bit Reload Timer 3

00006A_HA/D Data 0

00006B_HA/D Data 1

00006C_HADC Setting 0

00006D_HADC Setting 1

A/D Converter

R

R/W

Low voltage/CPU

operation detection

reset

Low Voltage/CPU Operation Detection Reset

Control Register

00006E_H

LVRC

R/W, W

W

00111000_B

00006F_HROM Mirror Function Select

ROMM

ROM Mirror

XXXXXXX1_B

000070_Hto

00007F_H

Reserved

000080_Hto

00008F_H

Reserved for CAN Interface 1. Refer to “CAN Controllers”

Reserved

000090_H

to

00009D_H

Address Match

Detection 0

00009E_HAddress Detect Control Register 0

00009F_HDelayed Interrupt/Release Register

PACSR0

DIRR

R/W

00000000_B

Delayed Interrupt genera-

tion module

XXXXXXX0_B

Low-Power

consumption

Control Circuit

Low-power Consumption Mode

0000A0_H

LPMCR

CKSCR

W, R/W

R, R/W

00011000_B

11111100_B

Control Register

Low-Power

consumption

Control Circuit

0000A1_HClock Selection Register

(Continued)

Document Number: 002-04496 Rev. *A

Page 24 of 63

MB90360E Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

0000A2_Hto

0000A7_H

Reserved

0000A8_HWatchdog Control Register

0000A9_HTimebase Timer Control Register

0000AA_HWatch Timer Control register

WDTC

TBTC

WTC

R, W

Watchdog Timer

Timebase Timer

Watch Timer

XXXXX111_B

1XX00100_B

1X001000_B

W, R/W

R, R/W

0000AB_Hto

0000AD_H

Reserved

Flash Control Status

0000AE_H

(Flash Devices only.

Otherwise reserved)

FMCS

Reserved

R, R/W

Flash Memory

000X0000_B

0000AF_H

0000B0_HInterrupt Control Register 00

0000B1_HInterrupt Control Register 01

0000B2_HInterrupt Control Register 02

0000B3_HInterrupt Control Register 03

0000B4_HInterrupt Control Register 04

0000B5_HInterrupt Control Register 05

0000B6_HInterrupt Control Register 06

0000B7_HInterrupt Control Register 07

0000B8_HInterrupt Control Register 08

0000B9_HInterrupt Control Register 09

0000BA_HInterrupt Control Register 10

0000BB_HInterrupt Control Register 11

0000BC_HInterrupt Control Register 12

0000BD_HInterrupt Control Register 13

0000BE_HInterrupt Control Register 14

0000BF_HInterrupt Control Register 15

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

W, R/W

00000111_B

Interrupt Control

0000C0_Hto

0000C9_H

Reserved

0000CA_HExternal Interrupt Enable 1

0000CB_HExternal Interrupt Source 1

ENIR1

EIRR1

R/W

00000000_B

XXXXXXXX_B

00000000_B

XXXX0000_B

0000CC_H

Detection Level Setting 1

0000CD_H

External Interrupt 1

ELVR1

R/W

0000CE_HExternal Interrupt Source Select

0000CF_HPLL/Sub clock Control Register

EISSR

R/W

W

PSCCR

PLL

(Continued)

Document Number: 002-04496 Rev. *A

Page 25 of 63

MB90360E Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

0000D0_Hto

0000FF_H

Reserved

007900_H

to

007917_H

Reserved

PRLLC

007918_H

007919_H

Reload Register LC

Reload Register HC

R/W

R

XXXXXXXX_B

PRLHC

PRLLD

PRLHD

PRLLE

PRLHE

PRLLF

PRLHF

IPCP0

IPCP1

IPCP2

IPCP3

16-bit PPG C/D

16-bit PPG E/F

Input Capture 0/1

Input Capture 2/3

00791A_HReload Register LD

00791B_HReload Register HD

00791C_HReload Register LE

00791D_HReload Register HE

00791E_HReload Register LF

00791F_HReload Register HF

007920_H

007921_H

007922_H

007923_H

007924_H

007925_H

007926_H

007927_H

Input Capture 0

Input Capture 1

Input Capture 2

Input Capture 3

R

007928_H

to

Reserved

00793F_H

007940_H

007941_H

007942_H

007943_H

Timer Data 0

TCDT0

R/W

00000000_B

0XXXXXXX_B

Timer Data 0

Free-run Timer 0

Timer Control Status 0

TCCSL0

TCCSH0

007944_H

to

Reserved

00794B_H

00794C_H

00794D_H

00794E_H

00794F_H

R/W

XXXXXXXX_B

TMR2/TMRL

R2

16-bit Reload

Timer 2

Timer 2/Reload 2

Timer 3/Reload 3

TMR3/TMRL

R3

16-bit Reload

Timer 3

007950_H

to

Reserved

00795F_H

(Continued)

Document Number: 002-04496 Rev. *A

Page 26 of 63

MB90360E Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

Clock Supervisor Control

Register

007960_H

CSVCR

R, R/W

Clock supervisor

00011100_B

007961_H

to

Reserved

00796D_H

CAN Direct Mode Register

(MB90V340E only)

00796E_H

CDMR

R/W

CAN clock sync

XXXXXXX0_B

00796F_H

to

Reserved

0079DF_H

0079E0_HDetect Address Setting 0

0079E1_HDetect Address Setting 0

0079E2_HDetect Address Setting 0

0079E3_HDetect Address Setting 1

0079E4_HDetect Address Setting 1

0079E5_HDetect Address Setting 1

0079E6_HDetect Address Setting 2

0079E7_HDetect Address Setting 2

0079E8_HDetect Address Setting 2

PADR0

PADR1

PADR2

R/W

XXXXXXXX_B

Address Match

Detection 0

0079E9_H

to

Reserved

0079EF_H

0079F0_HDetect Address Setting 3

0079F1_HDetect Address Setting 3

0079F2_HDetect Address Setting 3

0079F3_HDetect Address Setting 4

0079F4_HDetect Address Setting 4

0079F5_HDetect Address Setting 4

0079F6_HDetect Address Setting 5

0079F7_HDetect Address Setting 5

0079F8_HDetect Address Setting 5

PADR3

PADR4

PADR5

R/W

XXXXXXXX_B

Address Match

Detection 1

0079F9_H

to

Reserved

007BFF_H

007C00_H

to

007CFF_H

Reserved for CAN Interface 1. Refer to “CAN Controllers”

007D00_H

to

007DFF_H

(Continued)

Document Number: 002-04496 Rev. *A

Page 27 of 63

MB90360E Series

(Continued)

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

007E00_H

to

Reserved

007FFF_H

Notes:  Initial value of “X” represents unknown value.

 Any write access to reserved addresses in I/O map should not be performed. A read access to reserved

addresses results in reading “X”.

Document Number: 002-04496 Rev. *A

Page 28 of 63

MB90360E Series

9. CAN Controllers

^■^CoSⁿu^fop^rp^mor^sts^totr^Can^As^Nm^Sis^ps^eio^cn^if/ⁱr^ce^ac^tie^opⁿti^Von^erin^2.s⁰ta^Pn^ad^ra^tr^Ad^afrⁿa^dm^Pe^aa^rtn^Bd extended frame formats

■ Supports transmitting of data frames by receiving remote frames

^■¹⁶2^t9^ra-bⁿit^smID^ittaⁱⁿn^gd^/r8^e-^cb^eyⁱt^veⁱⁿd^gat^ma^{essage buffers}

 Multi-level message buffer configuration

■ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance

mask

 2 acceptance mask registers in either standard frame format or extended frame formats

■ Bit rate programmable from 10 kbps/s to 2 Mbps/s (when input clock is at 16 MHz)

List of Control Registers (1)

Address

Register

Abbreviation

BVALR

TREQR

TCANR

TCR

Access

R/W

W

Initial Value

CAN1

000080_H

000081_H

000082_H

000083_H

000084_H

000085_H

000086_H

000087_H

000088_H

000089_H

00008A_H

00008B_H

00008C_H

00008D_H

00008E_H

00008F_H

Message buffer valid register

Transmit request register

Transmit cancel register

Transmission complete register

Receive complete register

00000000 00000000_B

R/W

RCR

Remote request receiving

register

RRTRR

ROVRR

RIER

Receive overrun register

Reception interrupt enable

register

Document Number: 002-04496 Rev. *A

Page 29 of 63

MB90360E Series

List of Control Registers (2)

Address

CAN1

Register

Control status register

Last event indicator register

Receive and transmit error counter

Bit timing register

Abbreviation

CSR

Access

Initial Value

007D00_H

007D01_H

007D02_H

007D03_H

007D04_H

007D05_H

007D06_H

007D07_H

007D08_H

007D09_H

007D0A_H

007D0B_H

007D0C_H

007D0D_H

007D0E_H

007D0F_H

007D10_H

007D11_H

007D12_H

007D13_H

007D14_H

007D15_H

007D16_H

007D17_H

007D18_H

007D19_H

007D1A_H

007D1B_H

R/W, W

R/W, R

0XXXX0X1 00XXX000_B

000X0000 XXXXXXXX_B

00000000 00000000_B

LEIR

R/W

R

RTEC

BTR

R/W

11111111 X1111111_B

XXXXXXXX XXXXXXXX_B

00000000 00000000_B

IDE register

IDER

Transmit RTR register

TRTRR

RFWTR

TIER

Remote frame receive

waiting register

XXXXXXXX XXXXXXXX_B

00000000 00000000_B

Transmit interrupt enable

register

XXXXXXXX XXXXXXXX_B

Acceptance mask select

register

AMSR

AMR0

AMR1

R/W

Acceptance mask register 0

Acceptance mask register 1

Document Number: 002-04496 Rev. *A

Page 30 of 63

MB90360E Series

List of Message Buffers (ID Registers)

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C00_H

to

XXXXXXXX_B

to

General-purpose RAM



R/W

007C1F_H

XXXXXXXX_B

007C20_H

007C21_H

007C22_H

007C23_H

007C24_H

007C25_H

007C26_H

007C27_H

007C28_H

007C29_H

007C2A_H

007C2B_H

007C2C_H

007C2D_H

007C2E_H

007C2F_H

007C30_H

007C31_H

007C32_H

007C33_H

007C34_H

007C35_H

007C36_H

007C37_H

007C38_H

007C39_H

007C3A_H

007C3B_H

007C3C_H

007C3D_H

007C3E_H

007C3F_H

XXXXXXXX XXXXXXXX_B

ID register 0

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

R/W

XXXXXXXX XXXXXXXX_B

(Continued)

Document Number: 002-04496 Rev. *A

Page 31 of 63

MB90360E Series

(Continued)

Address

Register

Abbreviation

Access

Initial Value

CAN1

007C40_H

007C41_H

007C42_H

007C43_H

007C44_H

007C45_H

007C46_H

007C47_H

007C48_H

007C49_H

007C4A_H

007C4B_H

007C4C_H

007C4D_H

007C4E_H

007C4F_H

007C50_H

007C51_H

007C52_H

007C53_H

007C54_H

007C55_H

007C56_H

007C57_H

007C58_H

007C59_H

007C5A_H

007C5B_H

007C5C_H

007C5D_H

007C5E_H

007C5F_H

XXXXXXXX XXXXXXXX_B

ID register 8

IDR8

R/W

ID register 9

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

IDR9

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

R/W

Document Number: 002-04496 Rev. *A

Page 32 of 63

MB90360E Series

List of Message Buffers (DLC Registers and Data Registers)

Address

CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

XXXXXXXX_B

007C60_H

007C61_H

007C62_H

007C63_H

007C64_H

007C65_H

007C66_H

007C67_H

007C68_H

007C69_H

007C6A_H

007C6B_H

007C6C_H

007C6D_H

007C6E_H

007C6F_H

007C70_H

007C71_H

007C72_H

007C73_H

007C74_H

007C75_H

007C76_H

007C77_H

007C78_H

007C79_H

007C7A_H

007C7B_H

007C7C_H

007C7D_H

007C7E_H

007C7F_H

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

XXXXXXXX_B

(Continued)

Document Number: 002-04496 Rev. *A

Page 33 of 63

MB90360E Series

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C80_H

to

007C87_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 0

(8 bytes)

DTR0

R/W

007C88_H

to

007C8F_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 1

(8 bytes)

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

R/W

007C90_H

to

007C97_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 2

(8 bytes)

007C98_H

to

007C9F_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 3

(8 bytes)

007CA0_H

to

007CA7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 4

(8 bytes)

007CA8_H

to

007CAF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 5

(8 bytes)

007CB0_H

to

007CB7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 6

(8 bytes)

007CB8_H

to

007CBF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 7

(8 bytes)

007CC0_H

to

007CC7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 8

(8 bytes)

007CC8_H

to

007CCF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 9

(8 bytes)

007CD0_H

to

007CD7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 10

(8 bytes)

007CD8_H

to

007CDF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 11

(8 bytes)

007CE0_H

to

007CE7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 12

(8 bytes)

007CE8_H

to

007CEF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 13

(8 bytes)

(Continued)

Document Number: 002-04496 Rev. *A

Page 34 of 63

MB90360E Series

(Continued)

Address

Register

Abbreviation

Access

Initial Value

CAN1

007CF0_H

to

007CF7_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 14

(8 bytes)

DTR14

R/W

007CF8_H

to

007CFF_H

XXXXXXXX_B

to

XXXXXXXX_B

Data register 15

(8 bytes)

DTR15

R/W

Document Number: 002-04496 Rev. *A

Page 35 of 63

MB90360E Series

10. Interrupt Factors, Interrupt Vectors, Interrupt Control Register

Interrupt control

register

Interrupt vector

EI²OS

corresponding

Interrupt cause

Number

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

Address

FFFFDC_H

FFFFD8_H

FFFFD4_H

FFFFD0_H

FFFFCC_H

FFFFC8_H

FFFFC4_H

FFFFC0_H

FFFFBC_H

FFFFB8_H

FFFFB4_H

FFFFB0_H

FFFFAC_H

FFFFA8_H

FFFFA4_H

FFFFA0_H

FFFF9C_H

FFFF98_H

FFFF94_H

FFFF90_H

FFFF8C_H

FFFF88_H

FFFF84_H

FFFF80_H

FFFF7C_H

FFFF78_H

FFFF74_H

FFFF70_H

FFFF6C_H

FFFF68_H

FFFF64_H

Number

Address

Reset

N



INT9 instruction

Exception

N

Reserved

N

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

0000B0_H

0000B1_H

0000B2_H

0000B3_H

0000B4_H

0000B5_H

0000B6_H

0000B7_H

0000B8_H

0000B9_H

0000BA_H

0000BB_H

0000BC_H

0000BD_H

Reserved

N

CAN 1 reception

CAN 1 transmission/node status

Reserved

N

Reserved

N

Reserved

N

Reserved

N

16-bit reload timer 2

16-bit reload timer 3

Reserved

Y1

N

Reserved

N

PPG C/D

N

PPG E/F

N

Timebase timer

External interrupt 8 to 11

Watch timer

N

Y1

N

External interrupt 12 to 15

A/D converter

Y1

N

16-bit free-run timer 0

Reserved

N

Reserved

N

Input capture 0 to 3

Reserved

Y1

N

LIN-UART 0 reception

LIN-UART 0 transmission

LIN-UART 1 reception

LIN-UART 1 transmission

Y2

Y1

Y2

Y1

(Continued)

Document Number: 002-04496 Rev. *A

Page 36 of 63

MB90360E Series

(Continued)

Interrupt control

register

Interrupt vector

Number Address

EI²OS

corresponding

Interrupt cause

Number

Address

Reserved

N

#39

#40

#41

#42

FFFF60_H

FFFF5C_H

FFFF58_H

FFFF54_H

ICR14

ICR15

0000BE_H

Reserved

Flash memory

0000BF_H

Delayed interrupt generation module

Y1 : Usable

Y2 : Usable, with EI²OS stop function

N : Unusable

Notes:  The peripheral resources sharing the ICR register have the same interrupt level.

 When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one

can use extended intelligent I/O service at a time.

 When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O

service, the other one cannot use interrupts.

Document Number: 002-04496 Rev. *A

Page 37 of 63

MB90360E Series

11. Electrical Characteristics

11.1 Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V_SS 6.0

2.0

V_CC

AV_CC

AVR

V_I

V_SS 0.3

V

Power supply voltage*¹

V_SS 0.3

V_CC AV_CC*

2

V_SS 0.3

AV_CC AVR*²

Input voltage*¹

V_SS 0.3

*3

Output voltage*¹

V_O

V_SS 0.3

Maximum clamp current

Total Maximum clamp current

I_CLAMP

2.0



mA *6

mA *4

mA *5

mA *4

mA *5

mA *4

mA *5

|I_CLAMP

I_OL1

|

40



15

“L” level maximum output current

“L” level average output current

I_OL2



40

I_OLAV1

I_OLAV2

I_OL1



4



30



125

“L” level maximum overall output current

I_OL2



160

I_OLAV1

I_OLAV2

I_OLAV1

I_OLAV2

I_OH1

*4 105 °C  T_A 125 °C



40

mA

*5 105 °C  T_A 125 °C

*4 40 °C  T_A 105 °C

*5 40 °C  T_A 105 °C

“L” level average overall output current



15

40

4

mA *4

mA *5

mA *4

mA *5

mA *4

mA *5

“H” level maximum output current

“H” level average output current

I_OH2

I_OHAV1

I_OHAV2

I_OH1

30

125

160

“H” level maximum overall output current

I_OH2

I_OHAV1

I_OHAV2

I_OHAV1

I_OHAV2

*4 105 °C  T_A 125 °C



40

mA

*5 105 °C  T_A 125 °C

*4 40 °C  T_A 105 °C

*5 40 °C  T_A 105 °C

“H” level average overall output current

Flash memory updata not

performed



308

390

mW

Power consumption

P_D

Flash memory updata

performed

40

55

105

125

150

°C

Operating temperature

Storage temperature

T_A

*7

T_STG

(Continued)

Document Number: 002-04496 Rev. *A

Page 38 of 63

MB90360E Series

(Continued)

*1: This parameter is based on V_SS AV_SS 0 V.

*2: Set AV_CCand V_CCto the same voltage. Make sure that AV_CCdoes not exceed V_CCand that the voltage at the

analog inputs does not exceed AV_CCwhen the power is switched on.

*3: V_Iand V_Oshould not exceed V_CC 0.3 V. V_Ishould not exceed the specified ratings. However, if the maximun

current to/from an input is limited by some means with external components, the I_CLAMPrating supersedes the

V_Irating.

*4: Applicable to pins : P24 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87

*5: Applicable to pins : P20 to P23

*6: Applicable to pins: P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87

 Use within recommended operating conditions.

 Use at DC voltage (current) .

 The B signal should always be applied a connecting limit resistance between the B signal and the

microcontroller.

 The value of the limiting resistance should be set so that when the B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

 Note that when the microcontroller drive current is low, such as in the power saving modes, the B input

potential may pass through the protective diode and increase the potential at the V_CCpin, and this may affect

other devices.

 Note that if a B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

 Note that if the B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

 Care must be taken not to leave the B input pin open.

 Recommended circuit sample:

 Input/output equivalent circuits

Protective diode

VCC

Limiting

P-ch

N-ch

resistance

B input (0 V to 16 V)

R

*7: There is a restriction of reliability if the product is used exceeding T_A 105 °C.

Contact the sales or support representative.

It is ensured to write/erase data to the Flash memory between T_A  40 °C and 105 °C.

WARNING:

Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Document Number: 002-04496 Rev. *A

Page 39 of 63

MB90360E Series

11.2 Recommended Conditions

(V_SS AV_SS 0 V)

Value

Typ

5.0

Parameter

Symbol

Unit

Remarks

Min

Max

4.0

5.5

V

Under normal operation

V_CC

,

Under normal operation when not using the

A/D converter and not Flash programming.

Power supply voltage

3.5

3.0

5.0

5.5

AV_CC



Maintains RAM data in stop mode

Use a ceramic capacitor or comparable ca-

pacitor of the AC characteristics. Bypass

capacitor at the V_CCpin should be greater

than this capacitor.

Smoothing capacitor

C_S

T_A

0.1



1.0

F

40



105

125

°C

Operating temperature

*

*: There is a restriction of reliability if the product is used exceeding T_A 105 °C.

Contact the sales or support representative.

It is ensured to write/erase data to the Flash memory between T_A  40 °C and 105 °C.

 C Pin Connection Diagram

C

CS

WARNING:

The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Document Number: 002-04496 Rev. *A

Page 40 of 63

MB90360E Series

11.3 DC Characteristics

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Sym-

Parameter

bol

Condition

Unit

Remarks

Min

Typ

Max

Pin inputs if CMOS hystere-

sis input levels are selected

(except P82, P85)

V_IHS



0.8 V_CC



V_CC 0.3

V

Pin inputs if

V_IHA

Input “H”

voltage



0.8 V_CC

0.7 V_CC



V_CC 0.3

V

Automotive input

levels are selected

P82, P85 inputs if CMOS in-

put levels are selected

V_IHS

RST input pin (CMOS hyster-

esis)

V_IHR

V_IHM



0.8 V_CC



V_CC 0.3

V

V_CC 0.3

MD input pin

Pin inputs if CMOS hystere-

sis input levels are selected

(except P82, P85)

V_ILS



V_SS 0.3



0.2 V_CC

V

Pin inputs if

V_ILA



V_SS 0.3



0.5 V_CC

0.3 V_CC

V

Automotive input

levels are selected

Input “L”

voltage

V_ILS

P82, P85 inputs if CMOS in-

put levels are selected

RST input pin (CMOS hyster-

esis)

V_ILR

V_ILM



V_SS 0.3

V_CC 0.5



0.2 V_CC

V_SS 0.3



V

MD input pin

Other than

P20 to P23

V_CC 4.5 V,

I_OH 4.0 mA

V_OH

V_OHI

V_OL

V_OLI

I_IL

Output “H”

voltage

V_CC 4.5 V,

I_OH 14.0 mA

P20 to P23

V_CC 0.5



V

Other than

P20 to P23

V_CC 4.5 V,

I_OL 4.0 mA



0.4

 1

100

Output “L”

voltage

V_CC 4.5 V,

I_OL 20.0 mA

P20 to P23



V

Input leak cur-

rent

V_CC 5.5 V,

V_SS V_I V_CC



1

25



A

k

Pull-up

resistance

P20 to P27,

RST

R_UP



50

(Continued)

Document Number: 002-04496 Rev. *A

Page 41 of 63

MB90360E Series

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

MB90362E,

Pull-down

resistance

MB90362ES,

MB90362TE,

MB90362TES

R_DOWN

MD2



25

50

100

k

V_CC 5.0 V,

Internal frequency: 24 MHz,

At normal operation.



35

50

12

45

60

20

mA

V_CC 5.0 V,

Internal frequency: 24 MHz,

At writing Flash memory.

Flash memory

devices

I_CC

V_CC 5.0 V,

Internal frequency: 24 MHz,

At erasing Flash memory.

Flash memory

devices

V_CC 5.0 V,

Internal frequency: 24 MHz,

I_CCS

At sleep mode.

Devices without

T-suffix



0.3

0.4

0.8

1.0

V_CC 5.0 V,

Internal frequency: 2 MHz,

At main timer mode

I_CTS

mA

Devices with

T-suffix

V_CC 5.0 V,

Internal frequency: 24 MHz,

At PLL timer mode,

I_CTSPLL



4

7

6

External frequency  4 MHz

MB90F362E,

MB90F367E,

MB90362E,

MB90367E

Power supply

current*

Stopping clock

supervisor

V_CC



40

60

90

110

10

30

60

80

100

150

200

250

50

V_CC 5.0 V

Internal frequency: 8

kHz,

At sub operation,

T_A 25C

Operatingclock

supervisor

MB90F367E,

MB90367E

I_CCL

A

MB90F362TE,

MB90F367TE,

MB90362TE,

MB90367TE

Stopping clock

supervisor

Operatingclock

supervisor

MB90F367TE,

MB90367TE

MB90F362E,

MB90F367E,

MB90362E,

MB90367E

Stopping clock

supervisor

V_CC 5.0 V

Internal frequency: 8

kHz,

At sub sleep,

T_A 25C

Operatingclock

supervisor

MB90F367E,

MB90367E

100

150

200

I_CCLS

A

MB90F362TE,

MB90F367TE,

MB90362TE,

MB90367TE

Stopping clock

supervisor

Operatingclock

supervisor

MB90F367TE,

MB90367TE

(Continued)

Document Number: 002-04496 Rev. *A

Page 42 of 63

MB90360E Series

(Continued)

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

MB90F362E,

MB90F367E,

MB90362E,

MB90367E

Stopping clock

supervisor



8

30

V_CC 5.0 V

Internal frequency: 8

kHz,

At watch mode,

T_A 25C

Operatingclock

supervisor

MB90F367E,

MB90367E



30

60

70

I_CCT

A

MB90F362TE,

MB90F367TE,

MB90362TE,

MB90367TE

Stopping clock

supervisor

Power supply

current*

130

V_CC

Operatingclock

supervisor

MB90F367TE,

MB90367TE



80

5

170

25

Devices without

T-suffix

A

V_CC 5.0 V,

At stop mode, T_A 25C

I_CCH

Devices with

T-suffix

50

130

Other than

AV_CC

AV_SS, AVR,

_CC, V_SS, C

,

Input capacity

C_IN



5

15

pF

V

*: The power supply current is measured with an external clock.

Document Number: 002-04496 Rev. *A

Page 43 of 63

MB90360E Series

11.4 AC Characteristics

11.4.1 Clock Timing

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

1/2 when PLL stops,

When using an oscillation circuit

3



16

MHz

PLL  1,

When using an oscillation circuit

4

3

4



16

12

8

PLL  2,

When using an oscillation circuit

X0, X1

PLL  3,

When using an oscillation circuit

PLL  4,

When using an oscillation circuit

6

PLL  6,

When using an oscillation circuit

4

f_C

Clock frequency*

1/2 when PLL stops,

When using an external clock

24

12

8

PLL  1,

When using an external clock

PLL  2,

When using an external clock

X0, X1

PLL  3,

When using an external clock

PLL  4,

When using an external clock

6

PLL  6,

When using an external clock

4

fCL

X0A, X1A

—

62.5

41.67

10

32.768

100

333

—

kHz

ns

s

ns

s

ns

X0, X1



When using an oscillation circuit

When using an external clock

t_CYL

Clock cycle time

X0, X1

tCYLL

P_WH, P_WL

P_WHL, P_WLL

t_CR, t_CF

f_CP

X0A, X1A

30.5



X0

X0A

X0



10



Input clock pulse width

Duty ratio is about 30 to 70.

5

15.2



Input clock rise and fall time



5

When using external clock

1.5



24

50

666



MHz When using main clock

kHz When using sub clock

Internal operating clock

frequency (machine clock)

f_CPL



8.192



t_CP



41.67

20

ns

When using main clock

When using sub clock

Internal operating clock

cycle time (machine clock)

t_CPL



122.1

s

*: When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned in “Relation

among external clock frequency and internal clock frequency”.

Document Number: 002-04496 Rev. *A

Page 44 of 63

MB90360E Series

 Clock Timing

t

CYL

0.8 VCC

0.2 VCC

X0

P

WH

PWL

t

CF

tCR

t

CYLL

0.8 VCC

X0A

0.2 VCC

P

WHL

PWLL

t

CF

tCR

Document Number: 002-04496 Rev. *A

Page 45 of 63

MB90360E Series

 Guaranteed PLL Operation Range

Guaranteed operation range

5.5

4.0

3.5

Guaranteed A/D converter

operation range

Guaranteed PLL operation range

1.5

4

24

Internal clock f^CP(MHz)

Guaranteed operation range of MB90360E series

Guaranteed oscillation frequency range

× 6 × 4

× 3

× 2

× 1

24

16

12

8

×1/2

(PLL off)

4.0

1.5

3

4

8

12

24

16

External clock fC (MHz) *

*: When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz.

Document Number: 002-04496 Rev. *A

Page 46 of 63

MB90360E Series

11.4.2 Reset Standby Input

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Max

500



ns

Under normal operation

In stop mode, sub clock mode,

sub sleep mode, and watch

mode

Oscillation time of oscillator*

Reset input time

t_RSTL

RST



s

 100 s

100



In timebase timer mode

*: Oscillation time of oscillator is the time that the amplitude reaches 90. In the crystal oscillator, the oscillation time is between

several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of s and several ms. With an external

clock, the oscillation time is 0 ms.

 Under normal operation:

tRSTL

RST

0.2 VCC

 In stop mode, sub clock mode, sub sleep mode, and watch mode:

tRSTL

RST

X0

0.2 VCC

90% of

amplitude

Internal operation

clock

100 μs

Oscillation time

of oscillator

Oscillation stabilization

waiting time

Instruction execution

Internal reset

Document Number: 002-04496 Rev. *A

Page 47 of 63

MB90360E Series

11.4.3 Power-on Reset

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

30

Power on rise time

Power off time

t_R

V_CC

ms



t_OFF



Due to repetitive operation

tR

2.7 V

V

CC

0.2 V

tOFF

Note: If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you start up smoothly

by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while

not using the PLL clock. However, if voltage drops are within

1 V/s, you can operate while using the PLL clock.

VCC

We recommend a rise of

50 mV/ms maximum.

3 V

Holds RAM data

VSS

Document Number: 002-04496 Rev. *A

Page 48 of 63

MB90360E Series

11.4.4 LIN-UART0/1

■ Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

t_SLOVI

t_IVSHI

t_SHIXI

SCK0, SCK1

5 t_CP



ns

SCK0, SCK1,

SOT0, SOT1

SCK   SOT delay time

Valid SIN  SCK 

50

_CP+ 80

0

50



Internal shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK0, SCK1,

SIN0, SIN1

t

ns

SCK0, SCK1,

SIN0, SIN1

SCK   Valid SIN hold time



Serial clock “L” pulse width

Serial clock “H” pulse width

t_SHSL

t_SLSH

SCK0, SCK1

3 t_CP- t_R

t_CP+ 10



ns

SCK0, SCK1,

SOT0, SOT1

SCK   SOT delay time

Valid SIN  SCK 

t_SLOVE

t_IVSHE

t_SHIXE



2 t_CP+ 60

ns

External shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK0, SCK1,

SIN0, SIN1

30



SCK0, SCK3,

SIN0, SIN1

SCK   Valid SIN hold time

t

_CP+ 30

SCK fall time

SCK rise time

t_F

SCK0, SCK1



10

ns

t_R

Notes:  AC characteristic in CLK synchronized mode.

 C_Lis load capacity value of pins when testing.

 t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

 Internal Shift Clock Mode

t

SCYC

2.4 V

SCK0, SCK1

SOT0, SOT1

0.8 V

t

SLOVI

2.4 V

0.8 V

t

IVSHI

t

SHIXI

V

IH

IL

V

IH

IL

SIN0, SIN1

Document Number: 002-04496 Rev. *A

Page 49 of 63

MB90360E Series

 External Shift Clock Mode

t

SLSH

t

SHSL

V

IH

VIH

SCK0, SCK1

V

IL

VIL

t

SLOVE

t

F

t

R

2.4 V

0.8 V

SOT0, SOT1

SIN0, SIN1

t

IVSHE

t

SHIXE

V

IH

IL

V

IH

IL

■ Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

SCK0, SCK1

5 t_CP



ns

SCK0, SCK1,

SOT0, SOT1

SCK   SOT delay time

Valid SIN  SCK 

t_SHOVI

50

_CP+ 80

0

50



Internal shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK0, SCK1,

SIN0, SIN1

t_IVSLI

t_SLIXI

t

ns

SCK0, SCK1,

SIN0, SIN1

SCK   Valid SIN hold time



Serial clock “H” pulse width

Serial clock “L” pulse width

t_SHSL

t_SLSH

SCK0, SCK1

3 t_CP- t_R

t_CP+ 10



ns

SCK0, SCK1,

SOT0, SOT1

SCK   SOT delay time

Valid SIN  SCK 

t_SHOVE

t_IVSLE

t_SLIXE



2 t_CP+ 60

ns

External shift clock

mode output pins are

CL  80 pF  1 TTL.

SCK0, SCK1,

SIN0, SIN1

30



SCK0, SCK1,

SIN0, SIN1

SCK   Valid SIN hold time

t

_CP+ 30

SCK fall time

SCK rise time

t_F

SCK0, SCK1



10

ns

t_R

Notes:  C_Lis load capacity value of pins when testing.

 t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Document Number: 002-04496 Rev. *A

Page 50 of 63

MB90360E Series

 Internal Shift Clock Mode

t

SCYC

2.4 V

SCK0, SCK1

0.8 V

t

SHOVI

2.4 V

0.8 V

SOT0, SOT1

SIN0, SIN1

t

IVSLI

t

SLIXI

V

IH

IL

V

IH

IL

 External Shift Clock Mode

t

SHSL

t

SLSH

V

IH

V

IH

SCK0, SCK1

V

IL

V

IL

t

SHOVE

t

R

t

F

2.4 V

0.8 V

SOT0, SOT1

SIN0, SIN1

t

IVSLE

t

SLIXE

V

IH

IL

V

IH

IL

V

■ Bit setting: ESCR:SCES  0, ECCR:SCDE  1

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

SCK0, SCK1

5 t_CP



ns

SCK0, SCK1,

SOT0, SOT1

SCK   SOT delay time

t_SHOVI

50

t_CP 80

0

50



SCK0, SCK1,

SIN0, SIN1

Internal clock operation output

pins are

CL  80 pF  1 TTL.

Valid SIN  SCK 

t_IVSLI

t_SLIXI

t_SOVLI

ns

SCK0, SCK1,

SIN0, SIN1

SCK   Valid SIN hold time

SOT  SCK  delay time



SCK0, SCK1,

SOT0, SOT1

3 t_CP 70



Notes:  C_Lis load capacity value of pins when testing.

 t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Document Number: 002-04496 Rev. *A

Page 51 of 63

MB90360E Series

t

SCYC

2.4 V

SCK0, SCK1

SOT0, SOT1

0.8 V

t

SHOVI

t

SOVLI

2.4 V

0.8 V

2.4 V

0.8 V

t

IVSLI

tSLIXI

V

IH

IL

V

IH

IL

SIN0, SIN1

Document Number: 002-04496 Rev. *A

Page 52 of 63

MB90360E Series

■ Bit setting: ESCR:SCES  1, ECCR:SCDE  1

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t_SCYC

t_SLOVI

SCK0, SCK1

5 t_CP



ns

SCK0, SCK1,

SOT0, SOT1

SCK   SOT delay time

50

t_CP 80

0

50



SCK0, SCK1,

SIN0, SIN1

Internal clock operation out-

put pins are

CL  80 pF  1 TTL.

Valid SIN  SCK 

t_IVSHI

t_SHIXI

t_SOVHI

ns

SCK0, SCK1,

SIN0, SIN1

SCK   Valid SIN hold time

SOT  SCK  delay time



SCK0, SCK1,

SOT0, SOT1

3 t_CP 70



Notes:  C_Lis load capacity value of pins when testing.

 t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

tSCYC

2.4 V

SCK0, SCK1

0.8 V

tSLOVI

tSOVHI

2.4 V

0.8 V

2.4 V

0.8 V

SOT0, SOT1

SIN0, SIN1

tIVSHI

tSHIXI

VIH

VIL

VIH

VIL

11.4.5 Trigger Input Timing

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

ADTG

t_TRGH

t_TRGL

Input pulse width



5 t_CP



ns

Note: t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

Document Number: 002-04496 Rev. *A

Page 53 of 63

MB90360E Series

V

IH

VIH

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

ADTG

V

IL

VIL

t

TRGH

t

TRGL

11.4.6 Timer Related Resource Input Timing

(T_A 40 °C to 125 °C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

t_TIWH

t_TIWL

TIN2, TIN3

IN0 to IN3

Input pulse width



4 t_CP



ns

Note: t_CPis internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.

VIH

VIL

TIN2, TIN3

IN0 to IN3

tTIWH

tTIWL

11.4.7 Timer Related Resource Output Timing

(T_A –40C to +125C, V_CC 5.0 V  10, f_CP 24 MHz, V_SS 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

TOT2, TOT3

PPGC to PPGF

CLK   T_OUTchange time

t_TO



30



ns

2.4 V

CLK

2.4 V

TOT2, TOT3

PPGC to PPGF

0.8 V

tTO

Document Number: 002-04496 Rev. *A

Page 54 of 63

MB90360E Series

11.5 A/D Converter

Parameter

(TA  40 °C to 125 °C, 3.0 V  AVR  AV_SS, V_CC AV_CC 5.0 V  10, f_CP 24 MHz, V_SS AV_SS 0 V)

Value

Symbol

Unit

Remarks

Min

Typ

Max

10

Resolution



bit

Total error

3.0

2.5

LSB

Nonlinearity error

Differential

nonlinearity error



1.9

LSB

V

AV_SS

1.5  LSB



AV_SS

0.5  LSB



AV_SS

2.5  LSB

Zero reading voltage

V_OT

V_FST

AN0 to AN15

Full scale reading

voltage

AVR 

3.5  LSB

AVR 

1.5  LSB

AVR 

0.5  LSB

V

1.0

2.0

0.5

1.2

4.5 V  AV_CC 5.5 V

4.0 V  AV_CC< 4.5 V

4.5 V  AV_CC 5.5 V

4.0 V  AV_CC< 4.5 V

Compare time

Sampling time



16500

s



Analog port input

current

I_AIN

V_AIN



AN0 to AN15

AVR

0.3

AV_SS



+0.3

AVR

AV_CC

A

V

Analog input

voltage range

Reference

voltage range

AV_SS 2.7

V

I_A

I_AH

I_R

AV_CC

AVR



3.5



7.5

5

mA

A

Power supply current

*

600



900

5

Reference

voltage supply current

I_RH

AVR

Offset between

input channels



AN0 to AN15



4

LSB

*: If A/D converter is not operating, a current when CPU is stopped is applicable (V_CC AV_CC AVR  5.0 V) .

Document Number: 002-04496 Rev. *A

Page 55 of 63

MB90360E Series

 About the external impedance of analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage

changed to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy

the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and

either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than

the minimum value. And, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.

 Analog input equivalent circuit model

R

Comparator

Analog input

C

During sampling: ON

MB90F362E/TE/ES/TES, MB90F367E/TE/ES/TES

R

C

4.5 V  AV_CC 5.5 V

2.0 k (Max)

8.2 k (Max)

16.0 pF (Max)

4.0 V  AV < 4.5 V

CC

MB90362E/TE/ES/TES, MB90367E/TE/ES/TES,

MB90V340E-101/102/103/104

R

C

4.5 V  AV_CC 5.5 V

2.0 k (Max)

8.2 k (Max)

14.4 pF (Max)

4.0 V  AV < 4.5 V

CC

Note: The values are reference values.

Document Number: 002-04496 Rev. *A

Page 56 of 63

MB90360E Series

 The relationship between external impedance and minimum sampling time

 At 4.5 V  AV_CC 5.5 V

(External impedance  0 k to 20 k)

(External impedance  0 k to 100 k)

MB90362E/TE/ES/TES,

MB90367E/TE/ES/TES,

MB90362E/TE/ES/TES,

MB90367E/TE/ES/TES,

MB90V340E-101/102/103/104

20

18

16

14

12

10

8

100

90

80

70

60

50

40

30

20

MB90F362E/TE/ES/TES

MB90F367E/TE/ES/TES

MB90F362E/TE/ES/TES

MB90F367E/TE/ES/TES

6

4

2

0

10

0

1

2

3

4

5

6

7

8

0

5

10

15

20

25

30

35

Minimum sampling time [s]

 At 4.0 V  AV < 4.5 V

CC

(External impedance  0 k to 20 k)

(External impedance  0 k to 100 k)

MB90362E/TE/ES/TES,

MB90367E/TE/ES/TES,

MB90V340E-101/102/103/104

MB90362E/TE/ES/TES,

MB90367E/TE/ES/TES,

MB90V340E-101/102/103/104

20

100

18

16

14

12

10

8

90

80

70

60

50

40

30

20

MB90F362E/TE/ES/TES

MB90F367E/TE/ES/TES

MB90F362E/TE/ES/TES

MB90F367E/TE/ES/TES

6

4

2

0

10

0

1

2

3

4

5

6

7

8

0

5

10

15

20

25

30

35

Minimum sampling time [s]

 About errors

As | AVR  AV_SS| becomes smaller, values of relative errors grow larger.

Document Number: 002-04496 Rev. *A

Page 57 of 63

MB90360E Series

11.6 Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Non linearity

error

:

Deviation between a line across zero-transition line ( “00 0000 0000_B”   “00 0000 0001_B” ) and

full-scale transition line ( “11 1111 1110_B”   “11 1111 1111_B” ) and actual conversion characteristics.

Differential

linearity error

:

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Total error

: Difference between an actual value and an theoretical value. A total error includes zero transition error,

full-scale transition error, and linear error.

Total error

3FFH

1.5 LSB

3FEH

3FDH

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

VNT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVR

Analog input

V

_NT {1 LSB  (N  1)  0.5 LSB}

[LSB]

Total error of digital output “N” 

1 LSB (Ideal value) 

1 LSB

AVR  AV

SS

[V]

1024

N: A/D converter digital output value

V

(Ideal value)  AV_SS 0.5 LSB [V]

(Ideal value)  AVR  1.5 LSB [V]

: A voltage at which digital output transits from (N  1) to N.

OT

FST

NT

(Continued)

Document Number: 002-04496 Rev. *A

Page 58 of 63

MB90360E Series

(Continued)

Non linearity error

Differential linearity error

Ideal

characteristics

3FF

3FE

3FD

H

Actual conversion

characteristics

N + 1

H

Actual conversion

characteristics

{1 LSB × (N − 1)

+ V^OT

}

V

FST (actual

measurement

value)

N

V

NT (actual

measurement value)

004

003

002

001

H

V

(N + 1) T

(actual measurement

Actual conversion

characteristics

N − 1

N − 2

value)

V

NT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

V

OT (actual measurement value)

Analog input

AVSS

AVR

AVSS

AVR

Analog input

V

_NT {1 LSB  (N  1)  V

}

OT

[LSB]

Non linearity error of digital output N 

1 LSB

V ( )  V

N+1

1 LSB

T

NT

Differential linearity error of digital output N 

1 LSB 

1 LSB [LSB]

[V]

V

_FST V

OT

1022

N

: A/D converter digital output value

: Voltage at which digital output transits from “000 ” to “001 .”

V

OT

H

: Voltage at which digital output transits from “3FE ” to “3FF .”

FST

H

11.7 Flash Memory Program/Erase Characteristics

Value

Typ

Parameter

Conditions

Unit

Remarks

Min

Max

Excludes programming prior to

erasure

Chip erase time



1

15

s

T_A 40 °C to 105 °C

V_CC 5.0 V

Word (16-bit width)

programming time

Except for the overhead time of

the system level



16



3600

s

Program/Erase cycle



10000

20



cycle

year

Flash memory data

retention time

Average

T_A 85 °C



*

*: Corresponding value comes from the technology reliability evaluation result (using Arrhenius equation to translate high temperature

measurements into normalized value at 85 °C) .

Document Number: 002-04496 Rev. *A

Page 59 of 63

MB90360E Series

12. Ordering Information

Part number

MB90F362EPMT

Package

Remarks

MB90F362TEPMT

MB90F362ESPMT

MB90F362TESPMT

MB90F367EPMT

MB90F367TEPMT

MB90F367ESPMT

MB90F367TESPMT

MB90362EPMT

48-pin plastic LQFP

(FPT-48P-M26)

MB90362TEPMT

MB90362ESPMT

MB90362TESPMT

MB90367EPMT

MB90367TEPMT

MB90367ESPMT

MB90367TESPMT

MB90V340E-101CR

MB90V340E-102CR

MB90V340E-103CR

MB90V340E-104CR

299-pin ceramic PGA

(PGA-299C-A01)

For evaluation

Document Number: 002-04496 Rev. *A

Page 60 of 63

MB90360E Series

13. Package Dimension

48-pin plastic LQFP

Lead pitch

0.50 mm

7 × 7 mm

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Gullwing

Plastic mold

1.70 mm MAX

0.17 g

Code

(Reference)

P-LFQFP48-7×7-0.50

(FPT-48P-M26)

48-pin plastic LQFP

(FPT-48P-M26)

Note 1) * : These dimensions include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

9.00 0.20(.354 .008)SQ

+0.40

7.00 ^–0.10.276 ^–⁺^.^.⁰⁰⁰¹⁴⁶SQ

0.145 0.055

(.006 .002)

*

36

25

37

24

Details of "A" part

0.08(.003)

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

INDEX

48

13

0.10 0.10

(.004 .004)

(Stand off)

"A"

0˚~8˚

1

12

LEAD No.

0.50(.020)

0.25(.010)

0.20 0.05

M

0.08(.003)

(.008 .002)

0.60 0.15

(.024 .006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F48040S-c-2-2

Document Number: 002-04496 Rev. *A

Page 61 of 63

MB90360E Series

14. Major Changes

Spansion Publication Number: DS07-13746-3Et

Page

Section

Change Results

Changed are following names.



^UART LIN-UART

^{16-bit I/O timer} 16-bit free-run timer

4, 5

15

Product Lineup

Added the row of LIN-UART.

Handling Devices

Added the item “17.Serial communication”.

Electrical Characteristics

Absolute Maximum Ratings

Changed the maximum rating values and Remarks on Ratings of Power

consumption.

37

³⁰⁰ 308 Flash memory updata not performed

390 Flash memory updata performed

AC Characteristics

A/D Converter

Changed the characteristics of (4)LIN-UART0/1.

^{(4) UART0/UART1} (4)LIN-UART0/1

Changed the items of “Zero reading voltage” and “Full scale reading volt-

age”.

48 to 52

55

Ordering Information

Changed the part numbers;

^{MB90V340E-101} MB90V340E-101CR

^{MB90V340E-102} MB90V340E-102CR

^{MB90V340E-103} MB90V340E-103CR

^{MB90V340E-104} MB90V340E-104CR

61

NOTE: Please see “Document History” about later revised information.

Document History

Document Title: MB90360E Series F²MC-16LX 16-bit Microcontroller Datasheet

Document Number: 002-04496

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**



AKIH

11/16/2006 Migrated to Cypress and assigned document number 002-04496.

No change to document contents or format.

*A

5223311

AKIH

04/19/2016 Updated to Cypress template

Document Number: 002-04496 Rev. *A

Page 62 of 63

MB90360E Series

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

Automotive

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Community | Forums | Blogs | Video | Training

Lighting & Power Control

Memory

Technical Support

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United

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Document Number: 002-04496 Rev. *A

Revised April 19, 2016

Page 63 of 63


型号：	MB90362ESPMT
厂家：	CYPRESS
描述：	Microcontroller, 16-Bit, MROM, F2MC-16LX CPU, 24MHz, CMOS, PQFP48, 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-48 微控制器
文件：	总63页 (文件大小：5719K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90362ESPMT [CYPRESS]

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