MB90423GCPMC [CYPRESS]
Microcontroller, 16-Bit, MROM, F2MC-16L CPU, 16MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-100;型号: | MB90423GCPMC |
厂家: | CYPRESS |
描述: | Microcontroller, 16-Bit, MROM, F2MC-16L CPU, 16MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-100 时钟 微控制器 外围集成电路 |
文件: | 总89页 (文件大小:2201K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13711-5E
16-Bit Original Microcontroller
CMOS
F2MC-16LX MB90420G/425G Series
MB90423GA/423GC/F423GA/F423GC/427GA/427GC/428GA/428GC/
MB90F428GA/F428GC/V420G
■ DESCRIPTIONS
The FUJITSU MICROELECTRONICS MB90420G/425G Series is a 16-bit general purpose high-capacity micro-
controller designed for vehicle meter control applications etc.
The instruction set retains the same AT architecture as the FUJITSU MICROELECTRONICS original F2MC-8L
and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing
mode, enhanced (signed) multipler-divider computation and bit processing.
In addition, a 32-bit accumulator is built in to enable long word processing.
■ FEATURES
• 16-bit input capture (4 channels)
Detects rising, falling, or both edges.
16-bit capture register × 4
Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.
• 16-bit reload timer (2 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Event count function selection provided
• Watch timer (main clock)
Operates directly from oscillator clock.
Compensates for oscillator deviation
Read/write enabled second/minute/hour register
Signal interrupt
(Continued)
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in
system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.8
MB90420G/425G Series
• 16-bit PPG (3 channels)
Output pins (3) , external trigger input pin (1)
Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interruptions to CPU can be generated/deleted by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• A/D converter
10-bit or 8-bit resolution × 8 channels (input multiplexed)
Conversion time : 6.13 µs or less (at fCP = 16 MHz)
External trigger startup available (P50/INT0/ADTG)
Internal timer startup available (16-bit reload timer 1)
• UART (2 channels)
Full duplex double buffer type
Supports asynchronous/synchronous transfer (with start/stop bits)
Internal timer can be selected as clock (16-bit reload timer 0)
Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps
Synchronous : 500 Kbps, 1Mbps, 2Mbps (at fCP = 16 MHz)
• CAN interface *1
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and messages for data and ID
Multiple message support
Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks
Supports up to 1 Mbps
CAN WAKEUP function (connects RX internally to INT0)
• LCD controller/driver (1 channel)
Segment driver and command driver with direct LCD panel (display) drive capability
• Low voltage/Program Looping detect reset *2
Automatic reset when low voltage is detected
Program Looping detection function
• Stepping motor controller (4 channels)
High current output for all channels × 4
Synchronized 8/10-bit PWM for all channels × 2
• Sound generator
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16MHz)
Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)
• Input/output ports
Push-pull output and Schmitt trigger input
Programmable in bit units for input/output or peripheral signals.
(Continued)
2
DS07-13711-5E
MB90420G/425G Series
(Continued)
• Flash memory
Supports automatic programming, Embeded AlgorithmTM, write/erase/erase pause/erase resume instructions
Flag indicates algorithm completion
Minato Electronics flash writer
Boot block configuration
Erasable by blocks
Block protection by external programming voltage
*1 : MB90420G series has 2 channels built-in, MB90425G series has 1 channel built-in
*2 : Built-in to MB90420GA/425GA series only. Not built-in to MB90420GC/425GC series.
Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc.
DS07-13711-5E
3
MB90420G/425G Series
■ PRODUCT LINEUP
• MB90420G Series
Part
number
MB90F423GA
MB90F423GC
MB90423GA
MB90423GC
MB90V420G
Evaluation model
2 systems
Parameter
Configuration
CPU
Flash ROM model
Mask ROM model
F2MC-16LX CPU
Clock
1 system
2 systems
1 system
2 systems
On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)
Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)
System clock
ROM
Flash ROM 128 KB
6 KB
Mask ROM 128 KB
6 KB
External
6 KB
RAM
CAN interface
2 channels
Low voltage/
CPU operation
detection reset
Yes
No
Yes
No
No
PGA-256
No
Packages
QFP100, LQFP100
Emulator
dedicated
power supply*
⎯
* : When used with emulation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-50
Hardware Manual (2.7 “Emulator Dedicated Power Supply Pin”) .
• MB90425G Series
Part number
MB90F428GA MB90F428GC MB90427GA MB90427GC MB90428GA MB90428GC
Parameter
Configuration
CPU
Flash ROM model
Mask ROM model
F2MC-16LX CPU
1 system 2 systems
Clock
1 system
2 systems
1 system
2 systems
On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)
Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)
System clock
ROM
Flash ROM 128 KB
6 KB
Mask ROM 64 KB
4 KB
Mask ROM 128 KB
6 KB
RAM
CAN interface
1 channel
Low voltage/CPU
operation
Yes
No
Yes
No
Yes
No
detection reset
Packages
QFP100, LQFP100
Emulator
dedicated
power supply
⎯
Note : MB90V420G can be used as evaluation model for MB90420G/425G series.
4
DS07-13711-5E
MB90420G/425G Series
■ PIN ASSIGNMENTS
• QFP 100
(TOP VIEW)
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
VSS
SEG8
SEG9
SEG10
SEG11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
X0A
X1A
P57/SGA
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DVSS
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVCC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVCC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
VCC
P45/SEG19
P46/SEG20
P47/SEG21
C
P90/SEG22
P91/SEG23
V0
P53/INT3
MD2
(FPT-100P-M06)
DS07-13711-5E
5
MB90420G/425G Series
• LQFP 100
(TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DVSS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVCC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVCC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
V
SS
SEG8
SEG9
SEG10
SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
V
CC
P45/SEG19
P46/SEG20
P47/SEG21
C
(FPT-100P-M20)
6
DS07-13711-5E
MB90420G/425G Series
■ PIN DESCRIPTIONS
Pin no.
Circuit
type
Symbol
Description
LQFP
80
QFP
82
X0
X1
High speed oscillator input pin.
A
81
83
High speed oscillator output pin.
Low speed oscillator input pin. If no oscillator is connected, apply
pull-down processing.
78
80
X0A
X1A
A
Low speed oscillator output pin. If no oscillator is connected, leave
open.
77
75
79
77
RST
P00
B
Reset input pin.
General purpose input/output port.
UART ch.0 serial data input pin.
INT4 external interrupt input pin.
General purpose input/output port.
UART ch.0 serial data output pin.
INT5 external interrupt input pin.
General purpose input/output port.
UART ch.0 serial clock input/output pin.
INT6 external interrupt input pin.
General purpose input/output port.
UART ch.1 serial data input pin.
INT7 external interrupt input pin.
General purpose input/output port.
UART ch.1 serial data output pin.
General purpose input/output port.
UART ch.1 serial clock input/output pin.
16-bit PPG ch.0-2 external trigger input pin.
General purpose input/output port.
16-bit PPG ch.0 output pin.
83
84
85
85
86
87
SIN0
INT4
P01
G
SOT0
INT5
P02
G
G
SCK0
INT6
P03
86
87
88
88
89
90
SIN1
INT7
P04
G
G
G
SOT1
P05
SCK1
TRG
P06
89
91
PPG0
TOT1
P07
G
16-bit reload timer ch.1 TOT output pin.
General purpose input/output port.
16-bit PPG ch.1 output pin.
90
91
92
93
PPG1
TIN1
P10
G
G
16-bit reload timer ch.1 TIN output pin.
General purpose input/output port.
16-bit PPG ch.2 output pin.
PPG2
(Continued)
DS07-13711-5E
7
MB90420G/425G Series
Pin no.
Circuit
Symbol
type
Description
General purpose input/output port.
LQFP
QFP
P11
TOT0
92
94
G
16-bit reload timer ch.0 TOT output pin.
Real-time watch timer WOT output pin.
General purpose input/output port.
16-bit reload timer ch.0 TIN output pin.
Input capture ch.3 trigger input pin.
General purpose input/output ports.
Input capture ch.0-2 trigger input pins.
WOT
P12
93
95
TIN0
G
G
IN3
P13 to P15
IN2 to IN0
94 to 96 96 to 98
99 to 100, COM0 to
97 to 100
1 to 8,
I
I
LCD controller/driver common output pins.
1 to 2
COM3
3 to 10,
10 to 13 12 to 15
SEG0 to
SEG11
LCD controller/driver segment output pins.
General purpose output ports.
P36 to P37
14 to 15 16 to 17
E
E
E
SEG12 to
SEG13
LCD controller/driver segment output pins.
General purpose input output ports.
LCD controller/driver segment output pins.
General purpose input output ports.
LCD controller/driver segment output pins.
P40 to P47
16 to 20, 18 to 22,
22 to 24 24 to 26
SEG14 to
SEG21
P90, P91
26, 27
34
28, 29
36
SEG22,
SEG23
P50
INT0
General purpose input output ports.
INT0 external interrupt input pin.
G
F
ADTG
A/D converter external trigger input pin.
General purpose input output ports.
P60 to P67
36 to 39, 38 to 41,
41 to 44 43 to 46
AN0 to
AN7
A/D converter input pins.
P51
INT1
General purpose input output port.
INT1 external interrupt input pin.
CAN interface 1 RX intput pin.
General purpose input output port.
INT2 external interrupt input pin.
CAN interface 1 TX output pin.
General purpose input output port.
INT3 external interrupt input pin.
45
47
G
(RX1 *1)
P52
46
50
48
52
INT2
G
G
(TX1 *1)
P53
INT3
(Continued)
8
DS07-13711-5E
MB90420G/425G Series
Pin no.
LQFP QFP
Circuit
type
Symbol
Description
P70 to P73
General purpose input output ports.
PWM1P0
PWM1M0
PWM2P0
PWM2M0
52 to 55 54 to 57
57 to 60 59 to 62
62 to 65 64 to 67
67 to 70 69 to 72
H
H
H
H
Stepping motor controller ch.0 output pins.
General purpose input output ports.
P74 to P77
PWM1P1
PWM1M1
PWM2P1
PWM2M1
Stepping motor controller ch.1 output pins.
General purpose input output ports.
P80 to P83
PWM1P2
PWM1M2
PWM2P2
PWM2M2
Stepping motor controller ch.2 output pins.
General purpose input output ports.
P84 to P87
PWM1P3
PWM1M3
PWM2P3
PWM2M3
Stepping motor controller ch.3 output pins.
P54
TX0
General purpose input output port.
CAN interface 0 TX output pin.
72
73
74
75
G
G
P55
General purpose output port.
RX0
CAN interface 0 RX input pin.
P56
General purpose input output port.
Sound generator SGO output pin.
Free-run timer clock input pin.
74
76
76
78
SGO
FRCK
P57
G
G
General purpose input output port.
Sound generator SGA output pin.
LCD controller /driver reference power supply pins.
SGA
V0 to V3
28 to 31 30 to 33
56, 66 58, 68
51, 61, 71 53, 63, 73
⎯
⎯
High current output buffer with dedicated power supply input pins
(pin numbers 54-57, 59-62, 64-67, 69-72) .
DVCC
DVSS
High current output buffer with dedicated power supply GND pins
(pin numbers 54-57, 59-62, 64-67, 69-72) .
⎯
32
35
33
34
37
35
AVCC
AVSS
⎯
⎯
⎯
A/D converter dedicated power supply input pin.
A/D converter dedicated GND supply pin.
A/D converter Vref + input pin. Vref − AVss.
(Continued)
AVRH
DS07-13711-5E
9
MB90420G/425G Series
(Continued)
Pin no.
Circuit
Symbol
type
Description
LQFP
47, 48
49
QFP
49, 50
51
MD0, MD1
MD2
C
Test mode input pins. Connect to VCC.
C/D *2 Text mode input pin. Connect to VSS.
External capacitor pin. Connect an 0.1 µF capacitor between this
pin and VSS.
25
27
C
⎯
21, 82
23, 84
VCC
VSS
⎯
⎯
Power supply input pins.
GND power supply pins.
9, 40, 79 11, 42, 81
*1 : MB90420G series only.
*2 : Type C in the flash ROM models, type D in the mask ROM models.
10
DS07-13711-5E
MB90420G/425G Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation feedback resistance :
approx. 1 MΩ (X0, X1 : MAIN)
• Oscillation feedback resistance :
approx. 10 MΩ (X0A, X1A : SUB)
X1/X1A
X0/X0A
A
Standby control signal
• Pull-up resistance attached :
approx. 50 kΩ, hysteresis input
B
C
Hysteresis input
Hysteresis input
• Hysteresis input
• Pull-down resistance attached :
approx. 50 kΩ, hysteresis input
Hyteresis input
D
• CMOS output
• LCDC output
• Hysteresis input
E
LCDC output
Hysteresis input
(Continued)
DS07-13711-5E
11
MB90420G/425G Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• Hysteresis input
• Analog input
F
Analog input
Hysteresis input
• CMOS output
• Hysteresis input
G
Hysteresis input
• CMOS high current output
• Hysteresis input
High current
H
Hysteresis input
• LCDC output
I
LCDC output
12
DS07-13711-5E
MB90420G/425G Series
■ HANDLING DEVICES
Precautions for Handling Semiconductor Devices
• Strictly observe maximum rated voltages (prevent latchup)
When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output
pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in
excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup
condition, supply current can increase dramatically and may destroy semiconductor elements. In using semi-
conductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power
supply (AVCC, AVRH) , analog input and dedicated power supply for the high current output buffer pins (DVCC)
do not exceed the digital power supply (VCC) .
Once the digital power supply (VCC) is switched on, the analog power (AVCC,AVRH) and dedicated power supply
for the high current output buffer pins (DVCC) may be turned on in any sequence.
• Stable supply voltage
Even within the warranted operating range of VCC supply voltage, sudden fluctuations in supply voltage can
cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial fre-
quencies (50 Hz to 60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur
during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.
• Power-on procedures
In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during power-
on should be attained within 50 µs (0.2 V to 2.7 V) .
• Treatment of unused pins
If unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanent
damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least
2 kΩ.
Any unused input/output pins should be left open in output status, or if found set to input status, they should be
treated in the same way as input pins.
Any unused output pins should be left open.
• Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS.
• Use of external clock signals
Even when an external clock is used, a stabilization period is required following a power-on reset or release
from sub clock mode or stop mode. Also, when an external clock is used it should drive only the X0 pin and the
X1 pin should be left open, as shown in the following figure.
X0
OPEN
X1
MB90420G/425G Series
Sample external clock connection
DS07-13711-5E
13
MB90420G/425G Series
• Power supply pins
Devices are designed to prevent problems such as latchup when multiple VCC and VSS supply pins are used, by
providing internal connections between pins having the same potential. However, in order to reduce unwanted
radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total
output current ratings, all such pins should always be connected externally to power supplies and ground.
As shown in figure below, all VCC power supply pins must have the same potential. All VSS power supply pins
should be handled in the same way. If there are multiple VCC or VSS systems, the device will not operate properly
even within the warranted operating range.
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VSS
Power supply input pins (VCC/VSS)
In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little
impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC and
VSS as close to the pins as possible.
• Proper sequence of A/D converter power supply analog input
A/D converter power (AVCC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply
(VCC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off
before the digital power supply is switched on (VCC) . In both power-on and shut-off, care should be taken that
AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input ports, be
sure that the input voltage does not exceed AVCC. (There is no problem if analog power supplies and digital
power supplies are turned off and on at the same time.)
• Handling the power supply for high-current output buffer pins (DVCC, DVSS)
Always apply power to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is turned
on. Also when switching power off, always shut off the power supply to the high-current output buffer pins (DVCC,
DVSS) before switching off the digital power supply (VCC) . (There will be no problem if high-current output buffer
pins and digital power supplies are turned off and on at the same time.)
Even when high-current output buffer pins are used as general purpose ports, the power for high current output
buffer pins (DVCC, DVSS) should be applied to these pins.
• Pull-up/pull-down resistance
The MB90420G/425G series does not support internal pull-up/pull-down resistance. If necessary, use external
components.
14
DS07-13711-5E
MB90420G/425G Series
• Precautions for when not using a sub clock signal.
If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave
the X1A pin open.
• Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
DS07-13711-5E
15
MB90420G/425G Series
■ BLOCK DIAGRAM
X0, X1
X0A, X1A
RST
Clock control
CPU
F2MC-16LX core
circuit
RAM
Interrupt
controller
Low voltage/
CPU operation
detection reset
ROM
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
Sound generator
P57/SGA
P56/SGO/FRCK
P55/RX0
P54/TX0
P53/INT3
P52/INT2 (/TX1)
P51/INT1 (/RX1)
P50/INT0/ADTG
Port 8
CAN controller
Port 5
Stepping
motor
Controller
0/1/2/3
External interrupt
(8 ch)
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
P00/SIN0/INT4
P01/SOT0/INT5
P02/SCK0/INT6
P03/SIN1/INT7
P04/SOT1
P05/SCK1/TRG
P06/PPG0/TOT1
P07/PPG1/TIN1
UART0/1
Prescaler
0/1
Port 7
Port 6
Port 0
P67 to P60/
AN7 to AN0
AVCC/AVSS
AVRH
A/D converter
(8 ch)
PPG0/1/2
Port 1
P10/PPG2
P11/TOT0/WOT
P12/TIN0/IN3
P13/IN2
P14/IN1
P15/IN0
P91, P90/
SEG23, SEG22
Port 9
Port 4
Port 3
Reload timer
0/1
P47 to P40/
SEG21 to SEG14
Real-time
Watch timer
P37, P36/
SEG13 to SEG12
ICU0/1/2/3
SEG11 to SEG0
COM3 to COM0
V3 to V0
Free-run timer
LCD controller/
driver
Evaluation device (MB90V420G)
No built-in ROM
Built-in RAM is 6 KB.
Note:MB90420Gseriesisequippedwith2-channelCANinterfaceandMB90425Gseriesisequippedwith1-channel
CAN interface. MB90F423GA, MB90423GA, MB90F428GA, MB90427GA and MB90428GA have low volt-
age/CPUoperationdetectionreset. MB90F423GC, MB90423GC, MB90F428GC, MB90427GC, MB90428GC
and MB90V420G do not have low voltage/CPU operation detection reset.
See “■ Product Lineup” for detail.
16
DS07-13711-5E
MB90420G/425G Series
■ MEMORY MAP
Single chip mode
(with ROM mirror function)
000000
H
Peripheral area
0000C0
H
H
000100
Register
RAM area
Address #2
003900
H
H
Peripheral area
004000
ROM area
(FF bank image)
010000
H
Address #1
FFFFFF
: Internal access memory
: Access prohibited
ROM area
H
Parts No.
Address #1
FE0000H
FF0000H
FE0000H
FE0000H
FE0000H
FE0000H
Address #2
001900H
001100H
001900H
001900H
001900H
001900H
MB90423GA/GC
MB90427GA/GC
MB90428GA/GC
MB90F423GA/GC
MB90F428GA/GC
MB90V420G
Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The
image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of
small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address,
so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example
when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank
ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore
because the ROM data from FF4000H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is
recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH.
DS07-13711-5E
17
MB90420G/425G Series
■ I/O MAP
• Other than CAN Interface
Address
00H
Register name
Port 0 data register
Symbol Read/write Peripheral function Initial value
PDR0
PDR1
R/W
R/W
Port 0
Port 1
XXXXXXXX
- - XXXXXX
01H
Port 1 data register
02H
(Disabled)
03H
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
XX - - - - - -
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
- - - - - -XX
04H
05H
06H
07H
08H
09H
0AH to
0FH
(Disabled)
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Port 0 direction register
Port 1 direction register
DDR0
DDR1
R/W
R/W
Port 0
Port 1
0 0 0 0 0 0 0 0
- - 0 0 0 0 0 0
(Disabled)
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Analog input enable
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
ADER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3
Port 4
0 0 - - - - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
Port 5
Port 6
Port 7
Port 8
Port 9
Port 6, A/D
1 1 1 1 1 1 1 1
1BH to
1FH
(Disabled)
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
A/D control status register lower
A/D control status register higher
A/D data register lower
ADCSL
ADCSH
ADCRL
ADCRH
R/W
R/W
R
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
XXXXXXXX
0 0 1 0 1 XXX
XXXXXXXX
XXXXXXXX
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 - - 0 0 0 0 0
A/D converter
A/D data register higher
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare clear register
Timer data register
CPCLR
TCDT
16-bit free-run timer
Timer control status register lower
Timer control status register higher
TCCSL
TCCSH
(Continued)
18
DS07-13711-5E
MB90420G/425G Series
Address
2AH
2BH
2CH
2DH
2EH
2FH
Register name
Symbol Read/write Peripheral function Initial value
PPG0 control status register lower
PCNTL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 - 0 0
0 0 0 0 0 1 0 0
16-bit PPG0
16-bit PPG1
16-bit PPG2
PPG0 control status register higher PCNTH0
PPG1 control status register lower PCNTL1
PPG1 control status register higher PCNTH1
PPG2 control status register lower PCNTL2
PPG2 control status register higher PCNTH2
30H
External interrupt enable
External interrupt request
External interrupt level lower
External interrupt level higher
Serial mode register 0
ENIR
EIRR
31H
External interrupt
32H
ELVRL
ELVRH
SMR0
SCR0
33H
34H
35H
Serial control register 0
UART 0
Input data register 0/
Output data register 0
SIDR0/
SODR0
36H
R/W
XXXXXXXX
37H
38H
39H
Serial status register 0
Serial mode register 1
Serial control register 1
SSR0
SMR1
SCR1
R/W
R/W
R/W
0 0 0 0 1 0 0 0
0 0 0 0 0 − 0 0
0 0 0 0 0 1 0 0
UART1
Input data register 1/
Output data register 1
SIDR1/
SODR1
3AH
R/W
XXXXXXXX
0 0 0 0 1 0 0 0
3BH
3CH
Serial status register 1
SSR1
R/W
(Disabled)
3DH
Clock division control register 0
CAN wake-up control register
Clock division control register 1
CDCR0
CWUCR
CDCR1
R/W
R/W
R/W
Prescaler
CAN
0 - - - 0 0 0 0
- - - - - - - 0
0 - - - 0 0 0 0
3EH
3FH
Prescaler
40H to 4FH
50H
Area reserved for CAN interface 0
Timer control status register 0 lower TMCSR0L
R/W
0 0 0 0 0 0 0 0
- - - 0 0 0 0 0
Timer control status register 0 high-
51H
TMCSR0H
R/W
er
16-bit reload timer 0
16-bit reload timer 1
52H
53H
54H
XXXXXXXX
XXXXXXXX
0 0 0 0 0 0 0 0
Timer register 0/
Reload register 0
TMR0/
TMRLR0
R/W
Timer control status register 1 lower TMCSR1L
R/W
R/W
Timer control status register 1 high-
55H
TMCSR1H
- - - 0 0 0 0 0
er
56H
57H
58H
59H
XXXXXXXX
XXXXXXXX
0 0 0 - - 0 0 0
0 0 0 0 0 0 0 0
(Continued)
Timer register 1/
Reload register 1
TMR1/
TMRLR1
R/W
Watch timer control register lower
Watch timer control register higher
WTCRL
WTCRH
R/W
R/W
Real-time
watch timer
DS07-13711-5E
19
MB90420G/425G Series
Address
5AH
5BH
5CH
5DH
5EH
5FH
60H
Register name
Sound control register lower
Sound control register higher
Frequency data register
Amplitude data register
Decrement grade register
Tone count register
Symbol Read/write
Peripheral function
Initial value
0 0 0 0 0 0 0 0
0 - - - - - 0 0
XXXXXXXX
0 0 0 0 0 0 0 0
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
0 0 0 0 0 0 0 0
SGCRL
SGCRH
SGFR
R/W
R/W
R/W
R/W
R/W
R/W
Sound generator
SGAR
SGDR
SGTR
Input capture register 0
Input capture register 1
Input capture register 2
Input capture register 3
IPCP0
IPCP1
IPCP2
IPCP3
R
R
R
R
61H
Input capture 0/1
Input capture 2/3
62H
63H
64H
65H
66H
67H
68H
Input capture control status 0/1 ICS01
Input capture control status 2/3 ICS23
R/W
(Disabled)
R/W
Input capture 0/1
Input capture 2/3
69H
6AH
6BH
6CH
6DH
0 0 0 0 0 0 0 0
(Disabled)
R/W
LCD control register lower
LCD control register higher
LCRL
LCRH
0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0
LCD controller/
driver
R/W
Low voltage/CPU operation
detection reset control register
Low voltage/CPU opera-
tion detection reset
6EH
LVRC
R/W
W
1 0 1 1 1 0 0 0
X X X X X X X 1
6FH
ROM mirror
ROMM
ROM mirror
70H to 7FH
Area reserved for CAN interface 1
Stepping motor
controller0
80H
81H
82H
PWM control register 0
PWC0
PWC1
R/W
0 0 0 0 0 - - 0
0 0 0 0 0 - - 0
(Disabled)
R/W
Stepping motor
controller1
PWM control register 1
83H
84H
85H
86H
(Disabled)
R/W
PWM control register 2
PWM control register 3
PWC2
PWC3
Stepping motor controller2 0 0 0 0 0 - - 0
Stepping motor controller3 0 0 0 0 0 - - 0
(Disabled)
R/W
87H to
9DH
(Disabled)
(Continued)
20
DS07-13711-5E
MB90420G/425G Series
Address
Register name
Symbol Read/write Peripheral function Initial value
Address match
detection function
9EH
ROM correction control register
PACSR
R/W
- - - - - 0 - 0
9FH
A0H
A1H
Delay interrupt/release
Power saving mode
Clock select
DIRR
R/W
R/W
R/W
Delayed interrupt
- - - - - - - 0
0 0 0 1 1 0 0 0
1 1 1 1 1 1 0 0
LPMCR
CKSCR
Power saving
control circuit
A2H to
A7H
(Disabled)
A8H
A9H
Watchdog control
WDTC
TBTC
R/W
R/W
Watchdog timer
Time base timer
XXXXX 1 1 1
1 - - 0 0 1 0 0
Time base timer control register
Watch timer
(sub-clock)
AAH
Watch timer control register
WTC
R/W
1 X 0 0 0 0 0 0
ABH to
ADH
(Disabled)
AEH
AFH
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
Flash control register
FMCS
R/W
Flash interface
0 0 0 X 0 XX 0
(Disabled)
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
Interrupt controller
C0H to
FFH
(Disabled)
(Continued)
DS07-13711-5E
21
MB90420G/425G Series
Address
1FF0H
1FF1H
1FF2H
1FF3H
1FF4H
1FF5H
Register name
ROM correction address 0
ROM correction address 1
ROM correction address 2
ROM correction address 3
ROM correction address 4
ROM correction address 5
Symbol Read/write Peripheral function Initial value
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Address match
detection function
3900H to
391FH
(Disabled)
3920H
3921H
3922H
3923H
3924H
3925H
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPG0 down counter register
PPG0 cycle setting register
PPG0 duty setting register
PDCR0
PCSR0
PDUT0
R
W
W
16-bit PPG 0
16-bit PPG 1
16 bit PPG 2
3926H to
3927H
(Disabled)
3928H
3929H
392AH
392BH
392CH
392DH
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPG1 down counter register
PPG1 cycle setting register
PPG1 duty setting register
PDCR1
PCSR1
PDUT1
R
W
W
392EH to
392FH
(Disabled)
3930H
3931H
3932H
3933H
3934H
3935H
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPG2 down counter register
PPG2 cycle setting register
PPG2 duty setting register
PDCR2
PCSR2
PDUT2
R
W
W
3936H to
3959H
(Disabled)
(Continued)
22
DS07-13711-5E
MB90420G/425G Series
Address
395AH
395BH
395CH
395DH
395EH
395FH
Register name
Symbol Read/write Peripheral function Initial value
XXXXXXXX
Sub second data register
WTBR
R/W
XXXXXXXX
- - - XXXXX
- - XXXXXX
- - XXXXXX
- - - XXXXX
Real time
watch timer
Second data register
Minute data register
Hour data register
WTSR
WTMR
WTHR
R/W
R/W
R/W
3960H to
396BH
LCD controller/
driver
LCD display RAM
VRAM
R/W
XXXXXXXX
396CH to
397FH
(Disabled)
3980H
3981H
3982H
3983H
3984H
3985H
XXXXXXXX
- - - - - - XX
XXXXXXXX
- - - - - - XX
- - 0 0 0 0 0 0
- 0 0 0 0 0 0 0
PWM1 compare register 0
PWM2 compare register 0
PWC10
PWC20
R/W
R/W
Stepping motor
controller 0
PWM1 select register 0
PWM2 select register 0
PWS10
PWS20
R/W
R/W
3986H to
3987H
(Disabled)
3988H
3989H
398AH
398BH
398CH
398DH
XXXXXXXX
- - - - - - XX
XXXXXXXX
- - - - - - XX
- - 0 0 0 0 0 0
- 0 0 0 0 0 0 0
PWM1 compare register 1
PWM2 compare register 1
PWC11
PWC21
R/W
R/W
Stepping motor
controller 1
PWM1 select register 1
PWM2 select register 1
PWS11
PWS21
R/W
R/W
398EH to
398FH
(Disabled)
3990H
3991H
3992H
3993H
3994H
3995H
XXXXXXXX
- - - - - - XX
XXXXXXXX
- - - - - - XX
- - 0 0 0 0 0 0
- 0 0 0 0 0 0 0
PWM1 compare register 2
PWM2 compare register 2
PWC12
PWC22
R/W
R/W
Stepping motor
controller 2
PWM1 select register 2
PWM2 select register 2
PWS12
PWS22
R/W
R/W
3996H to
3997H
(Disabled)
(Continued)
DS07-13711-5E
23
MB90420G/425G Series
(Continued)
Address
3998H
Register name
Symbol Read/write Peripheral function Initial value
XXXXXXXX
PWM1 compare register 3
PWC13
PWC23
R/W
R/W
3999H
- - - - - - XX
XXXXXXXX
- - - - - - XX
- - 0 0 0 0 0 0
- 0 0 0 0 0 0 0
399AH
399BH
399CH
399DH
Stepping motor
controller 3
PWM2 compare register 3
PWM1 select register 3
PWM2 select register 3
PWS13
PWS23
R/W
R/W
399EH to
39FFH
(Disabled)
3A00H to
3AFFH
Area reserved for CAN interface 0
Area reserved for CAN interface 1
Area reserved for CAN interface 0
Area reserved for CAN interface 1
(Disabled)
3B00H to
3BFFH
3C00H to
3CFFH
3D00H to
3DFFH
3E00H to
3EFFH
• Initial value symbols :
“0” initial value 0.
“1” initial value 1.
“X” initial value undetermined
“-” initial value undetermined (none)
• Write/read symbols :
“R/W” read/write enabled
“R” read only
“W” write only
• Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access
attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.
24
DS07-13711-5E
MB90420G/425G Series
• I/O Map for CAN Interface
Address
Read/
write
Register name
Message buffer valid area
Transmission request register
Transmission cancel register
Transmission completed register
Receiving completed register
Remote request receiving register
Receiving overrun register
Receiving interrupt enable register
Control status register
Symbol
BVALR
TREQR
TCANR
TCR
Initial value
CAN0
CAN1
000040H 000070H
000041H 000071H
000042H 000072H
000043H 000073H
000044H 000074H
000045H 000075H
000046H 000076H
000047H 000077H
000048H 000078H
000049H 000079H
00004AH 00007AH
00004BH 00007BH
00004CH 00007CH
00004DH 00007DH
00004EH 00007EH
00004FH 00007FH
003C00H 003D00H
003C01H 003D01H
003C02H 003D02H
003C03H 003D03H
003C04H 003D04H
003C05H 003D05H
003C06H 003D06H
003C07H 003D07H
003C08H 003D08H
003C09H 003D09H
003C0AH 003D0AH
003C0BH 003D0BH
003C0CH 003D0CH
003C0DH 003D0DH
003C0EH 003D0EH
003C0FH 003D0FH
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W,R) 0 0 - - - 0 0 0 0 - - - - 0 - 1
RCR
RRTRR
ROVRR
RIER
CSR
Last event indicator register
RX/TX error counter
LEIR
(R/W)
(R)
- - - - - - - - 0 0 0 - 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTEC
BTR
Bit timing register
(R/W) - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IDE register
IDER
(R/W)
XXXXXXXX XXXXXXXX
Transmission RTR register
TRTRR
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Remote frame receiving wait register RFWTR
Transmission interrupt enable register TIER
(R/W)
XXXXXXXX XXXXXXXX
(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(Continued)
DS07-13711-5E
25
MB90420G/425G Series
Address
Read/
write
Register name
Symbol
Initial value
CAN0
CAN1
003C10H 003D10H
003C11H 003D11H
003C12H 003D12H
003C13H 003D13H
003C14H 003D14H
003C15H 003D15H
003C16H 003D16H
003C17H 003D17H
003C18H 003D18H
003C19H 003D19H
003C1AH 003D1AH
003C1BH 003D1BH
003A00H 003B00H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask select register
Acceptance mask register 0
AMSR
(R/W)
(R/W)
AMR0
XXXXX- - -
XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask register 1
General purpose RAM
ID register 0
AMR1
⎯
(R/W)
(R/W)
(R/W)
XXXXX- - -
XXXXXXXX
to
to
XXXXXXXX to XXXXXXXX
XXXXXXXX XXXXXXXX
003A1FH 003B1FH
003A20H 003B20H
003A21H 003B21H
003A22H 003B22H
003A23H 003B23H
003A24H 003B24H
003A25H 003B25H
003A26H 003B26H
003A27H 003B27H
003A28H 003B28H
003A29H 003B29H
003A2AH 003B2AH
003A2BH 003B2BH
003A2CH 003B2CH
003A2DH 003B2DH
003A2EH 003B2EH
003A2FH 003B2FH
003A30H 003B30H
003A31H 003B31H
003A32H 003B32H
003A33H 003B33H
IDR0
XXXXX- - -
XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 1
ID register 2
ID register 3
ID register 4
IDR1
IDR2
IDR3
IDR4
(R/W)
(R/W)
(R/W)
(R/W)
XXXXX- - -
XXXXXXXX
XXXXXXXX XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXXXXX XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXXXXX XXXXXXXX
XXXXX- - -
XXXXXXXX
(Continued)
26
DS07-13711-5E
MB90420G/425G Series
Address
CAN0 CAN1
Read/
write
Register name
Symbol
Initial value
003A34H 003B34H
003A35H 003B35H
003A36H 003B36H
003A37H 003B37H
003A38H 003B38H
003A39H 003B39H
003A3AH 003B3AH
003A3BH 003B3BH
003A3CH 003B3CH
003A3DH 003B3DH
003A3EH 003B3EH
003A3FH 003B3FH
003A40H 003B40H
003A41H 003B41H
003A42H 003B42H
003A43H 003B43H
003A44H 003B44H
003A45H 003B45H
003A46H 003B46H
003A47H 003B47H
003A48H 003B48H
003A49H 003B49H
003A4AH 003B4AH
003A4BH 003B4BH
003A4CH 003B4CH
003A4DH 003B4DH
003A4EH 003B4EH
003A4FH 003B4FH
003A50H 003B50H
003A51H 003B51H
003A52H 003B52H
003A53H 003B53H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 5
IDR5
(R/W)
XXXXX- - -
XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXX- - -
ID register 6
ID register 7
ID register 8
ID register 9
ID register 10
ID register 11
ID register 12
IDR6
IDR7
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
IDR8
IDR9
IDR10
IDR11
IDR12
XXXXXXXX
(Continued)
DS07-13711-5E
27
MB90420G/425G Series
Address
Read/
write
Register name
Symbol
Initial value
CAN0
CAN1
003A54H 003B54H
003A55H 003B55H
003A56H 003B56H
003A57H 003B57H
003A58H 003B58H
003A59H 003B59H
003A5AH 003B5AH
003A5BH 003B5BH
003A5CH 003B5CH
003A5DH 003B5DH
003A5EH 003B5EH
003A5FH 003B5FH
003A60H 003B60H
003A61H 003B61H
003A62H 003B62H
003A63H 003B63H
003A64H 003B64H
003A65H 003B65H
003A66H 003B66H
003A67H 003B67H
003A68H 003B68H
003A69H 003B69H
003A6AH 003B6AH
003A6BH 003B6BH
003A6CH 003B6CH
003A6DH 003B6DH
003A6EH 003B6EH
003A6FH 003B6FH
003A70H 003B70H
003A71H 003B71H
003A72H 003B72H
003A73H 003B73H
003A74H 003B74H
003A75H 003B75H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
ID register 13
ID register 14
ID register 15
IDR13
(R/W)
(R/W)
(R/W)
XXXXX- - -
XXXXXXXX
XXXXX- - -
XXXXXXXX
XXXXX- - -
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
IDR14
IDR15
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLCR0
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
DLCR10 (R/W)
- - - -XXXX
(Continued)
28
DS07-13711-5E
MB90420G/425G Series
Address
CAN0 CAN1
Read/
write
Register name
Symbol
Initial value
003A76H 003B76H
003A77H 003B77H
003A78H 003B78H
003A79H 003B79H
003A7AH 003B7AH
003A7BH 003B7BH
003A7CH 003B7CH
003A7DH 003B7DH
003A7EH 003B7EH
003A7FH 003B7FH
003A80H 003B80H
DLC register 11
DLCR11 (R/W)
DLCR12 (R/W)
DLCR13 (R/W)
DLCR14 (R/W)
DLCR15 (R/W)
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
DLC register 12
DLC register 13
DLC register 14
DLC register 15
- - - -XXXX
- - - -XXXX
- - - -XXXX
- - - -XXXX
to
to
Data register 0 (8 bytes)
Data register 1 (8 bytes)
Data register 2 (8 bytes)
Data register 3 (8 bytes)
Data register 4 (8 bytes)
Data register 5 (8 bytes)
Data register 6 (8 bytes)
Data register 7 (8 bytes)
Data register 8 (8 bytes)
Data register 9 (8 bytes)
DTR0
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
003A87H 003B87H
003A88H 003B88H
to
to
003A8FH 003B8FH
003A90H 003B90H
to
to
003A87H 003B97H
003A98H 003B98H
to
to
003A9FH 003B9FH
003AA0H 003BA0H
to
to
003AA7H 003BA7H
003AA8H 003BA8H
to
to
003AAFH 003BAFH
003AB0H 003BB0H
to
to
003AB7H 003BB7H
003AB8H 003BB8H
to
to
003ABFH 003BBFH
003AC0H 003BC0H
to
to
003AC7H 003BC7H
003AC8H 003BC8H
to
to
XXXXXXXX to XXXXXXXX
003ACFH 003BCFH
(Continued)
DS07-13711-5E
29
MB90420G/425G Series
(Continued)
Address
Read/
write
Register name
Symbol
Initial value
CAN0
003AD0H 003BD0H
to to
CAN1
Data register 10 (8 bytes)
Data register 11 (8 bytes)
Data register 12 (8 bytes)
Data register 13 (8 bytes)
Data register 14 (8 bytes)
Data register 15 (8 bytes)
DTR10
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
XXXXXXXX to XXXXXXXX
003AD7H 003BD7H
003AD8H 003BD8H
to
to
DTR11
DTR12
DTR13
DTR14
DTR15
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
XXXXXXXX to XXXXXXXX
003ADFH 003BDFH
003AE0H 003BE0H
to
to
003AE7H 003BE7H
003AE8H 003BE8H
to
to
003AEFH 003BEFH
003AF0H 003BF0H
to
to
003AF7H 003BF7H
003AF8H 003BF8H
to
to
003AFFH 003BFFH
30
DS07-13711-5E
MB90420G/425G Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt control register
EI2OS
compatible
Interrupt vector
Priority
Interrupt source
2
*
Number Address
#08 08H FFFFDCH
#09 09H FFFFD8H
#10 0AH FFFFD4H
#11 0BH FFFFD0H
#12 0CH FFFFCCH
#13 0DH FFFFC8H
#14 0EH FFFFC4H
#15 0FH FFFFC0H
#16 10H FFFFBCH
#17 11H FFFFB8H
#18 12H FFFFB4H
#19 13H FFFFB0H
#20 14H FFFFACH
#21 15H FFFFA8H
#22 16H FFFFA4H
#23 17H FFFFA0H
#24 18H FFFF9CH
#25 19H FFFF98H
#26 1AH FFFF94H
#27 1BH FFFF90H
#28 1CH FFFF8CH
#29 1DH FFFF88H
#30 1EH FFFF84H
#31 1FH FFFF80H
#32 20H FFFF7CH
#33 21H FFFF78H
#34 22H FFFF74H
#35 23H FFFF70H
#36 24H FFFF6CH
#37 25H FFFF68H
#38 26H FFFF64H
#39 27H FFFF60H
#40 28H FFFF5CH
#41 29H FFFF58H
#42 2AH FFFF54H
ICR
⎯
Address
Reset
×
×
×
×
×
×
×
⎯
⎯
⎯
High
INT9 instruction
⎯
Exception processing
CAN0 RX
⎯
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
0000B0H *1
0000B1H *1
0000B2H *1
0000B3H *1
0000B4H *1
0000B5H *1
0000B6H *1
0000B7H *1
0000B8H *1
0000B9H *1
0000BAH *1
0000BBH *1
0000BCH *1
0000BDH *1
0000BEH *1
0000BFH *1
CAN0 TX/NS
CAN1 RX
CAN1 TX/NS
Input capture 0
DTP/external interrupt - ch 0 detected
Reload timer 0
DTP/external interrupt - ch 1 detected
Input capture 1
DTP/external interrupt - ch 2 detected
Input capture 2
DTP/external interrupt - ch 3 detected
Input capture 3
DTP/external interrupt - ch 4/5 detected
PPG timer 0
DTP/external interrupt - ch 6/7 detected
PPG timer 1
Reload timer 1
PPG timer 2
Real time watch timer
Free-run timer over flow
A/D converter conversion end
Free-run timer clear
Sound generator
×
×
×
×
×
×
Time base timer
Watch timer (sub-clock)
UART 1 RX
UART 1 TX
UART 0 RX
UART 0 TX
Flash memory status
Delayed interrupt generator module
×
×
Low
DS07-13711-5E
31
MB90420G/425G Series
: Compatible, with EI2OS stop function
: Compatible
: Compatible when interrupt sources sharing ICR are not in use
× : Not compatible
*1 : • Peripheral functions sharing the ICR register have the same interrupt level.
• If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other
cannot be used.
• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services,
the interrupt from the other function cannot be used.
*2 : Priority applies when interrupts of the same level are generated.
32
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■ PERIPHERAL FUNCTIONS
1. I/O Ports
The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/O
pins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled in
bit units by the port direction register (DDR) as required. The following list shows each of the functions as well
as the shared peripheral function for each port.
• Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG)
• Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/watch timer/ICU)
• Port 3 : General purpose I/O port, shared with peripheral functions (LCD)
• Port 4 : General purpose I/O port, shared with peripheral functions (LCD)
• Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG)
• Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter)
• Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)
• Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)
• Port 9 : General purpose I/O port, shared with peripheral functions (LCD)
(1) List of Functions
Input
format
Output for-
mat
Port
Pin name
Function
General purpose I/O port
Peripheral function
P00/SIN0/INT4 to
P07/PPG1
Port 0
General purpose I/O port
Peripheral function
P10/PPG2 to
P15/IN0
Port 1
Port 3
Port 4
Port 5
CMOS
(hysteresis)
(Automotive level*)
General purpose I/O port
Peripheral function
P36/SEG12,
P37/SEG13
General purpose I/O port
Peripheral function
P40/SEG14 to
P47/SEG21
General purpose I/O port
Peripheral function
P50/INT0 to
P57/SGA
CMOS
Analog
CMOS
(hysteresis)
(Automotive level*)
General purpose I/O port
P60/AN0 to
P67/AN7
Port 6
Peripheral function
General purpose I/O port
Peripheral function
P70/PWM1P0 to
P77/PWM2M1
Port 7
Port 8
Port 9
CMOS
(hysteresis)
(Automotive level*)
General purpose I/O port
Peripheral function
P80/PWM1P2 to
P87/PWM2M3
General purpose I/O port
Peripheral function
P90/SEG22,
P91/SEG23
(Continued)
DS07-13711-5E
33
MB90420G/425G Series
(Continued)
Port
bit7
P07
PPG1
TIN1
⎯
bit6
P06
bit5
P05
SCK1
⎯
bit4
P04
SOT1
⎯
bit3
P03
SIN1
INT7
P13
IN2
bit2
P02
SCK0
INT6
P12
IN3
bit1
P01
bit0
P00
SIN0
INT4
P10
PPG2
⎯
Port 0
PPG0
TOT1
⎯
SOT0
INT5
P11
P15
IN0
P14
IN1
Port 1
⎯
⎯
WOT
TOT0
⎯
⎯
⎯
⎯
⎯
⎯
TIN0
⎯
P37
SEG13
P47
SEG21
P57
SGA
⎯
P36
⎯
⎯
⎯
⎯
Port 3
Port 4
SEG12
P46
⎯
⎯
⎯
⎯
⎯
⎯
P45
SEG19
P55
RX0
⎯
P44
SEG18
P54
TX0
⎯
P43
SEG17
P53
INT3
⎯
P42
SEG16
P52
INT2
TX1
P62
AN2
P72
P41
P40
SEG14
P50
INT0
⎯
SEG20
P56
SEG15
P51
Port 5
SGO
FRCK
P66
INT1
RX1
P61
P67
AN7
P77
P65
AN5
P75
P64
AN4
P74
P63
AN3
P73
P60
AN0
P70
Port 6
Port 7
Port 8
Port 9
AN6
P76
AN1
P71
PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0
P87 P86 P85 P84 P83 P82 P81 P80
PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 PWM1P2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P91
P90
SEG23
SEG22
*: Range of input voltage.
For ratings see “3. DC Characteristics” in “■ ELECTRICAL CHARACTERISTICS”.
Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write
“0” to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to “1” at reset.
34
DS07-13711-5E
MB90420G/425G Series
(2) Block Diagrams
Ports 0, 1, 3, 4, 5, 7, 8, 9
Peripheral function output
Peripheral function input
Peripheral function output enabled
PDR (Port data register)
PDR read
PDR write
Output latch
Pin
DDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL = 1)
or LCD output enabled
Port 6
ADER
Analog input
PDR (Port data register)
RDR read
Output latch
PDR write
Pin
DDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL = 1)
DS07-13711-5E
35
MB90420G/425G Series
2. Watchdog Timer/Time Base Timer/Watch Timer
The watchdog timer, timer base timer, and watch timer have the following circuit configuration.
• Watchdog timer : Watchdog counter, control register, watchdog reset circuit
• Time base timer : 18-bit timer, interval interrupt control circuit
• Watch timer
: 15-bit timer, interval interrupt control circuit
(1) Watchdog timer function
The watchdog timer is composed of a 2-bit watchdog counter that uses the carry signal from the 18-bit time
base timer or 15-bit watch timer as a clock source, plus a control register and watchdog reset control circuit.
After startup, this function will reset the CPU if not cleared within a given time.
(2) Time base timer function
The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count clock
(base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Other
functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or
other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS
bit or SCS bit in the CKSCR register.
(3) Watch timer function
The watch timer provides functions including a clock source for the watchdog timer, a sub clock base oscillator
stabilization wait timer, and an interval timer to generate an interrupt at fixed intervals. Note that the watch timer
uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.
36
DS07-13711-5E
MB90420G/425G Series
• Block Diagram
Main base oscillator
divided by 2
TBTC
211
213
Clock input
TBC1
TBC0
Selector
216
218
Time base timer
TBR
TBIE
TBOF
211 213 216 218
TBTRES
S
R
AND
Q
Time base
interrupt
WDTC
WT1
2-bit
counter
CLR
Watchdog reset
generator circuit
CLR
Selector
OF
To WDGRST
internal reset
generator circuit
WT0
WTE
WTC
AND
WDCS
SCM
Power-on reset,
sub-clock stop
S
R
SCE
Q
210 213 214 216
28
29
210
211
WTC2
to
WTC0
Selector
212
213
214
216
Watch timer
WTR
WTIE
WTOF
S
R
AND
Q
Clock input
WTRES
Sub base oscillator divided by 4
From power-on generator
Watch interrupt
WDTC
PONR
WRST
ERST
SRST
RST pin
From RST bit in LPMCR
register
DS07-13711-5E
37
MB90420G/425G Series
3. Input Capture
This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits.
(1) Input capture ( × 4)
The input capture circuits consist of four independent external input pins and corresponding capture registers
and control registers. When the specified edge of the external signal input (at the input pin) is detected, the value
of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be
generated.
• The valid edge (rising edge, falling edge, both edges) of the external signal can be selected.
• The four input capture circuits can operate independently.
• The interrupt can be generated from the valid edge of the external input signal.
(2) 16-bit free-run timer ( × 1)
The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and
prescaler. The output values from this counter are used as the base time for the input capture circuits.
• The counter clock operation can be selected from 8 options. The eight internal clock settings are φ, φ/2, φ/4,
φ/8, φ/16, φ/32, φ/64, φ/128 where φ represents the machine clock cycle.
• Interrupts can be generated from overflow events, or from compare match events with the compare register.
(Compare match operation requires a mode setting.)
• The counter value can be initialized to “0000H” by a reset, soft clear, or a compare match with the compare
register.
(3) Block diagram
φ
interrupt
#31 (1F
H)
Divider
Clock
IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0
16-bit free-run timer
Interrupt
#33 (21
16-bit compare clear register
Compare circuit
H)
MSI2 to MSI0
ICLR ICRE
A/D startup
IN0/2
Edge detection
Capture data register 0/2
Capture data register 1/3
EG11
ICP1
EG10
EG01
EG00
Edge detection
IN1/3
ICP0
ICE0
ICE1
Interrupt
#19, #23
Interrupt
#15, #21
38
DS07-13711-5E
MB90420G/425G Series
4. 16-bit Reload Timer
The 16-bit reload timer can either count down in synchronization with three types of internal clock signals in
internal clock mode, or count down at the detection of the designated edge of an external signal. The user may
select either function. This timer defines a transition from 0000H to FFFFH as an underflow event. Thus an
underflow occurs when counting from the value [Reload register setting + 1].
A selection of two counter operating modes are available. In reload mode, the counter is reset to the count value
and continues counting after an underflow, and in one-shot mode the count stops after an underflow. The counter
can generate an interrupt when an underflow occurs, and is compatible with the expanded intelligent I/O services
(EI2OS) .
(1) 16-bit Reload timer operating modes
Clock mode
Counter mode
16-bit reload timer operation
Reload mode
Soft trigger operation
External trigger operation
External gate input operation
Internal clock mode
One-shot mode
Reload mode
Event count mode
(external clock mode)
Soft trigger operation
One-shot mode
(2) Internal clock mode
One of three input clocks is selected as the count clock, and can be used in one of the following operations.
• Soft trigger operation
When “1” is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operation
starts.Trigger input at the TRG bit is normally valid with an external trigger input, as well as an external gate
input.
• External trigger operation
Count operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin.
• External gate input operation
Counting continues as long as the selected signal level (“L” or “H”) is input at the TIN0/1 pin.
(3) Event count mode (External clock mode)
In this mode a down count event occurs when a selected valid edge (rising, falling, both edges) is input at the
TIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used.
(4) Counter operation
• Reload mode
In down count operation, when an underflow event (transition from “0000H” to “FFFFH”) occurs, the set count
value is reloaded and count operation continues. The function can be used as an interval timer by generating
an interrupt request at each underflow event. Also, a toggle waveform that inverts at each underflow can be
output from the TOT0/1 pin.
Counter clock
Internal clock
External clock
Counter clock period
21/φ (0.125 µs)
23/φ (0.5 µs)
25/φ (2.0 µs)
23/φ or greater (0.5 µs)
Interval time
0.125 µs to 8.192 ms
0.5 µs to 32.768 ms
2.0 µs to 131.1 ms
0.5 µs or greater
φ : Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz.
DS07-13711-5E
39
MB90420G/425G Series
(5) One-shot mode
In down count operation, the count stops when an underflow event (transition from “0000H” to “FFFFH”) occurs.
This function can generate an interrupt at each underflow. While the counter is operating, a rectangular wave
form indicating that the count is in progress can be output form the TOT0 and TOT1 pins.
(6) Block diagram
Internal data bus
TMRLR0 *1
<TMRLR1>
16-bit reload register
Reload
control circuit
Reload signal
UF
TMR0 *1
<TMR1>
16-bit timer register (down counter)
CLK
Gate input
Machine
clock
Wait signal
3
Valid clock
decision circuit
Prescaler
To UART 0,1*1
<To A/D converter>
CLK
Output signal
generator
circuit
Input
control
circuit
Clock
selector
Pins
Pins
Inverted
P11/TOT0 *1
<P06/TOT1>
P12/TIN0 *1
<P07/TIN1>
External clock
EN
Select
3
2
signal
Operation
control
Function selection
circuit
⎯
⎯
⎯
⎯
CSL1 CSL0 WOD2 WOD1 WOD0 OUTEOUTL RELD INTE UF CNTE TRG
Timer control status register (TNGSR0)*1
<TNGSR1>
Interrupt
request signal
#17 (11h)*2
<#28 (1CH)>
*
*
1: Channel 0 and channel 1. Figures in < > are for channel 1.
2: Interrupt number
40
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5. Real Time Watch Timer
The real time watch timer is composed of a real time watch timer control register, sub second data register,
second/minute/hourdataregisters, 1/2clockdivider, 21-bitprescalerandsecond/minute/hourcounters. Because
the MCU oscillation frequency operates on a given real time watch timer operation, a 4 MHz frequency is
assumed. The real time watch timer operates as a real world timer and provides real world time information.
• Block diagram
OE
OE
Main oscillator clock
1/2 clock
21-bit
prescaler
WOT
divider
CO
EN
Sub second
register
UPDT
ST
Second
EN counter
LOAD
CI
Hour
counter
Minute
counter
CO
CO
CO
6-bit
6-bit
5-bit
Second/minute/hour register
INTE0 INT0
INTE1 INT1
INTE2 INT2
INTE3 INT3
IRQ#30
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MB90420G/425G Series
6. PPG Timer
The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting,
and 16-bit compare register with buffer for duty setting, plus pin control circuits.
The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the output
pulse can be adjusted by rewriting the values in the two 16-bit registers.
(1) PWM function
Programmable to output a pulse, synchronized with a trigger.
Can also be used as a D/A converter with an external circuit.
(2) One-shot function
Detects the edge of a trigger input, and outputs a single pulse.
(3) Pin control
• Set to “1” at a duty match (priority) .
• Reset to “0” at a counter borrow event
• Has a fixed output mode to output a simple all “L” ( or “H”) signal.
• Polarity can be specified
(4) 16-bit down counter
• Select from four types of counter operation clocks. Four internal clocks (φ, φ/4, φ/16, φ/64) φ : Machine clock
cycles.
• The counter value can be initialized to “FFFFH” at a reset or counter borrow event.
(5) Interrupt requests
• Timer startup
• Counter borrow event (period match)
• Duty match event
• Counter borrow event (period match) or duty match event
(6) Multiple channels can be set to start up at an external trigger, or to restart during operation.
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(7) Block diagram
PCSR
PDUT
Prescaler
1/1
1/4
Load
CK
1/16
1/64
CMP
PCNT
16-bit down counter
Borrow
Start
PPG mask
Machine clock
PPG
output
S
Q
R
Inversion bit
Enable
Interrupt
selection
Interrupt IRQ#25, 27, 29
Trigger input
P05/SCK1/TRG
Edge detection
Soft trigger
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MB90420G/425G Series
7. Delayed Interrupt Generator Module
The delayed interrupt generator module is a module that generates interrupts for task switching. This module
makes it possible to use software to generate/cancel interrupt requests to the F2MC-16LX CPU.
• Block diagram
F2MC-16LX bus
Delayed interrupt source generate/delete decoder
Source latch
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8. DTP/External Interrupt Circuit
The DTP (Data transfer peripheral) /external interrupt circuit is located between an externally connected periph-
eral device and the F2MC-16LX CPU and sends interrupt requests or data transfer requests generated from the
peripheral device to the CPU, thereby generating external interrupt requests or starting the expanded intelligent
I/O services (EI2OS) .
(1) DTP/external interrupt function
The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source.
And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an
external interrupt or start the expanded intelligent I/O service (EI2OS) .
When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI2OS) is
prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the
EI2OS is permitted the interrupt functions as a DTP function, using EI2OS for automatic data transfer, then
branching to an interrupt routine after the completion of the specified number of data transfers.
External interrupt
DTP function
Input pins
8 pins (P50/INT0/ADTG to P53/INT3, P00/SIN0/INT4 to P03/INT7)
Request level setting register (ELVR) sets the detection level, or selected edge for
each pin
Interrupt sources
“H” level/ “L” level/ rising edge/falling
“H” level/ “L” level input
edge input
Interrupt numbers
Interrupt control
Interrupt flags
#16 (10H) , #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) , #26 (1AH)
DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output
DTP/interrupt enable register (EIRR) stores interrupt sources
Process selection
When EI2OS prohibited (ICR : ISE = 0) When EI2OS is enabled (ICR : ISE = 1)
EI2OS performs automatic data transfer,
Branch to external interrupt processing
then after a specified number of cycles,
routine
Processing
branches to an interrupt routine
ICR : Interrupt control register
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MB90420G/425G Series
(2) Block diagram
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
Selector
Selector
Pin
Pin
P03/INT7
P50/INT0
Pin
Selector
Selector
Pin
P02/INT6
P51/INT1
Selector
Selector
Pin
Pin
P01/INT5
P52/INT2
Selector Selector
Pin
Pin
P00/INT4
P53/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#16 (10
#18 (12
#20 (14
#22 (16
H)
H)
H)
H)
#24 (18H)
#26 (1A
H)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
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9. 8/10-bit A/D Converter
The 8/10-bit A/D converter has functions for using RC sequential comparator conversion format to convert analog
input voltage into 10-bit or 8-bit digital values. The input signal is selected from 8-channel analog input pins, and
the conversion start can be selected from three types : by software, 16-bit reload timer 1 or a trigger input from
an external signal pin.
(1) 8/10-bit A/D converter functions
The A/D converter takes analog voltage signals (input voltage) input at analog input pins, and converts these to
digital values, providing the following features.
• Minimum conversion time is 6.13 µs (at machine clock frequency of 16 MHz, including sampling time) .
• Minimum sampling time is 3.75 µs (at machine clock 16 MHz)
• The conversion method is an RC sequential conversion in comparison with a sample hold circuit.
• Either 10-bit or 8-bit resolution can be selected.
• The analog input pin can select from 8 channels by a program setting.
• At completion of A/D conversion, an interrupt request can be generated, or EI2OS can be started.
• Because the conversion data protection function operates in an interrupt enabled state, no data is lost even
in continuous conversion.
• The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external
trigger input (falling edge) .
Three conversion modes are available
Conversion mode
Single conversion operation
Scan conversion operation
Converts multiple consecutive channels (up
to 8 channels may be specified) one time,
then stops.
Converts the specified channel (1 channel
only) one time, then stops.
Single conversion mode
Continuous conversion Converts the specified channel (1 channel Converts multiple consecutive channels (up
mode
only) repeatedly.
to 8 channels may be specified) repeatedly.
Converts multiple consecutive channels (up
to 8 channels may be specified) , however
pauses after conversion of each channel,
waits until the next start is applied.
Converts the specified channel (1 channel
Stop conversion mode only) one time, then pauses, waits until
the next start is applied.
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MB90420G/425G Series
(2) Block diagram
AVCC
AVRH
AVSS
D/A converter
MPX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
Sequential comparator
register
Comparator
AN7
Sample & hold circuit
A/D data register
ADCRH, L
A/D control status register, high
A/D control status register, low
Timer start
Trigger start
16-bit reload timer 1
P50/ADTG
ADCSH, L
Operating clock
φ
Prescaler
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10. UART
The UART is a general purpose serial data communication interface for synchronous communication, or asyn-
chronous (start-stop synchronized) communication withexternal devices. Functions include normal bi-directional
functions, as well as master/slave type communication functions (multi-processor mode : master side only
supported) .
(1) UART Functions
The UART is a general purpose serial data communication interface for sending and receiving of serial data with
other CPU’s or peripheral devices, and provides the following functions.
Functions
Data buffer
Full duplex double buffer
• Clock synchronous (no start/stop bits)
• Clock asynchronous (start-stop synchronized)
Transfer modes
• Exclusive baud rate generator provides a selection of 8 rates
• External clock input enabled
Baud rate
• Internal clock (can use internal clock feed from 16-bit reload timer)
• 7-bit (asynchronous normal mode only)
• 8-bit
Data length
Signal type
NRZ (Non return to zero)
• Framing errors
Receiving error detection
• Overrun errors
• Parity errors (not enabled in multiprocessor mode)
• Receiving interrupt (receiving completed, receiving error detection)
• Sending interrupt (sending completed)
• Sending/receiving both compatible with expanded intelligent I/O services
(EI2OS)
Interrupt request
Master/slave type
communication function 1 (master) -to-n (slave) communication enabled (only master side supported) .
(multi-processor mode)
Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only.
Data length
Operating mode
Synchronization
Stop bit length
No parity
Parity
0
1
2
Normal mode
7-bit or 8-bit
Asynchronous
Asynchronous
Synchronous
1-bit or 2-bit *2
None
Multi-processor mode
Normal mode
8 + 1 *1
⎯
⎯
8
⎯ : Setting not available
*1 : “+ ” indicates an address/data selection bit (A/D) for communication control.
*2 : In receiving only one stop bit is detected.
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MB90420G/425G Series
(2) Block diagram
Control bus
Receiving
interrupt signals
#39 (27H) *
<#37 (25H) *>
Sending
interrupt signals
Exclusive baud
rate generator
Machine clock
Communication
prescaler
Control register
(CDCR)
Sending clock
Clock
selector
#40 (28H) *
<#38 (26H) *>
Receiving
clock
Receiving
control
circuit
Sending
control
circuit
16-bit
reload timer
Pins
P02/SCK0
<P05/SCK1>
Start bit
detection circuit
Sending start
circuit
Receiving bit
counter
Sending bit
counter
Receiving parity
counter
Sending parity
counter
Pin
P01/SOT0
<P04/SOT1>
Receiving
shift register
Sending
shift register
Pins
P00/SIN0
<P03/SIN1>
Rece-
iving
end
Sending start
SIDR0/1
SODR0/1
Receiving status
judging circuit
EI2OS receiving error
generator circuit (to CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
PEN
P
PE
ORE
FRE
RDRF
TDRE
BOS
RIE
SBL
CL
A/D
REC
RXE
TXE
SMR0/1
register
SCR0/1
register
SSR0/1
register
SCKE
SOE
TIE
*: Interrupt number
50
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11. CAN Controller
The CAN controller is a self-contained module within a 16-bit microcomputer (F2MC-16LX) . The CAN (controller
area network) controller is the standard protocol for serial transmissions among automotive controllers and is
widely used in the industry.
(1) CAN controller features
The CAN controller has the following features.
• Conforms to CAN specifications version 2.0 A and B.
Supports sending and receiving in standard frame and expanded frame format.
• Supports data frame sending by means of remote frame receiving.
• 16 sending/receiving message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
• Supports full bit compare, full bit mask as well as partial bet mask filtering.
Provides two receiving mask registers for either standard frame or expanded frame format.
• Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16 MHz)
• CAN WAKE UP function
• The MB90420G series has a two-channel built-in CAN controller. The MB90425G series has a 1-channel built-
in CAN controller.
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(2) Block diagram
F2MC-16LX bus
TQ (operating clock)
Machine
clock
Prescaler 1-to-64
frequency divider
Bit timing generator
SYNC, TSEG1, TSEG2
PSC
PR
PH
RSJ
TOE
TS
BTR
CSR
RS
HALT
IDLE, SUSPND,
TX, RX, ERR,
OVRLD
Bus
state
machine
Node status change
interrupt generator
NIE
NT
NS1,0
Node status
change interrupt
Error
control
RTEC
Send/receive
sequencer
BVALR
TREQR
TBFx
clear
Error
frame
generator
Send buffer
decision
TBF
X
Receiving
Data
counter
filter
Overload
frame
control
generator
TDLC RDLC IDSEL
TBF
X
BITER, STFER,
CRCER, FRMER,
ACKER
Output
driver
TCANR
TRTRR
RFWTR
TCR
TX
ARBLOST
Send shift
register
Stuffing
TBFx, set, clear
ACK
generator
CRC
generator
Sending
completed
interrupt
TDLC
Sending completed
interrupt generator
TIER
CRCER
RBFx, set
RCR
RDLC
STFER
CRC generator
error check
Receiving
completed
interrupt
Receiving completed
interrupt generator
RIER
Receiving
shift register
Destuffing/
stuffing
error check
RBFx, TBFx, set clear
RRTRR
ROVRR
AMSR
AMR0
AMR1
RBFx
IDSEL
set
Arbitration
check
ARBLOST
BITER
Bit error
check
Acknowledge error
check
0
1
Receiving
filter
Receiving bufferx
decision
PH1
ACKER
FRMER
IDR0 ~ 15,
DLCR0 ~ 15,
DTR0 ~ 15,
RAM
RBF
X
Form error
check
Input
latch
RX
RAM address
generator
RBFX, TBFX, RDLC, TDLC, IDSEL
LEIR
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12. LCD Controller/Driver
The LCD controller/driver has a built-in 16 × 8-bit display data memory, and controls the LCD display by means
of four common outputs and 24 segment outputs. A selection of three duty outputs are available. This block can
drive an LCD (liquid crystal display) panel directly.
(1) LCD controller/driver functions
The LCD controller/driver provides functions for directly displaying the contents of display data memory (display
RAM) on the LCD panel by means of segment output and common output.
• LCD drive voltage divider resistance is built-in. External divider resistance can also be connected.
• Up to 4 common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to SEG23) can be used.
• 16-byte display data memory (display RAM) is built-in.
• The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) .
• Drives the LCD directly.
Bias
1/2 duty
1/3 duty
1/4 duty
×
×
1/2 bias
1/3 bias
×
: Recommended mode
× : Use prohibited
Note : When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting, they
cannot be used for segment output.
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MB90420G/425G Series
(2) Block diagram
V0 V1 V2 V3
LCDC control register Low
(LCRL)
Divider resistance
4
COM0
COM1
COM2
COM3
Time base
timer output
Timing
controller
Prescaler
Common
driver
SEG0
SEG1
SEG2
SEG3
SEG4
∼
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
24
Segment
driver
Display RAM,
16 × 8 bits
LCDC control register High
(LCRH)
Driver
Controller
54
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13. Low voltage/Program Looping Detection Reset Circuit
The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when
a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal
is generated.
The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal
reset signal if not cleared within a given time after startup.
(1) Low voltage detection reset circuit
Detection voltage
4.0 V 0.3 V
When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an
internal reset signal is output.
Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage
condition generates an internal reset and releases stop mode.
During an internal RAM write cycle, an internal reset is generated after the completion of writing. During the
output of this internal reset, the reset output from the low voltage detection circuit is suppressed.
(2) Program Looping detection reset circuit
The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts
automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval
elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an
internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has
a width of 5 machine cycles.
Interval duration
220/FC (Approx. 262 ms *)
* : This value assumes an oscillation clock waveform of 4 MHz.
During recovery from standby mode the detection period is the maximum interval plus 20 µs.
This circuit does not operate in modes where CPU operation is stopped.
The Program Looping detection reset circuit counter is cleared under any of the following conditions.
1. Writing “0” to the LVRC register CL bit
2. Internal reset
3. Main oscillation clock stop
4. Transition to sleep mode
5. Transition to time base timer mode or watch mode
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MB90420G/425G Series
(3) Block diagram
Voltage comparator
circuit
V
CC
−
+
V
SS
Constant
voltage
source
Program Looping detection circuit
Main oscillation clock
Counter
Over flow
Noise canceller
Clear
Reserved
Reserved Reserved
CL
LVRF Reserved CPUF
Reserved
Low voltage/CPU operation detection reset control register (LVRC)
Internal data bus
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14. Stepping Motor Controller
The stepping motor controller is composed of two PWM pulse generators, four motor drivers and selector logic
circuits.
The four motor drivers have a high output drive capacity and can be directly connected to the four ends of two
motor coils. They are designed to operate together with the PWM pulse generators and selector logic circuits
to control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse gener-
ators.
• Block diagram
Machine clock
OE1
Output enable
CK
EN
PWM1Pn
PWM1Mn
Prescaler
PWM1 pulse generator
PWM
Selector
P1
P0
PWM1 compare register
PWM2 pulse generator
PWM1 selector register
OE2
Output enable
CK
EN
SC
CE
PWM2Pn
PWM2Mn
Selector
PWM
Load
PWM2 compare register
BS
n : 0 ~ 3
PWM2 select register
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MB90420G/425G Series
15. Sound Generator
The sound generator is composed of a sound control register, frequency data register, amplitude data register,
decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter,
and tone pulse counter.
• Block diagram
Clock input
Prescaler
Frequency
counter
Toggle
flip-flop
8-bit PWM
pulse generator
CO
EN
PWM
CI
CO
EN
D
Q
EN
S1
S0
Reload
Reload
1/d
Frequency data
register
Amplitude data
register
DEC
DEC
Decrement
counter
CI
CO
EN
SGA
OE1
OE1
Decrement grade
register
Blend
SGO
OE2
Tone pulse
counter
TONE OE2
CI
CO
EN
INTE INT
ST
Tone count
register
IRQ#34
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16. Address Match Detect Function
If the address setting is the same as the address detection register, an INT9 instruction is executed. The
integrated address match detection function can be implemented by processing the INT9 interrupt service
routine.
Two address registers are used, each with its own compare enable bit. When there is a match between the
address register and program counter, and the compare enable bit is set to “1” , the INT9 instruction is forcibly
executed by the CPU.
• Block diagram
Address latch
Address detection
register
Enable bit
F2MC-16LX
CPU core
F2MC-16LX bus
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17. ROM Mirror Function Select Module
The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated
to the FF bank to be viewed in the 00 bank.
• Block diagram
F2MC-16LX bus
ROM mirror function select register
Address area
FF bank
00 bank
ROM
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■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
AVRH
DVCC
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VCC + 0.3
VSS − 0.3 VCC + 0.3
V
V
V
V
V
V
AVCC = VCC*2
Power supply voltage*1
AVCC ≥ AVRH*2
DVCC = VCC*2
*3
Input voltage*1
Output voltage*1
VO
Maximum clamp current
ICLAMP
− 400
⎯
+ 400
4
µA *7
Total maximum clamp current Σ | ICLAMP |
mA *7
IOL1
IOL2
⎯
15
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, P80 to P87
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, P80 to P87
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, P80 to P87
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, P80 to P87
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, P80 to P87
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, P80 to P87
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, and P80 to P87
mA Other than P70 to P77, and P80 to P87
mA P70 to P77, P80 to P87
mW
“L”level maximum
output current*4
⎯
40
IOLAV1
⎯
4
“L”level average output
current*5
IOLAV2
⎯
30
Σ IOL1
Σ IOL2
Σ IOLAV1
Σ IOLAV2
IOH1*4
IOH2*4
IOHAV1*5
IOHAV2*5
Σ IOH1
Σ IOH2
Σ IOHAV1*6
Σ IOHAV2*6
PD
⎯
100
“L”level maximum
total output current
⎯
330
⎯
50
“L”level average total
output current
⎯
250
⎯
− 15
− 40
− 4
“H”level maximum
output current
⎯
⎯
“H”level average
output current
⎯
− 30
− 100
− 330
− 50
− 250
500
⎯
“H”level maximum
total output current
⎯
⎯
“H”level average total
output current
⎯
Power consumption
Operating temperature
Storage temperature
⎯
TA
− 40
− 55
+ 105
+ 150
°C
TSTG
°C
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH and DVCC shall never exceed VCC.
Also, AVRH shall never exceed AVCC.
*3 : The maximum current to/from and input is limited by some means with extenal components, the ICLAMP rating
supersedes the VI rating.
*4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the
corresponding pins. The “average value” can be calculated from the formula of “operating current” times
“operating factor”.
(Continued)
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(Continued)
*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the
corresponding pins. The “average value” can be calculated from the formula of “operating current” times
“ operating factor”.
*7 : • Applicable to pins : P00 to P07, P10 to P15, P50 to P57, P70 to P77, P80 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The + B signal should always be applied with a limiting resistance placed between the + B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a + B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply
is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept + B
signal input.
• Sample recommended circuits :
• Input/Output equivalent circuits
Protective diode
VCC
P-ch
Limiting
resistance
+ B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
62
DS07-13711-5E
MB90420G/425G Series
2. Recommended Operating Conditions
Value
(VSS = DVSS = AVSS = 0.0 V)
Parameter Symbol
Unit
Remarks
Min
Max
(MB90F428GA, MB90F423GA, MB90428GA,
MB90427GA, MB90423GA)
Low voltage detection reset starts to work when power
supply voltage is 4.0 V 0.3 V.
3.7
5.5
V
(MB90F428GC, MB90F423GC, MB90428GC,
MB90427GC, MB90423GC)
3.0
4.3
5.5
5.5
V
V
VCC
Power supply
AVCC
voltage
Holding stop operation status
(MB90F428GA, MB90F423GA, MB90428GA,
MB90427GA, MB90423GA)
DVCC
Holding stop operation status
3.0
5.5
V
(MB90F428GC, MB90F423GC, MB90428GC,
MB90427GC, MB90423GC)
Use a ceramic capacitor or other capacitor of equivalent
Smoothing
CS
0.1
1.0
µF frequency characteristics. A bypass capacitor on the VCC pin
capacitor*
should have a capacitance greater than Cs.
Operating
TA
− 40
+ 105
°C
temperature
* : For smoothing capacitor Cs connections, see the illustration below.
• C pin connection
C
AVSS
VSS
DVSS
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
DS07-13711-5E
63
MB90420G/425G Series
3. DC Characteristics
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Typ
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
Min
Max
CMOS hysteresis
Automotive level
input pin*1
MD pin*2
CMOS hysteresis
Automotive level
input pin*1
MD pin*2
⎯
⎯
⎯
⎯
VCC + 0.3
VCC + 0.3
0.5 VCC
VIHS
VIHM
VILS
VILM
⎯
⎯
⎯
⎯
0.8 VCC
VCC − 0.3
VSS − 0.3
⎯
⎯
⎯
V
V
V
“H”level
input voltage
“L”level
input voltage
VSS − 0.3
VSS + 0.3
⎯
V
MB90F428GA/GC
MB90F423GA/GC
MB90428GA/GC
⎯
45
72
mA
Operating frequency
FCP = 16 MHz,
ICC
normal operation
⎯
⎯
⎯
38
15
13
61
24
21
mA MB90427GA/GC
MB90423GA/GC
MB90F428GA/GC
MB90F423GA/GC
MB90428GA/GC
mA MB90427GA/GC
MB90423GA/GC
mA
Operating frequency
FCP = 16 MHz,
sleep mode
ICCS
ICTS
ICCL
Operating frequency
FCP = 2 MHz,
⎯
⎯
0.75
0.35
1.0
0.7
mA
time base timer mode
MB90F428GC
MB90F423GC
mA MB90428GC
MB90427GC
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
subclock operation
MB90423GC
Powersupply
current*3
MB90F428GC
MB90F423GC
µA MB90428GC
MB90427GC
VCC
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
sub sleep operation
ICCLS
⎯
⎯
⎯
⎯
10
40
5
30
100
20
MB90423GC
MB90F428GC
MB90F423GC
µA MB90428GC
MB90427GC
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
watch mode
ICCT
MB90423GC
MB90F428GC
MB90F423GC
µA MB90428GC
MB90427GC
MB90423GC
TA = + 25 °C,
stop mode
ICCH
MB90F428GA
MB90F423GA
µA MB90428GA
MB90427GA
40
100
MB90423GA
(Continued)
64
DS07-13711-5E
MB90420G/425G Series
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Sym
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
Input leakage
current
VCC = DVCC = AVCC = 5.5 V
VSS < VI < VCC
IIL
All input pins
− 5
⎯
5
µA
Other than
Vcc, Vss,
Input
capacitance 1
DVcc, DVss,
Avcc,Avss,C,
P70 to P77,
P80 to P87
CIN1
⎯
⎯
5
15
pF
Input
capacitance 2
P70 to P77,
P80 to P87
CIN2
RUP
⎯
⎯
⎯
⎯
25
25
15
50
50
45
pF
kΩ
kΩ
Pull-up
resistance
RST, MD0,
MD1
100
100
Pull-down
resistance
RDOWN MD2
Other than
VOH1 P70 to P77,
P80 to P87
Output H
voltage 1
VCC = 4.5 V
IOH = −4.0 mA
VCC −
0.5
⎯
⎯
⎯
⎯
⎯
⎯
V
V
V
V
Output H
voltage 2
P70 to P77,
VOH2
VCC = 4.5 V
VCC −
P80 to P87
IOH = −30.0 mA
0.5
Other than
VOL1 P70 to P77,
P80 to P87
Output L
voltage 1
VCC = 4.5 V
IOL = 4.0 mA
⎯
⎯
0.4
0.55
Output L
voltage 2
P70 to P77,
VOL2
VCC = 4.5 V
IOL = 30.0 mA
P80 to P87
PWM1Pn,
PWM1Mn,
∆VOH2 PWM2Pn,
PWM2Mn,
Large current
output drive
capacity
VCC = 4.5 V
IOH = 30.0 mA
0
⎯
90
mV *4
VOH2 maximum variation
variation 1
n = 0 to 3
PWM1Pn,
PWM1Mn,
∆VOL2 PWM2Pn,
PWM2Mn,
Large current
output drive
capacity
VCC = 4.5 V
IOH = 30.0 mA
0
⎯
90
mV *4
VOL2 maximum variation
variation 2
n = 0 to 3
LCD internal
divider
resistance
V0 to V1,
RLCD V1 to V2,
V2 to V3
⎯
50
100
200
kΩ
(Continued)
DS07-13711-5E
65
MB90420G/425G Series
(Continued)
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Typ
Symbol
Parameter
Pin name
Conditions
Unit Remarks
Min
Max
COM0 to
COM3
output imped-
ance
COMn
(n = 0 to 3)
RVCOM
⎯
⎯
⎯
⎯
2.5
kΩ
SEG0 to
SEG3
output imped-
ance
SEGn
(n = 00 to 23)
RVSEG
⎯
⎯
⎯
15
kΩ
V0 to V3
COMm
(m = 0 to 3)
SEGn
LCD leakage
current
ILCDC
− 5.0
⎯
+ 5.0 µA
(n = 00 to 23)
*1 : All input pins except X0, X0A, MD0, MD1, MD2 pins.
*2 : MD0, MD1, MD2 pins.
*3 : Supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware
that supply current levels differ depending on whether an external clock or oscillator is used.
*4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simul-
taneously ON. Similarly for other channels.
66
DS07-13711-5E
MB90420G/425G Series
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Condi-
tions
Parameter
Symbol Pinname
Unit
Remarks
Min
⎯
Typ
4
Max
⎯
FC
FLC
tCYL
tLCYL
X0, X1
X0A, X1A
X0, X1
MHz
kHz
ns
Base oscillation
clock frequency
⎯
32.768
250
⎯
⎯
⎯
Base oscillation
clock cycle time
X0A, X1A
⎯
30.5
⎯
µs
Use duty ratio of
40 to 60% as a guideline
PWH, PWL
PWLH, PWLL
tcr, tcf
X0
X0A
10
⎯
⎯
⎯
15.2
⎯
⎯
⎯
5
ns
µs
ns
Input clock pulse
width
⎯
Input clock
rise, fall time
With external
clock signal
X0, X0A
Using main clock,
PLL clock
FCP
FLCP
tCP
⎯
⎯
⎯
⎯
2
⎯
⎯
16
⎯
MHz
Input operating
clock frequency
8.192
—
kHz Using sub clock
Using main clock,
PLL clock
62.5
⎯
500
⎯
ns
Input operating
clock cycle time
tLCP
122.1
µs Using sub clock
• X0 clock timing
tCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tcf
tcr
• X0A clock timing
tLCYL
0.8 VCC
0.2 VCC
X0A
PWLL
PWLH
tcf
tcr
DS07-13711-5E
67
MB90420G/425G Series
• Range of warranted operation
Relation between internal operating clock frequency and supply voltage
MB90F428GA, MB90F423GA, MB90428GA,
MB90427GA, MB90423GA
MB90V420G
range of warranted
operation
range of warranted operation
5.5
4.5
3.7
3.3
3.0
PLL range of
warranted operation
MB90F428GC, MB90F423GC, MB90428GC,
MB90427GC, MB90423GC
range of warranted operation
2
8
12
16
Internal clock frequency fCP (MHz)
The MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, and MB90423GA
enter reset mode at supply voltage below 4 V 0.3 V.
Relation between oscillator clock frequency and internal operating clock frequency
Internal operating clock frequency
PLL clock
Main clock
Multiplier Multiplier Multiplier Multiplier
× 1
× 2
× 3
× 4
Oscillation clock
frequency
4 MHz
2 MHz
⎯
8 MHz
12 MHz
16 MHz
• Sample oscillator circuit
Oscillator element
manufacturer
Oscillator
Frequency
C1
C2
Murata Manufacturing Co., Ltd. CSTCR4M00G15 ( ) A-R0
4 MHz
39 [pF] (Typ) 39 [pF] (Typ)
MB90F428A
X0
X1
CERALOCK®
C1
C
2
68
DS07-13711-5E
MB90420G/425G Series
AC ratings are defined for the following measurement reference voltage values:
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
0.5 VCC
2.4 V
0.8 V
DS07-13711-5E
69
MB90420G/425G Series
(2) Reset input
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
Symbol Pin name Conditions
Unit
Remarks
Min
Max
16 tCP
⎯
ns In normal operation
In stop mode,
Reset input time
tRSTL
RST
⎯
Oscillator oscillation
sub clock mode,
sub sleep mode,
watch mode
⎯
ms
time* + 16 tCP
*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several
hundred ms; for a FAR/ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this
is 100 µs.
Note : tCP : See “ (1) Clock input timing”.
• Under normal operation
tRSTL
RST
0.5 VCC
0.5 VCC
• In stop mode, sub clock mode, sub sleep mode, watch mode
t
RSTL
RST
X0
0.5 Vcc
0.5 Vcc
90 % of
amplitude
Internal
operation
clock
Oscillator
oscillation time
16 tcp
Oscillator stabilization wait time
Execution of the instruction
Internal
reset
70
DS07-13711-5E
MB90420G/425G Series
(3) Power-on reset, power on conditions
(VSS = 0.0 V, TA = 40 °C to + 105 °C)
Value
Pin
name
Symbol
Parameter
Conditions
Unit
Remarks
Min
0.05
⎯
Max
30
Power supply rise time
tR
ms
V
Power supply start voltage
Power supply attained voltage
Power supply cutoff time
VOFF
VON
tOFF
0.2
⎯
VCC
⎯
2.7
50
V
⎯
ms For repeat operation
tR
2.7 V
V
CC
0.2 V
0.2 V
0.2 V
tOFF
Extreme variations in voltage supply may activate a power-on reset.
As the illustration below shows, when varying supply voltage during operation the use of a smooth
voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the
device should not be used, however it is permissible to use the PLL clock during a voltage drop of
1V/s or less.
VCC
5.0 V
3.0 V
A rise slope of 50 mV or
less is recommended
RAM data hold
V
SS
0 V
DS07-13711-5E
71
MB90420G/425G Series
(4) UART0, UART1 timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Symbol
Conditions
Parameter
Pin name
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC
tSLOV
SCK0, SCK1
8 tCP
⎯
ns
ns
Internal shift
clock mode
SCK0, SCK1
SOT0, SOT1
SCK fall to SOT delay time
− 80
80
⎯
output pin CL =
80 pF + 1•TTL
Valid SIN to SCK rise
tIVSH
tSHIX
tSHSL
tSLSH
100
60
⎯
⎯
⎯
⎯
ns
ns
ns
ns
SCK0, SCK1
SIN0, SIN1
SCK rise to valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
4 tCP
4 tCP
SCK0, SCK1
External shift
clock mode
output pin CL =
80 pF + 1•TTL
SCK0, SCK1
SOT0, SOT1
SCK fall to SOT delay time
tSLOV
⎯
⎯
150
ns
Valid SIN to SCK rise
tIVSH
tSHIX
60
60
⎯
⎯
ns
ns
SCK0, SCK1
SIN0, SIN1
SCK rise to valid SIN hold time
Notes : • AC ratings are for CLK synchronous mode.
• CL is load capacitance connected to pin during testing.
• tCP : See “ (1) Clock timing”.
• Internal shift clock mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.5 VCC
0.8 VCC
0.5 VCC
SIN
• External shift clock mode
SCK
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.5 VCC
tSLOV
0.5 VCC
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.5 VCC
0.8 VCC
0.5 VCC
72
DS07-13711-5E
MB90420G/425G Series
(5) Timer input timing
Parameter
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIN0, TIN1,
IN0, IN1,
IN2, IN3,
tTIWH
tTIWL
Input pulse width
⎯
4 tCP
⎯
ns
Note : tCP : See “ (1) Clock timing”.
• Timer input timing
t
TIWH
tTIWL
0.8 VCC
0.8 VCC
TIN0 ∼ TIN1
IN0 ∼ IN3
0.5 VCC
0.5 VCC
(6) Trigger input timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
Symbol Pin name Conditions
Unit
Remarks
Min
5 tCP
1
Max
⎯
ns Under normal operation
tTRGH,
Input pulse width
INT0 to INT7
⎯
tTRGL
⎯
µs In stop mode
Note : tCP : See “ (1) Clock timing”.
• Trigger input timing
t
TRGH
tTRGL
0.8 VCC
0.8 VCC
INT0 ∼ INT7
0.5 VCC
0.5 VCC
DS07-13711-5E
73
MB90420G/425G Series
(7) Low voltage detection
(VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Symbol
Conditions
Parameter
Pin name
Unit
Remarks
Min
Typ
Max
Duringvoltage
drop
Detection voltage
Hysteresis width
VDL
VCC
VCC
⎯
⎯
3.7
4.0
4.3
V
V
Duringvoltage
rise
VHYS
0.1
⎯
⎯
Powersupplyvoltage
fluctuation ratio
dV/dt
td
VCC
⎯
⎯
− 0.1
⎯
⎯
0.02
35
V/µs
µs
Detection delay time
⎯
⎯
Internal reset
VCC
dV
dt
VDL
VHYS
td
td
74
DS07-13711-5E
MB90420G/425G Series
5. A/D Conversion Block
(1) Electrical Characteristics
(VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
Resolution
Symbol Pin name
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
5.0
LSB
LSB
LSB
Non-linear error
Differential linear error
⎯
⎯
2.5
⎯
⎯
1.9
AVSS
AVSS
AVSS
Zero transition voltage
VOT
AN0 to AN7
AN0 to AN7
V
V
1 LSB =
(AVRH − AVSS)
/ 1024
− 3.5 LSB + 0.5 LSB + 4.5 LSB
AVRH AVRH AVRH
− 6.5 LSB − 1.5 LSB + 1.5 LSB
Full scale transition
voltage
VFST
Sampling time
tSMP
tCMP
tCNV
⎯
⎯
⎯
2.000
4.125
6.125
⎯
⎯
⎯
⎯
⎯
⎯
µs
µs
µs
*1
Compare time
*2
*3
A/D conversion time
Analog port
input current
IAIN
AN0 to AN7
⎯
⎯
10
µA
VAVSS = VAIN = VAVCC
Analog input current
Reference voltage
VAIN
AVR+
IA
AN0 to AN7
AVRH
0
⎯
⎯
AVRH
AVCC
6.0
5
V
V
3.0
⎯
⎯
50
⎯
⎯
2.3
⎯
mA
Power supply current
AVCC
IAH
µA *4
IR
AVRH
AVRH
180
⎯
260
5
µA
VAVRH = 5.0 V
Reference voltage feed
current
IRH
µA *4
LSB
Inter-channel variation
—
AN0 to AN7
⎯
4
*1 : At FCP = 16 MHz, tSMP = 32 × tCP = 2.000 (µs) .
*2 : At FCP = 16 MHz, tCMP = 66 × tCP = 4.125 (µs) .
*3 : Equivalent to conversion time per channel at FCP = 16 MHz, and selection of tSMP = 32 × tCP and tCMP = 66 × tCP.
*4 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in
stop mode.
DS07-13711-5E
75
MB90420G/425G Series
• Notes of the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion presicion.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
C
MB90420GA/420GC
MB90F420GA/F420GC
MB90V420G
2.4 kΩ (Max)
2.6 kΩ (Max)
3.2 kΩ (Max)
36.4 pF (Max)
28.0 pF (Max)
30.0 pF (Max)
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
MB90V420G
20
MB90V420G
100
90
18
MB90F420GA/
MB90F420GA/
F420GC
80
70
60
50
40
30
20
10
0
16
14
12
10
8
F420GC
MB90420GA/
420GC
MB90420GA/
420GC
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVRH| becomes smaller, values of relative errors grow larger.
76
DS07-13711-5E
MB90420G/425G Series
(2) Definition of terms
• Resolution
Indicates the ability of the A/D converter to discriminate in analog conversion.
10-bit resolution indicates that analog voltage can be resolved into 210 = 1024 levels.
• Total error
Expresses the difference between actual and logical values. It is the total value of errors that can come from
offset error, gain error, non-linearity error and noise.
• Linearity error
Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s
zero transition point (00 0000 0000 ←→ 00 0000 0001) and full scale transition point (11 1111 1110 ←→ 11
1111 1111) .
• Differential linearity error
Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output code.
• 10-bit A/D converter conversion characteristics
11 1111 1111
11 1111 1110
11 1111 1101
11 1111 1100
.
.
.
1 LSB × N + VOT
.
.
.
.
.
.
Linearity error
.
.
.
.
00 0000 0011
00 0000 0010
00 0000 0001
00 0000 0000
VOT
VNT V(N + 1)T
VFST
Analog input
VFST − VOT
1 LSB =
Linearity error =
1022
VNT − (1 LSB × N + VOT)
[LSB]
1 LSB
V (N + 1) T − VNT
Differential linearity error =
− 1 [LSB]
1 LSB
DS07-13711-5E
77
MB90420G/425G Series
6. Flash Memory Program and Erase Performances
Value
Conditions
Parameter
Unit
Remarks
Min
⎯
Typ
1
Max
15
Sector erase time
Chip erase time
s
s
Excludes 00H programming prior erasure
Excludes 00H programming prior erasure
TA = + 25 °C
VCC = 5.0 V
⎯
5
⎯
Word (16 bit width)
programming time
⎯
10,000
10
16
⎯
⎯
3,600
⎯
µs Excludes system-level overhead
cycle
Erase/Program cycle
⎯
Flash data
retention time
Average
TA = + 85 °C
⎯
year *
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C)
78
DS07-13711-5E
MB90420G/425G Series
■ EXAMPLE CHARACTERISTICS
ICC − VCC (TA = + 25 °C)
40
35
30
25
20
15
10
5
FC = 16 MHz
FC = 11 MHz
FC = 8 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
0
3.5
4.5
5.5
6.5
VCC (V)
ICTS − VCC (TA = + 25 °C)
900
800
700
600
500
400
300
200
100
FC = 16 MHz
FC = 11 MHz
FC = 8 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
0
3.5
4.5
5.5
6.5
VCC (V)
ICCL − VCC (FC = 8 kHz)
500
400
300
200
100
TA = +25 °C
TA = +125 °C
TA = −40 °C
0
3.5
4.5
5.5
6.5
VCC (V)
DS07-13711-5E
79
MB90420G/425G Series
(Continued)
(Continued)
ICCLS − VCC (FC = 8 kHz)
70
60
50
40
30
20
10
0
TA = +125 °C
TA = +25 °C
TA = −40 °C
3.5
4.5
5.5
6.5
VCC (V)
ICCT − VCC (FC = 8 kHz)
70
60
50
40
30
20
10
0
TA = +125 °C
TA = +25 °C
TA = −40 °C
3.5
4.5
5.5
6.5
VCC (V)
80
DS07-13711-5E
MB90420G/425G Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F423GAPF
MB90F423GCPF
MB90F428GAPF
MB90F428GCPF
MB90423GAPF
MB90423GCPF
MB90427GAPF
MB90427GCPF
MB90428GAPF
MB90428GCPF
Plastic QFP, 100-pin
(FPT-100P-M06)
MB90F423GAPMC
MB90F423GCPMC
MB90F428GAPMC
MB90F428GCPMC
MB90423GAPMC
MB90423GCPMC
MB90427GAPMC
MB90427GCPMC
MB90428GAPMC
MB90428GCPMC
Plastic LQFP, 100-pin
(FPT-100P-M20)
DS07-13711-5E
81
MB90420G/425G Series
■ PACKAGE DIMENSIONS
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8˚
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-13711-5E
82
MB90420G/425G Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +–00..1200 .059 +–..000048
(Mounting height)
INDEX
0.10±0.10
(.004±.004)
(Stand off)
100
26
0˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
1
25
0.50(.020)
0.20±0.05
(.008±.002)
0.145±0.055
(.0057±.0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2
2005 FUJITSU LIMITED F100031S-c-2-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13711-5E
83
MB90420G/425G Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
The package code is changed.
(FPT-100P-M05 → FPT-100P-M20)
-
-
5
■ PIN ASSIGNMENTS
Figure of QFP package pin assignment is changed.
Order informations are changed.
(MB90423GAPFV → MB90423GAPMC,
MB90423GCPFV → MB90423GCPMC,
MB90427GAPFV → MB90427GAPMC,
MB90427GCPFV → MB90427GCPMC,
81 ■ ORDERING INFORMATION MB90428GAPFV → MB90428GAPMC,
MB90428GCPFV → MB90428GCPMC,
MB90F423GAPFV→ MB90F423GAPMC,
MB90F423GCPFV→ MB90F423GCPMC,
MB90F428GAPFV→ MB90F428GAPMC,
MB90F428GCPFV→ MB90F428GCPMC)
The package figure is changed.
83
■ PACKAGE DIMENSIONS
(FPT-100P-M05 → FPT-100P-M20)
The vertical lines marked in the left side of the page show the changes.
84
DS07-13711-5E
MB90420G/425G Series
MEMO
DS07-13711-5E
85
MB90420G/425G Series
MEMO
86
DS07-13711-5E
MB90420G/425G Series
MEMO
DS07-13711-5E
87
MB90420G/425G Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
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