MB90F347PFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13730-1E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90340 Series

MB90F342/C(S), MB90F343/C(S), MB90F345/C(S), MB90F346/C(S), MB90F347/C(S),

MB90F349/C(S), MB90341/C(S), MB90342/C(S), MB90346/C(S), MB90347/C(S),

MB90348/C(S), MB90349/C(S), MB90V340(S)

■ DESCRIPTION

The MB90340-series with up to 2 FULL-CAN* interfaces and FLASH ROM is especially designed for automotive

and industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and

Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full

CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program

memory up to 512 Kbytes. An internal voltage booster removes the necessity for a second programming voltage.

An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms

of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external

4 MHz clock.

The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free

running timers. 4 UARTs constitute additional functionality for communication purposes.

* : Controller Area Network (CAN) - License of Robert Bosch GmbH

Note : F²MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

■ PACKAGES

100-pin Plastic QFP

100-pin Plastic LQFP

(FPT-100P-M06)

(FPT-100P-M05)

MB90340 Series

■ FEATURES

• Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and

multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).

• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed. (devices without S-

suffix only)

• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-

plied PLL clock).

• 16 Mbyte CPU memory space

• 24-bit internal addressing

• Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes(23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

• Increased processing speed

• 4-byte instruction queue

• Powerful interrupt function

• Powerful 8-level, 34-condition interrupt feature

• Up to 16 external interrupts are supported

• Automatic data transfer function independent of CPU

• Expanded intelligent I/O service function (EI²OS) : up to 16 channels

• DMA : up to 16 channels

• Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)

• Watch mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode

• Process

• CMOS technology

• I/O port

• General-purpose input/output port (CMOS output)

- 80 ports (devices without S-suffix)

- 82 ports (devices with S-suffix)

• Timer

• Time-base timer, clock timer, watchdog timer : 1 channel

• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels

• 16-bit reload timer : 4 channels

• 16- bit input/output timer

- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)

2

MB90340 Series

- 16- bit input capture: (ICU) : 8 channels

- 16-bit output compare : (OCU) : 8 channels

• Full-CAN interface : up to 2 channels

• Compliant with Ver2.0A and Ver2.0B CAN specifications

• Flexible message buffering (mailbox and FIFO buffering can be mixed)

• CAN wake-up function

• UART (LIN/SCI) : up to 4 channels

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available

• I²C interface* : up to 2 channels (devices with C-suffix only)

• Up to 400 kbit/s transfer rate

• DTP/External interrupt : up to 16 channels, CAN wakeup : up to 2 channels

• Module for activation of expanded intelligent I/O service (EI²OS), DMA, and generation of external interrupt.

• Delay interrupt generator module

• Generates interrupt request for task switching.

• 8/10-bit A/D converter : 16/24 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)

• Program patch function

• Address matching detection for 6 address pointers.

• Internal voltage regulator

• Supports 3 V MCU core, offering low EMI and low power consumption figures

• Programmable input levels

• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)

• TTL level (initial level for External bus mode)

• ROM security function

• Protects the content of ROM (MASK ROM device only)

• External bus interface

• Clock monitor function

* : I²C license :

This product includes licensing of Phillips I²C patents if used by the customer in an I²C system subject to the I²C

standard specifications established by Phillips.

3

MB90340 Series

■ PRODUCT LINEUP

MB90F342/C(S),MB90F343/C(S)*¹, MB90F345/C(S),

MB90F346/C(S), MB90F347/C(S), MB90F349/C(S),

MB90341/C(S)*¹, MB90342/C(S)*¹, MB90346/C(S) ,

MB90347/C(S), MB90348/C(S)*¹, MB90349/C(S)*¹

Part Number

MB90V340(S)

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)

System clock

Boot-block, Flash memory

512 Kbytes : MB90F345/C (S)

384 Kbytes : MB90F343/C (S)

256 Kbytes : MB90F342/C (S) , MB90F349/C (S) , MB90342/C (S) ,

MB90349/C (S)

ROM

External

128 Kbytes : MB90F347/C (S) , MB90341/C (S) , MB90348/C (S) ,

MB90347/C (S)

64 Kbytes : MB90F346/C (S) , MB90346/C (S)

20 Kbytes : MB90F343/C (S) , MB90F345/C (S)

16 Kbytes : MB90F342/C (S) , MB90F349/C (S) , MB90341/C (S) ,

MB90342/C (S) , MB90348/C (S) , MB90349/C (S)

6 Kbytes : MB90F347/C (S) , MB90347/C (S)

RAM

30 Kbytes

Yes

2 Kbytes : MB90F346/C (S) , MB90346/C (S)

Emulator-specific

power supply^*2

0.35 µm CMOS with on-chip voltage regulator for internal

power supply + Flash memory with

On-chip charge pump for programming voltage

0.35 µm CMOS with

on-chip voltage regulator

for internal power supply

Technology

3.5 V - 5.5 V : at normal operating (not using A/D converter)

4.0 V - 5.5 V : at using A/D converter/Flash programming

4.5 V - 5.5 V : at using external bus

Operating

voltage range

5 V ± 10%

Temperature range

Package

−40 °C to +105 °C

QFP-100, LQFP-100

PGA-299

4 channels

5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

devices with ‘C’-suffix

devices without ‘C’-suffix :

: 2ch

I²C (400 kbit/s)

2 channel

devices with ‘C’-suffix

devices without ‘C’-suffix : 16ch

: 24ch

24 input channels

A/D

Converter

10-bit or 8-bit resolution

Conversion time : Min 3 µs include sample time (per one channel)

16-bit Reload Timer Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = Machine clock frequency)

(4 channels)

Supports External Event Count function

Signals an interrupt when overflowing

Supports Timer Clear when a match with Output Compare (Channel 0, 4)

Operation clock freq. : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = Machine clock freq.)

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7

16-bit

I/O Timer

(2 channels)

(Continued)

4

MB90340 Series

MB90F342/C(S),MB90F343/C(S)*¹,MB90F345/C(S),MB90F346/C(S),

Part Number

MB90F347/C(S), MB90F349/C(S), MB90341/C(S)*¹, MB90342/C(S)*¹, MB90V340(S)

MB90346/C(S) , MB90347/C(S), MB90348/C(S)*¹, MB90349/C(S)*¹

Parameter

16-bit Output

Compare

(8 channels)

Signals an interrupt when 16-bit I/O Timer match output compare registers.

A pair of compare registers can be used to generate an output signal.

16-bit Input Capture Rising edge, falling edge or rising & falling edge sensitive

(8 channels)

Signals an interrupt upon external event

Supports 8-bit and 16-bit operation modes

Sixteen 8-bit reload counters

8/16-bit

Sixteen 8-bit reload registers for L pulse width

ProgrammablePulse Sixteen 8-bit reload registers for H pulse width

Generator

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

(8 channels)

8-bit prescaler plus 8-bit reload counter

Operation clock freq. : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 µs@fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

2 channels : MB90F342/C (S) , MB90F343/C (S) , MB90F345/C (S) ,

MB90341/C (S) , MB90342/C (S)

1channel : MB90F346/C (S) , MB90F347/C (S) , MB90F349/C (S) ,

MB90346/C (S) , MB90347/C (S) , MB90348/C (S) ,

MB90349/C (S)

3 channels

Conforms to CAN Specification Version 2.0 Part A and B

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID’s

Supports multiple messages

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps

External Interrupt

(16 channels)

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

expanded inteligent I/O services (EI²OS) and DMA

D/A converter

2 channels

Up to100 kHz

Subclock for low

power operation

devices with ‘S’-suffix

devices without ‘S’-suffix : without subclock

: with subclock

Virtually all external pins can be used as general purpose I/O port

All push-pull outputs

I/O Ports

Bit-wise settable as input/output or peripheral signal

Settable in pin-wise of 8 as CMOS schmitt trigger/ automotive inputs (default)

TTL input level settable for external bus (32-pin only for external bus)

(Continued)

5

MB90340 Series

(Continued)

MB90F342/C(S),MB90F343/C(S)*¹,MB90F345/C(S),MB90F346/C(S),

MB90F347/C(S), MB90F349/C(S), MB90341/C(S)*¹, MB90342/C(S)*¹,

MB90346/C(S) , MB90347/C(S), MB90348/C(S)*¹, MB90349/C(S)*¹

Part Number

MB90V340(S)

Parameter

Supports automatic programming, Embedded Algorithm^TM*3

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Data retention time : 10 years

Flash

Memory

Boot block configuration

Erase can be performed on each block

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash (except for

MB90F346/C (S) )

ROM Security

Protects the content of ROM (MASK ROM device only)

*1 : The devices other than MB90F342/C (S) , MB90F345/C (S) , MB90F346/C (S) , MB90F347/C (S) ,

MB90F349/C (S) , MB90346/C (S) and MB90347/C (S) are under development.

*2 : It is setting of Jumper switch (TOOL V^CC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

6

MB90340 Series

■ PIN ASSIGNMENTS

• MB90V340(S)

(TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81

P75/AN21/INT5

P74/AN20/INT4

P73/AN19/INT3

P72/AN18/INT2

P71/AN17/INT1

P70/AN16/INT0

Vss

P04/AD04/INT12

P05/AD05/INT13

P06/AD06/INT14

P07/AD07/INT15

P10/AD08/TIN1

P11/AD09/TOT1

P12/AD10/SIN3/NT11R

P13/AD11/SOT3

P14/AD12/SCK3

Vcc

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P61/AN1/PPG2(3)

P60/AN0/PPG0(1)

AVss

QFP - 100

Vss

X1

X0

P15/AD13/SIN4

P16/AD14/SOT4

P17/AD15/SCK4

P20/A16/PPG9(8)

P21/A17/PPGB(A)

P22/A18/PPGD(C)

P23/A19/PPGF(E)

AVRL

AVRH

AVcc

P57/AN15/DA01

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

(FPT-100P-M06)

* : MB90V340: X0A, X1A

MB90V340S: P40, P41

(Continued)

7

MB90340 Series

(Continued)

(TOP VIEW)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

P01/AD01/INT9

P02/AD02/INT10

P03/AD03/INT11

P04/AD04/INT12

P05/AD05/INT13

P06/AD06/INT14

P07/AD07/INT15

P10/AD08/TIN1

P11/AD09/TOT1

P12/AD10/SIN3/NT11R

P13/AD11/SOT3

P14/AD12/SCK3

Vcc

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

MD1

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

MD2

P75/AN21/INT5

P74/AN20/INT4

P73/AN19/INT3

P72/AN18/INT2

P71/AN17/INT1

P70/AN16/INT0

Vss

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P61/AN1/PPG2(3)

P60/AN0/PPG0(1)

AVss

LQFP - 100

Vss

X1

X0

P15/AD13/SIN4

P16/AD14/SOT4

P17/AD15/SCK4

P20/A16/PPG9(8)

P21/A17/PPGB(A)

P22/A18/PPGD(C)

P23/A19/PPGF(E)

P24/A20/IN0

AVRL

AVRH

AVcc

P57/AN15/DA01

P56/AN14/DA00

P55/AN13

P25/A21/IN1

P54/AN12/TOT3

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

(FPT-100P-M05)

* : MB90V340 : X0A, X1A

MB90V340S : P40, P41

8

MB90340 Series

• MB90F342 (S) /MB90F343 (S) /MB90F345 (S) /MB90F346 (S) /MB90F347 (S) /MB90F349 (S) /MB90341 (S) /MB90342 (S) ,

MB90346 (S) /MB90347 (S) /MB90348 (S) /MB90349 (S)

(TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P75/INT5

P74/INT4

P73/INT3

P72/INT2

P71/INT1

P70/INT0

P04/AD04/INT12

P05/AD05/INT13

P06/AD06/INT14

P07/AD07/INT15

P10/AD08/TIN1

P11/AD09/TOT1

P12/AD10/SIN3/NT11R

P13/AD11/SOT3

P14/AD12/SCK3

Vcc

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

Vss

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P61/AN1/PPG2(3)

P60/AN0/PPG0(1)

AVss

QFP - 100

Vss

X1

X0

P15/AD13

P16/AD14

P17/AD15

P20/A16/PPG9(8)

P21/A17/PPGB(A)

P22/A18/PPGD(C)

P23/A19/PPGF(E)

AVRL

AVRH

AVcc

P57/AN15

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

(FPT-100P-M06)

* : MB90F342/F343/F345/F346/F347/F349/341/342/346/347/348/349 : X0A, X1A

MB90F342S/F343S/F345S/F346S/F347S/F349S/341S/342S/346S/347S/348S/349S : P40,P41

(Continued)

9

MB90340 Series

(Continued)

(TOP VIEW)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

76

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79

80

81

82

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88

89

90

91

92

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97

98

99

100

MD1

P01/AD01/INT9

P02/AD02/INT10

P03/AD03/INT11

P04/AD04/INT12

P05/AD05/INT13

P06/AD06/INT14

P07/AD07/INT15

P10/AD08/TIN1

P11/AD09/TOT1

P12/AD10/SIN3/NT11R

P13/AD11/SOT3

P14/AD12/SCK3

Vcc

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

MD2

P75/INT5

P74/INT4

P73/INT3

P72/INT2

P71/INT1

P70/INT0

Vss

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P61/AN1/PPG2(3)

P60/AN0/PPG0(1)

AVss

LQFP - 100

Vss

X1

X0

P15/AD13

P16/AD14

P17/AD15

AVRL

P20/A16/PPG9(8)

P21/A17/PPGB(A)

P22/A18/PPGD(C)

P23/A19/PPGF(E)

P24/A20/IN0

AVRH

AVcc

P57/AN15

P56/AN14

P55/AN13

P25/A21/IN1

P54/AN12/TOT3

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

(FPT-100P-M05)

* : MB90F342/F343/F345/F346/F347/F349/341/342/346/347/348/349 : X0A, X1A

MB90F342S/F343S/F345S/F346S/F347S/F349S/341S/342S/346S/347S/348S/349S : P40,P41

10

MB90340 Series

• MB90F342C (S) /MB90F343C (S) /MB90F345C (S) /MB90F346C (S) /MB90F347C (S) /MB90F349C (S) /

MB90341C (S) /MB90342C (S) ,

MB90346C (S) /MB90347C (S) /MB90348C (S) /MB90349C (S)

(TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

P75/AN21/INT5

P74/AN20/INT4

P73/AN19/INT3

P72/AN18/INT2

P71/AN17/INT1

P70/AN16/INT0

Vss

P04/AD04/INT12

P05/AD05/INT13

P06/AD06/INT14

P07/AD07/INT15

P10/AD08/TIN1

P11/AD09/TOT1

P12/AD10/SIN3/NT11R

P13/AD11/SOT3

P14/AD12/SCK3

Vcc

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P61/AN1/PPG2(3)

P60/AN0/PPG0(1)

QFP - 100

Vss

X1

X0

P15/AD13

P16/AD14

P17/AD15

AVss

P20/A16/PPG9(8)

P21/A17/PPGB(A)

P22/A18/PPGD(C)

P23/A19/PPGF(E)

AVRL

AVRH

AVcc

P57/AN15

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

(FPT-100P-M06)

* : MB90F342C/F343C/F345C/F346C/F347C/F349C/341C/342C/346C/347C/348C/349C : X0A, X1A

MB90F342CS/F343CS/F345CS/F346CS/F347CS/F349CS/341CS/342CS/346CS/347CS/348CS/349CS : P40, P41

(Continued)

11

MB90340 Series

(Continued)

(TOP VIEW)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

76

P01/AD01/INT9

P02/AD02/INT10

P03/AD03/INT11

P04/AD04/INT12

P05/AD05/INT13

P06/AD06/INT14

P07/AD07/INT15

P10/AD08/TIN1

P11/AD09/TOT1

P12/AD10/SIN3/NT11R

P13/AD11/SOT3

P14/AD12/SCK3

Vcc

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

MD1

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1

MD2

P75/AN21/INT5

P74/AN20/INT4

P73/AN19/INT3

P72/AN18/INT2

P71/AN17/INT1

P70/AN16/INT0

Vss

P67/AN7/PPGE(F)

P66/AN6/PPGC(D)

P65/AN5/PPGA(B)

P64/AN4/PPG8(9)

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P61/AN1/PPG2(3)

P60/AN0/PPG0(1)

AVss

LQFP - 100

Vss

X1

X0

P15/AD13

P16/AD14

P17/AD15

AVRL

P20/A16/PPG9(8)

P21/A17/PPGB(A)

P22/A18/PPGD(C)

P23/A19/PPGF(E)

P24/A20/IN0

AVRH

AVcc

P57/AN15

P56/AN14

P55/AN13

P25/A21/IN1

P54/AN12/TOT3

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

(FPT-100P-M05)

* : MB90F342C/F343C/F345C/F346C/F347C/F349C/341C/342C/346C/347C/348C/349C : X0A, X1A

MB90F342CS/F343CS/F345CS/F346CS/F347CS/F349CS/341CS/342CS/346CS/347CS/348CS/349CS : P40, P41

12

MB90340 Series

■ PIN DESCRIPTION

Pin No.

Circuit

type

Pin name

Function

LQFP100*²QFP100*¹

90

91

52

92

93

54

X1

X0

Oscillation output

Oscillation input

Reset input

A

E

RST

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P00 to P07

75 to 82

77 to 84

G

I/O pins for 8 lower bits of the external address/data bus.

This function is enabled when the external bus is enabled.

AD00 to AD07

INT8 to INT15

External interrupt request input pins for INT8 to INT15.

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P10

83

85

I/O pin for 8th bit of the external address/data bus.

This function is enabled when the external bus is enabled.

AD08

TIN1

Event input pin for the reload timer 1

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P11

84

86

I/O pin for 9th bit of the external address/data bus.

This function is enabled when the external bus is enabled.

AD09

TOT1

Output pin for the reload timer 1

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P12

I/O pin for 10th bit of the external address/data bus.

This function is enabled when the external bus is enabled.

85

87

N

AD10

SIN3

Serial data input pin for UART3

INT11R

Sub external interrupt request input pin for INT11

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P13

86

87

88

89

G

I/O pin for 11th bit of the external address/data bus.

This function is enabled when the external bus is enabled.

AD11

SOT3

Serial data output pin for UART3

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P14

I/O pin for 12th bit of the external address/data bus.

This function is enabled when the external bus is enabled.

AD12

SCK3

Clock I/O pin for UART3

(Continued)

13

MB90340 Series

Pin No.

Pin name

Circuit

type

Function

LQFP100^*2QFP100^*1

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P15

92

93

94

95

96

G

I/O pin for 13th bit of the external address/data bus.

This function is enabled when the external bus is enabled.

AD13

SIN4

Serial data input pin for UART4 (MB90V340 only)

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P16

I/O pin for 14th bit of the external address/data bus.

This function is enabled when the external bus is enabled.

AD14

SOT4

Serial data output pin for UART4 (MB90V340 only)

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled in single-chip

mode.

P17

I/O pin for 15th bit of the external address/data bus. This func-

tion is enabled when the external bus is enabled.

AD15

SCK4

Clock I/O pin for UART4 (MB90V340 only)

General purpose I/O. The register can be set to select whether

to use a pull-up resistor.In external bus mode, the pin is

enabled as a general-purpose I/O port when the corresponding

bit in the external address output control register (HACR) is 1.

P20 to P23

A16 to A19

Output pins for A16 to A19 of the external address bus. When

the corresponding bit in the external address output control

register (HACR) is 0, the pins are enabled as high address

output pins (A16 to A19).

95 to 98

97 to 100

G

PPG9,PPGB,

PPGD,PPGF

Output pins for PPGs

General purpose I/O. The register can be set to select whether

to use a pull-up resistor.In external bus mode, the pin is

enabled as a general-purpose I/O port when the corresponding

bit in the external address output control register (HACR) is 1.

P24 to P27

A20 to A23

99 to 2

1 to 4

G

Output pins for A20 to A23 of the external address bus. When

the corresponding bit in the external address output control

register (HACR) is 0, the pins are enabled as high address

output pins (A20 to A23).

IN0 to IN3

P30

Data sample input pins for input captures ICU0 to ICU3

General purpose I/O.The register can be set to select whether

to use a pull-up resistor.This function is enabled in single-chip

mode.

3

5

G

Address latch enable output pin. This function is enabled when

the external bus is enabled.

ALE

IN4

Data sample input pin for input capture ICU4

(Continued)

14

MB90340 Series

Pin No.

Circuit

type

Pin name

Function

LQFP100^*2QFP100^*1

General purpose I/O.The register can be set to select whether to

use a pull-up resistor.This function is enabled in single-chip

mode.

P31

4

6

G

Read strobe output pin for the data bus. This function is enabled

when the external bus is enabled.

RD

IN5

Data sample input pin for input capture ICU5

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the WR/WRL pin output disabled.

P32

Write strobe output pin for the data bus. This function is enabled

when both the external bus and the WR/WRL pin output are en-

abled. WRL is used to write-strobe 8 lower bits of the data bus in

16-bit access while WR is used to write-strobe 8 bits of the data

bus in 8-bit access.

5

7

G

WRL / WR

RX2

RX input pin for CAN2 Interface (MB90V340 only)

Sub external interrupt request input pin for INT10

INT10R

General purpose I/O. The register can be set to select whether to

use a pull-up resistor.This function is enabled either in single-chip

mode or with the WRH pin output disabled.

P33

Write strobe output pin for the 8 higher bits of the data bus. This

function is enabled when the external bus is enabled, when the

external bus 16-bit mode is selected, and when the WRH output

pin is enabled.

6

8

G

WRH

TX2

P34

TX Output pin for CAN2 (MB90V340 only)

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the hold function disabled.

7

8

9

G

Hold request input pin. This function is enabled when both the ex-

ternal bus and the hold function are enabled.

HRQ

OUT4

Waveform output pin for output compare OCU4

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the hold function disabled.

P35

10

11

Hold acknowledge output pin. This function is enabled when both

the external bus and the hold function are enabled.

HAK

OUT5

Waveform output pin for output compare OCU6

General purpose I/O. The register can be set to select whether to

use a pull-up resistor. This function is enabled either in single-chip

mode or with the external ready function disabled.

P36

Ready input pin. This function is enabled when both the

external bus and the external ready function are enabled.

RDY

OUT6

Waveform output pin for output compare OCU5

(Continued)

15

MB90340 Series

Pin No.

Pin name

Circuit

type

Function

LQFP100^*2QFP100^*1

General purpose I/O. The register can be set to select whether

to use a pull-up resistor. This function is enabled either in

single-chip mode or with the CLK output disabled.

P37

10

12

G

CLK output pin. This function is enabled when both the

external bus and CLK output are enabled.

CLK

OUT7

P40 to P41

X0A , X1A

P42

Waveform output pin for output compare OCU7

General purpose I/O (devices with S-suffix)

Oscillator input pins for sub-clock (devices without S-suffix)

General purpose I/O

F

B

11 to 12

13 to 14

IN6

Data sample input pin for input capture ICU6

16

18

F

RX input pin for CAN1 Interface

(MB90F342/F343/F345/341/342 only)

RX1

INT9R

P43

Sub external interrupt request input pin for INT10

General purpose I/O

17

18

19

20

21

IN7

F

H

Data sample input pin for input capture ICU7

TX Output pin for CAN1 (MB90F342/F343/F345/341/342 only)

General purpose I/O

TX1

P44

SDA0

FRCK0

P45

Serial data I/O pin for I2C 0 (devices with C-suffix)

Input for the 16-bit I/O Timer 0

General purpose I/O

SCL0

FRCK1

P46

Serial clock I/O pin for I2C 0 (devices with C-suffix)

Input for the 16-bit I/O Timer 1

General purpose I/O

20

21

22

23

H

SDA1

P47

Serial data I/O pin for I2C 1 (devices with C-suffix)

General purpose I/O

SCL1

P50

Serial clock I/O pin for I²C 1 (devices with C-suffix)

General purpose I/O

22

23

24

25

24

25

26

27

AN8

O

I

Analog input pin for the A/D converter

Serial data input pin for UART2

General purpose I/O

SIN2

P51

AN9

Analog input pin for the A/D converter

Serial data output pin for UART2

General purpose I/O

SOT2

P52

AN10

SCK2

P53

I

Analog input pin for the A/D converter

Clock I/O pin for UART2

General purpose I/O

AN11

TIN3

I

Analog input pin for the A/D converter

Event input pin for the reload timers 3

(Continued)

16

MB90340 Series

Pin No.

LQFP100^*2QFP100^*1

Circuit

type

Pin name

Function

P54

AN12

General purpose I/O

26

27

28

29

I

Analog input pin for the A/D converter

Output pin for the reload timer 3

General purpose I/O

TOT3

P55

AN13

Analog input pin for the A/D converter

General purpose I/O

P56 to P57

AN14 to AN15

DA00 to DA01

P60 to P67

AN0 to AN7

28, 29

30, 31

J

Analog input pin for the A/D converter

D/A converter analog output pins (MB90V340 only)

General purpose I/O

Analog input pins for the A/D converter

34 to 41

36 to 43

I

PPG0, 2, 4, 6,

8, A, C, E

Output pins for PPGs

P70 to P77

AN16 to AN23

INT0 to INT7

P80

General purpose I/O

43 to 48,

53, 54

45 to 50,

55, 56

Analog input pins for the A/D converter (devices with C-suffix)

External interrupt request input pins for INT0 to INT7

General purpose I/O

TIN0

Event input pin for the reload timers 0

Trigger input pin for the A/D converter

Sub external interrupt request input pin for INT12

General purpose I/O

55

56

57

58

59

F

ADTG

INT12R

P81

TOT0

Output pin for the reload timer 0

Output pin for the clock monitor

Sub external interrupt request input pin for INT13

General purpose I/O

CKOT

INT13R

P82

SIN0

Serial data input pin for UART0

Event input pin for the reload timers 2

Sub external interrupt request input pin for INT14

General purpose I/O

M

TIN2

INT14R

P83

58

59

60

61

SOT0

TOT2

F

Serial data output pin for UART0

Output pin for the reload timer 2

General purpose I/O

P84

SCK0

INT15R

P85

Clock I/O pin for UART0

Sub external interrupt request input pin for INT15

General purpose I/O

60

61

62

63

M

F

SIN1

Serial data input pin for UART1

General purpose I/O

P86

SOT1

Serial data output pin for UART1

(Continued)

17

MB90340 Series

(Continued)

Pin No.

Pin name

Circuit

type

Function

LQFP100^*2QFP100^*1

P87

General purpose I/O

Clock I/O pin for UART1

General purpose I/O

Output pins for PPGs

General purpose I/O

62

64

F

SCK1

P90 to P93

PPG1, 3, 5, 7

P94 to P97

65 to 68

67 to 70

Waveform output pins for output compares OCU0 to OCU3.

This function is enabled when the OCU enables waveform

output.

69 to 72

71 to 74

F

OUT0 to

OUT3

PA0

RX0

General purpose I/O

73

75

RX input pin for CAN0 Interface

Sub external interrupt request input pin for INT8

General purpose I/O

INT8R

PA1

74

30

76

32

F

K

TX0

TX Output pin for CAN0

AV^CC

Vcc power input pin for analog circuits

Reference voltage input for the A/D Converter. This power

supply must be turned on or off while a voltage higher than or

equal to AVRH is applied to AV^CC.

31

33

AVRH

L

32

33

34

35

AVRL

AV^SS

K

Lower reference voltage input for the A/D Converter

Vss power input pin for analog circuits

Input pins for specifying the operating mode. The pins must be

directly connected to Vcc or Vss

50, 51

49

52, 53

51

MD1, MD0

MD2

C

D

Input pin for specifying the operating mode. The pins must be

directly connected to Vcc or Vss.

13

63

88

15

65

90

V^CC

V^SS

C

Power (3.5 V to 5.5 V) input pins

14

42

64

89

16

44

66

91

Power (0V) input pins

This is the power supply stabilization capacitor pin. It should be

connected to a higher than or equal to 0.1 µF ceramic capaci-

15

17

K

tor.

*1 : FPT-100P-M06

*2 : FPT-100P-M05

18

MB90340 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

Oscillation circuit

• High-speed oscillation feedback

resistor = approx. 1 MΩ

X1

Xout

A

X0

Standby control signal

Oscillation circuit

X1A

Xout

• Low-speed oscillation feedback

resistor = approx. 1 MΩ

B

X0A

Standby control signal

Mask ROM and EVA device:

• CMOS Hysteresis input pin

R

• Resistor value : approx. 50 kΩ (Typ)

Hysteresis

inputs

C

Flash device:

• CMOS input pin

• Resistor value : approx. 50 kΩ (Typ)

Mask ROM and EVA device:

• CMOS Hysteresis input pin

• Resistor value : approx. 50 kΩ (Typ)

• Pull-down resistor valule: approx. 50 kΩ

R

Hysteresis

inputs

D

Pull-down

Resistor

Flash device:

• CMOS input pin

• Resistor value : approx. 50 kΩ (Typ)

• No Pull-down

CMOS Hysteresis input pin

• Resistor value : approx. 50 kΩ (Typ)

• Pull-up resistor valule: approx. 50 kΩ

Pull-up

E

Resistor

R

Hysteresis

inputs

(Continued)

19

MB90340 Series

Type

Circuit

Remarks

• CMOS level output(I^OL= 4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Pout

Nout

R

F

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

• CMOS level output(I^OL= 4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

pull-up control

Pout

• TTL input (With the standby-time input

shutdown function)

Nout

• Programmalble pullup resistor: 50 kΩ

approx.

R

G

Hysteresis inputs

Automotive inputs

TTL input

Standby control for

input shutdown

• CMOS level output(I^OL= 3 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Pout

Nout

R

H

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

(Continued)

20

MB90340 Series

Type

Circuit

Remarks

• CMOS level output(I^OL= 4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Pout

Nout

• A/D analog input

R

I

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Analog input

• CMOS level output(I^OL= 4 mA)

• D/A analg output

Pout

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Nout

R

• A/D analog input

Hysteresis inputs

J

Automotive inputs

Standby control for

input shutdown

Analog input

Analog output

• Power supply input protection circuit

K

• A/D converter reference voltage power

supply input pin, with the protection cir-

cuit

• Flash devices do not have a protection

circuit against V^CCfor pin AVRH

ANE

AVR

L

ANE

(Continued)

21

MB90340 Series

(Continued)

Type

Circuit

Remarks

• CMOS level output(IOL = 4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Pout

Nout

R

M

CMOS inputs

Automotive inputs

Standby control for

input shutdown

• CMOS level output(I^OL= 4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

pull-up control

Pout

• TTL input (With the standby-time input

shutdown function)

Nout

Programmable pullup registor:50 kΩ

approx

R

N

CMOS inputs

Automotive inputs

TTL input

Standby control for

input shutdown

• CMOS level output(I^OL= 4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Pout

Nout

• A/D analog input

R

O

CMOS inputs

Automotive inputs

Standby control for

input shutdown

Analog input

22

MB90340 Series

■ HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Treatment of unused pins

• Using external clock

• Precautions for when not using a sub clock signal

• Notes on during operation of PLL clock mode

• Power supply pins (V^CC/VSS)

• Pull-up/down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter

• Notes on Energization

• Stabilization of power supply voltage

• Initialization

• Port0 to port3 output during Power-on(External-bus mode)

• Notes on using CAN Function

• Flash security Function

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than V^CCor lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC and VSS.

• The AV^CCpower supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, also be careful not to let the analog power-supply voltage (AV^CC, AVRH) exceed the digital

power-supply voltage.

2. Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

3. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90340 Series

X0

Open

X1

4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the

X1A pin open.

23

MB90340 Series

5. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

6. Power supply pins (V^CC/V^SS)

• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential

are connected the inside of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and observe the standard for total output current, be sure to connect the V^CCand VSS pins to the power supply

and ground externally.

• Connect V^CCand VSS to the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between

VCC and VSS in the vicinity of VCC and VSS pins of the device

Vcc

Vss

Vcc

Vss

Vcc

MB90340

Series

Vcc

Vss

Vcc

Vss

7. Pull-up/down resistors

The MB90340 Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).

Use external components where needed.

8. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14)

after turning-on the digital power supply (VCC) .

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously

is acceptable) .

10. Connection of Unused Pins of A/D Converter if A/D Converter is used

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.

24

MB90340 Series

11. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

or more µs (0.2 V to 2.7 V)

12. Stabilization of power supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply

voltage operating range. Therefore, the VCC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at

commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient

of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

13. Initialization

Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,

turn on the power again.

14. Port 0 to port 3 output during Power-on (External-bus mode)

As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of

Port 0 to Port 3 might be unstable.

V 5

DD

V 3

Port0 to Port3

Port0 to 3 outputs

might be unstable

Port0 to 3 outputs = Hi-Z

15. Notes on using CAN Function

To use CAN function, please set ’1’ to DIRECT bit of CAN Direct Mode Register (CDMR).

If DIRECT bit is set to ’0’ (initial value), wait states will be performed when accessing CAN registers.

Please refer to Hardware Manual of MB90340 series for detail of CAN Direct Mode Register.

16. Flash security Function (except for MB90F346)

The security bit is located in the area of the flash memory.

If protection code 01H is written in the security bit, the flash memory is in the protected state by security.

Therefore please do not write 01H in this address if you do not use the security function.

Please refer to following table for the address of the security bit.

Flash memory size

Address for security bit

MB90F347

Embedded 1 Mbit Flash Memory

FE0001^H

MB90F342

MB90F349

Embedded 2 Mbit Flash Memory

FC0001H

MB90F343

MB90F345

Embedded 3 Mbit Flash Memory

Embedded 4 Mbit Flash Memory

F90001H

F80001H

25

MB90340 Series

■ BLOCK DIAGRAMS

MB90V340(S)

X0,X1

X0A,X1A ^*

Clock

16LX

CPU

RST

Controller

RAM 30 K

FRCK0

IO Timer 0

Input

Capture

8 ch

IN7 to IN0

Output

Compare

8 ch

OUT7 to OUT0

FRCK1

Prescaler

5 ch

IO Timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

Controller

3 ch

UART

5 ch

RX2 to RX0

TX2 to TX0

AVCC

16-bit Reload

Timer 4 ch

TIN3 to TIN0

AVSS

TOT3 to TOT0

10-bit ADC

24 ch

AN23 to AN0

AVRH

AD15 to AD00

A23 to A16

ALE

AVRL

ADTG

RD

10-bit

DAC

2 ch

External

Bus

Interface

WRL

DA01, DA00

WRH

HRQ

HAK

8/16-bit

PPG

16 ch

PPGF to PPG0

RDY

CLK

I²C

Interface

2 ch

SDA1, SDA0

SCL1, SCL0

INT15 to INT8

(INT15R to INT8R)

External

Interrupt

INT7 to INT0

DMAC

Clock

CKOT

Monitor

* : Only for MB90V340 ( without ‘S’ Suffix )

26

MB90340 Series

MB90F342/C (S) , MB90F343/C (S) , MB90F345/C (S) , MB90F346/C (S) , MB90F347/C (S) , MB90F349/C (S) ,

MB90341/C (S) , MB90342/C (S) , MB90346/C (S) , MB90347/C (S) , MB90348/C (S) , MB90349/C (S)

X0,X1

X0A,X1A ^*1

Clock

16LX

CPU

RST

Controller

RAM

2 K/6 K/16 K/

20 K

FRCK0

IO Timer 0

Input

Capture

8 ch

IN7 to IN0

ROM/Flash

64 K/128 K

256 K/384 K/

512 K

Output

Compare

8 ch

OUT7 to OUT0

FRCK1

Prescaler

4 ch

IO Timer 1

SOT3 to SOT0

SCK3 to SCK0

SIN3 to SIN0

CAN

RX0, RX1*³

TX0, TX1*³

UART

4 ch

Controller

1 ch/2 ch*³

AVCC

16-bit Reload

Timer 4 ch

TIN3 to TIN0

AVSS

TOT3 to TOT0

10-bit ADC

16/24 ch

AN15 to AN0

AN23 to AN16 ^*2

AVRH

AD15 to AD00

A23 to A16

ALE

AVRL

ADTG

RD

External

Bus

Interface

WRL

WRH

8/16-bit

PPG

16 ch

HRQ

PPGF to PPG0

HAK

RDY

CLK

I²C

Interface

2 ch

SDA1, SDA0^*2

SCL1, SCL0^*2

INT15 to INT8

External

Interrupt

(INT15R to INT8R)

INT7 to INT0

DMAC

Clock

Monitor

CKOT

*1 : Only for devices without ‘S’ Suffix

*2 : Only for devices with ‘C’ Suffix

*3 : Supported by MB90341/C(S), 342/C(S), F342/C(S), F343/C(S), F345/C(S) only

27

MB90340 Series

■ MEMORY MAP

MB90V340

MB90F345/C/S/CS

MB90F343/C/S/CS

FFFFFFH

ROM(FF bank)

ROM(FE bank)

ROM(FF bank)

ROM(FE bank)

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FF0000H

FEFFFFH

ROM(FE bank)

FE0000H

FDFFFFH

FE0000H

FDFFFFH

FE0000H

FDFFFFH

ROM(FD bank)

ROM(FC bank)

ROM(FB bank)

ROM(FA bank)

ROM(FD bank)

FD0000H

FCFFFFH

ROM(FC bank)

FC0000H

FBFFFFH

FC0000H

FBFFFFH

ROM(FB bank)

ROM(FA bank)

ROM(F9 bank)

FB0000H

FAFFFFH

FB0000H

FAFFFFH

ROM(FA bank)

FA0000H

F9FFFFH

FA0000H

F9FFFFH

F90000H

F9FFFFH

ROM(F9 bank)

ROM(F8 bank)

F90000H

F8FFFFH

ROM(F8 bank)

F80000H

00FFFFH

ROM

00FFFFH

ROM

(Image of FF bank)

ROM

(Image of FF bank)

008000H

007FFFH

008000H

007FFFH

008000H

007FFFH

Peripheral

007900H

0078FFH

007900H

0050FFH

RAM 30 K

RAM 20 K

Peripheral

RAM 20 K

Peripheral

000100H

0000EFH

000000H

0000EFH

Peripheral

000000H

0000EFH

000000H

: No access

28

MB90340 Series

MB90349/C/S/CS

MB90342/C/S/CS

MB90F349/C/S/CS

MB90F342/C/S/CS

MB90348/C/S/CS

MB90341/C/S/CS

MB90347/C/S/CS

MB90346/C/S/CS

MB90F346C/S/CS

MB90F347/C/S/CS

ROM (FF bank)

ROM (FE bank)

FFFFFFH

FF0000H

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FF0000H

FEFFFFH

ROM (FE bank)

ROM (FD bank)

FE0000H

FDFFFFH

FE0000H

FD0000H

FCFFFFH

ROM (FC bank)

FC0000H

00FFFFH

ROM

(Image of FF bank)

008000H

007FFFH

008000H

007FFFH

008000H

007FFFH

008000H

007FFFH

Peripheral

007900H

003FFFH

007900H

003FFFH

007900H

RAM 16 K

Peripheral

RAM 16 K

Peripheral

0018FEH

000100H

RAM 6 K

0008FFH

000100H

RAM 2 K

000100H

0000EFH

000000H

0000EFH

000000H

0000EFH

000000H

0000EFH

000000H

Peripheral

: No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without

using the far specification in the pointer declaration.

For example, an attempt to access 00C000^Haccesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000^Hand FFFFFFH is visible in bank 00, while the image between FF0000H and

FF7FFF^His visible only in bank FF.

29

MB90340 Series

■ I/O MAP

Abbrevia-

tion

Address

Register

Port 0 data register

Access

Resource name

Initial value

00^H

01H

02^H

03^H

04H

05^H

06^H

07H

08^H

09H

0A^H

0BH

0CH

0D^H

0EH

0FH

10^H

11H

12^H

13H

14H

15^H

16H

17H

18H

19^H

1AH

1BH

1C^H

1DH

1EH

1F^H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

ADER5

ADER6

ADER7

ILSR0

ILSR1

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

DDRA

R/W

Port 0

Port 1

XXXXXXXX

11111111

XXXXXXXX

00000000

00000100

Port 1 data register

Port 2 data register

Port 2

Port 3 data register

Port 3

Port 4 data register

Port 4

Port 5 data register

Port 5

Port 6 data register

Port 6

Port 7 data register

Port 7

Port 8 data register

Port 8

Port 9 data register

Port 9

Port A data register

Port A

Port 5, A/D

Port 6, A/D

Port 7, A/D

Ports

Analog Input Enable Port 5

Analog Input Enable Port 6

Analog Input Enable Port 7

Input level select register 0

Input level select register 1

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

Ports

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Reserved

Port 0 Pullup control register

Port 1 Pullup control register

Port 2 Pullup control register

Port 3 Pullup control register

PUCR0

PUCR1

PUCR2

PUCR3

R/W

Port 0

Port 1

Port 2

Port 3

00000000

(Continued)

R/W

W, R/W

30

MB90340 Series

Abbrevia-

tion

Address

Register

Serial Mode Register

Access

Resource name

Initial value

20^H

21^H

SMR0

SCR0

W,R/W

00000000

Serial Control Register

RDR0/

TDR0

22H

23^H

24^H

Reception/Transmission Data Register

Serial Status Register

R/W

00000000

00001000

000000XX

SSR0

R,R/W

UART0

R,W,R/

W

Extended Communication Control Reg.

ECCR0

25H

26^H

27H

28^H

29^H

Extended Status/Control Register

Baud Rate Register 0

ESCR0

BGR00

BGR01

SMR1

R/W

00000100

00000000

Baud Rate Register 1

R/W

Serial Mode Register

W,R/W

Serial Control Register

SCR1

RDR1/

TDR1

2A^H

2B^H

2CH

Reception/Transmission Data Register

Serial Status Register

R/W

00000000

00001000

000000XX

SSR1

R,R/W

UART1

R,W,

R/W

Extended Communication Control Reg.

ECCR1

2D^H

2E^H

2FH

30^H

31^H

32H

33^H

34H

35H

36H

37^H

38H

39^H

3A^H

3BH

3CH

3D^H

3EH

3FH

Extended Status/Control Register

Baud Rate Register 0

ESCR1

BGR10

BGR11

PPGC0

PPGC1

PPG01

R/W

00000100

00000000

0X000XX1

0X000001

000000X0

Baud Rate Register 1

R/W

PPG 0 operation mode control register

PPG 1 operation mode control register

PPG 0 and PPG 1 clock select register

W,R/W

R/W

16-bit Programable

Pulse

Generator 0/1

Reserved

PPG 2 operation mode control register

PPG 3 operation mode control register

PPG 2 and PPG 3 clock select register

PPGC2

PPGC3

PPG23

W,R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse

Generator 2/3

Reserved

PPG 4 operation mode control register

PPG 5 operation mode control register

PPG 4 and PPG 5 clock select register

ROM Correction Control Status 1

PPGC4

PPGC5

PPG45

PACSR1

PPGC6

PPGC7

PPG67

W,R/W

R/W

0X000XX1

0X000001

000000X0

00000000

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse

Generator 4/5

R/W

ROM Correction 1

PPG 6 operation mode control register

PPG 7 operation mode control register

PPG 6 and PPG 7 clock select register

W,R/W

R/W

16-bit Programable

Pulse

Generator 6/7

Reserved

(Continued)

31

MB90340 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

40^H

41H

42H

43^H

44^H

45^H

46^H

47^H

48H

49^H

4AH

4B^H

4CH

4D^H

4E^H

4FH

50^H

51H

52H

53^H

54H

55H

56^H

57^H

58H

59H

5A^H

5BH

5CH

5D^H

5EH

5FH

PPG 8 operation mode control register

PPG 9 operation mode control register

PPG 8 and PPG 9 clock select register

PPGC8

PPGC9

PPG89

W,R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse

Generator 8/9

Reserved

PPG A operation mode control register

PPG B operation mode control register

PPGCA

PPGCB

W,R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse

Generator A/B

PPG A and PPG B clock select register PPGAB

Reserved

PPG C operation mode control register

PPG D operation mode control register

PPGCC

PPGCD

W,R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse

Generator C/D

PPG C and PPG D clock select register PPGCD

Reserved

PPGCE

PPG E operation mode control register

PPG F operation mode control register

PPG E and PPG F clock select register

W,R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse

PPGCF

PPGEF

Generator E/F

Reserved

Input Capture Control Status 0/1

Input Capture Edge 0/1

ICS01

ICE01

ICS23

ICE23

ICS45

ICE45

ICS67

ICE67

OCS0

OCS1

OCS2

OCS3

OCS4

OCS5

OCS6

OCS7

R/W

00000000

XXX0X0XX

00000000

XXXXXXXX

00000000

XXXXXXXX

00000000

XXX000XX

0000XX00

0XX00000

0000XX00

0XX00000

0000XX00

0XX00000

0000XX00

0XX00000

(Continued)

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

Input Capture 6/7

Output Compare 0/1

Output Compare 2/3

Output Compare 4/5

Output Compare 6/7

Input Capture Control Status 2/3

Input Capture Edge 2/3

Input Capture Control Status 4/5

Input Capture Edge 4/5

Input Capture Control Status 6/7

Input Capture Edge 6/7

Output Compare Control Status 0

Output Compare Control Status 1

Output Compare Control Status 2

Output Compare Control Status 3

Output Compare Control Status 4

Output Compare Control Status 5

Output Compare Control Status 6

Output Compare Control Status 7

32

MB90340 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

60^H

61^H

62H

63^H

64^H

65H

66^H

67^H

68H

69H

6AH

6B^H

6CH

6DH

6E^H

6FH

Timer Control Status 0

Timer Control Status 1

Timer Control Status 2

Timer Control Status 3

A/D Control Status 0

A/D Control Status 1

A/D Data 0

TMCSR0

TMCSR1

TMCSR2

TMCSR3

ADCS0

R/W

R

00000000

XXXX0000

00000000

XXXX0000

00000000

XXXX0000

00000000

XXXX0000

000XXXX0

0000000X

00000000

XXXXXX00

00000000

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

ADCS1

ADCR0

A/D Converter

A/D Data 1

ADCR1

R

ADC Setting 0

ADSR0

R/W

ADC Setting 1

ADSR1

Reserved

ROMM

ROM Mirror

W

ROM Mirror

XXXXXXX1

70^Hto 8FH Reserved for CAN Interface 0/1. Refer to “■ CAN CONTROLLERS”

90H to 9AH

9BH

Reserved

DCSR

DMA Descriptor Channel Select

DMA Status L

R/W

00000000

XXXXXXX0

9C^H

DSRL

DSRH

DMA

9DH

DMA Status H

9EH

ROM Correction Control Status 0

Delayed Interrupt/release

PACSR0

DIRR

ROM Correction 0

Delayed Interrupt

9F^H

Low Power

Controller

A0H

A1^H

Low-power Mode Control

Clock Selection

LPMCR

CKSCR

W,R/W

R,R/W

00011000

11111100

Low Power

Controller

A2^H, A3H

A4^H

Reserved

DMA Stop Status

DSSR

ARSR

HACR

ECSR

WDTC

TBTC

R/W

W

DMA

00000000

0011XX00

00000000

0000000X

XXXXX111

1XX00100

(Continued)

A5H

Automatic ready function select reg.

External address output control reg.

Bus control signal selection register

Watchdog Control

External Memory

Access

A6H

W

A7^H

W

A8H

R,W

W,R/W

Watchdog Timer

Time Base Timer

A9H

Time Base Timer Control

33

MB90340 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

AA^H

AB^H

ACH

AD^H

Watch Timer Control register

WTC

R,R/W

Watch Timer

1X001000

Reserved

DMA Enable L

DMA Enable H

DERL

DERH

R/W

00000000

DMA

Flash Control Status

(FlashDevices only.

Otherwise reserved)

AE^H

FMCS

R,R/W

Flash Memory

000X0000

AFH

B0^H

Reserved

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

D/A Converter data 0

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

DAT0

W,R/W

R/W

00000111

XXXXXXXX

XXXXXXX0

B1H

B2^H

B3H

B4H

B5^H

B6H

B7H

Interrupt controller

B8^H

B9H

BA^H

BBH

BCH

BD^H

BEH

BFH

C0^H

C1^H

C2H

C3H

C4^H, C5H

C6H

C7H

C8^H

C9H

D/A Converter data 1

DAT1

R/W

D/A Converter

D/A Control 0

DACR0

DACR1

R/W

D/A Control 1

R/W

Reserved

External Interrupt Enable 0

External Interrupt Request 0

External Interrupt Level 0

ENIR0

EIRR0

ELVR0

R/W

00000000

XXXXXXXX

00000000

External Interrupt 0

00000000

(Continued)

34

MB90340 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

CA^H

CB^H

CCH

CD^H

CE^H

CFH

D0^H

D1^H

D2H

D3H

D4H

D5^H

D6H

D7H

D8^H

D9H

External Interrupt Enable 1

External Interrupt Request 1

External Interrupt Level 1

External Interrupt 1 Source Select

PLL/Subclock Control register

DMA Buffer Addrss Pointer L

DMA Buffer Addrss Pointer M

DMA Buffer Addrss Pointer H

DMA Control

ENIR1

EIRR1

ELVR1

EISSR

PSCCR

BAPL

R/W

W

00000000

XXXXXXXX

00000000

External Interrupt 1

PLL

00000000

XXXX0000

XXXXXXXX

00000000

R/W

W,R/W

BAPM

BAPH

DMACS

IOAL

DMA

I/O Register Address Pointer L

I/O Register Address Pointer H

Data Counter L

IOAH

DCTL

Data Counter H

DCTH

SMR2

SCR2

Serial Mode Register

Serial Control Register

00000000

RDR2/

TDR2

DA^H

DB^H

DCH

Reception/Transmission Data Register

Serial Status Register

R/W

00000000

00001000

000000XX

SSR2

R,R/W

UART2

R,W,

R/W

Extended Communication Control Reg. ECCR2

DD^H

DEH

DFH

Extended Status/Control Register

Baud Rate Register 0

ESCR2

BGR20

BGR21

R/W

00000100

00000000

Baud Rate Register 1

E0^Hto EFH Reserved for CAN Interface 2. Refer to “■ CAN CONTROLLERS”

F0^Hto FFH External

(Continued)

35

MB90340 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

7900^H

7901^H

7902^H

7903^H

7904^H

7905^H

7906^H

7907^H

7908^H

7909^H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

PRLLC

PRLHC

PRLLD

PRLHD

PRLLE

PRLHE

PRLLF

PRLHF

IPCP0

IPCP1

R/W

R

XXXXXXXX

(Continued)

16-bit Programable

Pulse

Generator 0/1

16-bit Programable

Pulse

Generator 2/3

16-bit Programable

Pulse

790A^HReload L

790B^HReload H

790C^HReload L

790D^HReload H

790E^HReload L

790F^HReload H

Generator 4/5

16-bit Programable

Pulse

Generator 6/7

7910^H

7911^H

7912^H

7913^H

7914^H

7915^H

7916^H

7917^H

7918^H

7919^H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

16-bit Programable

Pulse

Generator 8/9

16-bit Programable

Pulse

Generator A/B

16-bit Programable

Pulse

Generator C/D

791A^HReload L

791B^HReload H

791C^HReload L

791D^HReload H

791E^HReload L

791F^HReload H

16-bit Programable

Pulse

Generator E/F

7920^H

7921^H

7922^H

7923^H

Input Capture 0

Input Capture 1

R

Input Capture 0/1

R

36

MB90340 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

7924^H

7925^H

7926^H

7927^H

7928^H

7929^H

Input Capture 2

Input Capture 3

Input Capture 4

IPCP2

R

XXXXXXXX

00000000

R

Input Capture 2/3

IPCP3

R

IPCP3

R

IPCP4

R

IPCP4

R

Input Capture 4/5

Input Capture 6/7

Output Compare 0/1

Output Compare 2/3

Output Compare 4/5

Output Compare 6/7

I/O Timer 0

792A^HInput Capture 5

792B^HInput Capture 5

792C^HInput Capture 6

792D^HInput Capture 6

792E^HInput Capture 7

792F^HInput Capture 7

IPCP5

R

IPCP5

R

IPCP6

R

IPCP6

R

IPCP7

R

IPCP7

R

7930^H

7931^H

7932^H

7933^H

7934^H

7935^H

7936^H

7937^H

7938^H

7939^H

Output Compare 0

OCCP0

OCCP1

OCCP2

OCCP3

OCCP4

OCCP5

OCCP6

OCCP7

TCDT0

TCCSL0

TCCSH0

TCDT1

TCCSL1

TCCSH1

R/W

Output Compare 0

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

793A^HOutput Compare 5

793B^HOutput Compare 5

793C^HOutput Compare 6

793D^HOutput Compare 6

793E^HOutput Compare 7

793F^HOutput Compare 7

7940^H

7941^H

7942^H

7943^H

7944^H

7945^H

7946^H

7947^H

Timer Data 0

Timer Control 0

Timer Data 1

Timer Control 1

00000000

0XXXXXXX

00000000

I/O Timer 1

00000000

0XXXXXXX

(Continued)

37

MB90340 Series

Abbrevia-

tion

Address

Register

Timer 0/Reload 0

Access

Resource name

Initial value

7948^H

7949^H

794A^H

794B^H

794C^H

794D^H

794E^H

794F^H

7950^H

7951^H

R/W

XXXXXXXX

00000000

TMR0/

TMRLR0

16-bit Reload

Timer 0

R/W

TMR1/

TMRLR1

16-bit Reload

Timer 1

Timer 1/Reload 1

Timer 2/Reload 2

Timer 3/Reload 3

R/W

TMR2/

TMRLR2

16-bit Reload

Timer 2

R/W

TMR3/

TMRLR3

16-bit Reload

Timer 3

R/W

Serial Mode Register

Serial Control Register

SMR3

SCR3

W,R/W

00000000

RDR3/

TDR3

7952^H

7953^H

7954^H

Reception/Transmission Data Register

Serial Status Register

R/W

00000000

00001000

000000XX

SSR3

R,R/W

UART3

R,W,

R/W

Extended Communication Control Reg.

ECCR3

7955^H

7956^H

7957^H

7958^H

7959^H

Extended Status/Control Register

Baud Rate Register 0

ESCR3

BGR30

BGR31

SMR4

R/W

00000100

00000000

Baud Rate Register 1

R/W

Serial Mode Register

W,R/W

Serial Control Register

SCR4

RDR4/

TDR4

795A^HReception/Transmission Data Register

795B^HSerial Status Register

R/W

00000000

00001000

000000XX

SSR4

R,R/W

UART4

R,W,

R/W

795C^HExtended Communication Control Reg.

ECCR4

795D^HExtended Status/Control Register

795E^HBaud Rate Register 0

ESCR4

BGR40

BGR41

R/W

00000100

00000000

795F^HBaud Rate Register 1

7960^Hto

796BH

Reserved

796C^HClock output enable register

796D^H

CLKR

R/W

Clock Monitor

XXXX0000

Reserved

796E^HCAN Direct Mode Register

796F^HCAN RX/TX redirect register

CDMR

R/W

CAN clock sync

CAN 0/1

XXXXXXX0

XXXXXX00

(Continued)

CANSWR

38

MB90340 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

7970^H

7971^H

7972^H

7973^H

7974^H

7975^H

7976^H

7977^H

7978^H

I²C bus status register

I²C bus control register

IBSR0

IBCR0

ITBAL0

ITBAH0

ITMKL0

ITMKH0

ISBA0

R

W,R/W

R/W

00000000

11111111

00111111

00000000

01111111

00000000

I²C 10 bit slave address register

I²C 10 bit address mask register

I²C Interface 0

I²C 7 bit slave address register

I²C 7 bit address mask register

I²C data register

ISMK0

IDAR0

7979^H,

797AH

Reserved

797B^HI²C clock control register

ICCR0

R/W

I²C Interface 0

00011111

797C^Hto

797FH

Reserved

7980^H

7981^H

7982^H

7983^H

7984^H

7985^H

7986^H

7987^H

7988^H

I²C bus status register

I²C bus control register

IBSR1

IBCR1

ITBAL1

ITBAH1

ITMKL1

ITMKH1

ISBA1

R

W,R/W

R/W

00000000

11111111

00111111

00000000

01111111

00000000

I²C 10 bit slave address register

I²C 10 bit address mask register

I²C Interface 1

I²C 7 bit slave address register

I²C 7 bit address mask register

I²C data register

ISMK1

IDAR1

7989^H,

798AH

Reserved

ICCR1

Reserved

CMCR

Reserved

798B^HI²C clock control register

R/W

I²C Interface 1

Clock Modulator

00011111

0001X000

(Continued)

798C^Hto

79C1H

79C2^HClock Modulator Control Register

R,R/W

79C3^Hto

79DFH

39

MB90340 Series

(Continued)

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

79E0^HROM Correction Address 0

79E1^HROM Correction Address 0

79E2^HROM Correction Address 0

79E3^HROM Correction Address 1

79E4^HROM Correction Address 1

79E5^HROM Correction Address 1

79E6^HROM Correction Address 2

79E7^HROM Correction Address 2

79E8^HROM Correction Address 2

PADR0

PADR1

PADR2

R/W

XXXXXXXX

ROM Correction 0

79E9^Hto

79EFH

Reserved

79F0^HROM Correction Address 3

79F1^HROM Correction Address 3

79F2^HROM Correction Address 3

79F3^HROM Correction Address 4

79F4^HROM Correction Address 4

79F5^HROM Correction Address 4

79F6^HROM Correction Address 5

79F7^HROM Correction Address 5

79F8^HROM Correction Address 5

PADR3

PADR4

PADR5

R/W

XXXXXXXX

ROM Correction 1

79F9^Hto

79FFH

Reserved

7A00^Hto

7AFFH

Reserved for CAN Interface 0. Refer to “■ CAN CONTROLLERS”

Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

Reserved for CAN Interface 2. Refer to “■ CAN CONTROLLERS”

7B00^Hto

7BFFH

7C00^Hto

7CFFH

7D00^Hto

7DFFH

7E00^Hto

7EFFH

7F00^Hto

7FFFH

Notes : • Initial value of “X” represents unknown value.

• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary

functions of the MCU. A read access to these reserved addresses results reading “X” and any write

access should not be performed.

40

MB90340 Series

■ CAN CONTROLLERS

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

• Supports transmission/reception in standard frame and extended frame formats

• Supports transmitting of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

• 29-bit ID and 8-byte data

• Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message

buffer as ID acceptance mask

• Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz)

List of Control Registers (1)

Address

Register

Abbreviation Access

Initial Value

CAN0

CAN1

CAN2

000070^H

000071^H

000072H

000073^H

000074H

000075^H

000076H

000077^H

000078H

000079^H

00007AH

00007B^H

00007CH

00007D^H

00007EH

00007F^H

000080H

000081H

000082H

000083H

000084H

000085H

000086H

000087H

000088H

000089H

00008AH

00008BH

00008CH

00008DH

00008EH

00008FH

0000E0H

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

0000E6H

0000E7H

0000E8H

0000E9H

0000EAH

0000EBH

0000ECH

0000EDH

0000EEH

0000EFH

Message buffer

valid register

00000000

BVALR

TREQR

TCANR

TCR

R/W

W

Transmit request

register

00000000

Transmit cancel

register

00000000

Transmission

complete register

00000000

R/W

Receive complete

register

00000000

RCR

Remote request

receiving register

00000000

RRTRR

ROVRR

RIER

Receive overrun

register

00000000

Reception interrupt

enable register

00000000

41

MB90340 Series

List of Control Registers (2)

Address

Register

Abbreviation Access

Initial Value

CAN0

CAN1

CAN2

007B00^H

007B01^H

007B02H

007B03^H

007B04H

007B05^H

007B06H

007B07^H

007B08H

007B09^H

007B0AH

007B0B^H

007B0CH

007D00H

007D01H

007D02H

007D03H

007D04H

007D05H

007D06H

007D07H

007D08H

007D09H

007D0AH

007D0BH

007D0CH

007F00H

007F01H

007F02H

007F03H

007F04H

007F05H

007F06H

007F07H

007F08H

007F09H

007F0AH

007F0BH

007F0CH

Control status

register

R/W, W

R/W, R

0XXXX0X1

00XXX000

CSR

LEIR

Last event

indicator register

000X0000

XXXXXXXX

R/W

R

Receive/transmit

error counter

00000000

RTEC

BTR

Bit timing

register

11111111

X1111111

R/W

XXXXXXXX

IDE register

IDER

TRTRR

Transmit RTR

register

00000000

Remote frame

receive waiting

register

XXXXXXXX

RFWTR

TIER

R/W

007B0D^H

007D0DH

007F0DH

007B0EH

007B0F^H

007B10H

007B11^H

007B12H

007B13^H

007B14H

007B15^H

007B16H

007B17^H

007B18H

007B19^H

007B1AH

007B1B^H

007D0EH

007D0FH

007D10H

007D11H

007D12H

007D13H

007D14H

007D15H

007D16H

007D17H

007D18H

007D19H

007D1AH

007D1BH

007F0EH

007F0FH

007F10H

007F11H

007F12H

007F13H

007F14H

007F15H

007F16H

007F17H

007F18H

007F19H

007F1AH

007F1BH

Transmit interrupt

enable register

00000000

XXXXXXXX

Acceptance mask

select register

AMSR

AMR0

AMR1

R/W

XXXXXXXX

Acceptance mask

register 0

XXXXXXXX

Acceptance mask

register 1

XXXXXXXX

42

MB90340 Series

List of Message Buffers (ID Registers) (1)

Address

CAN1

Register

Abbreviation

Access

Initial Value

CAN0

CAN2

007A00^H

to

007A1FH

007C00H

to

007C1FH

007E00H

to

007E1FH

XXXXXXXX

to

XXXXXXXX

General-

purpose RAM

R/W

007A20^H

007A21^H

007A22H

007A23^H

007A24H

007A25^H

007A26H

007A27^H

007A28H

007A29^H

007A2AH

007A2B^H

007A2CH

007A2D^H

007A2EH

007A2F^H

007A30H

007A31^H

007A32H

007A33^H

007A34H

007A35^H

007A36H

007A37^H

007A38H

007A39^H

007A3AH

007A3B^H

007A3CH

007A3D^H

007A3EH

007A3F^H

007C20H

007C21H

007C22H

007C23H

007C24H

007C25H

007C26H

007C27H

007C28H

007C29H

007C2AH

007C2BH

007C2CH

007C2DH

007C2EH

007C2FH

007C30H

007C31H

007C32H

007C33H

007C34H

007C35H

007C36H

007C37H

007C38H

007C39H

007C3AH

007C3BH

007C3CH

007C3DH

007C3EH

007C3FH

007E20H

007E21H

007E22H

007E23H

007E24H

007E25H

007E26H

007E27H

007E28H

007E29H

007E2AH

007E2BH

007E2CH

007E2DH

007E2EH

007E2FH

007E30H

007E31H

007E32H

007E33H

007E34H

007E35H

007E36H

007E37H

007E38H

007E39H

007E3AH

007E3BH

007E3CH

007E3DH

007E3EH

007E3FH

XXXXXXXX

ID register 0

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

R/W

XXXXXXXX

43

MB90340 Series

List of Message Buffers (ID Registers) (2)

Address

Register

Abbreviation

Access

Initial Value

CAN0

CAN1

CAN2

007A40^H

007A41^H

007A42H

007A43^H

007A44H

007A45^H

007A46H

007A47^H

007A48H

007A49^H

007A4AH

007A4B^H

007A4CH

007A4D^H

007A4EH

007A4F^H

007A50H

007A51^H

007A52H

007A53^H

007A54H

007A55^H

007A56H

007A57^H

007A58H

007A59^H

007A5AH

007A5B^H

007A5CH

007A5D^H

007A5EH

007A5F^H

007C40H

007C41H

007C42H

007C43H

007C44H

007C45H

007C46H

007C47H

007C48H

007C49H

007C4AH

007C4BH

007C4CH

007C4DH

007C4EH

007C4FH

007C50H

007C51H

007C52H

007C53H

007C54H

007C55H

007C56H

007C57H

007C58H

007C59H

007C5AH

007C5BH

007C5CH

007C5DH

007C5EH

007C5FH

007E40H

007E41H

007E42H

007E43H

007E44H

007E45H

007E46H

007E47H

007E48H

007E49H

007E4AH

007E4BH

007E4CH

007E4DH

007E4EH

007E4FH

007E50H

007E51H

007E52H

007E53H

007E54H

007E55H

007E56H

007E57H

007E58H

007E59H

007E5AH

007E5BH

007E5CH

007E5DH

007E5EH

007E5FH

XXXXXXXX

ID register 8

IDR8

R/W

XXXXXXXX

ID register 9

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

IDR9

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

R/W

XXXXXXXX

44

MB90340 Series

List of Message Buffers (DLC Registers and Data Registers) (1)

Address

CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

XXXXXXXX

CAN0

CAN2

007A60^H

007A61^H

007A62H

007A63^H

007A64H

007A65^H

007A66H

007A67^H

007A68H

007A69^H

007A6AH

007A6B^H

007A6CH

007A6D^H

007A6EH

007A6F^H

007A70H

007A71^H

007A72H

007A73^H

007A74H

007A75^H

007A76H

007A77^H

007A78H

007A79^H

007A7AH

007A7B^H

007A7CH

007A7D^H

007A7EH

007A7F^H

007C60H

007C61H

007C62H

007C63H

007C64H

007C65H

007C66H

007C67H

007C68H

007C69H

007C6AH

007C6BH

007C6CH

007C6DH

007C6EH

007C6FH

007C70H

007C71H

007C72H

007C73H

007C74H

007C75H

007C76H

007C77H

007C78H

007C79H

007C7AH

007C7BH

007C7CH

007C7DH

007C7EH

007C7FH

007E60H

007E61H

007E62H

007E63H

007E64H

007E65H

007E66H

007E67H

007E68H

007E69H

007E6AH

007E6BH

007E6CH

007E6DH

007E6EH

007E6FH

007E70H

007E71H

007E72H

007E73H

007E74H

007E75H

007E76H

007E77H

007E78H

007E79H

007E7AH

007E7BH

007E7CH

007E7DH

007E7EH

007E7FH

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

45

MB90340 Series

List of Message Buffers (DLC Registers and Data Registers) (2)

Address

CAN1

Register

Abbreviation

Access

Initial Value

CAN0

CAN2

007A80^H

to

007A87H

007C80H

to

007C87H

007E80H

to

007E87H

XXXXXXXX

to

XXXXXXXX

Data register 0

(8 bytes)

DTR0

R/W

007A88^H

to

007A8FH

007C88H

to

007C8FH

007E88H

to

007E8FH

XXXXXXXX

to

XXXXXXXX

Data register 1

(8 bytes)

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

R/W

007A90^H

to

007A97H

007C90H

to

007C97H

007E90H

to

007E97H

XXXXXXXX

to

XXXXXXXX

Data register 2

(8 bytes)

007A98H

to

007A9FH

007C98H

to

007C9FH

007E98H

to

007E9FH

XXXXXXXX

to

XXXXXXXX

Data register 3

(8 bytes)

007AA0^H

to

007AA7H

007CA0H

to

007CA7H

007EA0H

to

007EA7H

XXXXXXXX

to

XXXXXXXX

Data register 4

(8 bytes)

007AA8H

to

007AAFH

007CA8H

to

007CAFH

007EA8H

to

007EAFH

XXXXXXXX

to

XXXXXXXX

Data register 5

(8 bytes)

007AB0^H

to

007AB7H

007CB0H

to

007CB7H

007EB0H

to

007EB7H

XXXXXXXX

to

XXXXXXXX

Data register 6

(8 bytes)

007AB8H

to

007ABFH

007CB8H

to

007CBFH

007EB8H

to

007EBFH

XXXXXXXX

to

XXXXXXXX

Data register 7

(8 bytes)

007AC0^H

to

007AC7H

007CC0H

to

007CC7H

007EC0H

to

007EC7H

XXXXXXXX

to

XXXXXXXX

Data register 8

(8 bytes)

007AC8H

to

007ACFH

007CC8H

to

007CCFH

007EC8H

to

007ECFH

XXXXXXXX

to

XXXXXXXX

Data register 9

(8 bytes)

007AD0^H

to

007AD7H

007CD0H

to

007CD7H

007ED0H

to

007ED7H

XXXXXXXX

to

XXXXXXXX

Data register 10

(8 bytes)

007AD8^H

to

007ADFH

007CD8H

to

007CDFH

007ED8H

to

007EDFH

XXXXXXXX

to

XXXXXXXX

Data register 11

(8 bytes)

007AE0H

to

007AE7^H

007CE0H

to

007CE7^H

007EE0H

to

007EE7^H

XXXXXXXX

to

XXXXXXXX

Data register 12

(8 bytes)

007AE8^H

to

007AEFH

007CE8H

to

007CEFH

007EE8H

to

007EEFH

XXXXXXXX

to

XXXXXXXX

Data register 13

(8 bytes)

46

MB90340 Series

List of Message Buffers (DLC Registers and Data Registers) (3)

Address

CAN1

Register

Abbreviation

Access

Initial Value

CAN0

CAN2

007AF0^H

to

007AF7H

007CF0H

to

007CF7H

007EF0H

to

007EF7H

XXXXXXXX

to

XXXXXXXX

Data register 14

(8 bytes)

DTR14

R/W

007AF8^H

to

007AFFH

007CF8H

to

007CFFH

007EF8H

to

007EFFH

XXXXXXXX

to

XXXXXXXX

Data register 15

(8 bytes)

DTR15

R/W

47

MB90340 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

Interrupt vector

EI²OS

clear

DMA ch

number

register

Interrupt cause

Number

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

Address

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

Number

Address

Reset

N

INT9 instruction

Exception

N

CAN 0 RX

N

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

CAN 0 TX/NS

N

CAN 1 RX / Input Capture 6

CAN 1 TX/NS / Input Capture 7

CAN 2 RX / I²C0

Y1

N

CAN 2 TX/NS

N

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

PPG 0/1/4/5

Y1

N

0

1

2

PPG 2/3/6/7

N

PPG 8/9/C/D

N

PPG A/B/E/F

N

Time Base Timer

N

External Interrupt 0 to 3, 8 to 11

Watch Timer

Y1

N

3

External Interrupt 4 to 7, 12 to 15

A/D Converter

Y1

N

4

5

I/O Timer 0 / I/O Timer 1

Input Capture 4/5 / I²C1

Output Compare 0/1/4/5

Input Capture 0 to 3

Output Compare 2/3/6/7

UART 0 RX

Y1

Y2

Y1

Y2

Y1

6

7

8

9

10

11

12

13

UART 0 TX

UART 1 RX / UART 3 RX

UART 1 TX / UART 3 TX

0000BDH

(Continued)

48

MB90340 Series

(Continued)

Interrupt cause

Interrupt control

Interrupt vector

EI²OS

clear

DMA ch

number

register

Number

#39

Address

FFFF60^H

FFFF5CH

FFFF58H

FFFF54H

Number

Address

UART 2 RX / UART 4 RX

UART 2 TX / UART 4 TX

Flash Memory

Y2

Y1

N

14

15

ICR14

ICR15

0000BEH

#40

#41

0000BFH

Delayed interrupt

N

#42

Y1 : Usable

Y2 : Usable, with EI²OS stop function

N

: Unusable

Notes : • The peripheral resources sharing the ICR register have the same interrupt level.

• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service

at a time.

• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O

Service, the other one cannot use interrupts.

49

MB90340 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0 V)

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

VSS − 0.3 VSS + 6.0

V

AVCC

VCC = AVCC*1

Power supply voltage

AVRH,

AVRL

AVCC ≥ AVRH, AVCC ≥ AVRL,

AVRH ≥ AVRL

VSS − 0.3 VSS + 6.0

V

Input voltage

V^I

VO

VSS − 0.3 VSS + 6.0

V

*2

Output voltage

Maximum Clamp Current

ICLAMP

Σ|I^CLAMP|

I^OL

−4.0

+4.0

40

mA *4

mA *3

mW MB90F347

°C

Total Maximum Clamp Current

“L” level maximum output current

“L” level average output current

“L” level maximum overall output current

“L” level average overall output current

“H” level maximum output current

“H” level average output current

“H” level maximum overall output current

“H” level average overall output current

Power consumption

15

I^OLAV

ΣIOL

4

100

50

ΣI^OLAV

I^OH

−15

−4

IOHAV

ΣI^OH

ΣI^OHAV

P^D

−100

−50

340

+105

+150

Operating temperature

TA

−40

−55

Storage temperature

T^STG

°C

(Continued)

50

MB90340 Series

(Continued)

*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AVCC when the power is switched on.

*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun

current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI

rating.

*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P70 to P77, P80 to P87, P90 to P97, PA0 to PA1

*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67

P70 to P77, P80 to P87, P90 to P97, PA0 to PA1

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

VCC

Limiting

resistance

P-ch

+B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

51

MB90340 Series

2. Recommended Conditions

(VSS = AVSS = 0 V)

Value

Typ

Parameter

Symbol

Unit

Remarks

Min

Max

4.0

5.0

5.5

V

Under normal operation

Under normal operation, when not

using the A/D converter and not

Flash programming.

3.5

5.0

5.5

V

V^CC,

AVCC

Power supply voltage

4.5

3.0

5.5

V

When External bus is used.

Maintains RAM data in stop mode

Use a ceramic capacitor or capac-

itor of better AC characteristics.

Capacitor at the V^CCshould be

greater than this capacitor.

Smooth capacitor

C^S

0.1

1.0

µF

°C

Operating temperature

TA

−40

+105

C

CS

C Pin Connection Diagram

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

52

MB90340 Series

3. DC Characteristics

Sym-

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Parameter

Condition

Unit

Remarks

bol

Min

Typ

Max

Port inputs if CMOS

hysteresis input levels

are selected (except

UART SIN input pins

and I²C input pins)

V^IHS

0.8 VCC

VCC + 0.3

V

Port inputs if

AUTOMOTIVE input

levels are selected

VIHA

V^IHT

V^IHS

0.8 VCC

2.0

VCC + 0.3

V

Input H

voltage

(At V^CC=

5 V ± 10%)

Port inputs if TTL input

levels are selected

UART SIN inputs if

CMOS input levels are

selected

0.7 VCC

I²C Port inputs if CMOS

hysteresis input levels

are selected

V^IHI

0.7 VCC

VCC + 0.3

V

RST input pin (CMOS

hysteresis)

V^IHR

0.8 VCC

VCC + 0.3

V

VIHM

VCC − 0.3

MD input pin

Port inputs if CMOS

hysteresis input levels

are selected (except

UART SIN input pins

and I²C input pins)

V^ILS

VSS − 0.3

0.2 VCC

V

Port inputs if

AUTOMOTIVE input

levels are selected

V^ILA

V^ILT

V^ILS

VSS − 0.3

0.5 VCC

0.8

V

Input L

voltage

(At V^CC=

5 V ± 10%)

Port inputs if TTL

input levels are selected

UART SIN inputs if

CMOS input levels are

selected

0.3 VCC

I²C Port inputs if CMOS

hysteresis input levels

are selected

V^ILI

VSS − 0.3

0.3 VCC

V

RST input pin (CMOS

hysteresis)

V^ILR

V^ILM

V^OH

VSS − 0.3

V^CC− 0.5

0.2 VCC

V

VSS + 0.3

MD input pin

Output H

voltage

Normal

outputs

VCC = 4.5 V,

IOH = −4.0 mA

Output H

voltage

I²Ccurrent VCC = 4.5 V,

V^OHI

V^OL

V^OLI

V^CC− 0.5

V

outputs

I^OH= −3.0 mA

Output L

voltage

Normal

outputs

VCC = 4.5 V,

IOL = 4.0 mA

0.4

Output L

voltage

I²Ccurrent VCC = 4.5 V,

outputs IOL = 3.0 mA

(Continued)

53

MB90340 Series

(Continued)

(TA = −40 °C to +105, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min Typ Max

Input leak current

I^IL

VCC = 5.5 V, VSS < VI < VCC

−1

1

µA

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

RST

Pull-up

resistance

R^UP

25

50

100 kΩ

Except

100 kΩ Flash

devices

Pull-down

resistance

R^DOWN

MD2

25

50

55

70

75

25

0.3

VCC = 5.0 V,

Internal frequency : 24 MHz,

At normal operation.

70

85

90

35

0.8

mA MB90F347

VCC = 5.0 V,

Internal frequency : 24 MHz,

At writing FLASH memory.

I^CC

V^CC= 5.0 V,

Internal frequency : 24 MHz,

At erasing FLASH memory.

VCC = 5.0 V,

Internal frequency : 24 MHz,

At Sleep mode.

I^CCS

VCC = 5.0 V,

Internal frequency : 2 MHz,

At Main Timer mode

I^CTS

VCC = 5.0 V,

Power supply

current*

Internal frequency : 24 MHz,

At PLL Timer mode,

external frequency = 4 MHz

VCC

I^CTSPLL6

4

7

mA MB90F347

VCC = 5.0V

Internal frequency: 8 kHz,

At sub operation

TA = +25°C

I^CCL

170

20

360 µA MB90F347

VCC = 5.0V

Internal frequency: 8 kHz,

At sub sleep

I^CCLS

50

60

µA MB90F347

TA = +25°C

VCC = 5.0V

Internal frequency: 8 kHz,

At watch mode

TA = +25°C

I^CCT

10

VCC = 5.0 V,

At Stop mode,

T^A= +25°C

I^CCH

7

5

100 µA MB90F347

Other than C, AVCC, AVSS,

AVRH, AVRL, V^CC, VSS,

Input capacity

C^IN

15

pF

* : Current values are tentative. They are subject to change without notice according to improvements in the

characteristics. The power supply current is measured with an external clock.

54

MB90340 Series

4. AC Characteristics

(1) Clock Timing

(T^A= −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

When using an oscillation

circuit

X0, X1

3

16

MHz

f^C

Clock frequency

When using an external

clock*

X0, X1

X0A, X1A

X0, X1

3

24

MHz

kHz

ns

f^CL

—

32.768 100

333

When using an oscillation

circuit

62.5

t^CYL

Clock cycle time

When using an external

clock

X0, X1

41.67

333

ns

t^CYLL

P^WH, PWL

P^WHL, PWLL

t^CR, tCF

f^CP

X0A, X1A

X0

10

5

30.5

15.2

—

µs

ns

µs

ns

Duty ratio is about 30% to

70%.

Input clock pulse width

X0A

Input clock rise and fall time

X0

5

When using external clock

1.5

24

MHz When using main clock

kHz When using sub clock

Internal operating clock

frequency (machine clock)

fCPL

8.192

122.1

50

t^CP

41.67

20

666

ns

When using main clock

When using sub clock

Internal operating clock

cycle time (machine clock)

tCPL

µs

* : Whem selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as

mentioned in “Relation among external clock frequency and machine clock frequency”.

tCYL

0.8 VCC

X0

0.2 VCC

PWH

PWL

tCF

tCR

tCYLL

0.8 VCC

0.2 VCC

X0A

PWHL

PWLL

tCF

tCR

Clock Timing

55

MB90340 Series

Guaranteed operation range

5.5

4.0

Guaranteed A/D Converter

operation range

3.5

Guaranteed PLL operation range

1.5

24

4

Machine clock f^CP(MHz)

Guaranteed operation range of MB90340 series

Guaranteed oscillation frequency range

x 2

x 1

x 6 x 4

x 3

24

16

12

Internal clock

f^CP(MHz)

x 1/2

(PLL off)

8

4.0

1.5

12

16

3

8

4

24

External clock f^C(MHz) *

* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz

External clock frequency and Machine clock frequency

56

MB90340 Series

(2) Reset Standby Input

Parameter Symbol

(T^A= −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)

Value

Unit

Remarks

Min

Max

500

ns

Under normal operation

In Stop mode, Sub Clock

mode, Sub Sleep mode

and Watch mode

Reset input

t^RSTL

Oscillation time of oscillator*

RST

ns

time

+ 100 µs

100

µs

In Time Timer mode

* : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators,

the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.

Under normal operation:

tRSTL

RST

0.2 VCC

In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

100

s

Oscillation time

of oscillator

Oscillation stabilization

waiting time

Instruction execution

Internal reset

57

MB90340 Series

(3) Power On Reset

(T^A= −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

Power on rise time

Power off time

t^R

VCC

30

ms

t^OFF

ms Due to repetitive operation

tR

2.7 V

VCC

0.2 V

tOFF

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you startup smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

VCC

We recommend a rise of

50 mV/ms maximum.

Holds RAM data

3 V

VSS

58

MB90340 Series

(4) Bus Timing (Read)

(T^A= –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min

Max

ALE pulse width

t^LHLL

ALE

tCP/2 − 10

ns

ALE, A23 to

A16, AD15

to AD00

Valid address

ALE ↓ time

tAVLL

t^LLAX

tAVRL

tCP/2 − 15

tCP − 15

ns

ALE, AD15

to AD00

ALE ↓

Address valid time

A23 toA16,

AD15 to

Valid address

RD ↓ time

AD00, RD

A23 to A16,

AD15 to

AD00

Valid address

input

Valid data

t^AVDV

5 tCP/2 − 40

3 tCP/2 − 50

ns

RD pulse width

tRLRH

tRLDV

RD

3 tCP/2 − 20

ns

RD, AD15 to

AD00

RD ↓

Valid data input

Data hold time

RD, AD15 to

AD00

RD ↑

RD ↓

RD ↑

tRHDX

tRHLH

tRHAX

0

ns

ALE ↑ time

RD, ALE

tCP/2 − 15

tCP/2 − 10

RD, A23 to

A16

Address valid time

A23 to A16,

AD15 to

Valid address

CLK ↑ time

t^AVCH

tCP/2 − 15

ns

AD00, CLK

RD ↓

CLK ↑ time

RD ↓ time

tRLCH

tLLRL

RD, CLK

ALE, RD

tCP/2 − 15

ns

ALE ↓

59

MB90340 Series

tRLCH

tAVCH

2.4 V

CLK

ALE

RD

tLLAX

tAVLL

tLHLL

tRHLH

2.4 V

0.8 V

2.4 V

tAVRL

tRLRH

2.4 V

0.8 V

tLLRL

tRHAX

2.4 V

0.8 V

2.4 V

0.8 V

A23 to A16

tRLDV

tRHDX

tAVDV

2.4 V

0.8 V

VIH

VIL

2.4 V

0.8 V

VIH

VIL

AD15 to AD00

Address

Read data

60

MB90340 Series

(5) Bus Timing (Write)

Parameter

(T^A= –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Value

Symbol

Condition

Unit Remarks

Min

Max

A23 to A16,

AD15 to AD00,

WR

Valid address

WR ↓ time

tAVWL

t^CP−15

ns

WR pulse width

tWLWH

tDVWH

WR

3 tCP/2 − 20

ns

Valid data output

time

WR ↑

AD15 to AD00,

WR

AD15 to AD00,

WR

WR ↑

Data hold time

tWHDX

tWHAX

15

ns

A23 to A16,

WR

Address valid time

tCP/2 − 10

WR ↑

WR ↓

ALE ↑ time

CLK ↑ time

tWHLH

tWLCH

WR, ALE

WR, CLK

tCP/2 − 15

ns

tWLCH

2.4 V

CLK

tWHLH

2.4 V

ALE

tAVWL

tWLWH

2.4 V

WR (WRL, WRH)

0.8 V

tWHAX

2.4 V

0.8 V

2.4 V

0.8 V

A23 to A16

tDVWH

tWHDX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to AD00

Address

Write data

61

MB90340 Series

(6) Ready Input Timing

(T^A= –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Rated Value

Min Max

Sym-

bol

Test

Condition

Parameter

Units Remarks

RDY setup time

RDY hold time

t^RYHS

RDY

45

0

ns

tRYHH

Note : If the RDY setup time is insufficient, use the auto-ready function.

2.4 V

CLK

ALE

RD/WR

tRYHS

tRYHH

VIH

RDY

When WAIT is not used.

RDY

VIL

When WAIT is used.

62

MB90340 Series

(7) Hold Timing

Parameter

(T^A= –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)

Value

Symbol

Condition

Units

Remarks

Min

Max

Pin floating

time

HAK ↓

Pin valid

tXHAL

tHAHV

HAK

30

t^CP

ns

HAK ↑ time

time

tCP

2 tCP

Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.

2.4V

HAK

0.8V

tHAHV

tXHAL

High-Z

2.4V

0.8V

2.4V

0.8V

Each pin

63

MB90340 Series

(8) UART0/1/2/3/4

(T^A= −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

SCK0 to SCK4

8 t^CP*

ns

SCK0 to SCK4,

SOT0 to SOT4

SCK ↓ → SOT delay time

tSLOV

−80

100

60

+80

Internal clock

operation output

pins are

SCK0 to SCK4,

SIN0 to SIN4

Valid SIN → SCK ↑

t^IVSH

t^SHIX

ns

CL = 80 pF + 1 TTL.

SCK0 to SCK4,

SIN0 to SIN4

SCK ↑ → Valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

tSHSL

SCK0 to SCK4

4 t^CP*

ns

t^SLSH

4 tCP*

SCK0 to SCK4, External clock

SOT0 to SOT4 operation output

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

150

ns

pins are

CL = 80 pF + 1 TTL.

SCK0 to SCK4,

SIN0 to SIN4

60

SCK0 to SCK4,

SIN0 to SIN4

SCK ↑ → Valid SIN hold time

* : Refer to “ (1) Clock timing” rating for t^CP(internal operating clock cycle time).

Notes : • AC characteristic in CLK synchronized mode.

• C^Lis load capacity value of pins when testing.

• tCP is the machine cycle (Unit : ns)

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

SOT

0.8 V

tIVSH

tSHIX

VIH

VIL

SIN

VIL

Internal Shift Clock Mode

64

MB90340 Series

tSLSH

tSHSL

VIH

SCK

SOT

VIL

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

VIH

VIL

VIH

VIL

SIN

External Shift Clock Mode

(9) Trigger Input Timing

Parameter

(T^A= −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)

Value

Symbol

Condition

Unit

Remarks

Min

Max

INT0 to INT15,

INT0R to INT15R,

ADTG

t^TRGH

tTRGL

Input pulse width

5 tCP

ns

VIH

INT0 to INT15,

INT0R to INT15R,

ADTG

VIL

tTRGH

tTRGL

65

MB90340 Series

(10) Timer Related Resource Input Timing

(T^A= −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

t^TIWH

t^TIWL

TIN0 to TIN3

IN0 to IN7

Input pulse width

4 t^CP

ns

VIH

VIL

TIN0 to TIN3,

IN0 to IN7

tTIWH

tTIWL

(11) Timer Related Resource Output Timing

(T^A= –40° to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

TOT0 to TOT3,

PPG0 to PPGF

CLK ↑

T^OUTchange time

tTO

30

ns

2.4 V

CLK

2.4 V

0.8 V

TOT0 to TOT3,

PPG0 to PPGF

tTO

66

MB90340 Series

5. A/D Converter

(T

A

= −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

10

Resolution

bit

Total error

±3.0

±2.5

LSB

Nonlinearity error

Differential

nonlinearity error

±1.9

LSB

Zero reading

voltage

V^OT

AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB

AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB

Full scale reading

voltage

V^FST

1.0

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AV^CC≤ 4.5 V

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AVCC ≤ 4.5 V

Compare time

Sampling time

µs

2.0

0.5

µs

1.2

Analog port input

current

I^AIN

AN0 to AN23

−0.3

+0.3

µA

Analog input

voltage range

VAIN

AVRL

AVRH

V

AVRH

AVRL

AVCC

AVRL + 2.7

AV^CC

V

Reference

voltage range

0

AVRH − 2.7

IA

I^AH

IR

3.5

7.5

5

mA

µA

Power supply

current

AVCC

*

AVRH

600

900

5

Reference

voltage current

IRH

Offset between

input channels

AN0 to AN23

4

LSB

* : When not operating A/D converter, this is the current (V^CC= AVCC = AVRH = 5.0 V) .

Note : The accuracy gets worse as AVRH − AVRL becomes smaller.

67

MB90340 Series

6. Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Non linearity

error

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differential

linearity error

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error

: Difference between an actual value and an ideal value. A total error includes zero transition

error, full-scale transition error, and linear error.

Zero reading

voltage

: Input voltage which results in the minimum conversion value.

Full scale

: Input voltage which results in the maximum conversion value.

reading voltage

Total error

3FF

1.5 LSB

3FE

3FD

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

VNT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVRL

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVRH − AVRL

1 LSB = (Ideal value)

[V]

1024

VOT (Ideal value) = AVRL + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

V^NT: A voltage at which digital output transitions from (N − 1) to N.

(Continued)

68

MB90340 Series

(Continued)

Non linearity error

Differential linearity error

Ideal

characteristics

3FF

3FE

3FD

Actual conversion

characteristics

{1 LSB × (N − 1)

N + 1

Actual conversion

characteristics

+ VOT }

VFST (actual

measurement

value)

N

VNT (actual

measurement value)

004

003

002

001

V (N + 1) T

(actual measurement

value)

Actual conversion

characteristics

N − 1

N − 2

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

VOT (actual measurement value)

Analog input

AVRL

AVRH

AVRL

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

[LSB]

Non linearity error of digital output N =

1 LSB

V (^N+1) T − VNT

−1 LSB [LSB]

1 LSB

Differential linearity error of digital output N =

1 LSB =

VFST − VOT

[V]

1022

V^OT: Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

69

MB90340 Series

7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs :

Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AV^CC≤ 5.5 V,

sampling period ≤ 0.5 µs)

If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors

and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high

as internal capacitor.

If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.

• Analog input circuit model

R

Analog input

Comparator

C

4.5 V ≤ AVCC ≤ 5.5 V : R=: 2.52 kΩ, C=: 10.7 pF

4.0 V ≤ AVCC ≤ 4.5 V : R=: 13.6 kΩ, C=: 10.7 pF

Note : Use the values in the figure only as a guideline.

8. Flash Memory Program/Erase Characteristics

Value

Parameter

Conditions

Unit

Remarks

Min

Typ

Max

Excludes programming

prior to erasure

Sector erase time

Chip erase time

1

15

s

T^A= +25 °C

VCC = 5.0 V

Excludes programming

prior to erasure

9

Word (16 bit width)

programming time

Except for the over head

time of the system

16

3,600

µs

Programs/Erase cycle

10,000

cycle

70

MB90340 Series

■ ORDERING INFORMATION

Part number

MB90F342PF

Package

Remarks

MB90F342SPF

MB90F342CPF

MB90F342CSPF

MB90F342PFV

MB90F342SPFV

MB90F342CPFV

MB90F342CSPFV

MB90F343PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90F343SPF

MB90F343CPF

MB90F343CSPF

MB90F343PFV

MB90F343SPFV

MB90F343CPFV

MB90F343CSPFV

MB90F345PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90F345SPF

MB90F345CPF

MB90F345CSPF

MB90F345PFV

MB90F345SPFV

MB90F345CPFV

MB90F345CSPFV

MB90F346PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90F346SPF

MB90F346CPF

MB90F346CSPF

MB90F346PFV

MB90F346SPFV

MB90F346CPFV

MB90F346CSPFV

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

(Continued)

71

MB90340 Series

Part number

MB90F347PF

Package

Remarks

MB90F347SPF

MB90F347CPF

MB90F347CSPF

MB90F347PFV

MB90F347SPFV

MB90F347CPFV

MB90F347CSPFV

MB90F349PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90F349SPF

MB90F349CPF

MB90F349CSPF

MB90F349PFV

MB90F349SPFV

MB90F349CPFV

MB90F349CSPFV

MB90341PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90341SPF

100-pin Plastic QFP

(FPT-100P-M06)

MB90341CPF

MB90341CSPF

MB90341PFV

MB90341SPFV

MB90341CPFV

MB90341CSPFV

MB90342PF

100-pin Plastic LQFP

(FPT-100P-M05)

MB90342SPF

100-pin Plastic QFP

(FPT-100P-M06)

MB90342CPF

MB90342CSPF

MB90342PFV

MB90342SPFV

MB90342CPFV

MB90342CSPFV

100-pin Plastic LQFP

(FPT-100P-M05)

(Continued)

72

MB90340 Series

(Continued)

Part number

Package

Remarks

MB90346PF

MB90346SPF

MB90346CPF

MB90346CSPF

MB90346PFV

MB90346SPFV

MB90346CPFV

MB90346CSPFV

MB90347PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90347SPF

MB90347CPF

MB90347CSPF

MB90347PFV

MB90347SPFV

MB90347CPFV

MB90347CSPFV

MB90348PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90348SPF

MB90348CPF

MB90348CSPF

MB90348PFV

MB90348SPFV

MB90348CPFV

MB90348CSPFV

MB90349PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

MB90349SPF

MB90349CPF

MB90349CSPF

MB90349PFV

MB90349SPFV

MB90349CPFV

MB90349CSPFV

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Plastic LQFP

(FPT-100P-M05)

299-pin Ceramic PGA

(PGA-299C-A01)

MB90V340

For evaluation

73

MB90340 Series

■ PACKAGE DIMENSIONS

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness including plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

*

20.00±0.20(.787±.008)

80

51

81

50

0.10(.004)

17.90±0.40

(.705±.016)

*

14.00±0.20

(.551±.008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8˚

1

30

0.65(.026)

0.32±0.05

(.013±.002)

0.17±0.06

(.007±.002)

M

0.13(.005)

0.25±0.20

(.010±.008)

(Stand off)

0.80±0.20

(.031±.008)

"A"

0.88±0.15

(.035±.006)

C

2002 FUJITSU LIMITED F100008S-c-5-5

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

74

MB90340 Series

(Continued)

100-pin Plastic LQFP

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

(FPT-100P-M05)

16.00±0.20(.630±.008)SQ

*

14.00±0.10(.551±.004)SQ

75

51

76

50

0.08(.003)

Details of "A" part

1.50 ⁺–0⁰.^.1²0⁰.059 –⁺.^.0⁰0⁰4⁸

(Mounting height)

INDEX

0.10±0.10

(.004±.004)

(Stand off)

100

26

0˚~8˚

"A"

0.50±0.20

(.020±.008)

0.25(.010)

1

25

0.60±0.15

(.024±.006)

0.50(.020)

0.20±0.05

(.008±.002)

0.145±0.055

(.0057±.0022)

M

0.08(.003)

C

2003 FUJITSU LIMITED F100007S-c-4-6

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

75

MB90340 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0305

FUJITSU LIMITED Printed in Japan


型号：	MB90F347PFV
厂家：	CYPRESS
描述：	Microcontroller, 16-Bit, FLASH, 24MHz, CMOS, PQFP100, PLASTIC, LQFP-100 微控制器
文件：	总76页 (文件大小：1033K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90F347PFV [CYPRESS]

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