MB95108ANPFV [CYPRESS]
Microcontroller, 8-Bit, MROM, 16.25MHz, CMOS, PQFP64, 10 X 10 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-64;型号: | MB95108ANPFV |
厂家: | CYPRESS |
描述: | Microcontroller, 8-Bit, MROM, 16.25MHz, CMOS, PQFP64, 10 X 10 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-64 时钟 微控制器 外围集成电路 |
文件: | 总72页 (文件大小:783K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12614-2Ea
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100AM Series
MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/
MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/
MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103
■ DESCRIPTION
The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://edevice.fujitsu.com/micom/en-support/
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2006.11
MB95100AM Series
(Continued)
• Timer
• 8/16-bit compound timer × 2 channels
• 16-bit reload timer
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
• Timebase timer
• Watch prescaler (for dual clock product)
• LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• I2C*
Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
• I/O ports :
• The number of maximum ports
• Single clock product : 54 ports
• Dual clock product : 52 ports
• Port configuration
• General-purpose I/O ports (N-ch open drain) : 6 ports
• General-purpose I/O ports (CMOS)
: Single clock product : 48 ports
Dual clock product : 46 ports
• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-
ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
2
MB95100AM Series
■ MEMORY LINEUP
Flash
RAM
MB95F104AMS/F104ANS/F104AJS
MB95F104AMW/F104ANW/F104AJW
MB95F106AMS/F106ANS/F106AJS
MB95F106AMW/F106ANW/F106AJW
MB95F108AMS/F108ANS/F108AJS
MB95F108AMW/F108ANW/F108AJW
16K bytes
512 bytes
32K bytes
60K bytes
1K byte
2K bytes
3
MB95100AM Series
■ PRODUCT LINEUP
Part number
MB95F
104AMS/
MB95F
106AMS/
MB95F
108AMS
MB95F
104ANS/ 104AMW/ 104ANW/
MB95F MB95F MB95F
MB95F
MB95F
MB95F
104AJS/
MB95F
106AJS/
MB95F
108AJS
MB95F
104AJW/
MB95F
106AJW/
MB95F
108AJW
MB95
108AM
106ANS/ 106AMW/ 106ANW/
MB95F
MB95F
MB95F
108ANS
108AMW 108ANW
Parameter
MASK
ROM
Type
Flash memory product
product
ROM capacity*1
RAM capacity*1
Reset output
60 Kbytes (Max)
2 Kbytes (Max)
No
Yes
Selectable
single/dual
clock*3
Clock system
Single clock
Dual clock
No
Single clock Dual clock
Low voltage
detection reset
Yes/No
No
Yes
No
Yes
Yes
Clock supervisor
Number of basic instructions
Instruction bit length
Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
CPU functions
Data bit length
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time : 0.6 μs (at machine clock frequency 16.25 MHz)
• Single clock product : 54 ports (N-ch open drain : 6 ports, CMOS : 48 ports)
• Dual clock product : 52 ports (N-ch open drain : 6 ports, CMOS : 46 ports)
Programmable input voltage levels of port :
General-pur-
pose I/O ports
Automotive input level / CMOS input level / hysteresis input level
Timebase timer Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Reset generated cycle
Watchdog timer At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register
I2C
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
UART/SIO
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
(Continued)
4
MB95100AM Series
MB95F
104AMS/ 104ANS/ 104AMW/ 104ANW/ 104AJS/ 104AJW/
MB95F MB95F MB95F MB95F MB95F MB95F
106AMS/ 106ANS/ 106AMW/ 106ANW/ 106AJS/ 106AJW/
MB95F MB95F MB95F MB95F MB95F MB95F
108AMS 108ANS 108AMW 108ANW 108AJS 108AJW
MB95F
MB95F
MB95F
MB95F
MB95F
Part number
MB95
108AM
Parameter
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer
LIN-UART
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capa-
ble
LIN functions available as the LIN master or LIN slave.
8/10-bit A/D converter
(12 channels)
8-bit or 10-bit resolution can be selected.
Two clock modes and two counter operating modes can be selected. Square wave-
form output
Count clock : 7 internal clocks and external clock can be selected.
Counter operating mode : reload mode or one-shot mode can be selected.
16-bit reload timer
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer
× 1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
waveform output
8/16-bit compound
timer (2 channels)
Count clock : 7 internal clocks and external clock can be selected
PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”.
Counter operating clock : Eight selectable clock sources
8/16-bit PPG
(2 channels)
Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when
selecting clock source 1 second and setting counter value to 60)
Watch counter
(for dual clock product)
Watch prescaler
(for dual clock product)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(12 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
4
Supports automatic programming, Embedded AlgorithmTM
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
*
Flash memory
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
(MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW only)
Standby mode
Sleep, stop, watch (for dual clock product) , and timebase timer
(Continued)
5
MB95100AM Series
(Continued)
*1 : For ROM capacity and RAM capacity, refer to “■ MEMORY LINEUP”.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Specify clock mode when ordering MASK ROM.
*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of the evaluation product in MB95100AM series is MB95FV100D-103. When using it, the MCU
board (MB2146-303A) is required.
6
MB95100AM Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown as follows.
Oscillation stabilization wait time
Remarks
(214-2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part
number
MB95F104AMS/F104ANS/ MB95F104AMW/F104ANW/
F104AJS F104AJW
MB95F106AMS/F106ANS/ MB95F106AMW/F106ANW/
F106AJS
MB95F108AMS/F108ANS/ MB95F108AMW/F108ANW/
F108AJS F108AJW
MB95108AM
MB95FV100D-103
F106AJW
Parameter
FPT-64P-M03
FPT-64P-M09
BGA-224P-
M08
: Available
: Unavailable
7
MB95100AM Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95100AM series but also those of other products
to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95100AM series are therefore access-barred. Read/write access to
these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting
in unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or write unexpectedly) .
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
flash memory and MASK ROM products, do not use these values in the program.
The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access to
these bits does not cause hardwaremalfunctions. Since the Evaluation, Flash memory, and MASKROMproducts
are designed to behave completely the same way in terms of hardware and software.
• Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
The current consumption of Flash memory product is typically greater than for MASK ROM product.
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating Voltage
The operating voltage are different among the Evaluation, Flash memory, and MASK ROM products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Difference between RST and MOD Pins
The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull-down resistor is provided for
the MOD pin of the MASK ROM product.
8
MB95100AM Series
■ PIN ASSIGNMENT
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVcc
AVR
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P64/EC1
P63/TO11
P62/TO10
P61/PPG11
P60/PPG10
P53/TRG1
P52/PPG1
P51/SDA0
P50/SCL0
P24/EC0
P23/TO01
P22/TO00
P21/PPG01
P20/PPG00
P14/PPG0
P13/TRG0/ADTG
PE3/INT13
PE2/INT12
PE1/INT11
PE0/INT10
P83
P82
P81
P80
P71/TI0
P70/TO0
MOD
X0
X1
Vss
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(FPT-64P-M03, FPT-64P-M09)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
9
MB95100AM Series
■ PIN DESCRIPTION
I/O
Circuit
type*
Pin no.
Pin name
Function
A/D converter power supply pin
1
2
AVcc
AVR
⎯
⎯
A/D converter reference input pin
3
PE3/INT13
PE2/INT12
PE1/INT11
PE0/INT10
P83
4
General-purpose I/O port.
The pins are shared with the external interrupt input.
P
5
6
7
8
P82
O
H
General-purpose I/O port
9
P81
10
P80
General-purpose I/O port.
The pin is shared with 16-bit reload timer ch.0 output.
11
12
P71/TI0
General-purpose I/O port.
The pin is shared with 16-bit reload timer ch.0 input.
P70/TO0
13
14
15
16
17
18
MOD
X0
B
A
An operating mode designation pin
Main clock input oscillation pin
Main clock input/output oscillation pin
Power supply pin (GND)
X1
Vss
Vcc
C
⎯
⎯
⎯
Power supply pin
Capacitor connection pin
Single clock product is general-purpose port (PG2) .
Dual clock product is sub clock input/output oscillation pin (32 kHz).
19
20
PG2/X1A
PG1/X0A
H/A
B’
Single clock product is general-purpose port (PG1) .
Dual clock product is sub clock input oscillation pin (32 kHz).
21
22
23
24
25
26
27
28
29
RST
Reset pin
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
General-purpose I/O port.
The pins are shared with external interrupt input. Large current port.
C
G
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input.
30
P10/UI0
(Continued)
10
MB95100AM Series
I/O
Circuit
type*
Pin no.
Pin name
Function
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output.
31
32
P11/UO0
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
P12/UCK0
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and
A/D trigger input (ADTG).
P13/TRG0/
ADTG
33
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
34
P14/PPG0
35
36
37
38
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.0 output.
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.0 output.
H
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 clock input.
39
40
41
42
43
P24/EC0
P50/SCL0
P51/SDA0
P52/PPG1
P53/TRG1
General-purpose I/O port.
The pin is shared with I2C ch.0 clock I/O.
I
General-purpose I/O port.
The pin is shared with I2C ch.0 data I/O.
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 output.
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 trigger input.
44
45
46
47
P60/PPG10
P61/PPG11
P62/TO10
P63/TO11
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.1 output.
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.1 output.
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.1 clock input.
K
48
49
50
51
P64/EC1
P65/SCK
P66/SOT
P67/SIN
General-purpose I/O port.
The pin is shared with LIN-UART clock I/O.
General-purpose I/O port.
The pin is shared with LIN-UART data output.
General-purpose I/O port.
The pin is shared with LIN-UART data input.
L
J
52
53
54
55
P43/AN11
P42/AN10
P41/AN09
P40/AN08
General-purpose I/O port.
The pins are shared with A/D converter analog input.
(Continued)
11
MB95100AM Series
(Continued)
I/O
Circuit
type*
Pin no.
Pin name
Function
56
57
58
59
60
61
62
63
64
P37/AN07
P36/AN06
P35/AN05
P34/AN04
P33/AN03
P32/AN02
P31/AN01
P30/AN00
AVss
General-purpose I/O port.
The pins are shared with A/D converter analog input.
J
⎯
A/D converter power supply pin (GND)
*: For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”
12
MB95100AM Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation circuit
Clock input
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
X1 (X1A)
N-ch
A
X0 (X0A)
Feedback resistance : approx. 10 MΩ
Standby control
• Only for input
Hysteresis input only for MASK ROM
product
Mode input
R
B
With pull-down resistor only for MASK
ROM product
• Hysteresis input only for MASK ROM
product
Reset input
B’
• Reset output
Reset output
N-ch
• CMOS output
• Hysteresis input
• Automotive input
P-ch
Digital output
Digital output
N-ch
C
Hysteresis input
Automotive input
Standby control
External interrupt
enable
• CMOS output
R
P-ch
• CMOS input
Pull-up control
Digital output
• Hysteresis input
• With pull-up control
• Automotive input
P-ch
N-ch
Digital output
G
CMOS input
Hysteresis input
Automotive input
Standby control
(Continued)
13
MB95100AM Series
Type
Circuit
Remarks
• CMOS output
• Hysteresis input
• With pull-up control
• Automotive input
R
P-ch
Pull-up control
Digital output
P-ch
N-ch
H
Digital output
Hysteresis input
Automotive input
Standby control
• N-ch open drain output
• CMOS input
• Hysteresis input
• Automotive input
Digital output
N-ch
CMOS input
I
Hysteresis input
Automotive input
Standby control
• CMOS output
• Hysteresis input
• Analog input
• With pull-up control
• Automotive input
R
P-ch
Pull-up control
P-ch
N-ch
Digital output
Digital output
J
Analog input
Hysteresis input
Automotive input
A/D control
Standby control
• CMOS output
• Hysteresis input
• Automotive input
P-ch
N-ch
Digital output
Digital output
K
Hysteresis input
Automotive input
Standby control
(Continued)
14
MB95100AM Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• CMOS input
• Hysteresis input
• Automotive input
P-ch
Digital output
Digital output
N-ch
L
CMOS input
Hysteresis input
Automotive input
Standby control
• N-ch open drain output
• Hysteresis input
• Automotive input
Digital output
N-ch
Hysteresis input
Automotive input
O
Standby control
• CMOS output
• Hysteresis input
• With pull-up control
• Automotive input
R
P-ch
Pull-up control
P-ch
Digital output
Digital output
N-ch
P
Hysteresis input
Automotive input
Standby control
External
interrupt control
15
MB95100AM Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC, AVR) and analog input voltage from exceeding
the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50 Hz/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the
transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply
is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
■ PIN CONNECTION
• Treatment of Unused Input Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent dam-
age. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins. If there is unused output pin, make it to open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS near
this device.
16
MB95100AM Series
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pins to VCC or VSS pins and to provide a low-impedance connection.
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C pin connection diagram
C
C
S
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN11 pins.
17
MB95100AM Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
FPT-64P-M03
TEF110-108F35AP
FPT-64P-M09
TEF110-108F36AP
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
• MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW (60 Kbytes)
Flash memory
SA1 (4 Kbytes)
CPU address
1000H
Programmer address*
71000H
1FFFH
2000H
71FFFH
72000H
SA2 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA5 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to “17222”.
2) Load program data to programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer
18
MB95100AM Series
• MB95F106AMS/F106ANS/F106AJS/F106AMW/F106ANW/F106AJW (32 Kbytes)
Flash memory
CPU address
8000H
Programmer address*
78000H
SA5 (16 Kbytes)
BFFFH
C000H
7BFFFH
7C000H
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to "17222"
2) Load program data to programmer addresses 78000H to 7FFFFH.
3) Programmed by parallel programmer
• MB95F104AMS/F104ANS/F104AJS/F104AMW/F104ANW/F104AJW (16 Kbytes)
Flash memory
SA6 (4 Kbytes)
CPU address
C000H
Programmer address*
7C000H
CFFFH
D000H
7CFFFH
7D000H
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to "17222"
2) Load program data to programmer addresses 7C000H to 7FFFFH.
3) Programmed by parallel programmer
19
MB95100AM Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
RST
Reset control
Clock control
ROM
RAM
X0,X1
PG2/X1A*
PG1/X0A*
Interrupt control
Wild register
Watch prescaler
Watch counter
P00/INT00 to P07/INT07
External interrupt ch.0 to ch.7
P60/PPG10
P61/PPG11
8/16-bit PPG ch.1
P10/UI0
P11/UO0
P12/UCK0
P62/TO10
P63/TO11
P64/EC1
UART/SIO
8/16-bit compound
timer ch.1
P13/TRG0/ADTG
P14/PPG0
16-bit PPG ch.0
P65/SCK
P66/SOT
P67/SIN
LIN-UART
P20/PPG00
P21/PPG01
8/16-bit PPG ch.0
P70/TO0
P71/TI0
P22/TO00
P23/TO01
P24/EC0
16-bit reload timer
8/16-bit compound
timer ch.0
P80 to P83
P30/AN00 to P37/AN07
PE0/INT10 to PE3/INT13
External interrupt ch.8 to ch.11
P40/AN08 to P43/AN11
8/10-bit
A/D converter
AVCC
AVSS
AVR
P50/SCL0
P51/SDA0
I 2C
P52/PPG1
P53/TRG1
16-bit PPG ch.1
Port
Port
Other pins
MOD, VCC, VSS, C
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
20
MB95100AM Series
■ CPU CORE
1. Memory space
Memory space of the MB95100AM series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95100AM series is shown below.
• Memory Map
MB95F104AMS/F104ANS/F104AJS
MB95F106AMS/F106ANS/F106AJS
MB95F108AMS/F108ANS/F108AJS
MB95F104AMW/F104ANW/F104AJW
MB95F106AMW/F106ANW/F106AJW
MB95108AM
MB95FV100D-103
MB95F108AMW/F108ANW/F108AJW
0000H
0000H
0000H
I/O
I/O
I/O
0080H
0100H
0200H
0080H
0100H
0200H
0080H
0100H
0200H
RAM 2 Kbytes
Register
RAM
RAM 3.75 Kbytes
Register
Register
Address #1
0F80H
0880H
0F80H
Access
prohibited
Access
prohibited
0F80H
Extension I/O
Extension I/O
Extension I/O
Address #2
1000H
1000H
MASK ROM
60 Kbytes
Flash memory
60 Kbytes
Flash memory
FFFFH
FFFFH
FFFFH
21
MB95100AM Series
Flash
RAM
Address #1
Address #2
MB95F104AMS/F104ANS/F104AJS
MB95F104AMW/F104ANW/F104AJW
MB95F106AMS/F106ANS/F106AJS
MB95F106AMW/F106ANW/F106AJW
MB95F108AMS/F108ANS/F108AJS
MB95F108AMW/F108ANW/F108AJW
16 Kbytes
512 bytes
0280H
C000H
32 Kbytes
60 Kbytes
1 Kbyte
0480H
0880H
8000H
1000H
2 Kbytes
22
MB95100AM Series
2. Register
The MB95100AM series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower one byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower one byte is used.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register for index modification.
: A 16-bit pointer to point to a memory address.
: A 16-bit register to indicate a stack area.
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register.
Initial Value
16-bit
FFFDH
0000H
0000H
0000H
0000H
0000H
0030H
: Program counter
: Accumulator
PC
A
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the Program Status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R4
R3
R2
R1
R0 DP2 DP1 DP0
H
I
IL1
IL0
N
Z
PS
C
V
RP
DP
CCR
23
MB95100AM Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
OP code lower
"0" "0" "0" "0" "0" "0" "0" "1"
R4 R3 R2 R1 R0 b2
b1
b0
Generated address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
0000H to 007FH (without mapping)
0080H to 00FFH (without mapping)
0100H to 017FH
XXXB (no effect to mapping)
0000H to 007FH
000B (initial value)
001B
010B
011B
100B
101B
110B
111B
0180H to 01FFH
0200H to 027FH
0080H to 00FFH
0280H to 02FFH
0300H to 037FH
0380H to 03FFH
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
I flag
Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by this bit.
:
:
:
IL1, IL0
IL1
0
IL0
0
Interrupt level
Priority
0
1
2
High
0
1
1
0
1
1
3
Low = no interruption
N flag
Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
:
:
:
Z flag
V flag
Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag
Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
:
24
MB95100AM Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-
registers. Up to a total of 32 banks can be used on the MB95100AM series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100
H
+ 8 × (RP)
Address 100H
R0
R1
R0
R1
R0
R1
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
1FFH
Bank 31
107H
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
Bank 0
Memory area
25
MB95100AM Series
■ I/O MAP
Register
Address
Register name
R/W
Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
0010H
0011H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
001AH
001BH
PDR0
DDR0
PDR1
DDR1
⎯
Port 0 data register
Port 0 direction register
Port 1 data register
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
⎯
Port 1 direction register
(Disabled)
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
⎯
Oscillation stabilization wait time setting register
PLL control register
R/W
R/W
R/W
R/W
R
11111111B
00000000B
1010X011B
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
⎯
System clock control register
Standby control register
Reset source register
Timebase timer control register
Watch prescaler control register
Watchdog timer control register
(Disabled)
R/W
R/W
R/W
⎯
PDR2
DDR2
PDR3
DDR3
PDR4
DDR4
PDR5
DDR5
PDR6
DDR6
PDR7
DDR7
PDR8
DDR8
Port 2 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port 2 direction register
Port 3 data register
Port 3 direction register
Port 4 data register
Port 4 direction register
Port 5 data register
Port 5 direction register
Port 6 data register
Port 6 direction register
Port 7 data register
Port 7 direction register
Port 8 data register
Port 8 direction register
001CH to
0025H
⎯
(Disabled)
⎯
⎯
0026H
0027H
PDRE
DDRE
Port E data register
R/W
R/W
00000000B
00000000B
Port E direction register
0028H,
0029H
⎯
(Disabled)
⎯
⎯
002AH
PDRG
Port G data register
R/W
00000000B
(Continued)
26
MB95100AM Series
Register
abbreviation
Address
Register name
R/W Initial value
002BH
002CH
002DH
002EH
002FH
0030H
0031H
0032H
0033H
0034H
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
DDRG
⎯
Port G direction register
(Disabled)
R/W
⎯
00000000B
⎯
PUL1
Port 1 pull-up register
R/W
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
⎯
PUL2
Port 2 pull-up register
PUL3
Port 3 pull-up register
PUL4
Port 4 pull-up register
PUL5
Port 5 pull-up register
PUL7
Port 7 pull-up register
⎯
(Disabled)
PULE
Port E pull-up register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
Port G pull-up register
8/16-bit compound timer 01 control status register 1 ch.0
8/16-bit compound timer 00 control status register 1 ch.0
8/16-bit compound timer 11 control status register 1 ch.1
8/16-bit compound timer 10 control status register 1 ch.1
8/16-bit PPG1 control register ch.0
8/16-bit PPG0 control register ch.0
8/16-bit PPG1 control register ch.1
8/16-bit PPG0 control register ch.1
16-bit reload timer control status register (Upper byte) ch.0
16-bit reload timer control status register (Lower byte) ch.0
PC00
PC11
PC10
TMCSRH0
TMCSRL0
0040H,
0041H
⎯
(Disabled)
⎯
⎯
0042H
0043H
0044H
0045H
PCNTH0
PCNTL0
PCNTH1
PCNTL1
16-bit PPG status control register (Upper byte) ch.0
16-bit PPG status control register (Lower byte) ch.0
16-bit PPG status control register (Upper byte) ch.1
16-bit PPG status control register (Lower byte) ch.1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
0046H,
0047H
⎯
(Disabled)
⎯
⎯
0048H
0049H
004AH
004BH
004CH
004DH
EIC00
EIC10
EIC20
EIC30
EIC01
EIC11
External interrupt circuit control register ch.0/ch.1
External interrupt circuit control register ch.2/ch.3
External interrupt circuit control register ch.4/ch.5
External interrupt circuit control register ch.6/ch.7
External interrupt circuit control register ch.8/ch.9
External interrupt circuit control register ch.10/ch.11
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
(Continued)
27
MB95100AM Series
Register
Address
Register name
R/W Initial value
abbreviation
004EH,
⎯
(Disabled)
⎯
⎯
004FH
0050H
0051H
0052H
0053H
0054H
0055H
0056H
0057H
0058H
0059H
005AH
SCR
SMR
LIN-UART serial control register
LIN-UART serial mode register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
00000000B
00001000B
00000000B
00000100B
000000XXB
00000000B
00100000B
00000001B
00000000B
00000000B
SSR
LIN-UART serial status register
RDR/TDR
ESCR
ECCR
SMC10
SMC20
SSR0
LIN-UART reception/transmission data register
LIN-UART extended status control register
LIN-UART extended communication control register
UART/SIO serial mode control register 1 ch.0
UART/SIO serial mode control register 2 ch.0
UART/SIO serial status register ch.0
TDR0
UART/SIO serial output data register ch.0
UART/SIO serial input data register ch.0
RDR0
005BH to
005FH
⎯
(Disabled)
⎯
⎯
0060H
0061H
0062H
0063H
0064H
0065H
IBCR00
IBCR10
IBSR0
IDDR0
IAAR0
ICCR0
I2C bus control register 0 ch.0
I2C bus control register 1 ch.0
I2C bus status register ch.0
I2C data register ch.0
I2C address register ch.0
I2C clock control register ch.0
R/W
R/W
R
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
R/W
R/W
R/W
0066H to
006BH
⎯
(Disabled)
⎯
⎯
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
WCSR
⎯
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register (Upper byte)
8/10-bit A/D converter data register (Lower byte)
Watch counter status register
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
00000000B
⎯
(Disabled)
FSR
Flash memory status register
R/W
R/W
R/W
⎯
000X0000B
00000000B
00000000B
SWRE0
SWRE1
⎯
Flash memory sector writing control register 0
Flash memory sector writing control register 1
(Disabled)
⎯
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W
R/W
00000000B
00000000B
(Continued)
28
MB95100AM Series
Register
abbreviation
Address
Register name
R/W Initial value
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
⎯
⎯
⎯
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
Interrupt level setting register 0
Interrupt level setting register 1
R/W
R/W
R/W
R/W
R/W
R/W
⎯
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
⎯
ILR2
Interrupt level setting register 2
ILR3
Interrupt level setting register 3
ILR4
Interrupt level setting register 4
ILR5
Interrupt level setting register 5
⎯
(Disabled)
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register address setting register (Upper byte) ch.0
Wild register address setting register (Lower byte) ch.0
Wild register data setting register ch.0
Wild register address setting register (Upper byte) ch.1
Wild register address setting register (Lower byte) ch.1
Wild register data setting register ch.1
Wild register address setting register (Upper byte) ch.2
Wild register address setting register (Lower byte) ch.2
Wild register data setting register ch.2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0F89H to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit compound timer 01 control status register 0 ch.0
8/16-bit compound timer 00 control status register 0 ch.0
8/16-bit compound timer 01 data register ch.0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 00 data register ch.0
8/16-bit compound timer 00/01 timer mode control register
ch.0
0F96H
TMCR0
R/W
00000000B
0F97H
0F98H
0F99H
0F9AH
T11CR0
T10CR0
T11DR
T10DR
8/16-bit compound timer 11 control status register 0 ch.1
8/16-bit compound timer 10 control status register 0 ch.1
8/16-bit compound timer 11 data register ch.1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 10 data register ch.1
8/16-bit compound timer 10/11 timer mode control register
ch.1
0F9BH
TMCR1
R/W
00000000B
0F9CH
0F9DH
0F9EH
0F9FH
PPS01
PPS00
PDS01
PDS00
8/16-bit PPG1 cycle setting buffer register ch.0
8/16-bit PPG0 cycle setting buffer register ch.0
8/16-bit PPG1 duty setting buffer register ch.0
8/16-bit PPG0 duty setting buffer register ch.0
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
(Continued)
29
MB95100AM Series
Register
Address
Register name
R/W Initial value
abbreviation
0FA0H
0FA1H
0FA2H
0FA3H
0FA4H
0FA5H
PPS11
PPS10
PDS11
PDS10
PPGS
REVC
8/16-bit PPG1 cycle setting buffer register ch.1
8/16-bit PPG0 cycle setting buffer register ch.1
8/16-bit PPG1 duty setting buffer register ch.1
8/16-bit PPG0 duty setting buffer register ch.1
8/16-bit PPG start register
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
8/16-bit PPG output inversion register
TMRH0/
TMRLRH0
16-bit timer register (Upper byte) ch.0/
16-bit reload register (Upper byte) ch.0
0FA6H
0FA7H
R/W
R/W
⎯
00000000B
00000000B
⎯
TMRL0/
TMRLRL0
16-bit timer register (Lower byte) ch.0/
16-bit reload register (Lower byte) ch.0
0FA8H,
0FA9H
⎯
(Disabled)
0FAAH
0FABH
0FACH
0FADH
0FAEH
0FAFH
0FB0H
0FB1H
0FB2H
0FB3H
0FB4H
0FB5H
PDCRH0
PDCRL0
PCSRH0
PCSRL0
PDUTH0
PDUTL0
PDCRH1
PDCRL1
PCSRH1
PCSRL1
PDUTH1
PDUTL1
16-bit PPG down counter register (Upper byte) ch.0
16-bit PPG down counter register (Lower byte) ch.0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
16-bit PPG duty setting buffer register (Upper byte) ch.0
16-bit PPG duty setting buffer register (Lower byte) ch.0
16-bit PPG down counter register (Upper byte) ch.1
16-bit PPG down counter register (Lower byte) ch.1
16-bit PPG cycle setting buffer register (Upper byte) ch.1
16-bit PPG cycle setting buffer register (Lower byte) ch.1
16-bit PPG duty setting buffer register (Upper byte) ch.1
16-bit PPG duty setting buffer register (Lower byte) ch.1
R
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
R
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
0FB6H to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
0FBDH
BGR1
BGR0
LIN-UART baud rate generator register 1
LIN-UART baud rate generator register 0
R/W
R/W
00000000B
00000000B
UART/SIO dedicated baud rate generator
prescaler selection register ch.0
0FBEH
0FBFH
PSSR0
BRSR0
⎯
R/W
R/W
⎯
00000000B
00000000B
⎯
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
0FC0H,
0FC1H
(Disabled)
0FC2H
0FC3H
AIDRH
AIDRL
A/D input disable register (Upper byte)
A/D input disable register (Lower byte)
R/W
R/W
00000000B
00000000B
(Continued)
30
MB95100AM Series
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
0FC4H to
0FE2H
⎯
WCDR
⎯
(Disabled)
Watch counter data register
(Disabled)
⎯
R/W
⎯
⎯
00111111B
⎯
0FE3H
0FE4H to
0FE6H
0FE7H
ILSR2
⎯
Input level select register 2
(Disabled)
R/W
⎯
00000000B
⎯
0FE8H,
0FE9H
0FEAH
CSVCR
⎯
Clock supervisor control register
(Disabled)
R/W
⎯
00011100B
⎯
0FEBH to
0FEDH
0FEEH
0FEFH
ILSR
Input level select register
R/W
R/W
00000000B
01000000B
WICR
Interrupt pin control register
0FF0H to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
W
: Read only
: Write only
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
31
MB95100AM Series
■ INTERRUPT SOURCE TABLE
Vector table address
Same level
priority order
(atsimultaneous
occurrence)
Interrupt
request
number
Bit name of
interrupt level
setting register
Interrupt source
Upper
FFFAH
FFF8H
FFF6H
FFF4H
Lower
FFFBH
FFF9H
FFF7H
FFF5H
External interrupt ch.0
High
IRQ0
IRQ1
IRQ2
IRQ3
L00 [1 : 0]
L01 [1 : 0]
L02 [1 : 0]
L03 [1 : 0]
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
UART/SIO ch.0
IRQ4
IRQ5
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFF3H
FFF1H
FFEFH
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
L04 [1 : 0]
L05 [1 : 0]
L06 [1 : 0]
L07 [1 : 0]
L08 [1 : 0]
L09 [1 : 0]
L10 [1 : 0]
L11 [1 : 0]
L12 [1 : 0]
L13 [1 : 0]
L14 [1 : 0]
L15 [1 : 0]
L16 [1 : 0]
L17 [1 : 0]
L18 [1 : 0]
L19 [1 : 0]
L20 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
8/16-bit compound timer ch.0 (Upper)
LIN-UART (reception)
LIN-UART (transmission)
8/16-bit PPG ch.1 (Lower)
8/16-bit PPG ch.1 (Upper)
16-bit reload timer ch.0
8/16-bit PPG ch.0 (Upper)
8/16-bit PPG ch.0 (Lower)
8/16-bit compound timer ch.1 (Upper)
16-bit PPG ch.0
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
I2C ch.0
16-bit PPG ch.1
8/10-bit A/D converter
Timebase timer
Watch prescaler/Watch counter
External interrupt ch.8
External interrupt ch.9
External interrupt ch.10
External interrupt ch.11
8/16-bit compound timer ch.1 (Lower)
Flash memory
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
IRQ22
IRQ23
FFCEH
FFCCH
FFCFH
FFCDH
L22 [1 : 0]
L23 [1 : 0]
Low
32
MB95100AM Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Vcc
AVcc
Vss − 0.3
Vss + 6.0
*2
Power supply voltage*1
V
AVR
VI
Vss − 0.3
Vss − 0.3
Vss − 0.3
− 2.0
Vss + 6.0
Vss + 6.0
Vss + 6.0
+ 2.0
*2
*3
*3
Input voltage*1
Output voltage*1
VO
V
Maximum clamp current
ICLAMP
mA Applicable to pins*4
Total maximum clamp
current
Σ|ICLAMP|
⎯
⎯
20
mA Applicable to pins*4
IOL1
IOL2
15
15
Other than P00 to P07
“L” level maximum
output current
mA
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
IOLAV1
4
(1 pin)
mA
“L” level average
current
⎯
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOLAV2
12
“L” level total maximum
output current
ΣIOL
⎯
⎯
100
50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“L” level total average
output current
ΣIOLAV
IOH1
IOH2
− 15
− 15
Other than P00 to P07
“H” level maximum
output current
⎯
mA
P00 to P07
Other than P00 to P07
Average output current =
IOHAV1
− 4
− 8
operating current × operating ratio
(1 pin)
mA
“H” level average
current
⎯
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOHAV2
“H” level total maximum
output current
ΣIOH
⎯
⎯
− 100
− 50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“H” level total average
output current
ΣIOHAV
(Continued)
33
MB95100AM Series
(Continued)
Rating
Parameter
Symbol
Unit
Min
⎯
Max
320
Power consumption
Operating temperature
Storage temperature
Pd
TA
mW
°C
− 40
− 55
+ 85
+ 150
Tstg
°C
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V.
*3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71,
PE0 to PE3
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affect
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
Vcc
Limiting
P-ch
resistance
+ B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
34
MB95100AM Series
2. Recommended Operating Conditions
(AVss = Vss = 0.0 V)
Value
Sym-
bol
Condi-
tions
Parameter
Pin name
Unit
Remarks
Min
Max
At normal
operating
2.42*1
2.3
5.5
Other than
MB95FV100D-103
Retain
status of
stop
5.5
5.5
5.5
Power
supply
voltage
operation
VCC,
AVCC
⎯
⎯
V
At normal
operating
2.7
Retain
status of
stop
MB95FV100D-103
2.3
operation
A/D converter
reference
input voltage
V
AVR
⎯
⎯
4.0
0.1
AVCC
1.0
Smoothing
capacitor
CS
TA
⎯
⎯
⎯
⎯
μF *2
− 40
+ 5
+ 85
+ 35
Other than MB95FV100D-103
MB95FV100D-103
Operating
temperature
°C
*1 : The value is 2.88 V when the low voltage detection reset is used.
*2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC
pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the
diagram below.
• C pin connection diagram
C
C
S
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
35
MB95100AM Series
3. DC Characteristics
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Typ
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min
Max
Hysteresis
input of CMOS
input level
Vcc +
0.3
VIH P10, P50, P51, P67
*1
0.7 Vcc
⎯
V
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
Pin input at
selecting of
Automotive
input level
VIHA
⎯
0.8 VCC
⎯
VCC + 0.3
V
V
P60 to P67, P70, P71,
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
“H” level input
voltage
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
Vcc +
0.3
VIHS
*1
0.8 Vcc
0.7 Vcc
⎯
Hysteresis input
P60 to P67, P70, P71,
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
CMOS input
(MASK ROM
product is
hysteresis
input)
Vcc +
0.3
VIHM RST, MOD
⎯
⎯
⎯
V
V
Hysteresis
input of CMOS
input level
Vss −
0.3
VIL P10, P50, P51, P67
*1
0.3 Vcc
0.5 VCC
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
Pin input at
selecting of
Automotive
input level
VILA
⎯
VSS − 0.3
⎯
V
P60 to P67, P70, P71,
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
“L” level input
voltage
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
Vss −
VILS
*1
⎯
⎯
0.2 Vcc
0.3 Vcc
V
V
Hysteresis input
0.3
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
CMOS input
(MASK ROM
product is
hysteresis
input)
Vss −
0.3
VILM RST, MOD
⎯
(Continued)
36
MB95100AM Series
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min Typ Max
Open-drain
output
application
voltage
P50, P51,
P80 to P83
Vss −
0.3
Vss +
5.5
VD
⎯
⎯
V
Output pin other than
P00 to P07
IOH =
VCC −
VOH1
⎯
⎯
⎯
⎯
V
V
− 4.0 mA
0.5
“H” level output
voltage
IOH =
− 8.0 mA
VCC −
0.5
VOH2 P00 to P07
Output pin other than
VOL1
IOL = 4.0 mA
IOL = 12 mA
⎯
⎯
⎯
⎯
0.4
0.4
V
V
“L” level output
voltage
P00 to P07, RST*3
VOL2 P00 to P07
Input leakage
current (Hi-Z
output leakage
current)
Port other than
P50, P51, P80 to P83 Vcc
0.0 V < VI <
When the pull-up
prohibition setting
ILI
− 5
⎯
⎯
+ 5
μA
μA
Open-drain
output leakage ILIOD
current
P50, P51,
P80 to P83
0.0 V < VI <
Vss + 5.5 V
⎯
5
P10 to P14,P20 to P24,
P30 to P37, P40 to P43,
When the pull-up
permission setting
Pull-up resistor RPULL P52, P53, P70, P71,
VI = 0.0 V
25
50
100
kΩ
PE0 to PE3, PG1*2,
PG2*2
Pull-down
RMOD MOD
resistor
VI = Vcc
25
50
5
100
15
kΩ MASK ROM product
Input
Other than AVcc, AVss,
AVR, Vcc, Vss
CIN
f = 1 MHz
⎯
pF
capacitance
Flash memory product
9.5 12.5 mA (At other than writing
and erasing)
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main clock
mode
⎯
Flash memory product
mA (At writing and
erasing)
⎯
⎯
⎯
30
35
(divided by 2)
Vcc
7.2
9.5
mA MASK ROM product
Power supply
current*4
ICC (External clock
operation)
Flash memory product
15.2 20.0 mA (At other than writing
and erasing)
FCH = 32 MHz
FMP = 16 MHz
Main clock
mode
Flash memory product
35.7 42.5 mA (At writing and
erasing)
⎯
⎯
(divided by 2)
11.6 15.2 mA MASK ROM product
(Continued)
37
MB95100AM Series
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C )
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min
Typ Max
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main sleep mode
(divided by 2)
⎯
4.5
7.2
7.5
mA
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
⎯
⎯
12.0 mA
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
Dual clock
product only
ICCL
45
100
μA
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
Dual clock
product only
ICCLS
⎯
⎯
10
81
μA
μA
Vcc
(External clock
operation)
Power supply
current*4
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
Dual clock
product only
ICCT
4.6
27.0
VCC = 5.5 V
Flash memory
product
⎯
⎯
9.3
7.0
12.5 mA
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
MASK ROM
product
9.5
mA
ICCMPLL
Flash memory
product
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
⎯
⎯
14.9 20.0 mA
11.2 15.2 mA
MASK ROM
product
VCC = 5.5 V
FCL = 32 kHz
Dual clock
product only
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
ICCSPLL
⎯
160
400
μA
(Continued)
38
MB95100AM Series
(Continued)
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
VCC = 5.5 V
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
ICTS
⎯
0.15 1.10 mA
VCC
(External clock
operation)
VCC = 5.5 V
Main stop
ICCH
ILVD
ICSV
Sub stop mode
TA = + 25 °C
⎯
⎯
⎯
3.5
38
20
20
50
36
μA mode for single
clock product
Currentconsumptionfor
low voltage detection
circuit only
μA
μA
VCC
Power
At oscillating 100 kHz
current consumption of
internal CR oscillator
supply
current*4
VCC = 5.5 V
FCH = 16 MHz
At operating of A/D
conversion
IA
⎯
⎯
2.4
1
4.7
5
mA
AVcc
VCC = 5.5 V
FCH = 16 MHz
At stopping A/D
conversion
IAH
μA
TA = + 25 °C
*1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR).
*2 : Single clock products only
*3 : Product without clock supervisor only
*4 : • The power-supply current is determined by the external clock. When the low voltage detection option is
selected, the power-supply current will be a value of adding current consumption of the low voltage detection
circuit (ILVD) to the specified value. Also, when both low voltage detection option and clock supervisor are
selected, the power-supply current will be a value of adding current consumption of the low voltage detection
circuit (ILVD) and current consumption of internal CR oscillator (ICSV) to the specified value.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
39
MB95100AM Series
4. AC Characteristics
(1) Clock Timing
(Vcc = 2.42 V to 5.0 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Condi-
tions
Parameter
Pin name
Unit
16.25 MHz
Remarks
Min
Typ
Max
When using main
oscillation circuit
1.00
⎯
1.00
3.00
3.00
3.00
⎯
⎯
⎯
⎯
32.50 MHz When using external clock
10.00 MHz Main PLL multiplied by 1
8.13 MHz Main PLL multiplied by 2
6.50 MHz Main PLL multiplied by 2.5
When using sub
FCH
X0, X1
Clock frequency
⎯
⎯
32.768
32.768
⎯
⎯
⎯
kHz
oscillation circuit
FCL
X0A, X1A
X0, X1
kHz When using sub PLL
⎯
When using oscillation
circuit
61.5
1000
ns
tHCYL
Clock cycle time
30.8
⎯
1000
ns When using external clock
tLCYL X0A, X1A
⎯
30.5
⎯
μs When using sub clock
tWH1
tWL1
X0
61.5
⎯
⎯
15.2
⎯
⎯
⎯
5
ns
When using external clock
Duty ratio is about 30% to
70%.
Input clock pulse width
tWH2
X0A
tWL2
μs
Input clock rise time and
fall time
tCR
X0, X0A
tCF
⎯
ns When using external clock
40
MB95100AM Series
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
t
LCYL
t
WH2
tWL2
t
CR
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of sub clock input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0A
X1A
X0A
X1A
Open
F
CL
F
CL
41
MB95100AM Series
(2) Source Clock/Machine Clock
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym- Pin
Parameter
Unit
Remarks
bol name
Min
Typ
Max
When using main clock
Min : FCH = 16.25 MHz,
PLL multiplied by 1
Max : FCH = 1 MHz, divided by 2
When using sub clock
61.5
⎯
2000
ns
Source clock*1
(Clock before setting
division)
tSCLK
⎯
7.6
⎯
61.0
μs Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
FSP
⎯
⎯
0.50
⎯
⎯
16.25 MHz When using main clock
131.072 kHz When using sub clock
When using main clock
Source clock frequency
FSPL
16.384
61.5
7.6
⎯
⎯
32000
ns Min : FSP = 16.25 MHz, no division
Machine clock*2
(Minimum instruction
execution time)
Max : FSP = 0.5 MHz, divided by 16
tMCLK
⎯
When using sub clock
976.5
μs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
1.024
⎯
⎯
16.250 MHz When using main clock
131.072 kHz When using sub clock
Machine clock
frequency
⎯
FMPL
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
42
MB95100AM Series
• Outline of clock generation block
FCH
Divided by 2
(main oscillation)
Main PLL
× 1
× 2
× 2.5
Division
circuit
× 1
× 1/4
× 1/8
× 1/16
SCLK
( source clock )
MCLK
( machine clock )
FCL
Divided by 2
(sub oscillation)
Clock mode select bit
( SYCC : SCS1, SCS0 )
Sub PLL
× 2
× 3
× 4
43
MB95100AM Series
• Operating voltage − Operating frequency (TA = − 40 °C to + 85 °C)
• MB95F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/F108AMS/F108ANS/F108AJS/F104AMW/
MB95F104ANW/F104AJW/F106AMW/F106ANW/F106AJW/F108AMW/F108ANW/F108AJW
Main clock mode, main PLL mode
operating guarantee range
Sub PLL, Sub clock mode, watch mode,
operating guarantee range
5.5
5.5
3.5
2.42
2.42
0.5 MHz 3 MHz
10 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operating guarantee range
Main clock operating guarantee range
Source clock frequency (FSP)
PLL operating guarantee range
Source clock frequency (FSPL)
• Operating voltage − Operating frequency (TA = + 5 °C to + 35 °C)
• MB95FV100D-103
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and
watch mode operation guarantee range
5.5
5.5
3.5
2.7
2.7
0.5 MHz 3 MHz
10 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
PLL operation guarantee range
Source clock frequency (FSPL)
44
MB95100AM Series
• Main PLL operation frequency
16 MHz
15 MHz
14 MHz
13 MHz
12 MHz
11 MHz
× 2.5
10 MHz
9 MHz
× 1
× 2
8 MHz
7.5MHz
7 MHz
6 MHz
5 MHz
4 MHz
3 MHz
0 MHz
3 MHz 4 MHz 5 MHz
6.4 MHz 8 MHz
10 MHz
Main clock frequency (FMP)
45
MB95100AM Series
(3) External Reset
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Min
Parameter
Symbol
Unit
Remarks
Max
2 tMCLK*1
⎯
ns At normal operating
RST “L” level
pulse width
Oscillationtimeofoscillator*2
At stop mode, sub clock mode,
μs
tRSTL
⎯
⎯
+ 100
sub sleep mode, and watch mode
100
μs At timebase timer mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of
μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 μs
Oscillation stabilization wait time
Oscillation time
of oscillator
Execute instruction
Internal reset
46
MB95100AM Series
(4) Power-on Reset
Parameter
(AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Conditions
Unit
Remarks
Min
Max
Power supply rising time
Power supply cutoff time
tR
⎯
⎯
⎯
50
ms
ms
Waiting time until
power-on
tOFF
1
⎯
tR
tOFF
2.5 V
0.2 V
0.2 V
0.2 V
VCC
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below
.
VCC
Limiting the slope of rising within
30 mV/ms is recommended.
2.3 V
Hold condition in STOP mode
VSS
47
MB95100AM Series
(5) Peripheral Input Timing
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Unit
Min
Max
Peripheral input “H” pulse
width
INT00 to INT07,
INT10 to INT13,
EC0, EC1, TI0, TRG0/ADTG,
TRG1
tILIH
tIHIL
2 tMCLK*
⎯
ns
ns
Peripheral input “L” pulse
width
2 tMCLK*
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
tIHIL
INT00 to INT07,
INT10 to INT13, EC0, EC1,
TI0, TRG0/ADTG, TRG1
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
48
MB95100AM Series
(6) UART/SIO, Serial I/O Timing
Parameter
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
UCK ↓ → UO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
UCK0
UCK0, UO0
UCK0, UI0
UCK0, UI0
UCK0
4 tMCLK*
− 190
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal
clock
operation
+ 190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
4 tMCLK*
4 tMCLK*
⎯
UCK ↑ → valid UI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK ↓ → UO time
⎯
⎯
UCK0
⎯
External
clock
operation
UCK0, UO0
UCK0, UI0
UCK0, UI0
190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
UCK ↑ → valid UI hold time
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK0
0.8 V
0.8 V
tSLOV
UO0
2.4 V
0.8 V
tIVSH
tSHIX
UI0
• External shift clock mode
UCK0
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLSH
tSHSL
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
49
MB95100AM Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
5 tMCLK*3
− 95
Max
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
tSLOVI SCK, SOT
+ 95
tIVSHI
tSHIXI
tSLSH
tSHSL
SCK, SIN
SCK, SIN
SCK
tMCLK*3 + 190
⎯
SCK ↑ → valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSLOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSHE SCK, SIN operation output pin :
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SCK fall time
tSHIXE SCK, SIN
tMCLK*3 + 95
⎯
tF
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
50
MB95100AM Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
0.8 V
0.8 V
tSLOVI
2.4 V
0.8 V
SOT
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
SIN
• External shift clock mode
tSLSH
tSHSL
SCK
SOT
SIN
0.8 VCC
tF
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tSHIXE
tIVSHE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
51
MB95100AM Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
5 tMCLK*3
− 95
Max
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
SCK
SCK, SOT
SCK, SIN
SCK, SIN
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
+ 95
tMCLK*3 + 190
⎯
SCK ↓ → valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSHOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSLE
tSLIXE
tF
SCK, SIN operation output pin :
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SCK fall time
SCK, SIN
tMCLK*3 + 95
⎯
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
52
MB95100AM Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
2.4 V
0.8 V
tSHOVI
2.4 V
0.8 V
SOT
SIN
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
SCK
tSHSL
tSLSH
0.8 VCC
0.8 VCC
0.2 VCC
tR
0.2 VCC
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
SOT
SIN
tSLIXE
tIVSLE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
53
MB95100AM Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
− 95
+ 95
⎯
Internal clock
SCK, SIN operation output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SOT → SCK ↓ delay time
tSLIXI
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
tSOVLI
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tSLIXI
tIVSLI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
54
MB95100AM Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
− 95
+ 95
⎯
Internal clock
SCK, SIN operating output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SOT → SCK ↑ delay time
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSOVHI
tSLOVI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tIVSHI
tSHIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
55
MB95100AM Series
(8) I2C Timing
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin
name
Standard-
mode
Parameter
Symbol
Conditions
Fast-mode Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL0
0
100
0
400 kHz
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
SCL0
SDA0
tHD;STA
4.0
⎯
0.6
⎯
μs
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
SCL0
SCL0
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
μs
μs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
SCL0
SDA0
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
4.7
0
⎯
3.45*2
⎯
0.6
0
⎯
0.9*3
⎯
μs
μs
μs
μs
μs
R = 1.7 kΩ,
C = 50 pF*1
SCL0
SDA0
Data hold time SCL ↓ → SDA ↓ ↑
Data setup time SDA ↓ ↑ → SCL ↑
SCL0
SDA0
0.25
4
0.1
0.6
1.3
Stop condition setup time SCL ↑ →
SDA ↑
SCL0
SDA0
⎯
⎯
Bus free time between stop
condition and start condition
SCL0
SDA0
4.7
⎯
⎯
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
tWAKEUP
SDA0
SCL0
tHD;STA
tHD;DAT
tHIGH
tBUF
tLOW
tSU;STO
tHD;STA
tSU;DAT
tSU;STA
56
MB95100AM Series
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value*2
Sym- Pin
bol name
Parameter
Condition
Unit
Remarks
Min
Max
⎯
SCL clock “L” width
SCL clock “H” width
tLOW SCL0
tHIGH SCL0
(2 + nm / 2) tMCLK − 20
(nm / 2) tMCLK − 20
ns Master mode
(nm / 2 ) tMCLK + 20
ns Master mode
Master mode
Maximum value is
Start condition hold
time
SCL0
tHD;STA
(−1 + nm / 2) tMCLK − 20 (−1 + nm) tMCLK + 20
ns applied when m, n = 1, 8.
Otherwise, the minimum
value is applied.
SDA0
Stop condition setup
time
SCL0
tSU;STO
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode
SDA0
Start condition setup
time
SCL0
tSU;STA
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns Master mode
ns
SDA0
Busfreetimebetween
stop condition and
start condition
SCL0
tBUF
(2 nm + 4) tMCLK − 20
3 tMCLK − 20
⎯
⎯
SDA0
SCL0
tHD;DAT
Data hold time
Data setup time
ns Master mode
Master mode
SDA0
When assuming that “L”
of SCL is not extended,
the minimum value is
applied to first bit of
continuous data.
SCL0
tSU;DAT
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
ns
SDA0
R = 1.7 kΩ,
C = 50 pF*1
Otherwise,themaximum
value is applied.
Minimum value is
applied to interrupt at 9th
SCL↓.
Maximum value is
applied to interrupt at 8th
SCL↓.
Setup time between
clearing interrupt and tSU;INT SCL0
SCL rising
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
4 tMCLK − 20
4 tMCLK − 20
⎯
⎯
SCL clock “L” width
SCL clock “H” width
tLOW SCL0
tHIGH SCL0
ns At reception
ns At reception
Start condition
detection
SCL0
tHD;STA
Undetected when 1 tMCLK
is used at reception
2 tMCLK − 20
2 tMCLK − 20
⎯
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
SDA0
Stop condition
detection
SCL0
tSU;STO
Undetected when 1 tMCLK
is used at reception
SDA0
Restart detection
condition
SCL0
tSU;STA
Undetected when 1 tMCLK
is used at reception
2 tMCLK − 20
SDA0
SCL0
tBUF
Bus free time
Data hold time
Data setup time
2 tMCLK − 20
ns At reception
SDA0
SCL0
tHD;DAT
At slave transmission
mode
2 tMCLK − 20
ns
ns
SDA0
SCL0
tSU;DAT
At slave transmission
mode
tLOW − 3 tMCLK − 20
SDA0
(Continued)
57
MB95100AM Series
(Continued)
(Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value*2
Sym- Pin
Parameter
Data hold time
Condition
Unit
Remarks
bol name
Min
Max
SCL0
tHD;DAT
0
⎯
ns At reception
ns At reception
SDA0
SCL0
tSU;DAT
Data setup time
R = 1.7 kΩ,
C = 50 pF*1
tMCLK − 20
⎯
⎯
SDA0
Oscillationstabilization
wait time
SDA↓→SCL↑
(at wake-up function)
SCL0
tWAKEUP
ns
SDA0
+ 2 tMCLK − 20
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR0) .
• n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) .
• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8)
(m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4) : 3.3 MHz < tMCLK ≤ 10 MHz
: 3.3 MHz < tMCLK ≤ 4 MHz
58
MB95100AM Series
(9) Low Voltage Detection
Parameter
(AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Value
Typ
2.70
2.60
100
⎯
Symbol
Unit
Remarks
Min
2.52
2.42
70
Max
2.88
2.78
⎯
Release voltage
VDL+
VDL-
VHYS
Voff
V
V
At power-supply rise
Detection voltage
At power-supply fall
Hysteresis width
mV
V
Power-supply start voltage
Power-supply end voltage
⎯
2.3
Von
4.9
⎯
⎯
V
Slope of power supply that reset release
signal generates
0.3
⎯
⎯
3000
⎯
⎯
⎯
⎯
μs
μs
μs
Power-supply voltage
change time
(at power supply rise)
tr
Slope of power supply that reset release
signal generates within rating (VDL+)
Slope of power supply that reset
detection signal generates
300
Power-supply voltage
change time
(at power supply fall)
tf
Slope of power supply that reset
⎯
300
⎯
μs detection signal generates within rating
(VDL-)
Reset release delay time
Reset detection delay time
td1
td2
⎯
⎯
⎯
⎯
400
30
μs
μs
Current consumption for low voltage
detection circuit only
Current consumption
ILVD
⎯
38
50
μA
VCC
Von
Voff
time
tr
tf
VCC
VDL+
VDL-
VHYS
Internal reset signal
time
td1
td2
59
MB95100AM Series
(10) Clock Supervisor Clock
(Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Value
Typ
100
⎯
Parameter
Symbol
Unit
Remarks
Min
50
Max
200
10
Oscillation frequency
Oscillation start time
fOUT
twk
kHz
⎯
μs
Current consumption of built-in CR
oscillator, at oscillation of 100 kHz
Current consumption
ICSV
⎯
20
36
μA
60
MB95100AM Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Resolution
Symbol
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
bit
Total error
− 3.0
− 2.5
− 1.9
⎯
+ 3.0
+ 2.5
+ 1.9
LSB
LSB
LSB
⎯
Linearity error
⎯
Differential linear error
⎯
AVss −
AVss +
AVss +
Zero transition voltage
VOT
V
V
1.5 LSB
0.5 LSB
2.5 LSB
Full-scale transition
voltage
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR +
0.5 LSB
VFST
0.9
1.8
⎯
⎯
16500
16500
μs 4.5 V ≤ AVcc ≤ 5.5 V
μs 4.0 V ≤ AVcc < 4.5 V
Compare time
⎯
4.5 V ≤ AVcc ≤ 5.5 V,
μs At external impedance <
5.4 kΩ
0.6
1.2
⎯
⎯
∞
∞
Sampling time
⎯
4.0 V ≤ AVcc < 4.5 V,
μs At external impedance <
2.4 kΩ
Analog input current
Analog input voltage
Reference voltage
IAIN
VAIN
⎯
− 0.3
AVss
⎯
⎯
⎯
+ 0.3
AVR
μA
V
AVss + 4.0
AVcc
V
AVR pin
AVR pin,
During A/D operation
IR
⎯
⎯
600
900
5
μA
Reference voltage
supply current
AVR pin,
At stop mode
IRH
⎯
μA
61
MB95100AM Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
R
C
4.5 V ≤ AVcc ≤ 5.5 V 2.0 kΩ (Max)
4.0 V ≤ AVcc < 4.5 V 8.2 kΩ (Max)
16 pF (Max)
16 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
100
20
18
90
AVCC ≥ 4.5 V
80
16
AVCC ≥ 4.5 V
70
14
60
12
AVCC ≥ 4.0 V
AVCC ≥ 4.0 V
50
10
40
30
20
10
0
8
6
4
2
0
8
14
0
2
4
6
10
12
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
• About errors
As |AVR - AVSS| becomes smaller, values of relative errors grow larger.
62
MB95100AM Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ←
→ “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”)
compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FE
H
3FE
H
Actual conversion
characteristic
1.5 LSB
3FD
H
3FD
H
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
H
H
H
H
004
003
002
001
H
H
H
H
V
NT
V
OT
Actual conversion
characteristic
1 LSB
0.5 LSB
Ideal characteristics
AVSS
AVSS
AVR
AVR
Analog input
Analog input
Total error of
digital output N
AVR − AVss
1024
VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
1 LSB =
(V)
[LSB]
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
63
MB95100AM Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
004H
Actual conversion
characteristic
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristic
003H
Ideal
characteristics
002H
VFST
(measurement
value)
Actual conversion
characteristic
001H
Actual conversion
characteristic
VOT (measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error
Differential linear error
Actual conversion
characteristic
Ideal characteristics
3FFH
3FEH
3FDH
N+1H
NH
Actual conversion
characteristic
{1 LSB × N + VOT}
V (N+1)T
VFST
(measurement
value)
VNT
004H
003H
002H
001H
N-1H
N-2H
VNT
Actual conversion
characteristic
Actual conversion
characteristic
Ideal characteristics
VOT (measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error in
digital output N
VNT − {1 LSB × N + VOT}
V (N + 1) T − VNT
Differential linear error
in digital output N
=
=
− 1
1 LSB
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
64
MB95100AM Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2*1
0.5*2
s
s
Excludes 00H programming prior erasure.
Excludes 00H programming prior erasure.
Sector erase time
(16 Kbytes sector)
⎯
0.5*1
7.5*2
Byte programming time
Erase/program cycle
⎯
32
3,600
μs Excludes system-level overhead.
cycle
10000
⎯
⎯
Power supply voltage at erase/
program
4.5
⎯
⎯
5.5
V
Flash memory data retention
time
20*3
⎯
year Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
65
MB95100AM Series
■ MASK OPTION
MB95F104AMS MB95F104AMW
MB95F104ANS MB95F104ANW
MB95F104AJS MB95F104AJW
MB95F106AMS MB95F106AMW
MB95F106ANS MB95F106ANW MB95FV100D-103
MB95F106AJS MB95F106AJW
MB95F108AMS MB95F108AMW
MB95F108ANS MB95F108ANW
MB95F108AJS MB95F108AJW
Part number
MB95108AM
No.
Specify when
ordering
Setting
disabled
Setting
disabled
Setting
disabled
Specifying procedure
MASK
Clock mode select
• Single-system clock mode
• Dual-system clock mode
Single-system
clock mode
Dual-system
clock mode
Changing by the
switch on MCU board
1
2
3
Selectable
Low voltage detection
reset*
• With low voltage detection
reset
• Without low voltage
detection reset
Specify when
ordering MASK
Specified by
part number
Specified by
part number
Changing by the
switch on MCU board
Clock supervisor*
• With clock supervisor
• Without clock supervisor
Specify when
ordering MASK
Specified by
part number
Specified by
part number
Changing by the
switch on MCU board
MCU board switch set
as following ;
Reset output*
• With reset output
• Without reset output
• With supervisor :
Specify when
ordering MASK
Specified by
part number
Specified by
part number
4
Without reset
output
• Without supervisor :
With reset output
Fixed to
oscillation
Fixed to
oscillation
Fixed to
oscillation
Fixed to
oscillation
Oscillation stabilization
wait time
5
stabilization wait stabilizationwait stabilization wait
stabilization wait
time of
time of
time of
time of
(214-2) /FCH
(214-2) /FCH
(214-2) /FCH
(214-2) /FCH
* : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output.
66
MB95100AM Series
Low voltage detection
reset
Part number
Clock mode select
Clock supervisor
Reset output
No
Yes
Yes
No
No
No
Yes
Yes
No
Single-system
Yes
No
MB95108AM
Yes
Yes
No
Dual-system
Yes
Yes
No
No
Yes
No
MB95F104AMS
MB95F104ANS
MB95F104AJS
MB95F106AMS
MB95F106ANS
MB95F106AJS
MB95F108AMS
MB95F108ANS
MB95F108AJS
MB95F104AMW
MB95F104ANW
MB95F104AJW
MB95F106AMW
MB95F106ANW
MB95F106AJW
MB95F108AMW
MB95F108ANW
MB95F108AJW
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Single-system
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Dual-system
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
Single-system
Dual-system
Yes
Yes
No
No
Yes
No
MB95FV100D-103
Yes
Yes
No
Yes
Yes
No
Yes
67
MB95100AM Series
■ ORDERING INFORMATION
Part number
Package
MB95108AMPFV
MB95F104AMSPFV/F104ANSPFV/F104AJSPFV
MB95F104AMWPFV/F104ANWPFV/F104AJWPFV
MB95F106AMSPFV/F106ANSPFV/F106AJSPFV
MB95F106AMWPFV/F106ANWPFV/F106AJWPFV
MB95F108AMSPFV/F108ANSPFV/F108AJSPFV
MB95F108AMWPFV/F108ANWPFV/F108AJWPFV
64-pin plastic LQFP
(FPT-64P-M03)
MB95108AMPFM
MB95F104AMSPFM/F104ANSPFM/F104AJSPFM
MB95F104AMWPFM/F104ANWPFM/F104AJWPFM
MB95F106AMSPFM/F106ANSPFM/F106AJSPFM
MB95F106AMWPFM/F106ANWPFM/F106AJWPFM
MB95F108AMSPFM/F108ANSPFM/F108AJSPFM
MB95F108AMWPFM/F108ANWPFM/F108AJWPFM
64-pin plastic LQFP
(FPT-64P-M09)
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
MB2146-303
(MB95FV100D-103PBT)
(
)
68
MB95100AM Series
■ PACKAGE DIMENSIONS
64-pin plastic LQFP
Lead pitch
0.50 mm
10.0 × 10.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.32g
Code
(Reference)
(FPT-64P-M03)
P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M03)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00 0.20(.472 .008)SQ
*
10.00 0.10(.394 .004)SQ
0.145 0.055
(.006 .002)
48
33
49
32
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 –+..000048
INDEX
0.10 0.10
(.004 .004)
(Stand off)
0˚~8˚
64
17
"A"
0.25(.010)
0.50 0.20
(.020 .008)
1
16
LEAD No.
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
(.008 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2003 FUJITSU LIMITED F64009S-c-5-8
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
69
MB95100AM Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.65 mm
12 × 12 mm
Package width ×
package length
Lead shape
Sealing method
Mounting height
Gullwing
Plastic mold
1.70 mm MAX
P-LQFP64-12×12-0.65
Code
(Reference)
(FPT-64P-M09)
64-pin plastic LQFP
(FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00 0.20(.551 .008)SQ
*
12.00 0.10(.472 .004)SQ
0.145 0.055
(.0057 .0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
0.25(.010)
INDEX
0~8
˚
64
17
0.50 0.20
(.020 .008)
0.10 0.10
(.004 .004)
(Stand off)
"A"
1
16
0.60 0.15
(.024 .006)
0.65(.026)
0.32 0.05
(.013 .002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F64018S-c-3-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
70
MB95100AM Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Added the part numbers.
( MB95F104AJS/MB95F104AJW
MB95F106AJS/MB95F106AJW
MB95F108AJS/MB95F108AJW)
⎯
⎯
Added the description "Clock supervisor" in the
section "Option".
4
■ PRODUCT LINEUP
■ PROGRAMMING FLASH MEMORY
18
31
MICROCONTROLLERS USING PARALLEL Inserted "• Programming Method".
PROGRAMMER
■ I/O MAP
Added the address 0FEAH.
"Verified the Min value in the section of "Other
than MB95FV100D-103", "In normal operating"
of "Power supply voltage";
2.45 → 2.42.
35
2. Recommended Operating Conditions
Verified the value in *1;
2.9 V → 2.88 V.
Moved “H” level input voltage and “L” level input
voltage to the section "3. DC Characteristics".
Added the pin name at the "Pin name" in the
section of VIHA, “H” level input voltage.
36
39
Added the pin name at the "Pin name" in the
section of VILA, “L” level input voltage.
3. DC Characteristics
Deleted the line of "FCH = 16 MHz" in the section
"ICTS" of Power supply current.
Changed in the table;
VCC = 2.5 V to 5.5 V → VCC = 2.42 V to 5.5 V.
4. AC Characteristics
(1) Clock Timing
40
45
Changed the Max value on the third column of
the clock frequency;
16.25 → 10.00
4. AC Characteristics
(2) Source Clock/Machine Clock
Verified the diagram of Main PLL operation
frequency range.
Changed the release voltage:
2.55 → 2.52 (Min value)
2.85 → 2.88 (Max value)
59
(9) Low Voltage Detection
Changed the detection voltage:
2.45 → 2.42 (Min value)
2.75 → 2.78 (Max value)
71
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.
相关型号:
©2020 ICPDF网 联系我们和版权申明