MB96F315YWAPMC-GSE2 [CYPRESS]
RISC Microcontroller, CMOS, PQFP48, 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48;
| 型号： | MB96F315YWAPMC-GSE2 |
| 厂家： | 
CYPRESS |
| 描述： | RISC Microcontroller, CMOS, PQFP48, 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48 微控制器 |
| 文件： | 总74页 (文件大小：2025K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
FME-MB96310 rev 2
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96310 Series
MB96F313/F315 *1
■ DESCRIPTION
MB96310 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller
For the information for microcontroller support, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.1
MB96310 Series
■ FEATURES
Feature
Description
Technology
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 56 MHz internal, 17.8 ns instruction cycle time
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
CPU
• 8-byte instruction execution queue
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
• 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using
ceramic resonator depends on Q-factor).
• Up to 56 MHz external clock
• 32-100 kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection,
watchdog
System clock
• Clock source selectable from main- and subclock oscillator (part number suffix “W”)
and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
and low power consumption figures
On-chip voltage regula-
tor
Low voltage reset
Code Security
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
• Replaces ROM content
Memory Patch Function
DMA
• Can also be used to implement embedded debug support
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
Interrupts
Timers
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
2
FME-MB96310 rev 2
MB96310 Series
Feature
Description
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• SAR-type
USART
• 10-bit resolution
A/D converter
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
• 16-bit wide
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
• Event count function
Reload Timers
Free Running Timers
Input Capture Units
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of
peripheral clock frequency
• 16-bit wide
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
• 16-bit wide
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
• PWM operation and one-shot operation
Programmable Pulse
Generator
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer overflow as clock input
• Can be triggered by software or reload timer
FME-MB96310 rev 2
3
MB96310 Series
Feature
Description
• Can be clocked either from sub oscillator (devices with part number suffix “W”), main
oscillator or from the RC oscillator
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
Real Time Clock
• Read/write accessible second/minute/hour registers
• Can signal interrupts every half second/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock
• Edge sensitive or level sensitive
• Interrupt mask and pending bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
External Interrupts
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
Non Maskable Interrupt
• Pin shared with external interrupt 0.
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs
• Bit-wise programmable as input/output or peripheral signal
• Bit-wise programmable input enable
I/O Ports
• Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL
• Bit-wise programmable pull-up resistor
• Bit-wise programmable output driving strength for EMI optimization
• 48-pin plastic LQFP M26
Packages
• Supports automatic programming, Embedded Algorithm
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles: 10,000 times
Flash Memory
• Data retention time: 20 years
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash
• Low voltage detection during Flash erase
4
FME-MB96310 rev 2
MB96310 Series
■ PRODUCT LINEUP
Features
MB96V300B
Evaluation sample
MB96(F)31x
Flash product: MB96F31x
Mask ROM product: MB9631x
Product type
Product options
YS
RS
YW
RW
AS
Low voltage reset persistently on / Single clock devices
Low voltage reset can be disabled / Single clock devices
Low voltage reset persistently on / Dual clock devices
NA
Low voltage reset can be disabled / Dual clock devices
No CAN / Low voltage reset can be disabled / Single clock devices
No CAN / Low voltage reset can be disabled / Dual clock devices
AW
Flash/
ROM
RAM
8KB
ROM/Flash
96KB
MB96F313Y, MB96F313R, MB96F313A *1
MB96F315Y, MB96F315R, MB96F315A *1
memory emulation
by external RAM,
92KB internal RAM
160KB
8KB
Package
BGA416
FPT-48P-M26
4 channels
3 channels
12 channels
DMA
16 channels
10 channels
40 channels
USART
A/D Converter
A/D Converter Reference
Voltage switch
yes
No
6 channels + 1
channel (for PPG)
16-bit Reload Timer
4 channels + 1 channel (for PPG)
4 channels (without external clock input pin)
16-bit Free-Running
Timer
4 channels
16-bit Output Compare
16-bit Input Capture
12 channels
12 channels
2 channels
4 channels (plus 3 channels for LIN USART)
16-bit Programmable
Pulse Generator
20 channels
14 channels
CAN Interface
External Interrupts
Non-Maskable Interrupt
Real Time Clock
I/O Ports
5 channels
1 channel
16 channels
11 channels
1 channel
1
136
34 for part number with suffix "W", 36 for part number with suffix "S"
FME-MB96310 rev 2
5
MB96310 Series
Features
MB96V300B
MB96(F)31x
Clock output function
Low voltage reset
2 channels
Yes
On-chip RC-oscillator
Yes
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
6
FME-MB96310 rev 2
MB96310 Series
■ BLOCK DIAGRAM
Block diagram of MB96(F)31x
CKOT0_R, CKOT1, CKOT1_R
CKOTX1
X0, X1
X0A, X1A *1
RSTX
MD0...MD2
NMI
Clock &
Mode Controller
Interrupt
Controller
Flash
Memory A
Memory Patch
Unit
16FX
CPU
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Controller
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
RAM
Boot ROM
AVCC
VCC
VSS
C
AVSS
AVRH
AN0, AN1, AN3, AN4
AN6 ... AN10
AN12, AN14, AN16
ADTG_R
10-bit ADC
12 ch.
CAN
Interface
1 ch.
TX2
RX2
TIN1
TOT0_R, TOT2_R
TOT1, TOT3
SIN2, SIN2_R, SIN7_R, SIN8_R
SOT2, SOT2_R, SOT7_R, SOT8_R
SCK2, SCK2_R, SCK7_R, SCK8_R
16-bit Reload
Timer
USART
3 ch.
4 ch.
TTG0, TTG1, TTG4, TTG8, TTG9, TTG12
TTG8_R, TTG9_R, TTG16_R, TTG17_R
PPG0, PPG1, PPG3, PPG4
I/O Timer 0
ICU 0/1
16-bit PPG
14 ch.
IN0, IN1
PPG6, PPG7, PPG12, PPG14
PPG8_R, PPG9_R, PPG16_R ... PPG19_R
RLT6
I/O Timer 1
ICU 4/5/6
OCU 6/7
IN4, IN5
OUT6, OUT7
Real Time
Clock
I/O Timer 2
ICU 9
INT0, INT8 ... INT13
INT2_R, INT4_R
INT7_R, INT10_R
INT3_R1
External
Interrupt
I/O Timer 3
ICU 10
*1: X0A, X1A only available on devices with suffix “W”
FME-MB96310 rev 2
7
MB96310 Series
■ PIN ASSIGNMENTS
Pin assignment of MB96(F)31x
36 34 34 33 32 31 30 29 28 27 26 25
P01_0 / CKOT1 / TIN1 / TTG16_R
P00_3 / INT11 / SCK8_R
P00_5/ INT13 / SIN8_R / PPG9_R
P00_4 / INT12 / SOT8_R / PPG8_R
P00_2 / INT10 / SIN7_R
P00_1 / INT9 / SOT7_R / TTG9_R
P00_0 / INT8 / SCK7_R / TTG8_R
MD0
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
C
37
38
39
40
41
42
43
44
45
46
47
48
P02_5 / IN1 / TTG1 / TTG9 / ADTG_R
P03_0 / IN4 / TTG4 / TTG12 / TOT0_R
P03_1 / IN5 / TOT2_R
P03_2 / INT10_R / RX2
P03_3 / TX2
LQFP - 48
Package code (mold)
FPT-48P-M26
P03_6 / OUT6
P03_7 / OUT7
MD1
P06_0 / AN0 / PPG0
P06_1 /AN1 / PPG1
AVcc
MD2
X1A / P04_1*1
X0A / P04_0*1
1
2
3
4
5
6
7
8
9 10 11 12
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
(FPT-48P-M26)
8
FME-MB96310 rev 2
MB96310 Series
■ PIN FUNCTION DESCRIPTION
Pin Function description (1 of 2)
Pin name
Feature
Description
ADTG_R
ANn
ADC
ADC
Relocated A/D converter trigger input
A/D converter channel n input
AVCC
Supply
Analog circuits power supply
AVRH
AVSS
ADC
A/D converter high reference voltage input
Analog circuits power supply
Supply
C
Voltage regulator
Clock output function
Clock output function
Clock output function
ICU
Internally regulated power supply stabilization capacitor pin
Clock Output function n output
CKOTn
CKOTn_R
CKOTXn
INn
Relocated Clock Output function n output
Clock Output function n inverted output
Input Capture Unit n input
INTn
External Interrupt
External Interrupt
Core
External Interrupt n input
INTn_R
MDn
Relocated External Interrupt n input
Input pins for specifying the operating mode.
Non-Maskable Interrupt input
NMI
External Interrupt
OCU
OUTn
Pxx_n
PPGn
PPGn_R
RSTX
RXn
Output Compare Unit n waveform output
General purpose IO
GPIO
PPG
Programmable Pulse Generator n output
Relocated Programmable Pulse Generator n output
Reset input
PPG
Core
CAN
CAN interface n RX input
SCKn
SCKn_R
SINn
USART
USART n serial clock input/output
Relocated USART n serial clock input/output
USART n serial data input
USART
USART
SINn_R
SOTn
SOTn_R
TINn
USART
Relocated USART n serial data input
USART n serial data output
USART
USART
Relocated USART n serial data output
Reload Timer n event input
Reload Timer
Reload Timer
Reload Timer
TINn_R
TOTn
Relocated Reload Timer n event input
Reload Timer n output
FME-MB96310 rev 2
9
MB96310 Series
Pin Function description (2 of 2)
Pin name
Feature
Description
TOTn_R
TTGn
TTGn_R
TXn
Reload Timer
PPG
Relocated Reload Timer n output
Programmable Pulse Generator n trigger input
Relocated Programmable Pulse Generator n trigger input
CAN interface n TX output
PPG
CAN
VCC
Supply
Supply
Clock
Power supply
VSS
Power supply
X0
Oscillator input
X0A
Clock
Subclock Oscillator input (only for devices with suffix "W")
Oscillator output
X1
Clock
X1A
Clock
Subclock Oscillator output (only for devices with suffix "W")
10
FME-MB96310 rev 2
MB96310 Series
■ PIN CIRCUIT TYPE
Pin circuit types
FPT-48P-M26
Circuit
Pin no.
type *1
1
2
Supply
G
I
3 to 12
B *2
13, 14
13, 14
15 to 17
18 to 32
33
H *3
C
H
E
34, 35
36, 37
38
A
Supply
F
39 to 45
46, 47
48
H
I
Supply
*1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types
*2: Devices with suffix ”W”
*3: Devices without suffix ”W”
FME-MB96310 rev 2
11
MB96310 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
High-speed oscillation circuit:
• Programmable between oscillation mode (ex-
ternal crystal or resonator connected to X0/X1
pins) and Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 MΩ. Feedback resistor is grounded in
the center when the oscillator is disabled or in
FCI mode
X1
R
0
1
Xout
MRFBE
FCI
R
X0
FCI or osc disable
B
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
2 * 5 MΩ. Feedback resistor is grounded in the
center when the oscillator is disabled
Xout
X1A
R
SRFBE
R
X0A
osc disable
C
E
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
R
Hysteresis
inputs
CMOS input pin
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
Hysteresis
inputs
12
FME-MB96310 rev 2
MB96310 Series
Type
Circuit
Remarks
F
• Power supply input protection circuit
G
• A/D converter ref+ (AVRH) power supply input
pin with protection circuit
ANE
AVR
• Flash devices do not have a protection circuit
against VCC for pin AVRH
ANE
H
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• CMOS hysteresis input with input shutdown
function
• Automotive input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
pull-up control
Pout
Nout
R
Hysteresis input
Automotive input
Standby control
for input shutdown
Standby control
for input shutdown
I
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• CMOS hysteresis input with input shutdown
function
Pull-up control
Pout
Nout
• Automotive input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
R
Hysteresis input
Standby control
for input shutdown
Automotive input
Analog input
Standby control
for input shutdown
FME-MB96310 rev 2
13
MB96310 Series
■ MEMORY MAP
MB96V300B
MB96(F)31x
FF:FFFFH
DE:0000H
USER ROM /
Emulation ROM
*4
Reserved
External Bus
Reserved
Boot-ROM
10:0000H
0F:E000H
Boot-ROM
Reserved
0E:0000H
02:0000H
External RAM
Reserved
Internal RAM
bank 1
01:0000H
00:8000H
ROM/RAM MIRROR
ROM/RAM MIRROR
Internal RAM
bank 0
RAMSTART0*2
Internal RAM
bank 0
Reserved
RAMSTART0*3
00:0C00H
External Bus
Peripherals
Peripherals
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
GPR*1
DMA
GPR*1
DMA
External Bus
Peripheral
Reserved
Peripheral
*1: Unused GPR banks can be used as RAM area
*2: For RAMSTART0 addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, see the ■ USER ROM MEMORY MAP FOR FLASH DEVICES on the
following pages.
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
14
FME-MB96310 rev 2
MB96310 Series
■ RAMSTART ADDRESSES
Devices
RAM size
RAMSTART0
MB96F313/F315
8KByte
00:6240H
FME-MB96310 rev 2
15
MB96310 Series
■ USER ROM MEMORY MAP FOR FLASH DEVICES
MB96F313
MB96F315
Flash size
96kByte
Flash size
160kByte
Alternative mode Flash memory
CPU address
mode address
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
S39 - 64K
S39 - 64K
S38 - 64K
Flash A
Reserved
Reserved
E0:0000H
DF:FFFFH
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
Flash A
Reserved
Reserved
DE:0000H
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
16
FME-MB96310 rev 2
MB96310 Series
■ SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010)
MB96F35x
Pin number
Normal function
USART Number
LQFP-64
9
SIN2
10
11
26
25
24
29
28
27
USART2
USART7
USART8
SOT2
SCK2
SIN7_R
SOT7_R
SCK7_R
SIN8_R
SOT8_R
SCK8_R
Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor
to support at least port P00_1 on pin 19.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the
customer to check the tool manual or to contact the tool vendor for alternative handshaking pins.
FME-MB96310 rev 2
17
MB96310 Series
■ I/O MAP
I/O map MB96(F)315x (1 of 22)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
Access
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
I/O Port P00 - Port Data Register
I/O Port P01 - Port Data Register
I/O Port P02 - Port Data Register
I/O Port P03 - Port Data Register
Reserved
PDR00
PDR01
PDR02
PDR03
R/W
R/W
R/W
R/W
-
I/O Port P05 - Port Data Register
I/O Port P06 - Port Data Register
I/O Port P07 - Port Data Register
PDR05
PDR06
PDR07
R/W
R/W
R/W
000008H-
000017H
Reserved
-
000018H
000019H
00001AH
00001BH
00001CH
00001DH
00001EH
00001FH
000020H
000021H
ADC0 - Control Status register Low
ADC0 - Control Status register High
ADC0 - Data Register Low
ADCSL
ADCSH
ADCRL
ADCRH
ADCS
ADCR
ADSR
R/W
R/W
R
ADC0 - Data Register High
R
ADC0 - Setting Register
R/W
R/W
R/W
-
ADC0 - Setting Register
ADC0 - Extended Configuration Register
Reserved
ADECR
FRT0 - Data register of free-running timer
FRT0 - Data register of free-running timer
TCDT0
TCCS0
R/W
R/W
FRT0 - Control status register of free-running timer
Low
000022H
000023H
TCCSL0
TCCSH0
R/W
R/W
FRT0 - Control status register of free-running timer
High
000024H
000025H
FRT1 - Data register of free-running timer
FRT1 - Data register of free-running timer
TCDT1
TCCS1
R/W
R/W
FRT1 - Control status register of free-running timer
Low
000026H
000027H
TCCSL1
TCCSH1
R/W
R/W
FRT1 - Control status register of free-running timer
High
18
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (2 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000028H-
Reserved
000039H
-
00003AH
00003BH
00003CH
00003DH
00003EH
00003FH
000040H
000041H
000042H
000043H
000044H
000045H
OCU6 - Output Compare Control Status
OCU7 - Output Compare Control Status
OCU6 - Compare Register
OCS6
OCS7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
OCCP6
OCCP7
OCU6 - Compare Register
OCU7 - Compare Register
OCU7 - Compare Register
ICU0/ICU1 - Control Status Register
ICU0/ICU1 - Edge register
ICS01
ICE01
ICU0 - Capture Register Low
ICU0 - Capture Register High
ICU1 - Capture Register Low
ICU1 - Capture Register High
IPCPL0
IPCPH0
IPCPL1
IPCPH1
IPCP0
IPCP1
R
R
R
000046H -
00004BH
Reserved
-
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
ICU4/ICU5 - Control Status Register
ICU4/ICU5 - Edge register
ICS45
ICE45
R/W
R/W
R
ICU4 - Capture Register Low
ICU4 - Capture Register High
ICU5 - Capture Register Low
ICU5 - Capture Register High
ICU6/ICU7 - Control Status Register
ICU6/ICU7 - Edge register
IPCPL4
IPCPH4
IPCPL5
IPCPH5
ICS67
IPCP4
IPCP5
R
R
R
R/W
R/W
R
ICE67
ICU6 - Capture Register Low
ICU6 - Capture Register High
ICU7 - Capture Register Low
ICU7 - Capture Register High
EXTINT0 - External Interrupt Enable Register
IPCPL6
IPCPH6
IPCPL7
IPCPH7
ENIR0
IPCP6
IPCP7
R
R
R
R/W
EXTINT0 - External Interrupt Interrupt request Reg-
ister
000059H
EIRR0
R/W
FME-MB96310 rev 2
19
MB96310 Series
I/O map MB96(F)315x (3 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00005AH
00005BH
00005CH
EXTINT0 - External Interrupt Level Select Low
EXTINT0 - External Interrupt Level Select High
EXTINT1 - External Interrupt Enable Register
ELVRL0
ELVRH0
ENIR1
ELVR0
R/W
R/W
R/W
EXTINT1 - External Interrupt Interrupt request Reg-
ister
00005DH
EIRR1
R/W
00005EH
00005FH
000060H
000061H
000062H
000062H
000063H
000063H
000064H
000065H
000066H
000066H
000067H
000067H
000068H
000069H
00006AH
00006AH
00006BH
00006BH
00006CH
00006DH
00006EH
00006EH
00006FH
EXTINT1 - External Interrupt Level Select Low
EXTINT1 - External Interrupt Level Select High
RLT0 - Timer Control Status Register Low
RLT0 - Timer Control Status Register High
RLT0 - Reload Register - for writing
RLT0 - Reload Register - for reading
RLT0 - Reload Register - for writing
RLT0 - Reload Register - for reading
RLT1 - Timer Control Status Register Low
RLT1 - Timer Control Status Register High
RLT1 - Reload Register - for writing
RLT1 - Reload Register - for reading
RLT1 - Reload Register - for writing
RLT1 - Reload Register - for reading
RLT2 - Timer Control Status Register Low
RLT2 - Timer Control Status Register High
RLT2 - Reload Register - for writing
RLT2 - Reload Register - for reading
RLT2 - Reload Register - for writing
RLT2 - Reload Register - for reading
RLT3 - Timer Control Status Register Low
RLT3 - Timer Control Status Register High
RLT3 - Reload Register - for writing
RLT3 - Reload Register - for reading
RLT3 - Reload Register - for writing
ELVRL1
ELVRH1
ELVR1
R/W
R/W
R/W
R/W
W
TMCSRL0
TMCSRH0
TMCSR0
TMRLR0
TMR0
R
W
R
TMCSRL1
TMCSRH1
TMCSR1
R/W
R/W
W
TMRLR1
TMR1
R
W
R
TMCSRL2
TMCSRH2
TMCSR2
R/W
R/W
W
TMRLR2
TMR2
R
W
R
TMCSRL3
TMCSRH3
TMCSR3
R/W
R/W
W
TMRLR3
TMR3
R
W
20
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (4 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
R
00006FH
000070H
RLT3 - Reload Register - for reading
RLT6 - Timer Control Status Register Low (dedic.
RLT for PPG)
TMCSRL6
TMCSRH6
TMCSR6
R/W
RLT6 - Timer Control Status Register High (dedic.
RLT for PPG)
000071H
000072H
000072H
000073H
000073H
R/W
W
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
TMRLR6
TMR6
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
R
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
W
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
R
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
000083H
000084H
000085H
000086H
PPG3-PPG0 - General Control register 1 Low
PPG3-PPG0 - General Control register 1 High
PPG3-PPG0 - General Control register 2 Low
PPG3-PPG0 - General Control register 2 High
PPG0 - Timer register
GCN1L0
GCN1H0
GCN2L0
GCN2H0
GCN10
GCN20
PTMR0
PCSR0
PDUT0
PCN0
R/W
R/W
R/W
R/W
R
PPG0 - Timer register
R
PPG0 - Period setting register
PPG0 - Period setting register
PPG0 - Duty cycle register
W
W
W
PPG0 - Duty cycle register
W
PPG0 - Control status register Low
PPG0 - Control status register High
PPG1 - Timer register
PCNL0
PCNH0
R/W
R/W
R
PTMR1
PCSR1
PDUT1
PCN1
PPG1 - Timer register
R
PPG1 - Period setting register
PPG1 - Period setting register
PPG1 - Duty cycle register
W
W
W
PPG1 - Duty cycle register
W
PPG1 - Control status register Low
PCNL1
R/W
FME-MB96310 rev 2
21
MB96310 Series
I/O map MB96(F)315x (5 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000087H
PPG1 - Control status register High
Reserved
PCNH1
R/W
-
000088H-
00008FH
000090H
000091H
000092H
000093H
000094H
000095H
000096H
000097H
000098H
000099H
00009AH
00009BH
00009CH
00009DH
00009EH
00009FH
0000A0H
0000A1H
0000A2H
0000A3H
PPG3 - Timer register
PTMR3
PCSR3
PDUT3
PCN3
R
R
PPG3 - Timer register
PPG3 - Period setting register
PPG3 - Period setting register
PPG3 - Duty cycle register
W
W
W
PPG3 - Duty cycle register
W
PPG3 - Control status register Low
PPG3 - Control status register High
PPG7-PPG4 - General Control register 1 Low
PPG7-PPG4 - General Control register 1 High
PPG7-PPG4 - General Control register 2 Low
PPG7-PPG4 - General Control register 2 High
PPG4 - Timer register
PCNL3
PCNH3
R/W
R/W
R/W
R/W
R/W
R/W
R
GCN1L1
GCN1H1
GCN2L1
GCN2H1
GCN11
GCN21
PTMR4
PCSR4
PDUT4
PCN4
PPG4 - Timer register
R
PPG4 - Period setting register
PPG4 - Period setting register
PPG4 - Duty cycle register
W
W
W
PPG4 - Duty cycle register
W
PPG4 - Control status register Low
PPG4 - Control status register High
PCNL4
PCNH4
R/W
R/W
0000A4H-
0000D3H
Reserved
-
0000D4H
0000D5H
0000D6H
0000D6H
0000D7H
0000D8H
USART2 - Serial Mode Register
USART2 - Serial Control Register
USART2 - TX Register
SMR2
SCR2
TDR2
RDR2
SSR2
ECCR2
R/W
R/W
W
USART2 - RX Register
R
USART2 - Serial Status
R/W
R/W
USART2 - Control/Com. Register
22
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (6 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0000D9H
0000DAH
0000DBH
0000DCH
USART2 - Ext. Status Register
ESCR2
BGRL2
BGRH2
ESIR2
R/W
R/W
R/W
R/W
USART2 - Baud Rate Generator Register Low
USART2 - Baud Rate Generator Register High
USART2 - Extended Serial Interrupt Register
BGR2
0000DDH-
0000FFH
Reserved
-
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000108H
000109H
00010AH
00010BH
00010CH
00010DH
00010EH
00010FH
000110H
000111H
000112H
000113H
000114H
000115H
000116H
000117H
DMA0 - Buffer address pointer low byte
DMA0 - Buffer address pointer middle byte
DMA0 - Buffer address pointer high byte
DMA0 - DMA control register
BAPL0
BAPM0
BAPH0
DMACS0
IOAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA0 - I/O register address pointer low byte
DMA0 - I/O register address pointer high byte
DMA0 - Data counter low byte
IOA0
IOAH0
DCTL0
DCTH0
BAPL1
BAPM1
BAPH1
DMACS1
IOAL1
DCT0
DMA0 - Data counter high byte
DMA1 - Buffer address pointer low byte
DMA1 - Buffer address pointer middle byte
DMA1 - Buffer address pointer high byte
DMA1 - DMA control register
DMA1 - I/O register address pointer low byte
DMA1 - I/O register address pointer high byte
DMA1 - Data counter low byte
IOA1
IOAH1
DCTL1
DCTH1
BAPL2
BAPM2
BAPH2
DMACS2
IOAL2
DCT1
DMA1 - Data counter high byte
DMA2 - Buffer address pointer low byte
DMA2 - Buffer address pointer middle byte
DMA2 - Buffer address pointer high byte
DMA2 - DMA control register
DMA2 - I/O register address pointer low byte
DMA2 - I/O register address pointer high byte
DMA2 - Data counter low byte
IOA2
IOAH2
DCTL2
DCTH2
DCT2
DMA2 - Data counter high byte
FME-MB96310 rev 2
23
MB96310 Series
I/O map MB96(F)315x (7 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000118H
000119H
00011AH
00011BH
00011CH
00011DH
00011EH
00011FH
DMA3 - Buffer address pointer low byte
DMA3 - Buffer address pointer middle byte
DMA3 - Buffer address pointer high byte
DMA3 - DMA control register
BAPL3
BAPM3
BAPH3
DMACS3
IOAL3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA3 - I/O register address pointer low byte
DMA3 - I/O register address pointer high byte
DMA3 - Data counter low byte
IOA3
IOAH3
DCTL3
DCTH3
DCT3
DMA3 - Data counter high byte
000120H-
00017FH
Reserved
-
000180H-
00037FH
CPU - General Purpose registers (RAM access)
GPR_RAM
R/W
000380H
000381H
000382H
000383H
DMA0 - Interrupt select
DMA1 - Interrupt select
DMA2 - Interrupt select
DMA3 - Interrupt select
DISEL0
DISEL1
DISEL2
DISEL3
R/W
R/W
R/W
R/W
000384H-
00038FH
Reserved
-
000390H
000391H
000392H
000393H
000394H
000395H
DMA - Status register low byte
DMA - Status register high byte
DMA - Stop status register low byte
DMA - Stop status register high byte
DMA - Enable register low byte
DMA - Enable register high byte
DSRL
DSRH
DSSRL
DSSRH
DERL
DSR
DSSR
DER
R/W
R/W
R/W
R/W
R/W
R/W
DERH
000396H-
00039FH
Reserved
-
0003A0H
0003A1H
0003A2H
0003A3H
0003A4H
Interrupt level register
ILR
IDX
ICR
R/W
R/W
R/W
R/W
R/W
Interrupt index register
Interrupt vector table base register Low
Interrupt vector table base register High
Delayed Interrupt register
TBRL
TBRH
DIRR
TBR
24
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (8 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003A5H
Non Maskable Interrupt register
Reserved
NMI
R/W
-
0003A6H-
0003ABH
0003ACH
0003ADH
0003AEH
0003AFH
0003B0H
0003B1H
0003B2H
0003B3H
0003B4H
0003B5H
0003B6H
0003B7H
0003B8H
0003B9H
0003BAH
0003BBH
0003BCH
0003BDH
0003BEH
0003BFH
0003C0H
0003C1H
0003C2H
0003C3H
0003C4H
0003C5H
0003C6H
EDSU communication interrupt selection Low
EDSU communication interrupt selection High
ROM mirror control register
EDSU2L
EDSU2H
ROMM
EDSU2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EDSU configuration register
EDSU
Memory patch control/status register ch 0/1
Memory patch control/status register ch 0/1
Memory patch control/status register ch 2/3
Memory patch control/status register ch 2/3
Memory patch control/status register ch 4/5
Memory patch control/status register ch 4/5
Memory patch control/status register ch 6/7
Memory patch control/status register ch 6/7
Memory Patch function - Patch address 0 low
Memory Patch function - Patch address 0 middle
Memory Patch function - Patch address 0 high
Memory Patch function - Patch address 1 low
Memory Patch function - Patch address 1 middle
Memory Patch function - Patch address 1 high
Memory Patch function - Patch address 2 low
Memory Patch function - Patch address 2 middle
Memory Patch function - Patch address 2 high
Memory Patch function - Patch address 3 low
Memory Patch function - Patch address 3 middle
Memory Patch function - Patch address 3 high
Memory Patch function - Patch address 4 low
Memory Patch function - Patch address 4 middle
Memory Patch function - Patch address 4 high
PFCS0
PFCS1
PFCS2
PFCS3
PFAL0
PFAM0
PFAH0
PFAL1
PFAM1
PFAH1
PFAL2
PFAM2
PFAH2
PFAL3
PFAM3
PFAH3
PFAL4
PFAM4
PFAH4
FME-MB96310 rev 2
25
MB96310 Series
I/O map MB96(F)315x (9 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003C7H
0003C8H
0003C9H
0003CAH
0003CBH
0003CCH
0003CDH
0003CEH
0003CFH
0003D0H
0003D1H
0003D2H
0003D3H
0003D4H
0003D5H
0003D6H
0003D7H
0003D8H
0003D9H
0003DAH
0003DBH
0003DCH
0003DDH
0003DEH
0003DFH
Memory Patch function - Patch address 5 low
Memory Patch function - Patch address 5 middle
Memory Patch function - Patch address 5 high
Memory Patch function - Patch address 6 low
Memory Patch function - Patch address 6 middle
Memory Patch function - Patch address 6 high
Memory Patch function - Patch address 7 low
Memory Patch function - Patch address 7 middle
Memory Patch function - Patch address 7 high
Memory Patch function - Patch data 0 Low
Memory Patch function - Patch data 0 High
Memory Patch function - Patch data 1 Low
Memory Patch function - Patch data 1 High
Memory Patch function - Patch data 2 Low
Memory Patch function - Patch data 2 High
Memory Patch function - Patch data 3 Low
Memory Patch function - Patch data 3 High
Memory Patch function - Patch data 4 Low
Memory Patch function - Patch data 4 High
Memory Patch function - Patch data 5 Low
Memory Patch function - Patch data 5 High
Memory Patch function - Patch data 6 Low
Memory Patch function - Patch data 6 High
Memory Patch function - Patch data 7 Low
Memory Patch function - Patch data 7 High
PFAL5
PFAM5
PFAH5
PFAL6
PFAM6
PFAH6
PFAL7
PFAM7
PFAH7
PFDL0
PFDH0
PFDL1
PFDH1
PFDL2
PFDH2
PFDL3
PFDH3
PFDL4
PFDH4
PFDL5
PFDH5
PFDL6
PFDH6
PFDL7
PFDH7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFD0
PFD1
PFD2
PFD3
PFD4
PFD5
PFD6
PFD7
0003E0H-
0003F0H
Reserved
-
0003F1H
0003F2H
0003F3H
Memory Control Status Register A
MCSRA
MTCRAL
MTCRAH
R/W
R/W
R/W
Memory Timing Configuration Register A Low
Memory Timing Configuration Register A High
MTCRA
26
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (10 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003F4H-
Reserved
0003F8H
-
0003F9H
0003FAH
0003FBH
0003FCH
0003FDH
Flash Memory Write Control register 1
Flash Memory Write Control register 2
Flash Memory Write Control register 3
Flash Memory Write Control register 4
Flash Memory Write Control register 5
FMWC1
FMWC2
FMWC3
FMWC4
FMWC5
R/W
R/W
R/W
R/W
R/W
0003FEH-
0003FFH
Reserved
-
000400H
000401H
000402H
000403H
000404H
000405H
000406H
000407H
000408H
000409H
00040AH
Standby Mode control register
Clock select register
SMCR
CKSR
R/W
R/W
R/W
R
Clock Stabilisation select register
Clock monitor register
CKSSR
CKMR
Clock Frequency control register Low
Clock Frequency control register High
PLL Control register Low
CKFCRL
CKFCRH
PLLCRL
PLLCRH
RCTCR
MCTCR
SCTCR
CKFCR
PLLCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PLL Control register High
RC clock timer control register
Main clock timer control register
Sub clock timer control register
Reset cause and clock status register with clear
function
00040BH
RCCSRC
R
00040CH
00040DH
00040EH
00040FH
Reset configuration register
RCR
R/W
R
Reset cause and clock status register
Watch dog timer configuration register
Watch dog timer clear pattern register
RCCSR
WDTC
WDTCP
R/W
W
000410H-
000414H
Reserved
-
000415H
000416H
000417H
Clock output activation register
COAR
COCR0
COCR1
R/W
R/W
R/W
Clock output configuration register 0
Clock output configuration register 1
FME-MB96310 rev 2
27
MB96310 Series
I/O map MB96(F)315x (11 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000418H
000419H
00041AH
00041BH
Clock Modulator control register
Reserved
CMCR
R/W
-
Clock Modulator Parameter register Low
Clock Modulator Parameter register High
CMPRL
CMPRH
CMPR
R/W
R/W
00041CH-
00042BH
Reserved
-
00042CH
00042DH
Voltage Regulator Control register
VRCR
CILCR
R/W
R/W
Clock Input and LVD Control Register
00042EH-
00042FH
Reserved
-
000430H
000431H
000432H
000433H
000434H
000435H
000436H
000437H
I/O Port P00 - Data Direction Register
I/O Port P01 - Data Direction Register
I/O Port P02 - Data Direction Register
I/O Port P03 - Data Direction Register
Reserved
DDR00
DDR01
DDR02
DDR03
R/W
R/W
R/W
R/W
-
I/O Port P05 - Data Direction Register
I/O Port P06 - Data Direction Register
I/O Port P07 - Data Direction Register
DDR05
DDR06
DDR07
R/W
R/W
R/W
000438H-
000443H
Reserved
-
000444H
000445H
000446H
000447H
000448H
000449H
00044AH
00044BH
I/O Port P00 - Port Input Enable Register
I/O Port P01 - Port Input Enable Register
I/O Port P02 - Port Input Enable Register
I/O Port P03 - Port Input Enable Register
Reserved
PIER00
PIER01
PIER02
PIER03
R/W
R/W
R/W
R/W
-
I/O Port P05 - Port Input Enable Register
I/O Port P06 - Port Input Enable Register
I/O Port P07 - Port Input Enable Register
PIER05
PIER06
PIER07
R/W
R/W
R/W
00044CH-
000457H
Reserved
-
000458H
I/O Port P00 - Port Input Level Register
PILR00
R/W
28
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (12 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000459H
00045AH
00045BH
00045CH
00045DH
00045EH
00045FH
I/O Port P01 - Port Input Level Register
I/O Port P02 - Port Input Level Register
I/O Port P03 - Port Input Level Register
Reserved
PILR01
PILR02
PILR03
R/W
R/W
R/W
-
I/O Port P05 - Port Input Level Register
I/O Port P06 - Port Input Level Register
I/O Port P07 - Port Input Level Register
PILR05
PILR06
PILR07
R/W
R/W
R/W
000460H-
00046BH
Reserved
-
00046CH
00046DH
00046EH
00046FH
000470H
000471H
000472H
000473H
I/O Port P00 - Extended Port Input Level Register
I/O Port P01 - Extended Port Input Level Register
I/O Port P02 - Extended Port Input Level Register
I/O Port P03 - Extended Port Input Level Register
Reserved
EPILR00
EPILR01
EPILR02
EPILR03
R/W
R/W
R/W
R/W
-
I/O Port P05 - Extended Port Input Level Register
I/O Port P06 - Extended Port Input Level Register
I/O Port P07 - Extended Port Input Level Register
EPILR05
EPILR06
EPILR07
R/W
R/W
R/W
000474H-
00047FH
Reserved
-
000480H
000481H
000482H
000483H
000484H
000485H
000486H
000487H
I/O Port P00 - Port Output Drive Register
I/O Port P01 - Port Output Drive Register
I/O Port P02 - Port Output Drive Register
I/O Port P03 - Port Output Drive Register
Reserved
PODR00
PODR01
PODR02
PODR03
R/W
R/W
R/W
R/W
-
I/O Port P05 - Port Output Drive Register
I/O Port P06 - Port Output Drive Register
I/O Port P07 - Port Output Drive Register
PODR05
PODR06
PODR07
R/W
R/W
R/W
000488H-
0004A7H
Reserved
-
0004A8H
0004A9H
I/O Port P00 - Pull-Up resistor Control Register
I/O Port P01 - Pull-Up resistor Control Register
PUCR00
PUCR01
R/W
R/W
FME-MB96310 rev 2
29
MB96310 Series
I/O map MB96(F)315x (13 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0004AAH
0004ABH
0004ACH
0004ADH
0004AEH
0004AFH
I/O Port P02 - Pull-Up resistor Control Register
I/O Port P03 - Pull-Up resistor Control Register
Reserved
PUCR02
PUCR03
R/W
R/W
-
I/O Port P05 - Pull-Up resistor Control Register
I/O Port P06 - Pull-Up resistor Control Register
I/O Port P07 - Pull-Up resistor Control Register
PUCR05
PUCR06
PUCR07
R/W
R/W
R/W
0004B0H-
0004BBH
Reserved
-
0004BCH
0004BDH
0004BEH
0004BFH
0004C0H
0004C1H
0004C2H
0004C3H
I/O Port P00 - External Pin State Register
I/O Port P01 - External Pin State Register
I/O Port P02 - External Pin State Register
I/O Port P03 - External Pin State Register
Reserved
EPSR00
EPSR01
EPSR02
EPSR03
R
R
R
R
-
I/O Port P05 - External Pin State Register
I/O Port P06 - External Pin State Register
I/O Port P07 - External Pin State Register
EPSR05
EPSR06
EPSR07
R
R
R
0004C4H-
0004CFH
Reserved
-
0004D0H
0004D1H
0004D2H
0004D3H
0004D4H
0004D5H
0004D6H
0004D7H
0004D8H
0004D9H
0004DAH
0004DBH
0004DCH
ADC analog input enable register 0
ADC analog input enable register 1
ADC analog input enable register 2
ADC analog input enable register 3
ADC analog input enable register 4
Reserved
ADER0
ADER1
ADER2
ADER3
ADER4
R/W
R/W
R/W
R/W
R/W
-
Peripheral Resource Relocation Register 0
Peripheral Resource Relocation Register 1
Peripheral Resource Relocation Register 2
Peripheral Resource Relocation Register 3
Peripheral Resource Relocation Register 4
Peripheral Resource Relocation Register 5
Peripheral Resource Relocation Register 6
PRRR0
PRRR1
PRRR2
PRRR3
PRRR4
PRRR5
PRRR6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
30
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (14 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0004DDH
0004DEH
0004DFH
0004E0H
0004E1H
0004E2H
0004E3H
0004E4H
0004E5H
0004E6H
0004E7H
0004E8H
0004E9H
0004EAH
0004EBH
0004ECH
0004EDH
0004EEH
0004EFH
0004F0H
0004F1H
Peripheral Resource Relocation Register 7
Peripheral Resource Relocation Register 8
Peripheral Resource Relocation Register 9
RTC - Sub Second Register L
PRRR7
PRRR8
PRRR9
WTBRL0
WTBRH0
WTBR1
WTSR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
WTBR0
RTC - Sub Second Register M
RTC - Sub-Second Register H
RTC - Second Register
RTC - Minutes
WTMR
RTC - Hour
WTHR
RTC - Timer Control Extended Register
RTC - Clock select register
WTCER
WTCKSR
WTCRL
WTCRH
CUCR
RTC - Timer Control Register Low
RTC - Timer Control Register High
CAL - Calibration unit Control register
Reserved
WTCR
CAL - Duration Timer Data Register Low
CAL - Duration Timer Data Register High
CAL - Calibration Timer Register 2 Low
CAL - Calibration Timer Register 2 High
CAL - Calibration Timer Register 1 Low
CAL - Calibration Timer Register 1 High
CUTDL
CUTDH
CUTR2L
CUTR2H
CUTR1L
CUTR1H
CUTD
CUTR2
CUTR1
R/W
R/W
R
R
R
R
0004F2H-
0004F9H
Reserved
-
R/W
-
0004FAH
RLT - Timer input select (for Cascading)
Reserved
TMISR
0004FBH-
0004FFH
000500H
000501H
FRT2 - Data register of free-running timer
FRT2 - Data register of free-running timer
TCDT2
TCCS2
R/W
R/W
FRT2 - Control status register of free-running timer
Low
000502H
TCCSL2
R/W
FME-MB96310 rev 2
31
MB96310 Series
I/O map MB96(F)315x (15 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
FRT2 - Control status register of free-running timer
High
000503H
TCCSH2
R/W
000504H
000505H
FRT3 - Data register of free-running timer
FRT3 - Data register of free-running timer
TCDT3
TCCS3
R/W
R/W
FRT3 - Control status register of free-running timer
Low
000506H
000507H
TCCSL3
TCCSH3
R/W
R/W
-
FRT3 - Control status register of free-running timer
High
000508H-
000513H
Reserved
000514H
000515H
000516H
000517H
000518H
000519H
00051AH
00051BH
00051CH
00051DH
00051EH
00051FH
ICU8/ICU9 - Control Status Register
ICU8/ICU9 - Edge Register
ICS89
ICE89
R/W
R/W
R
ICU8 - Capture Register Low
ICU8 - Capture Register High
ICU9 - Capture Register Low
ICU9 - Capture Register High
ICU10/ICU11 - Control Status Register
ICU10/ICU11 - Edge Register
ICU10 - Capture Register Low
ICU10 - Capture Register High
ICU11 - Capture Register Low
ICU11 - Capture Register High
IPCPL8
IPCPH8
IPCPL9
IPCPH9
ICS1011
ICE1011
IPCPL10
IPCPH10
IPCPL11
IPCPH11
IPCP8
IPCP9
R
R
R
R/W
R/W
R
IPCP10
IPCP11
R
R
R
000520H-
00053DH
Reserved
-
00053EH
00053FH
000540H
000540H
000541H
000542H
000543H
000544H
USART7 - Serial Mode Register
USART7 - Serial Control Register
USART7 - Serial TX Register
SMR7
SCR7
R/W
R/W
W
TDR7
USART7 - Serial RX Register
RDR7
SSR7
R
USART7 - Serial Status Register
USART7 - Ext. Control/Com. Register
USART7 - Ext. Status Com. Register
USART7 - Baud Rate Generator Register Low
R/W
R/W
R/W
R/W
ECCR7
ESCR7
BGRL7
BGR7
32
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (16 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000545H
000546H
000547H
000548H
000549H
00054AH
00054AH
00054BH
00054CH
00054DH
00054EH
00054FH
000550H
USART7 - Baud Rate Generator Register High
USART7 - Extended Serial Interrupt Register
Reserved
BGRH7
ESIR7
R/W
R/W
-
USART8 - Serial Mode Register
SMR8
SCR8
R/W
R/W
W
USART8 - Serial Control Register
USART8 - Serial TX Register
TDR8
USART8 - Serial RX Register
RDR8
R
USART8 - Serial Status Register
SSR8
R/W
R/W
R/W
R/W
R/W
R/W
USART8 - Ext. Control/Com. Register
USART8 - Ext. Status Com. Register
USART8 - Baud Rate Generator Register Low
USART8 - Baud Rate Generator Register High
USART8 - Extended Serial Interrupt Register
ECCR8
ESCR8
BGRL8
BGRH8
ESIR8
BGR8
000551H-
000563H
Reserved
-
000564H
000565H
000566H
000567H
000568H
000569H
00056AH
00056BH
00056CH
00056DH
00056EH
00056FH
000570H
000571H
000572H
PPG6 - Timer register
PTMR6
PCSR6
PDUT6
PCN6
R
R
PPG6 - Timer register
PPG6 - Period setting register
PPG6 - Period setting register
PPG6 - Duty cycle register
PPG6 - Duty cycle register
PPG6 - Control status register Low
PPG6 - Control status register High
PPG7 - Timer register
W
W
W
W
PCNL6
PCNH6
R/W
R/W
R
PTMR7
PCSR7
PDUT7
PCN7
PPG7 - Timer register
R
PPG7 - Period setting register
PPG7 - Period setting register
PPG7 - Duty cycle register
PPG7 - Duty cycle register
PPG7 - Control status register Low
W
W
W
W
PCNL7
R/W
FME-MB96310 rev 2
33
MB96310 Series
I/O map MB96(F)315x (17 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000573H
000574H
000575H
000576H
000577H
000578H
000579H
00057AH
00057BH
00057CH
00057DH
00057EH
00057FH
000580H
000581H
000582H
000583H
000584H
000585H
000586H
000587H
PPG7 - Control status register High
PPG11-PPG8 - General Control register 1 Low
PPG11-PPG8 - General Control register 1 High
PPG11-PPG8 - General Control register 2 Low
PPG11-PPG8 - General Control register 2 High
PPG8 - Timer register
PCNH7
GCN1L2
GCN1H2
GCN2L2
GCN2H2
R/W
R/W
R/W
R/W
R/W
R
GCN12
GCN22
PTMR8
PCSR8
PDUT8
PCN8
PPG8 - Timer register
R
PPG8 - Period setting register
PPG8 - Period setting register
PPG8 - Duty cycle register
W
W
W
PPG8 - Duty cycle register
W
PPG8 - Control status register Low
PPG8 - Control status register High
PPG9 - Timer register
PCNL8
PCNH8
R/W
R/W
R
PTMR9
PCSR9
PDUT9
PCN9
PPG9 - Timer register
R
PPG9 - Period setting register
PPG9 - Period setting register
PPG9 - Duty cycle register
W
W
W
PPG9 - Duty cycle register
W
PPG9 - Control status register Low
PPG9 - Control status register High
PCNL9
PCNH9
R/W
R/W
000588H-
000597H
Reserved
-
000598H
000599H
00059AH
00059BH
00059CH
00059DH
00059EH
PPG15-PPG12 - General Control register 1 Low
PPG15-PPG12 - General Control register 1 High
PPG15-PPG12 - General Control register 2 Low
PPG15-PPG12 - General Control register 2 High
PPG12 - Timer register
GCN1L3
GCN1H3
GCN2L3
GCN2H3
GCN13
GCN23
R/W
R/W
R/W
R/W
R
PTMR12
PCSR12
PPG12 - Timer register
R
PPG12 - Period setting register
W
34
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (18 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00059FH
0005A0H
0005A1H
0005A2H
0005A3H
PPG12 - Period setting register
PPG12 - Duty cycle register
W
W
PDUT12
PCN12
PPG12 - Duty cycle register
W
PPG12 - Control status register Low
PPG12 - Control status register High
PCNL12
PCNH12
R/W
R/W
0005A4H-
0005ABH
Reserved
-
0005ACH
0005ADH
0005AEH
0005AFH
0005B0H
0005B1H
0005B2H
0005B3H
PPG14 - Timer register
PTMR14
PCSR14
PDUT14
PCN14
R
R
PPG14 - Timer register
PPG14 - Period setting register
PPG14 - Period setting register
PPG14 - Duty cycle register
PPG14 - Duty cycle register
PPG14 - Control status register Low
PPG14 - Control status register High
W
W
W
W
PCNL14
PCNH14
R/W
R/W
0005B4H-
0005BBH
Reserved
-
0005BCH
0005BDH
0005BEH
0005BFH
0005C0H
0005C1H
0005C2H
0005C3H
0005C4H
0005C5H
0005C6H
0005C7H
0005C8H
0005C9H
PPG19-PPG16 - General Control register 1 Low
PPG19-PPG16 - General Control register 1 High
PPG19-PPG16 - General Control register 2 Low
PPG19-PPG16 - General Control register 2 High
PPG16 - Timer register
GCN1L4
GCN1H4
GCN2L4
GCN2H4
GCN14
GCN24
R/W
R/W
R/W
R/W
R
PTMR16
PCSR16
PDUT16
PCN16
PPG16 - Timer register
R
PPG16 - Period setting register
PPG16 - Period setting register
PPG16 - Duty cycle register
W
W
W
PPG16 - Duty cycle register
W
PPG16 - Control status register Low
PPG16 - Control status register High
PPG17 - Timer register
PCNL16
PCNH16
R/W
R/W
R
PTMR17
PPG17 - Timer register
R
FME-MB96310 rev 2
35
MB96310 Series
I/O map MB96(F)315x (19 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0005CAH
0005CBH
0005CCH
0005CDH
0005CEH
0005CFH
0005D0H
0005D1H
0005D2H
0005D3H
0005D4H
0005D5H
0005D6H
0005D7H
0005D8H
0005D9H
0005DAH
0005DBH
0005DCH
0005DDH
0005DEH
0005DFH
PPG17 - Period setting register
PPG17 - Period setting register
PPG17 - Duty cycle register
PPG17 - Duty cycle register
PPG17 - Control status register Low
PPG17 - Control status register High
PPG18 - Timer register
PCSR17
PDUT17
PCN17
W
W
W
W
PCNL17
PCNH17
R/W
R/W
R
PTMR18
PCSR18
PDUT18
PCN18
PPG18 - Timer register
R
PPG18 - Period setting register
PPG18 - Period setting register
PPG18 - Duty cycle register
PPG18 - Duty cycle register
PPG18 - Control status register Low
PPG18 - Control status register High
PPG19 - Timer register
W
W
W
W
PCNL18
PCNH18
R/W
R/W
R
PTMR19
PCSR19
PDUT19
PCN19
PPG19 - Timer register
R
PPG19 - Period setting register
PPG19 - Period setting register
PPG19 - Duty cycle register
PPG19 - Duty cycle register
PPG19 - Control status register Low
PPG19 - Control status register High
W
W
W
W
PCNL19
PCNH19
R/W
R/W
0005E0H-
00065FH
Reserved
-
000660H
000661H
000662H
000663H
Peripheral Resource Relocation Register 10
Peripheral Resource Relocation Register 11
Peripheral Resource Relocation Register 12
Peripheral Resource Relocation Register 13
PRRR10
PRRR11
PRRR12
PRRR13
R/W
R/W
R/W
W
000664H-
0008FFH
Reserved
-
000900H
CAN2 - Control register Low
CTRLRL2
CTRLR2
R/W
36
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (20 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000901H
000902H
000903H
000904H
000905H
000906H
000907H
000908H
000909H
00090AH
00090BH
00090CH
00090DH
CAN2 - Control register High (reserved)
CAN2 - Status register Low
CTRLRH2
STATRL2
STATRH2
ERRCNTL2
ERRCNTH2
BTRL2
R
R/W
R
STATR2
ERRCNT2
BTR2
CAN2 - Status register High (reserved)
CAN2 - Error Counter Low (Transmit)
CAN2 - Error Counter High (Receive)
CAN2 - Bit Timing Register Low
CAN2 - Bit Timing Register High
CAN2 - Interrupt Register Low
R
R
R/W
R/W
R
BTRH2
INTRL2
INTR2
CAN2 - Interrupt Register High
INTRH2
R
CAN2 - Test Register Low
TESTRL2
TESTRH2
BRPERL2
BRPERH2
TESTR2
BRPER2
R/W
R
CAN2 - Test Register High (reserved)
CAN2 - BRP Extension register Low
CAN2 - BRP Extension register High (reserved)
R/W
R
00090EH-
00090FH
Reserved
-
000910H
000911H
000912H
CAN2 - IF1 Command request register Low
CAN2 - IF1 Command request register High
CAN2 - IF1 Command Mask register Low
IF1CREQL2
IF1CREQH2
IF1CMSKL2
IF1CREQ2
IF1CMSK2
R/W
R/W
R/W
CAN2 - IF1 Command Mask register High (re-
served)
000913H
IF1CMSKH2
R
000914H
000915H
000916H
000917H
000918H
000919H
00091AH
00091BH
00091CH
00091DH
00091EH
CAN2 - IF1 Mask 1 Register Low
CAN2 - IF1 Mask 1 Register High
CAN2 - IF1 Mask 2 Register Low
CAN2 - IF1 Mask 2 Register High
CAN2 - IF1 Arbitration 1 Register Low
CAN2 - IF1 Arbitration 1 Register High
CAN2 - IF1 Arbitration 2 Register Low
CAN2 - IF1 Arbitration 2 Register High
CAN2 - IF1 Message Control Register Low
CAN2 - IF1 Message Control Register High
CAN2 - IF1 Data A1 Low
IF1MSK1L2
IF1MSK1H2
IF1MSK2L2
IF1MSK2H2
IF1ARB1L2
IF1ARB1H2
IF1ARB2L2
IF1ARB2H2
IF1MCTRL2
IF1MCTRH2
IF1DTA1L2
IF1MSK12
IF1MSK22
IF1ARB12
IF1ARB22
IF1MCTR2
IF1DTA12
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FME-MB96310 rev 2
37
MB96310 Series
I/O map MB96(F)315x (21 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00091FH
000920H
000921H
000922H
000923H
000924H
000925H
CAN2 - IF1 Data A1 High
IF1DTA1H2
IF1DTA2L2
IF1DTA2H2
IF1DTB1L2
IF1DTB1H2
IF1DTB2L2
IF1DTB2H2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN2 - IF1 Data A2 Low
CAN2 - IF1 Data A2 High
CAN2 - IF1 Data B1 Low
CAN2 - IF1 Data B1 High
CAN2 - IF1 Data B2 Low
CAN2 - IF1 Data B2 High
IF1DTA22
IF1DTB12
IF1DTB22
000926H-
00093FH
Reserved
-
000940H
000941H
000942H
CAN2 - IF2 Command request register Low
CAN2 - IF2 Command request register High
CAN2 - IF2 Command Mask register Low
IF2CREQL2
IF2CREQH2
IF2CMSKL2
IF2CREQ2
IF2CMSK2
R/W
R/W
R/W
CAN2 - IF2 Command Mask register High (re-
served)
000943H
IF2CMSKH2
R
000944H
000945H
000946H
000947H
000948H
000949H
00094AH
00094BH
00094CH
00094DH
00094EH
00094FH
000950H
000951H
000952H
000953H
000954H
CAN2 - IF2 Mask 1 Register Low
CAN2 - IF2 Mask 1 Register High
CAN2 - IF2 Mask 2 Register Low
CAN2 - IF2 Mask 2 Register High
CAN2 - IF2 Arbitration 1 Register Low
CAN2 - IF2 Arbitration 1 Register High
CAN2 - IF2 Arbitration 2 Register Low
CAN2 - IF2 Arbitration 2 Register High
CAN2 - IF2 Message Control Register Low
CAN2 - IF2 Message Control Register High
CAN2 - IF2 Data A1 Low
IF2MSK1L2
IF2MSK1H2
IF2MSK2L2
IF2MSK2H2
IF2ARB1L2
IF2ARB1H2
IF2ARB2L2
IF2ARB2H2
IF2MCTRL2
IF2MCTRH2
IF2DTA1L2
IF2DTA1H2
IF2DTA2L2
IF2DTA2H2
IF2DTB1L2
IF2DTB1H2
IF2DTB2L2
IF2MSK12
IF2MSK22
IF2ARB12
IF2ARB22
IF2MCTR2
IF2DTA12
IF2DTA22
IF2DTB12
IF2DTB22
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN2 - IF2 Data A1 High
CAN2 - IF2 Data A2 Low
CAN2 - IF2 Data A2 High
CAN2 - IF2 Data B1 Low
CAN2 - IF2 Data B1 High
CAN2 - IF2 Data B2 Low
38
FME-MB96310 rev 2
MB96310 Series
I/O map MB96(F)315x (22 of 22)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000955H
CAN2 - IF2 Data B2 High
IF2DTB2H2
R/W
-
000956H-
00097FH
Reserved
000980H
000981H
000982H
000983H
CAN2 - Transmission Request 1 Register Low
CAN2 - Transmission Request 1 Register High
CAN2 - Transmission Request 2 Register Low
CAN2 - Transmission Request 2 Register High
TREQR1L2
TREQR1H2
TREQR2L2
TREQR2H2
TREQR12
TREQR22
R
R
R
R
000984H-
00098FH
Reserved
-
000990H
000991H
000992H
000993H
CAN2 - New Data 1 Register Low
CAN2 - New Data 1 Register High
CAN2 - New Data 2 Register Low
CAN2 - New Data 2 Register High
NEWDT1L2
NEWDT1H2
NEWDT2L2
NEWDT2H2
NEWDT12
NEWDT22
R
R
R
R
000994H-
00099FH
Reserved
-
0009A0H
0009A1H
0009A2H
0009A3H
CAN2 - Interrupt Pending 1 Register Low
CAN2 - Interrupt Pending 1 Register High
CAN2 - Interrupt Pending 2 Register Low
CAN2 - Interrupt Pending 2 Register High
INTPND1L2
INTPND1H2
INTPND2L2
INTPND2H2
INTPND12
INTPND22
R
R
R
R
0009A4H-
0009AFH
Reserved
-
0009B0H
0009B1H
0009B2H
0009B3H
CAN2 - Message Valid 1 Register Low
CAN2 - Message Valid 1 Register High
CAN2 - Message Valid 2 Register Low
CAN2 - Message Valid 2 Register High
MSGVAL1L2
MSGVAL1H2
MSGVAL2L2
MSGVAL2H2
MSGVAL12
MSGVAL22
R
R
R
R
0009B4H-
0009CDH
Reserved
-
R/W
-
0009CEH
CAN2 - Output enable register
Reserved
COER2
0009CFH-
000BFFH
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved
address results in reading ‘X’.
FME-MB96310 rev 2
39
MB96310 Series
Registers of resources which are described in this table, but which are not supported by the device, should
also be handled as “Reserved”.
■ INTERRUPT VECTOR TABLE
Interrupt vector table MB96(F)31x (1 of 3)
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
0
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
-
-
1
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
INT9
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
EXCEPTION
NMI
-
-
Non-Maskable Interrupt
DLY
12
13
14
15
16
17
Delayed Interrupt
RC Timer
RC_TIMER
MC_TIMER
SC_TIMER
PLL_UNLOCK
EXTINT0
Main Clock Timer
Sub Clock Timer
Reserved
External Interrupt 0
Reserved
EXTINT2
EXTINT3
EXTINT4
Yes
Yes
Yes
19
20
21
External Interrupt 2
External Interrupt 3
External Interrupt 4
Reserved
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
Yes
Yes
Yes
Yes
Yes
Yes
Yes
23
24
25
26
27
28
29
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
Reserved
40
FME-MB96310 rev 2
MB96310 Series
Interrupt vector table MB96(F)31x (2 of 3)
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
380H
37CH
378H
374H
370H
36CH
368H
364H
360
Reserved
Reserved
CAN2
PPG0
PPG1
No
Yes
Yes
33
34
35
CAN Controller 2
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Reserved
PPG3
PPG4
Yes
Yes
37
38
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Reserved
35CH
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
PPG6
PPG7
PPG8
PPG9
Yes
Yes
Yes
Yes
40
41
42
43
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Reserved
Reserved
PPG12
PPG14
Yes
Yes
46
48
Programmable Pulse Generator 12
Reserved
Programmable Pulse Generator 14
Reserved
PPG16
PPG17
PPG18
PPG19
RLT0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
50
51
52
53
54
55
56
57
58
59
60
Programmable Pulse Generator 16
Programmable Pulse Generator 17
Programmable Pulse Generator 18
Programmable Pulse Generator 19
Reload Timer 0
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
PPGRLT
ICU0
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
ICU1
Input Capture Unit 1
Reserved
Reserved
ICU4
ICU5
ICU6
Yes
Yes
Yes
63
64
65
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
FME-MB96310 rev 2
41
MB96310 Series
Interrupt vector table MB96(F)31x (3 of 3)
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
2BCH
2B8H
2B4H
2B0H
2ACH
2A8H
2A4H
2A0H
29CH
298H
294H
290H
28CH
288H
Reserved
Reserved
ICU9
Yes
Yes
68
69
Input Capture Unit 9
Input Capture Unit 10
Reserved
ICU10
Reserved
Reserved
OCU6
OCU7
Yes
Yes
73
74
Output Compare Unit 6
Output Compare Unit 7
Reserved
Reserved
FRT0
FRT1
FRT2
FRT3
RTC0
CAL0
Yes
Yes
Yes
Yes
No
77
78
79
80
81
82
Free Running Timer 0
Free Running Timer 1
Free Running Timer 2
Free Running Timer 3
Real Timer Clock
Clock Calibration Unit
Reserved
No
ADC0
LINR2
LINT2
Yes
Yes
Yes
84
85
86
A/D Converter
LIN USART 2 RX
LIN USART 2 TX
Reserved
Reserved
LINR7
LINT7
Yes
Yes
Yes
Yes
No
89
90
91
92
93
LIN USART 7 RX
LIN USART 7 TX
LIN USART 8 RX
LIN USART 8 TX
Flash memory A (only Flash devices)
LINR8
LINT8
FLASH_A
42
FME-MB96310 rev 2
MB96310 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Unused sub clock signal
• Notes on PLL clock mode operation
• Power supply pins (VCC/VSS)
• Crystal oscillator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on energization
• Stabilization of power supply voltage
• Serial communication
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up,
those resistors should be more than 2 kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC
Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be
connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 pin must be driven and X1 pin left open.
X0
X1
FME-MB96310 rev 2
43
MB96310 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the
opposite phase to the X0 (X0A) pins.
X0
X1
4. Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
5. Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
6. Power supply pins (VCC/VSS
)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more
than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating
range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between
VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and
ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
8. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this
case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously
on or off is acceptable).
9. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on
should be slower than 50µs from 0.2 V to 2.7 V.
44
FME-MB96310 rev 2
MB96310 Series
11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage,
a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines,
the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in
the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
12. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
FME-MB96310 rev 2
45
MB96310 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
VCC
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
Power supply voltage
*1
AVCC
VCC = AVCC
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > AVRL, AVRL ≥ AVSS
AD Converter voltage references
VSS - 0.3 VSS + 6.0
V
*2
Input voltage
VI
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
VI ≤ VCC + 0.3V
VO ≤ VCC + 0.3V *2
Output voltage
VO
Applicable to general purpose
I/O pins *3
Maximum Clamp Current
ICLAMP
-4.0
+4.0
mA
mA
Applicable to general purpose
I/O pins *3
Total Maximum Clamp Current
“L” level maximum output current
Σ|ICLAMP|
-
-
40
15
IOL1
mA Normal outputs with driving
strength set to 5mA
“L” level average output current
IOLAV1
-
5
mA Normal outputs with driving
strength set to 5mA
“L” level maximum overall output current
“L” level average overall output current
”H” level maximum output current
ΣIOL1
ΣIOLAV1
IOH1
-
-
-
100
50
mA Normal outputs
mA Normal outputs
-15
mA Normal outputs with driving
strength set to 5mA
”H” level average output current
IOHAV1
-
-5
mA Normal outputs with driving
strength set to 5mA
”H” level maximum overall output current
”H” level average overall output current
ΣIOH1
-
-
-
-
-
-100
-50
mA Normal outputs
mA Normal outputs
ΣIOHAV1
220*5
450*5
615*5
TA=105oC
TA=85oC
TA=70oC
mW
mW
mW
Permitted Power dissipation (Flash de-
vices) *4
PD
TA=125oC, no Flash program/
erase *6
280*5
500*5
-
-
mW
mW
TA=105oC, no Flash program/
erase *6
0
+70
MB96V300B
oC
oC
-40
-40
-55
+105
+125
+150
Operating ambient temperature
Storage temperature
TA
*6
TSTG
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage
at the analog inputs does not exceed AVCC neither when the power is switched on.
46
FME-MB96310 rev 2
MB96310 Series
*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from a input is limited by some means with external components, the ICLAMP rating super-
sedes the VI rating. Input/output voltages of standard ports depend on VCC.
*3: • Applicable to all general purpose I/O pins (Pnn_m)
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Notethatifthe+Binputisappliedduringpower-on, thepowersupplyisprovidedfromthepinsandtheresulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage
reset in internal vector mode).
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0V to 16V)
R
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming or the clock
modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Fujitsu for reliability limitations when using under these conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
FME-MB96310 rev 2
47
MB96310 Series
2. Recommended Operating Conditions
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage
VCC
3.0
5.5
V
Use a low inductance capacitor
Smoothing capacitor at C
pin
CS
3.5
4.7 - 10
15
µF (for example X7R ceramic ca-
pacitor)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
48
FME-MB96310 rev 2
MB96310 Series
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
0.7
VCC +
Input H voltage
-
V
V
VCC ≥ 4.5V
CMOSHysteresis
0.7/0.3 input se-
lected
VCC
0.3
0.74
VCC
VCC +
0.3
Port inputs
Pnn_m
-
-
VCC < 4.5V
VIH
AUTOMOTIVE
Hysteresis input
selected
0.8
VCC
VCC +
0.3
V
V
External clock in
“Fast Clock Input
mode”
0.8
VCC
VCC +
0.3
-
-
VIHX0F
VIHX0S
X0
X0,X1,
External clock in
X0A,X1A “oscillation mode”
VCC +
0.3
2.5
V
V
V
CMOS Hysteresis in-
put
0.8
VCC
VCC +
0.3
-
-
VIHR
RSTX
-
-
VCC -
0.3
VCC +
0.3
VIHM
MD2-MD0
Input L voltage
CMOSHysteresis
0.7/0.3 input se-
lected
VSS -
0.3
-
V
V
0.3
VCC
Port inputs
Pnn_m
VIL
VSS -
0.3
0.5
VCC
-
-
VCC ≥ 4.5V
AUTOMOTIVE
Hysteresis input
selected
VSS -
0.3
0.46
VCC
VCC < 4.5V
External clock in
“Fast Clock Input
mode”
VSS -
-
-
0.2 VCC
VILX0F
VILX0S
X0
V
0.3
X0,X1,
External clock in
X0A,X1A “oscillation mode”
VSS -
0.3
0.4
V
V
V
CMOS Hysteresis in-
put
VSS -
0.3
-
-
0.2 VCC
VILR
VILM
RSTX
-
-
VSS -
0.3
VSS +
0.3
MD2-MD0
4.5V ≤ VCC ≤ 5.5V
IOH = -2mA
Output H voltage
Normal
outputs
Driving strength set
to 2mA
VCC -
0.5
-
-
-
-
VOH2
VOH5
V
V
3.0V ≤ VCC < 4.5V
IOH = -1.6mA
4.5V ≤ VCC ≤ 5.5V
IOH = -5mA
Normal
outputs
Driving strength set
to 5mA
VCC -
0.5
3.0V ≤ VCC < 4.5V
IOH = -3mA
FME-MB96310 rev 2
49
MB96310 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
4.5V ≤ VCC ≤ 5.5V
IOL = +2mA
Output L voltage
Normal
outputs
Driving strength set
to 2mA
-
-
0.4
VOL2
V
3.0V ≤ VCC < 4.5V
IOL = +1.6mA
4.5V ≤ VCC ≤ 5.5V
IOL = +5mA
Normal
outputs
Driving strength set
to 5mA
-
-
-
0.4
+1
VOL5
V
3.0V ≤ VCC < 4.5V
IOL = +3mA
VSS < VI < VCC
-1
Input leak current
Pull-up resistance
IIL
Pnn_m
µA Single port pin
AVSS, AVRL < VI <
AVCC, AVRH
40
25
100
50
160
100
VCC = 3.3V 10%
VCC = 5.0V 10%
kΩ
kΩ
Pnn_m,
RSTX
RUP
50
FME-MB96310 rev 2
MB96310 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
+25˚C
+125˚C
+25˚C
35
44
mA 0 Flash wait states
mA 2 Flash wait states
mA 1 Flash wait state
36
44
45
49
50
4.5
47
57
60
62
65
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1= 56MHz,
CLKP2 = 28MHz
ICCPLL
+125˚C
+25˚C
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
PLL Run mode with
CLKS1/2 = 96MHz,
CLKB = CLKP1= 48MHz,
CLKP2 = 24MHz
Power supply cur-
rent in Run
modes*
+125˚C
+25˚C
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
5.5
8.5
4
ICCMAIN
mA 1 Flash wait state
mA 1 Flash wait state
+125˚C 5.1
(CLKPLL, CLKSC and
CLKRC stopped)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
+25˚C
2.9
ICCRCH
+125˚C 3.5
6.5
(CLKMC, CLKPLL and
CLKSC stopped)
FME-MB96310 rev 2
51
MB96310 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
+25˚C 0.18
0.3
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
mA 1 Flash wait state
+125˚C 0.68
3.3
ICCRCL
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
+25˚C 0.15 0.25
Power supply cur-
rent in Run
modes*
mA 1 Flash wait state
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode, no Flash program-
ming/erasing allowed)
+125˚C 0.65
3.2
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
+25˚C
0.1
0.2
3
ICCSUB
mA 1 Flash wait state
(CLKMC, CLKPLL and
CLKRCstopped, noFlash
programming/erasing al-
lowed)
+125˚C 0.6
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
+25˚C
9
10.5
13
mA
mA
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C 9.7
PLL Sleep mode with
CLKS1/2 = CLKP1=
56MHz, CLKP2 = 28MHz
+25˚C
14
15.5
18
Power supply cur-
rent in Sleep
modes*
ICCSPLL
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C 14.8
PLL Sleep mode with
CLKS1/2 = 96MHz,
CLKP1= 48MHz,
+25˚C
15
16.5
CLKP2 = 24MHz
mA
+125˚C 15.8
19
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
52
FME-MB96310 rev 2
MB96310 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
+25˚C
+125˚C
+25˚C
1.5
1.8
ICCSMAIN
mA
4.5
2
(CLKPLL, CLKSC and
CLKRC stopped)
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
0.8
1.3
ICCSRCH
mA
4
+125˚C 1.4
+25˚C 0.09
(CLKMC, CLKPLL and
CLKSC stopped)
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
0.2
SMCR:LPMSS = 0
mA
3.1
Power supply cur-
rent in Sleep
modes*
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+125˚C 0.59
ICCSRCL
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
+25˚C 0.06 0.15
SMCR:LPMSS = 1
mA
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+125˚C 0.56
3
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
+25˚C 0.04 0.12
ICCSSUB
mA
mA
+125˚C 0.54
2.9
2
(CLKMC, CLKPLL and
CLKRC stopped)
PLL Timer mode with
CLKMC = 4MHz, CLKPLL
= 48MHz
+25˚C
1.6
Power supply cur-
rent in Timer
modes*
ICCTPLL
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C 2.1
4.8
FME-MB96310 rev 2
53
MB96310 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
Main Timer mode with
CLKMC = 4MHz,
+25˚C 0.13
0.2
SMCR:LPMSS = 0
mA
3
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in high power
mode)
+125˚C 0.63
ICCTMAIN
Main Timer mode with
CLKMC = 4MHz,
+25˚C
0.1
0.15
SMCR:LPMSS = 1
mA
2.9
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in low power
mode)
+125˚C 0.6
+25˚C 0.13
+125˚C 0.63
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
0.2
mA
3
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
ICCTRCH
RC Timer mode with
CLKRC = 2MHz,
+25˚C
0.1
0.15
Power supply cur-
rent in Timer
modes*
SMCR:LPMSS = 1
mA
2.9
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+125˚C 0.6
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
+25˚C 0.08 0.15
+125˚C 0.58 2.95
mA
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
ICCTRCL
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
+25˚C 0.05
0.1
mA
mA
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
+125˚C 0.55 2.85
Sub Timer mode with
CLKSC = 32kHz
+25˚C 0.03
0.1
ICCTSUB
(CLKMC, CLKPLL and
CLKRC stopped)
+125˚C 0.53 2.85
54
FME-MB96310 rev 2
MB96310 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C 0.02 0.08
VRCR:LPMB[2:0] = 110B
(Core voltage at 1.8V)
mA
mA
+125˚C 0.52
2.8
Power supply cur-
rent in Stop Mode
ICCH
+25˚C 0.015 0.06
VRCR:LPMB[2:0] = 000B
(Core voltage at 1.2V)
+125˚C 0.4
2.3
10
Power supply cur-
rentforactiveLow
Voltage detector
This current must be
Low voltage detector en-
abled (RCR:LVDE = 1)
ICCLVD
-
5
µA added to all Power
supply currents above
Power supply cur-
rent for active
Clock modulator
Clock modulator enabled
(CMCR:PDX = 1)
Must be added to all
mA
ICCCLOMO
ICCFLASH
CIN
-
-
-
3
15
5
4.5
40
15
current above
FlashWrite/Erase
current
Current for one Flash
module
Must be added to all
mA
current above
Other than C, AVCC,
pF AVSS, AVRH, AVRL,
VCC, VSS
Input capacitance
-
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz
external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of
the Hardware Manual for further details about voltage regulator control.
FME-MB96310 rev 2
55
MB96310 Series
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
3
-
16
MHz When using a crystal oscillator, PLL off
When using an opposite phase external
clock, PLL off
0
3.5
0
-
-
-
16
16
56
56
MHz
Clock frequency
fC
X0, X1
When using a crystal oscillator or oppo-
MHz
site phase external clock, PLL on
When using a single phase external
MHz
clockin“FastClockInputmode”, PLLoff
Clock frequency
Clock frequency
Clock frequency
fFCI
fCL
fCR
X0
When using a single phase external
MHz
3.5
32
0
-
clockin“FastClockInputmode”, PLLon
32.768
-
100 kHz When using an oscillation circuit
X0A, X1A
X0A
When using an opposite phase external
100 kHz
clock
When using a single phase external
clock
0
50
1
-
100
2
50
kHz
When using slow frequency of RC oscil-
lator
200 kHz
-
When using fast frequency of RC oscil-
lator
4
MHz
PLL Clock fre-
quency
Permitted VCO output frequency of PLL
(CLKVCO)
fCLKVCO
TPSKEW
-
-
64
-
-
-
-
200 MHz
PLL Phase Jitter
5
ns For CLKMC (PLL input clock) ≥ 4MHz
Inputclockpulse
width
PWH, PWL
X0,X1
8
-
-
ns Duty ratio is about 30% to 70%
Inputclockpulse
width
PWHL, PWLL X0A,X1A
5
-
µs
56
FME-MB96310 rev 2
MB96310 Series
tCYL
VIH
VIL
X0
PWH
PWL
tCYLL
VIH
VIL
X0A
PWHL
PWLL
FME-MB96310 rev 2
57
MB96310 Series
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Core Voltage Settings
Parameter
Symbol
1.8V
1.9V
Unit
Remarks
Min
Max
Min
Max
Internal System clock fre-
quency (CLKS1 and
CLKS2)
fCLKS1, fCLKS2
0
92
0
96
MHz
Internal CPU clock fre-
quency (CLKB), internal
peripheralclockfrequency
(CLKP1)
fCLKB, fCLKP1
fCLKP2
0
0
52
28
0
0
56
32
MHz
MHz
Internal peripheral clock
frequency (CLKP2)
58
FME-MB96310 rev 2
MB96310 Series
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Reset input time
Symbol
Pin
Unit
Remarks
Min
Typ
Max
tRSTL
RSTX
500
-
-
ns
tRSTL
RSTX
0.2 VCC
0.2 VCC
FME-MB96310 rev 2
59
MB96310 Series
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
0.05
1
Typ
Max
30
-
Power on rise time
Power off time
tR
Vcc
Vcc
-
-
ms
ms
tOFF
tR
2.7V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
VCC
3 V
Rising edge of 50 mV/ms
maximum is allowed
60
FME-MB96310 rev 2
MB96310 Series
External Input timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Used Pin input func-
Parameter Symbol
Pin
Condition
Unit
tion
Min
Max
INTn(_R)
NMI
External Interrupt
NMI
200
⎯
ns
Pnn_m
TINn
General Purpose IO
Reload Timer
Input pulse
width
tINH
tINL
⎯
2*tCLKP1 + 200
(tCLKP1=1/
fCLKP1)
TTGn(_R)
ADTG_R
INn
⎯
ns
PPG Trigger input
AD Converter Trigger
Input Capture
Note : Relocated Resource Inputs have same characteristics
VIH
VIH
External Pin input
VIL
VIL
tINH
tINL
FME-MB96310 rev 2
61
MB96310 Series
USART timing
WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum
output timing described in the different tables must then be increased by 10ns.
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
VCC = AVCC= 4.5V VCC = AVCC= 3.0V
to 5.5V
to 4.5V
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYCI
tSLOVI
SCKn
4 tCLKP1
⎯
4 tCLKP1
⎯
ns
ns
SCK ↓ → SOT delay
time
SCKn,
SOTn
-20
+20
⎯
-30
+30
⎯
SOT → SCK ↑ delay
time
SCKn,
SOTn
N*tCLKP1
- 20 *1
N*tCLKP1 -
30 *1
tOVSHI
tIVSHI
Internal Shift
Clock Mode
ns
ns
ns
ns
ns
ns
ns
ns
SCKn,
SINn
tCLKP1 +
45
tCLKP1 +
55
Valid SIN → SCK ↑
⎯
⎯
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tSHIXI
0
⎯
0
⎯
Serial clock “L” pulse
width
tCLKP1 +
10
tCLKP1 +
10
tSLSHE
tSHSLE
tSLOVE
tIVSHE
tSHIXE
SCKn
SCKn
⎯
⎯
Serial clock “H” pulse
width
tCLKP1 +
10
tCLKP1 +
10
⎯
⎯
SCK ↓ → SOT delay
time
SCKn,
SOTn
2 tCLKP1
+ 45
2 tCLKP1
+ 55
⎯
⎯
External Shift
Clock Mode
SCKn,
SINn
tCLKP1/2
+ 10
tCLKP1/2+
Valid SIN → SCK ↑
⎯
⎯
⎯
⎯
10
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tCLKP1 +
10
tCLKP1 +
10
SCK fall time
SCK rise time
tFE
tRE
SCKn
SCKn
⎯
⎯
20
20
⎯
⎯
20
20
ns
ns
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
4*tCLKP1
N
2
5*tCLKP1, 6*tCLKP1
7*tCLKP1, 8*tCLKP1
...
3
4
...
62
FME-MB96310 rev 2
MB96310 Series
tSCYCI
SCK for
0.8*VCC
ESCR:SCES = 0
0.2*VCC
0.2*VCC
0.8*VCC
SCK for
0.8*VCC
ESCR:SCES = 1
0.2*VCC
tOVSHI
tSLOVI
0.8*VCC
0.2*VCC
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Internal Shift Clock Mode
tSLSHE
tSHSLE
SCK for
VIH
VIL
VIH
VIH
VIL
ESCR:SCES = 0
VIL
SCK for
VIH
VIH
ESCR:SCES = 1
VIL
VIL
tSLOVE
tFE
tRE
0.8*VCC
0.2*VCC
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
External Shift Clock Mode
FME-MB96310 rev 2
63
MB96310 Series
5. Analog Digital Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min
-
Typ
Max
10
-
-
-
-
-
-
-
-
-
bit
Total error
-3
+3
LSB
LSB
Nonlinearity error
-2.5
+2.5
Differentialnonlinearity
error
-
-
-1.9
-
+1.9
LSB
LSB
AVRL - AVRL+ AVRL +
1.5 0.5 2.5
Zero reading voltage
VOT
ANn
Full scale reading
voltage
AVRH - AVRH - AVRH+
VFST
ANn
-
LSB
3.5
1.5
0.5
1.0
2.0
0.5
1.2
-
-
-
-
16,500 µs 4.5V ≤ ΑVCC ≤ 5.5V
Compare time
Sampling time
-
-
-
-
µs 3.0V ≤ ΑVCC < 4.5V
µs 4.5V ≤ ΑVCC ≤ 5.5V
µs 3.0V ≤ ΑVCC < 4.5V
-
-
Analog port input cur-
rent
AVSS, AVRL < VI <
IAIN
ANn
-3
-1
-
-
+3
+1
µA
AVCC, AVRH
TA = 25 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
Analog port input cur-
rent
IAIN
ANn
TA = 125 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
-3
-
+3
Analog input voltage
range
VAIN
AVRH
AVRL
IA
ANn
AVRH
AVRL
AVcc
AVcc
AVRL
-
AVRH
AVcc
V
V
V
0.75
AVcc
-
Reference voltage
range
0.25
AVCC
AVSS
-
2.5
-
A/D Converter ac-
-
-
-
-
-
5
5
1
5
4
mA
tive
Power supply current
A/D Converter not
operated
IAH
µA
AVRH/
AVRL
A/D Converter ac-
IR
0.7
-
mA
tive
Reference voltage cur-
rent
AVRH/
AVRL
A/D Converter not
operated
IRH
µA
Offset between input
channels
-
ANn
-
LSB
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
64
FME-MB96310 rev 2
MB96310 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”)
and full-scale transition line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB,
from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
1.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
N: A/D converter digital output value
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
FME-MB96310 rev 2
65
MB96310 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
3FE
N + 1
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
3FD
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004
003
002
001
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Nonlinearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential nonlinearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Notes on A/D Converter Section
• About the external impedance of the analog input and the sampling time of the A/D converter (with sample
and hold circuit):
If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the
internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision.
• analog input circuit model:
R
Comparator
Analog input
C
Sampling switch
Reference value:
• C = 8.5 pF (Max)
66
FME-MB96310 rev 2
MB96310 Series
To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum
sampling time must be considered and then either the resistor value and operating frequency must be adjusted
or the external impedance must be decreased so that the sampling time (Tsamp) is longer than the minimum
value. Usually, this value is set to 7τ, where τ = RC. If the external input resistance (Rext) connected to the analog
input is included, the sampling time is expressed as follows:
Tsamp [min] = 7 × (Rext + 2.6kΩ) × C for 4.5 ≤ AVcc ≤ 5.5
Tsamp [min] = 7 × (Rext + 12.1kΩ) × C for 3.0 ≤ AVcc ≤ 4.5
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
•
About the error
The accuracy gets worse as |AVRH - AVRL| becomes smaller.
FME-MB96310 rev 2
67
MB96310 Series
6. Low Voltage Detector characteristics
(TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Value
Max
Parameter
Symbol
Unit
Remarks
Min
After power-up or change
of detection level
Stabilization time TLVDSTAB
-
110
µs
CILCR:LVL[3:0]=”0000”
CILCR:LVL[3:0]=”0001”
CILCR:LVL[3:0]=”0010”
CILCR:LVL[3:0]=”0011”
CILCR:LVL[3:0]=”0100”
CILCR:LVL[3:0]=”0101”
CILCR:LVL[3:0]=”0110”
CILCR:LVL[3:0]=”0111”
CILCR:LVL[3:0]=”1000”
CILCR:LVL[3:0]=”1001”
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
Level 12
Level 13
Level 14
Level 15
VDL0
VDL1
VDL2
VDL3
VDL4
VDL5
VDL6
VDL7
VDL8
VDL9
VDL10
VDL11
VDL12
VDL13
VDL14
VDL15
2.65
2.85
3.05
3.45
3.55
3.65
3.75
3.85
3.95
4.05
2.95
3.2
V
V
V
V
V
V
V
V
V
V
3.4
3.85
3.95
4.1
4.2
4.3
4.4
4.5
not used
not used
not used
not used
not used
not used
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
Levels 10 to 15 are not used in this device.
V
dV
dt
-----
µs
For correct detection, the slope of the voltage level must satisfy
≤ 0.004
.
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of
Vcc = 2.7V. The electrical characteristics however are only valid in the specified range (usually down to 3.0V).
68
FME-MB96310 rev 2
MB96310 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the
reset and startup behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
VDLx, Max
VDLx, Min
dV
dt
Time [s]
Power Reset Extension Time
Low Voltage Reset Assertion
Normal Operation
FME-MB96310 rev 2
69
MB96310 Series
7. FLASH memory program/erase characteristics
(TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Sector erase time
Unit
Remarks
Min
Typ
Max
Without erasure pre-program-
ming time
-
0.9
3.6
s
s
Without erasure pre-program-
ming time (n is the number of
Flash sector of the device)
Chip erase time
-
-
n*0.9
23
n*3.6
370
Without overhead time for sub-
mitting write command
Word (16-bit width) programming time
us
Program/Erase cycle
10 000
20
-
-
-
-
cycle
year
Flash data retention time
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
70
FME-MB96310 rev 2
MB96310 Series
■ PACKAGE DIMENSION MB96(F)31x LQFP 48 - M26
48-pin plastic LQFP
Lead pitch
0.50 mm
7 × 7 mm
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Gullwing
Plastic mold
1.70 mm MAX
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
7.00 –0.10 .276 –+..000146 SQ
0.145±0.055
(.006±.002)
*
36
25
37
24
Details of "A" part
0.08(.003)
1.50 +–00..1200
.059 +–..000048
(Mounting height)
INDEX
48
13
0.10±0.10
(.004±.004)
(Stand off)
"A"
0˚~8˚
1
12
LEAD No.
0.50(.020)
0.25(.010)
0.20±0.05
M
0.08(.003)
(.008±.002)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F48040S-c-2-3
FME-MB96310 rev 2
71
MB96310 Series
■ ORDERING INFORMATION
MCU with CAN controller
Persistent
Subclock Low Volt-
age Reset
Part number
Flash/ROM
Package
MB96F313YSA PMC-GSE2 *1
MB96F313RSA PMC-GSE2 *1
MB96F313YWA PMC-GSE2 *1
MB96F313RWA PMC-GSE2 *1
MB96F315YSA PMC-GSE2 *1
MB96F315RSA PMC-GSE2 *1
MB96F315YWA PMC-GSE2 *1
MB96F315RWA PMC-GSE2 *1
MB96V300BRB-ES
Yes
No
No
Flash A (96KB)
Yes
Yes
No
48 pins Plastic LQFP
(FPT-48P-M26)
Yes
No
No
Flash A (160KB)
Yes
Yes
No
416 pin Plastic BGA
(BGA-416P-M02)
Emulated by ext. RAM
Yes
No
(for evaluation)
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
MCU without CAN controller
Persistent
Subclock Low Volt-
age Reset
Part number
Flash/ROM
Package
MB96F313ASA PMC-GSE2 *1
MB96F313AWA PMC-GSE2 *1
MB96F315ASA PMC-GSE2 *1
MB96F315AWA PMC-GSE2 *1
No
Flash A (96KB)
Flash A (160KB)
Yes
No
48 pins Plastic LQFP
(FPT-48P-M26)
No
Yes
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
72
FME-MB96310 rev 2
MB96310 Series
■ REVISION HISTORY
Revision
Date
Modification
Prelim 1
Prelim 2
2008-12-09 Creation
2009-01-09 • Interrupt vector table corrected (description of CAN2 interrupt)
• Low voltage detector spec updated (detection levels and stabilization time)
• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted
FME-MB96310 rev 2
73
MB96310 Series
FME-MB96310 rev 2
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.
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