MB96F348YSBPQC-GSE2_技术文档

MB96345/346, MB96F345

MB96F346/F347/F348

2

F MC-16FX, MB96340 Series, 16-bit

Proprietary Microcontroller Datasheet

MB96340 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The

CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new

16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the

same operation frequency, reduced power consumption and faster start-up time.

For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz

operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with

excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The

emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select

suitable operation frequencies for peripheral resources independent of the CPU speed.

MB96F345 : These devices are under development and specification is preliminary. These products under development may

change its specification without notice.

Cypress Semiconductor Corporation

Document Number: 002-04579 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 4, 2016

MB96340 Series

Features

Feature

Description

Technology

■ 0.18m CMOS

■ F²MC-16FX CPU

■ Up to 56 MHz internal, 17.8 ns instruction cycle time

■ Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different

addressing modes; barrel shift; variety of pointers)

CPU

■ 8-byte instruction execution queue

■ Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available

■ On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)

■ 3MHz-16MHzexternalcrystaloscillatorclock(maximumfrequencywhenusingceramicresonatordepends

on Q-factor).

■ Up to 56 MHz external clock for devices with fast clock input feature

■ 32-100 kHz subsystem quartz clock

System clock

■ 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog

■ Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC

oscillator, independently for CPU and 2 clock domains of peripherals.

■ Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode)

■ Clock modulator

■ Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power

consumption figures

On-chip voltage regulator

Low voltage reset

Code Security

■ Reset is generated when supply voltage is below minimum.

■ Protects ROM content from unintended read-out

■ Replaces ROM content

Memory Patch Function

DMA

■ Can also be used to implement embedded debug support

■ Automatic transfer function independent of CPU, can be assigned freely to resources

■ Fast Interrupt processing

Interrupts

Timers

■ 8 programmable priority levels

■ Non-Maskable Interrupt (NMI)

■ Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer,

17-bit Sub clock timer)

■ Watchdog Timer

■ Supports CAN protocol version 2.0 part A and B

■ ISO16845 certified

■ Bit rates up to 1 Mbit/s

■ 32 message objects

CAN

■ Each message object has its own identifier mask

■ Programmable FIFO mode (concatenation of message objects)

■ Maskable interrupt

■ Disabled Automatic Retransmission mode for Time Triggered CAN applications

■ Programmable loop-back mode for self-test operation

■ Full duplex USARTs (SCI/LIN)

■ Wide range of baud rate settings using a dedicated reload timer

■ Special synchronous options for adapting to different synchronous serial protocols

■ LIN functionality working either as master or slave LIN device

USART

Document Number: 002-04579 Rev. *A

Page 2 of 109

MB96340 Series

Feature

Description

■ Up to 400 kbps

I²C

■ Master and Slave functionality, 8-bit and 10-bit addressing

■ SAR-type

■ 10-bit resolution

A/D converter

■ Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion

mode, activation by software, external trigger or reload timer

A/D Converter Reference Volt- ■ 2 independent positive A/D converter reference voltages available

age switch

■ 16-bit wide

Reload Timers

Free Running Timers

Input Capture Units

■ Prescaler with 1/2¹, 1/2², 1/2³, 1/2⁴, 1/2⁵, 1/2⁶of peripheral clock frequency

■ Event count function

■ Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler

with 1, 1/2¹, 1/2², 1/2³, 1/2⁴, 1/2⁵, 1/2⁶, 1/2⁷,1/2⁸of peripheral clock frequency

■ 16-bit wide

■ Signals an interrupt upon external event

■ Rising edge, falling edge or rising & falling edge sensitive

■ 16-bit wide

Output Compare Units

■ Signals an interrupt when a match with 16-bit I/O Timer occurs

■ A pair of compare registers can be used to generate an output signal.

■ 16-bit down counter, cycle and duty setting registers

■ Interrupt at trigger, counter borrow and/or duty match

■ PWM operation and one-shot operation

Programmable Pulse Genera-

tor

■ Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow

as clock input

■ Can be triggered by software or reload timer

■ Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the

RC oscillator

■ Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)

■ Read/write accessible second/minute/hour registers

Real Time Clock

■ Can signal interrupts every half second/second/minute/hour/day

■ Internal clock divider and prescaler provide exact 1s clock

■ Edge sensitive or level sensitive

■ Interrupt mask and pending bit per channel

External Interrupts

■ Each available CAN channel RX has an external interrupt for wake-up

■ Selected USART channels SIN have an external interrupt for wake-up

■ Disabled after reset

■ Once enabled, can not be disabled other than by reset.

■ Level high or level low sensitive

Non Maskable Interrupt

■ Pin shared with external interrupt 0.

■ 8-bit or 16-bit bidirectional data

■ Up to 24-bit addresses

■ 6 chip select signals

External bus interface

■ Multiplexed address/data lines

■ Wait state request

■ External bus master possible

■ Timing programmable

Document Number: 002-04579 Rev. *A

Page 3 of 109

MB96340 Series

Feature

Description

■ Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined

thresholds

Alarm comparator

■ Threshold voltages defined externally or generated internally

■ Status is readable, interrupts can be masked separately

■ Virtually all external pins can be used as general purpose I/O

■ All push-pull outputs (except when used as I2C SDA/SCL line)

■ Bit-wise programmable as input/output or peripheral signal

■ Bit-wise programmable input enable

I/O Ports

■ Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL (TTL levels not supported

by all devices)

■ Bit-wise programmable pull-up resistor

■ Bit-wise programmable output driving strength for EMI optimization

Packages

■ 100-pin plastic QFP and LQFP

■ Supports automatic programming, Embedded Algorithm

■ Write/Erase/Erase-Suspend/Resume commands

■ A flag indicating completion of the algorithm

■ Number of erase cycles: 10,000 times

Flash Memory

■ Data retention time: 20 years

■ Erase can be performed on each sector individually

■ Sector protection

■ Flash Security feature to protect the content of the Flash

■ Low voltage detection during Flash erase

Document Number: 002-04579 Rev. *A

Page 4 of 109

MB96340 Series

Contents

1.

2.

3.

4.

5.

6.

7.

8.

9.

Product Lineup............................................................. 6

13.9 Pin handling when not using the A/D converter............ 58

13.10Notes on Power-on....................................................... 58

13.11Stabilization of power supply voltage ........................... 58

13.12Serial communication ................................................... 58

13.13Handling of Data Flash................................................. 58

Block Diagram.............................................................. 8

Pin Assignments.......................................................... 9

Pin Function Description .......................................... 11

Pin Circuit Type.......................................................... 13

I/O Circuit Type........................................................... 14

Memory Map............................................................... 17

User ROM Memory Map for Flash Devices ........... 19

User ROM Memory Map for Mask ROM Devices..... 22

14. Electrical Characteristics........................................... 59

14.1 Absolute Maximum Ratings.......................................... 59

14.2 Recommended Operating Conditions........................... 61

14.3 DC characteristics......................................................... 62

14.4 AC Characteristics........................................................ 71

14.5 Analog Digital Converter............................................... 89

14.6 Alarm Comparator......................................................... 93

14.7 Low Voltage Detector Characteristics........................... 95

14.8 Flash Memory Program/erase Characteristics.............. 97

10. Serial Programming Communication Interface....... 23

11. I/O Map........................................................................ 24

12. Interrupt Vector Table................................................ 52

15. Example Characteristics............................................ 98

16. Package Dimension MB96(F)34x LQFP 100P......... 102

17. Package Dimension MB96(F)34x QFP 100P........... 103

13. Handling Devices....................................................... 56

13.1 Latch-up prevention ..................................................... 56

13.2 Unused pins handling .................................................. 56

13.3 External clock usage.................................................... 56

13.4 Unused sub clock signal .............................................. 57

13.5 Notes on PLL clock mode operation............................ 57

13.6 Power supply pins (VCC/VSS)..................................... 57

13.7 Crystal oscillator and ceramic resonator circuit ........... 57

13.8 Turn on sequence of power supply to A/D converter and

analog inputs................................................................ 58

18. Ordering Information................................................ 104

18.1 MCU with CAN Controller ........................................... 104

18.2 MCU without CAN Controller...................................... 106

19. Revision History........................................................ 107

20. Main Changes in this Edition................................... 109

Document History ................................................................. 50

Document Number: 002-04579 Rev. *A

Page 5 of 109

MB96340 Series

1. Product Lineup

Features

MB96V300B

MB96(F)34x

Product type

Evaluation sample

Flash product: MB96F34x Mask ROM product: MB9634x

Product options

YS

RS

YW

RW

TS

Low voltage reset persistently on / Single clock

Low voltage reset can be disabled / Single clock

Low voltage reset persistently on / Dual clock

Low voltage reset can be disabled / Dual clock

indep. 32KB Flash / Low voltage reset persistently on / Single clock

indep. 32KB Flash / Low voltage reset can be disabled / Single clock

indep. 32KB Flash / Low voltage reset persistently on / Dual clock

indep. 32KB Flash / Low voltage reset can be disabled / Dual clock

64KB Data Flash / Low voltage reset persistently on / Single clock

64KB Data Flash / Low voltage reset can be disabled / Single clock

64KB Data Flash / Low voltage reset persistently on / Dual clock

64KB Data Flash / Low voltage reset can be disabled / Dual clock

No CAN / Low voltage reset can be disabled / Single clock devices

No CAN / indep. 32KB Flash / Low voltage reset can be disabled / Single clock

No CAN / Low voltage reset can be disabled / Dual clock

HS

TW

HW

FS

NA

DS

FW

DW

AS

CS

AW

CW

No CAN / indep. 32KB Flash / Low voltage reset can be disabled / Dual clock

Flash/ROM

160KB

RAM

8KB

MB96345Y ^[1], MB96345R ^[1]

MB96F345F ^[1], MB96F345D ^[1]

224KB

[Flash A: 160KB, Data

Flash A: 64KB]

8KB

ROM/Flash memory

emulation by external

RAM, 92KB internal

RAM

MB96F346Y, MB96346Y ^[1], MB96F346R, MB96346R ^[1], MB96F346A

MB96F347Y, MB96F347R, MB96F347A

288KB

416KB

544KB

16KB

24KB

MB96F348Y, MB96F348R, MB96F348A

576KB

[Flash A: 544KB, Flash

B: 32KB]

24KB

MB96F348T, MB96F348H, MB96F348C

Package

DMA

BGA416

FPT-100P-M20

6 channels

7 channels

FPT-100P-M22

16 channels

10 channels

USART

Document Number: 002-04579 Rev. *A

Page 6 of 109

MB96340 Series

Features

MB96V300B

MB96(F)34x

I²C

2 channels

A/D Converter

40 channels

24 channels

A/D Converter Reference Voltage

switch

yes

yes (except MB96F345Dyy or MB96F345Fyy)

4 channels + 1 channel (for PPG)

6 channels + 1

channel (for PPG)

16-bit Reload Timer

16-bit Free-Running Timer

16-bit Output Compare

16-bit Input Capture

4 channels

12 channels

2 channels

8 channels

16-bit Programmable Pulse

Generator

20 channels

5 channels

16 channels

MB96(F)34xAyy or MB96(F)34xCyy: no

MB96F345Dyy or MB96F345Fyy: 1 channel

others: 2 channels

CAN Interface

External Interrupts

Non-Maskable Interrupt

Real Time Clock

I/O Ports

16 channels

1 channel

1

136

80 for part number with suffix "W", 82 for part number with suffix "S"

2 channels

MB96F345Dyy or MB96F345Fyy: no

others: 2 channels

Alarm comparator

External bus interface

Chip select

Yes

Yes (multiplexed address/data)

6 signals

2 channels

Yes

Clock output function

Low voltage reset

On-chip RC-oscillator

Yes

[1]: These devices are under development and specification is preliminary. These products under development may change its

specification without notice.

Document Number: 002-04579 Rev. *A

Page 7 of 109

MB96340 Series

2. Block Diagram

Figure 1. Block diagram of MB96(F)34x

AD00 ... AD15

A16 ... A23

ALE

CKOT0, CKOT1

CKOTX0, CKOTX1

X0, X1

RDX

WR(L)X, WRHX

HRQ

X0A, X1A ^[1]

RSTX

MD0...MD2

HAKX

NMI, NMI_R

RDY

ECLK

LBX, UBX

CS0 ... CS5

Memory Patch

Unit

External Bus

Interface

Flash

Memory A

Flash Memory B

Clock &

Mode Controller

Interrupt

Controller

16FX

CPU

[2]

or Data Flash A

16FX Core Bus (CLKB)

Voltage

Regulator

DMA

Controller

Peripheral

Bus Bridge

Peripheral

Bus Bridge

Watchdog

RAM

Boot ROM

V_CC

V_SS

C

SDA0, SDA1

SCL0, SCL1

I2C

2 ch.

[3]

CAN

Interface

2 ch.

TX0, TX1

AV_CC

AV_SS

[3]

RX0, RX1

AVRH

10-bit ADC

24 ch.

[5]

AVRL/AVRH2

AN0 ... AN23

ADTG, ADTG_R

16-bit Reload

Timer

TIN0 ... TIN3

SIN0...SIN3, SIN2_R, SIN7_R...SIN9_R

SOT0...SOT3, SOT2_R, SOT7_R...SOT9_R

SCK0...SCK3, SCK2_R, SCK7_R...SCK9_R

USART

7 ch.

TOT0 ... TOT3

4 ch.

FRCK0

IN0 ... IN3

OUT0 ... OUT3

I/O Timer 0

ICU 0/1/2/3

OCU 0/1/2/3

[4]

ALARM0

Alarm

Comparator

[4]

*4

ALARM1

2 ch.

FRCK1

IN4 ... IN7

OUT4 ... OUT7

I/O Timer 1

ICU 4/5/6/7

OCU 4/5/6/7

TTG0 ... TTG15

PPG0 ... PPG15

16-bit PPG

16 ch.

RLT6

INT0 ... INT15

INT0_R ... INT2_R

INT4_R, INT5_R

INT7_R ... INT15_R

INT3_R1

External

Interrupt

Real Time

Clock

WOT

[1]: X0A, X1A only available on MB96(F)34xyWy

[2]: Flash B only available on MB96F34xCyy, MB96F34xHyy or MB96F34xTyy

Data Flash A only available on MB96F34xDyy or MB96F34xFyy

[3]: CAN interfaces are not available on MB96(F)34xAyy or MB96(F)34xCyy

CAN1 is not available on MB96F345Dyy or MB96F345Fyy

[4]: Alarm comparator is not available on MB96F345Dyy or MB96F345Fyy

[5]: A/D converter reference voltage switch is not available on MB96F345Dyy or MB96F345Fyy

Document Number: 002-04579 Rev. *A

Page 8 of 109

MB96340 Series

3. Pin Assignments

Figure 2. Pin assignment of MB96(F)34x (FPT-100P-M22)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

P00_4/AD04/INT12/SOT8_R

P00_5/AD05/INT13/SIN8_R

P00_6/AD06/INT14

P00_7/AD07/INT15

P01_0/AD08/CKOT1/TIN1

P01_1/AD09/CKOTX1/TOT1

P01_2/AD10/INT11_R/SIN3

P01_3/AD11/SOT3

P01_4/AD12/SCK3

Vcc

P07_5/AN21/INT5/SCK9_R

P07_4/AN20/INT4

P07_3/AN19/INT3

P07_2/AN18/INT2

P07_1/AN17/INT1

P07_0/AN16/INT0/NMI

Vss

P06_7/AN7/PPG7

P06_6/AN6/PPG6

P06_5/AN5/PPG5

P06_4/AN4/PPG4

P06_3/AN3/PPG3

P06_2/AN2/PPG2

P06_1/AN1/PPG1

P06_0/AN0/PPG0

AVss

QFP - 100

Vss

Package code (mold)

FPT-100P-M22

X1

X0

P01_5/AD13/INT7_R/SIN2_R

P01_6/AD14/SOT2_R

P01_7/AD15/SCK2_R

P02_0/A16/PPG12

P02_1/A17/PPG13

P02_2/A18/PPG14

P02_3/A19/PPG15

[4]

AVRL/AVRH2

AVRH

AVcc

100

P05_7/AN15/INT5_R

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

[1]:MB96(F)34xyWy: X0A, X1A

MB96(F)34xySy: P04_0, P04_1

[2]: TX0, RX0, TX1, RX1 are not available on MB96(F)34xAyy or MB96(F)34xCyy

TX1, RX1 are not available on MB96F345Dyy or MB96F345Fyy

[3]: ALARM0, ALARM1 are not available on MB96F345Dyy or MB96F345Fyy

[4]: AVRH2 is not available on MB96F345Dyy or MB96F345Fyy

(FPT-100P-M22)

Remark:

MB96(F)34x products are pin-compatible to F²MC-16LX family MB90340 series.

Document Number: 002-04579 Rev. *A

Page 9 of 109

MB96340 Series

Figure 3. Pin assignment of MB96(F)34x (FPT-100P-M20)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

MD1

MD2

P00_1AD01/INT9/SOT7_R

P00_2/AD02/INT10/SIN7_R

P00_3/AD03/INT11/SCK8_R

P00_4/AD04/INT12/SOT8_R

P00_5/AD05/INT13/SIN8_R

P00_6/AD06/INT14

P07_5/AN21/INT5/SCK9_R

P07_4/AN20/INT4

P07_3/AN19/INT3

P07_2/AN18/INT2

P07_1/AN17/INT1

P07_0/AN16/INT0/NMI

Vss

P00_7/AD07/INT15

P01_0/AD08/CKOT1/TIN1

P01_1/AD09/CKOTX1/TOT1

P01_2/AD10/INT11_R/SIN3

P01_3/AD11/SOT3

P06_7/AN7/PPG7

P06_6/AN6/PPG6

P06_5/AN5/PPG5

P06_4/AN4/PPG4

P06_3/AN3/PPG3

P06_2/AN2/PPG2

P06_1/AN1/PPG1

P06_0/AN0/PPG0

AVss

LQFP - 100

P01_4/AD12/SCK3

Vcc

Vss

Package code (mold)

FPT-100P-M20

X1

X0

P01_5/AD13/INT7_R/SIN2_R

P01_6/AD14/SOT2_R

P01_7/AD15/SCK2_R

P02_0/A16/PPG12

[4]

AVRL/AVRH2

AVRH

P02_1/A17/PPG13

AVcc

P02_2/A18/PPG14

P05_7/AN15/INT5_R

P05_6/AN14/INT4_R

P05_5/AN13/INT0_R/NMI_R

P05_4/AN12/TOT3/INT2_R

P02_3/A19/PPG15

P02_4/A20/TTG8/TTG0/IN0

P02_5/A21/TTG9/TTG1/IN1/ADTG_R

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

[1]:MB96(F)34xyWy: X0A, X1A

MB96(F)34xySy: P04_0, P04_1

[2]: TX0, RX0, TX1, RX1 are not available on MB96(F)34xAyy or MB96(F)34xCyy

TX1, RX1 are not available on MB96F345Dyy or MB96F345Fyy

[3]: ALARM0, ALARM1 are not available on MB96F345Dyy or MB96F345Fyy

[4]: AVRH2 is not available on MB96F345Dyy or MB96F345Fyy

(FPT-100P-M20)

Remark:

MB96(F)34x products are pin-compatible to F²MC-16LX family MB90340 series.

Document Number: 002-04579 Rev. *A

Page 10 of 109

MB96340 Series

4. Pin Function Description

Table 1: Pin Function description

Pin name

ADn

Feature

Description

External bus interface (multiplexed mode) address output and data

input/output

External bus

ADTG

ADTG_R

ALARMn

ALE

ADC

A/D converter trigger input

Relocated A/D converter trigger input

Alarm Comparator n input

Alarm comparator

External bus

ADC

External bus Address Latch Enable output

External bus address output

An

ANn

A/D converter channel n input

AV_CC

Supply

Analog circuits power supply

AVRH

AVRH2

AVRL

AV_SS

ADC

A/D converter high reference voltage input

Alternative A/D converter high reference voltage input

A/D converter low reference voltage input

Analog circuits power supply

ADC

Supply

C

CKOTn

CKOTXn

ECLK

CSn

Voltage regulator

Clock output function

External bus

Free Running Timer

External bus

ICU

Internally regulated power supply stabilization capacitor pin

Clock Output function n output

Clock Output function n inverted output

External bus clock output

External bus chip select n output

Free Running Timer n input

FRCKn

HAKX

HRQ

External bus Hold Acknowledge

External bus Hold Request

INn

Input Capture Unit n input

INTn

External Interrupt

External bus

Core

External Interrupt n input

INTn_R

LBX

Relocated External Interrupt n input

External Bus Interface Lower Byte select strobe output

Input pins for specifying the operating mode.

Non-Maskable Interrupt input

MDn

NMI

External Interrupt

OCU

NMI_R

OUTn

Pxx_n

PPGn

RDX

Relocated Non-Maskable Interrupt input

Output Compare Unit n waveform output

General purpose IO

GPIO

PPG

Programmable Pulse Generator n output

External bus interface read strobe output

External bus

Document Number: 002-04579 Rev. *A

Page 11 of 109

MB96340 Series

Table 1: Pin Function description

Pin name

Feature

Description

RDY

RSTX

RXn

External bus

Core

External bus interface external wait state request input

Reset input

CAN

CAN interface n RX input

SCKn

SCKn_R

SCLn

USART

I2C

USART n serial clock input/output

Relocated USART n serial clock input/output

I²C interface n clock I/O input/output

I²C interface n serial data I/O input/output

USART n serial data input

SDAn

SINn

I2C

USART

SINn_R

SOTn

SOTn_R

TINn

USART

Relocated USART n serial data input

USART n serial data output

USART

Relocated USART n serial data output

Reload Timer n event input

Reload Timer

PPG

TOTn

TTGn

TXn

Reload Timer n output

Programmable Pulse Generator n trigger input

CAN interface n TX output

CAN

UBX

External bus

Supply

External Bus Interface Upper Byte select strobe output

Power supply

V_CC

V_SS

Supply

RTC

Power supply

Real Timer clock output

WOT

WRHX

WRLX/WRX

X0

External bus

Clock

External bus High byte write strobe output

External bus Low byte / Word write strobe output

Oscillator input

X0A

Clock

Subclock Oscillator input (only for devices with suffix "W")

Oscillator output

X1

Clock

X1A

Clock

Subclock Oscillator output (only for devices with suffix "W")

Document Number: 002-04579 Rev. *A

Page 12 of 109

MB96340 Series

5. Pin Circuit Type

Table 2: Pin circuit types

FPT-100P-M20

FPT-100P-M22

Circuit

type ^[1]

Pin no.

type ^[1]

Pin no.

1-10

H

1-12

H

B ^[2]

11,12

13, 14

H ^[3]

11,12

13,14

15

13, 14

15,16

17

Supply

F

16,17

18-21

22-29

30

H

18,19

20-23

24-31

32

H

N

I

Supply

31-32

33

G

33-34

35

G

Supply

34 to 41

42

I

36 to 43

44

I

Supply

43 to 48

49 to 51

52

I

45 to 50

51 to 53

54

I

C

E

53 to 54

55 to 62

63, 64

65 to 87

88,89

90, 91

92-100

I

55 to 56

57 to 64

65, 66

67 to 89

90, 91

92, 93

94 to 100

I

H

Supply

H

Supply

H

Supply

A

Supply

A

H

[1]: Please refer to “ I/O Circuit Type” for details on the I/O circuit types

[2]: Devices with suffix ”W”

[3]: Devices without suffix ”W”

Document Number: 002-04579 Rev. *A

Page 13 of 109

MB96340 Series

6. I/O Circuit Type

Type

A

Circuit

Remarks

High-speed oscillation circuit:

■ Programmable between oscillation mode (external crystal

or resonator connected to X0/X1 pins) and Fast external

Clock Input (FCI) mode (external clock connected to X0

pin)

X1

R

■ Programmable feedback resistor = approx. 2 * 0.5 M.

Feedback resistor is grounded in the center when the

oscillator is disabled or in FCI mode

0

1

Xout

MRFBE

FCI

R

X0

FCI or osc disable

B

Low-speed oscillation circuit:

■ Programmable feedback resistor = approx. 2 * 5 M.

Feedback resistor is grounded in the center when the

oscillator is disabled

Xout

X1A

R

SRFBE

R

X0A

osc disable

C

■ Mask ROM and EVA device:CMOS Hysteresis input pin

■ Flash device:CMOS input pin

R

Hysteresis

inputs

E

■ CMOS Hysteresis input pin

■ Pull-up resistor value: approx. 50 k

Pull-up

Resistor

R

Hysteresis

inputs

Document Number: 002-04579 Rev. *A

Page 14 of 109

MB96340 Series

Type

Circuit

Remarks

F

■ Power supply input protection circuit

G

■ A/D converter ref+ (AVRH/AVRH2) power supply input pin

with protection circuit

■ Flashdevicesdonothave a protectioncircuitagainstVCC

ANE

AVR

for pins AVRH/AVRH2

■ Devices without AVRH reference switch do not have an

analog switch for the AVRL pin

ANE

H

■ CMOS level output (programmable I_OL= 5mA, I_OH= -5mA

and I_OL= 2mA, I_OH= -2mA)

pull-up control

Pout

■ 2 different CMOS hysteresis inputs with input shutdown

function *

■ Automotive input with input shutdown function

■ TTL input with input shutdown function *

■ Programmable pull-up resistor: 50k approx.

*MB96F345Dyy or MB96F345Fyy: Only Automotive input

and CMOS hysteresis input (0.7/0.3) are supported

Nout

R

Hysteresis input

Standby control

for input shutdown

Hysteresis input

Automotive input

TTL input

Standby control

for input shutdown

Standby control

for input shutdown

Standby control

for input shutdown

Document Number: 002-04579 Rev. *A

Page 15 of 109

MB96340 Series

Type

Circuit

Remarks

I

■ CMOS level output (programmable I_OL= 5mA, I_OH= -5mA

and I_OL= 2mA, I_OH= -2mA)

Pull-up control

■ 2 different CMOS hysteresis inputs with input shutdown

function *

■ Automotive input with input shutdown function

■ TTL input with input shutdown function *

■ Programmable pull-up resistor: 50k approx.

■ Analog input

Pout

Nout

*MB96F345Dyy or MB96F345Fyy: Only Automotive input

and CMOS hysteresis input (0.7/0.3) are supported

R

Hysteresis input

Standby control

for input shutdown

Hysteresis input

Automotive input

Standby control

for input shutdown

Standby control

for input shutdown

TTL input

Standby control

for input shutdown

Analog input

N

■ CMOS level output (I_OL= 3mA, I_OH= -3mA)

■ 2 different CMOS hysteresis inputs with input shutdown

pull-up control

Pout

function *

■ Automotive input with input shutdown function

■ TTL input with input shutdown function *

■ Programmable pull-up resistor: 50k approx.

*MB96F345Dyy or MB96F345Fyy: Only Automotive input

and CMOS hysteresis input (0.7/0.3) are supported

Nout

R

Hysteresis input

Standby control

for input shutdown

Standby control

for input shutdown

Hysteresis input

Automotive input

TTL input

Standby control

for input shutdown

Standby control

for input shutdown

Document Number: 002-04579 Rev. *A

Page 16 of 109

MB96340 Series

7. Memory Map

MB96V300B

MB96(F)34x

FF:FFFF

H

USER ROM /

External Bus^[4]

Emulation ROM

DE:0000

H

External Bus

10:0000

0F:E000

H

Boot-ROM

Reserved

Boot-ROM

Reserved

0F:0000

0C:0000

H

DATA FLASH /

Reserved^[4]

0E:0000

02:0000

H

External RAM

Reserved

[2]

Internal RAM

bank 1

Internal RAM

RAMEND1

RAM availability depending

on the device

[2]

bank 1

RAMSTART1

01:0000

00:8000

Reserved

H

ROM/RAM MIRROR

Internal RAM

bank 0

[2]

RAMSTART0

Internal RAM

bank 0

Reserved

External Bus end

address^[2]

[3]

External Bus

RAMSTART0

External Bus

Peripherals

00:0C00

H

Peripherals

00:0380

00:0180

00:0100

00:00F0

00:0000

H

GPR^[1]

DMA

GPR^[1]

DMA

External Bus

Peripheral

External Bus

Peripheral

[1]: Unused GPR banks can be used as RAM area

[2]: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.

[3]: For EVA device, RAMSTART0 depends on the configuration of the emulated device.

[4]: For details about USER ROM area or DATA FLASH area, see the User ROM Memory Map For Flash Devices and

User ROM Memory Map for Mask ROM Devices on the following pages.

The External Bus area and DMA area are only available if the device contains the corresponding resource.

The available RAM and ROM area depends on the device.

Document Number: 002-04579 Rev. *A

Page 17 of 109

MB96340 Series

■ RAM Start/End and External Bus End Addresses

Bank 0

Bank 1

External Bus

end address

Devices

RAMSTART0

RAMSTART1

RAMEND1

RAM size RAM size

MB96(F)345

MB96(F)346,MB96F347

MB96F348

8KByte

16KByte

24KByte

-

00:21FF_H

00:6240_H

00:4240_H

00:2240_H

-

Document Number: 002-04579 Rev. *A

Page 18 of 109

MB96340 Series

8. User ROM Memory Map For Flash Devices

MB96F345D

MB96F345F

Flash size 160kByte

+64KByte Data Flash

Alternative mode Flash memory

CPU address

mode address

FF:FFFF

3F:FFFF

H

S39 - 64K

S38 - 64K

FF:0000

3F:0000

H

Flash A

FE:FFFF

3E:FFFF

H

FE:0000

3E:0000

H

FD:FFFF

3D:FFFF

H

FD:0000

3D:0000

H

FC:FFFF

3C:FFFF

H

FC:0000

3C:0000

H

FB:FFFF

3B:FFFF

H

FB:0000

3B:0000

H

FA:FFFF

FA:0000

3A:FFFF

H

3A:0000

H

F9:FFFF

F9:0000

39:FFFF

39:0000

H

F8:FFFF

F8:0000

38:FFFF

38:0000

H

F7:FFFF

37:FFFF

H

F7:0000

37:0000

H

F6:FFFF

36:FFFF

H

External bus

F6:0000

36:0000

H

F5:FFFF

35:FFFF

H

F5:0000

35:0000

H

F4:FFFF

34:FFFF

H

F4:0000

34:0000

H

F3:FFFF

33:FFFF

H

F3:0000

33:0000

H

F2:FFFF

32:FFFF

H

F2:0000

32:0000

H

F1:FFFF

31:FFFF

H

F1:0000

31:0000

H

F0:FFFF

30:FFFF

H

F0:0000

30:0000

H

E0:FFFF

H

E0:0000

H

DF:FFFF

H

Reserved

SA3 - 8K

SA2 - 8K

SA1 - 8K

DF:8000

H

DF:7FFF

1F:7FFF

H

DF:6000

1F:6000

H

DF:5FFF

1F:5FFF

H

DF:4000

1F:4000

H

Flash A

DF:3FFF

1F:3FFF

H

DF:2000

1F:2000

H

DF:1FFF

DF:0000

1F:1FFF

H

[1]

SA0 - 8K

1F:0000

H

DE:FFFF

H

Reserved

DE:0000

0E:FFFF

0E:FF00

(0E:FFFF

(0E:FF00 )

H

)

H

[2]

Data Flash A

SDA0-256

0E:FEFF

H

Reserved

SDA4-16K

SDA3-16K

SDA2-16K

SDA1-16K

Reserved

0E:0000

0D:FFFF

0D:C000

(0F:FFFF )

H

(0F:C000

)

H

0D:BFFF

(0F:BFFF

)

H

0D:8000

(0F:8000

)

H

0D:7FFF

(0F:7FFF

H

0D:4000

(0F:4000

)

H

0D:3FFF

(0F:3FFF

H

(0F:0000 )

H

0D:0000

0C:FFFF

H

0C:0000

[1]: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000_H- DF:007F_H

[2]: Sector SDA0 contains the ROM Configuration Block RCBDA at CPU address DE:FF00_H- DE:FF2F_H

Document Number: 002-04579 Rev. *A

Page 19 of 109

MB96340 Series

MB96F346Y

MB96F346R

MB96F346A

MB96F347Y

MB96F347R

MB96F347A

Flash size

288kByte

Flash size

416kByte

Alternative mode Flash memory

CPU address mode address

FF:FFFF

3F:FFFF

H

S39 - 64K

S38 - 64K

S37 - 64K

S36 - 64K

S39 - 64K

S38 - 64K

S37 - 64K

S36 - 64K

S35 - 64K

S34 - 64K

FF:0000

3F:0000

H

FE:FFFF

3E:FFFF

H

FE:0000

3E:0000

H

FD:FFFF

3D:FFFF

H

FD:0000

3D:0000

H

Flash A

FC:FFFF

3C:FFFF

H

FC:0000

3C:0000

H

FB:FFFF

3B:FFFF

H

FB:0000

3B:0000

H

FA:FFFF

3A:FFFF

H

FA:0000

3A:0000

H

F9:FFFF

F9:0000

39:FFFF

39:0000

H

F8:FFFF

F8:0000

38:FFFF

38:0000

H

F7:FFFF

37:FFFF

H

F7:0000

37:0000

H

F6:FFFF

F6:0000

36:FFFF

36:0000

H

F5:FFFF

F5:0000

35:FFFF

35:0000

H

External bus

F4:FFFF

F4:0000

34:FFFF

34:0000

H

External bus

F3:FFFF

F3:0000

33:FFFF

33:0000

H

F2:FFFF

32:FFFF

H

F2:0000

32:0000

H

F1:FFFF

F1:0000

31:FFFF

31:0000

H

F0:FFFF

F0:0000

30:FFFF

30:0000

H

E0:FFFF

H

E0:0000

DF:FFFF

DF:8000

H

Reserved

SA3 - 8K

SA2 - 8K

SA1 - 8K

Reserved

SA3 - 8K

SA2 - 8K

SA1 - 8K

DF:7FFF

1F:7FFF

H

DF:6000

1F:6000

H

DF:5FFF

1F:5FFF

H

DF:4000

1F:4000

H

Flash A

DF:3FFF

1F:3FFF

H

DF:2000

1F:2000

H

DF:1FFF

1F:1FFF

1F:0000

H

[1]

SA0 - 8K

DF:0000

H

DE:FFFF

H

Reserved

DE:0000

H

[1]: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000_H- DF:007F_H

Document Number: 002-04579 Rev. *A

Page 20 of 109

MB96340 Series

MB96F348Y

MB96F348R

MB96F348A

MB96F348T

MB96F348H

MB96F348C

Flash size

544kByte

Flash size

576kByte

Alternative mode Flash memory

CPU address mode address

FF:FFFF

3F:FFFF

H

S39 - 64K

S38 - 64K

S37 - 64K

S36 - 64K

S35 - 64K

S34 - 64K

S33 - 64K

S32 - 64K

S39 - 64K

S38 - 64K

S37 - 64K

S36 - 64K

S35 - 64K

S34 - 64K

S33 - 64K

S32 - 64K

FF:0000

3F:0000

H

FE:FFFF

3E:FFFF

H

FE:0000

3E:0000

H

FD:FFFF

3D:FFFF

H

FD:0000

3D:0000

H

FC:FFFF

3C:FFFF

H

FC:0000

3C:0000

H

Flash A

FB:FFFF

3B:FFFF

H

FB:0000

3B:0000

H

FA:FFFF

3A:FFFF

H

FA:0000

3A:0000

H

F9:FFFF

39:FFFF

H

F9:0000

39:0000

H

F8:FFFF

38:FFFF

H

F8:0000

38:0000

H

F7:FFFF

37:FFFF

H

F7:0000

37:0000

H

F6:FFFF

36:FFFF

H

F6:0000

36:0000

H

F5:FFFF

35:FFFF

H

F5:0000

35:0000

H

F4:FFFF

34:FFFF

H

F4:0000

34:0000

H

F3:FFFF

33:FFFF

H

External bus

F3:0000

33:0000

H

F2:FFFF

32:FFFF

H

F2:0000

32:0000

H

F1:FFFF

31:FFFF

H

F1:0000

31:0000

H

F0:FFFF

30:FFFF

H

F0:0000

30:0000

H

E0:FFFF

H

E0:0000

H

DF:FFFF

H

Reserved

SA3 - 8K

SA2 - 8K

SA1 - 8K

Reserved

SA3 - 8K

SA2 - 8K

SA1 - 8K

DF:8000

H

DF:7FFF

1F:7FFF

H

DF:6000

1F:6000

H

DF:5FFF

1F:5FFF

H

DF:4000

1F:4000

H

Flash A

DF:3FFF

1F:3FFF

H

DF:2000

1F:2000

H

DF:1FFF

1F:1FFF

1F:0000

H

[1]

SA0 - 8K

DF:0000

H

DE:FFFF

H

Reserved

SB3 - 8K

SB2 - 8K

SB1 - 8K

DE:8000

DE:7FFF

DE:6000

DE:5FFF

DE:4000

DE:3FFF

DE:2000

H

1E:7FFF

H

1E:6000

H

1E:5FFF

H

Reserved

1E:4000

H

Flash B

1E:3FFF

H

1E:2000

H

DE:1FFF

1E:1FFF

H

[2]

SB0 - 8K

DE:0000

1E:0000

H

[1]: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000_H- DF:007F_H

[2]: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000_H- DE:002F_H

Document Number: 002-04579 Rev. *A

Page 21 of 109

MB96340 Series

9. User ROM Memory Map for Mask ROM Devices

MB96345

MB96346

ROM size

160kByte

ROM size

288kByte

CPU address

FF:FFFF

H

FF:0000

FE:FFFF

FE:0000

FD:FFFF

FD:0000

FC:FFFF

FC:0000

H

128K ROM

Reserved

H

256K ROM

H

FB:FFFF

E0:0000

H

External bus

Reserved

External bus

Reserved

DF:FFFF

H

DF:8000

H

DF:7FFF

H

32K ROM

DF:0080

DF:007F

DF:0000

H

ROM configuration

block RCB

ROM configuration

block RCB

DE:FFFF

H

Reserved

DE:0000

H

Document Number: 002-04579 Rev. *A

Page 22 of 109

MB96340 Series

10. Serial Programming Communication Interface

Table 3: USART pins for Flash serial programming (MD[2:0] = 010, Serial

Communication mode)

MB96F34x

Pin number

LQFP-100

Pin number

QFP-100

Normal function

USART Number

USART0

57

58

59

60

61

62

22

23

24

85

86

87

59

60

61

62

63

64

24

25

26

87

88

89

SIN0

SOT0

SCK0

SIN1

USART1

USART2

USART3

SOT1

SCK1

SIN2

SOT2

SCK2

SIN3

SOT3

SCK3

Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor

to support at least port P00_1 on pin 76/78.If handshaking is used by the tool but P00_1 is not available in customer’s

application, Cypress suggests to the customer to check the tool manual or to contact the tool vendor for alternative

handshaking pins.

Document Number: 002-04579 Rev. *A

Page 23 of 109

MB96340 Series

11. I/O Map

Table 4: I/O map MB96(F)34x

Abbreviation

8-bit access

Abbreviation

Access

Address

Register

16-bit access

000000_H

000001_H

000002_H

000003_H

000004_H

000005_H

000006_H

000007_H

000008_H

000009_H

00000A_H

00000B_H-000017_H

000018_H

000019_H

00001A_H

00001B_H

00001C_H

00001D_H

00001E_H

00001F_H

000020_H

000021_H

000022_H

000023_H

000024_H

000025_H

000026_H

000027_H

000028_H

000029_H

00002A_H

I/O Port P00 - Port Data Register

I/O Port P01 - Port Data Register

PDR00

PDR01

PDR02

PDR03

PDR04

PDR05

PDR06

PDR07

PDR08

PDR09

PDR10

R/W

-

I/O Port P02 - Port Data Register

I/O Port P03 - Port Data Register

I/O Port P04 - Port Data Register

I/O Port P05 - Port Data Register

I/O Port P06 - Port Data Register

I/O Port P07 - Port Data Register

I/O Port P08 - Port Data Register

I/O Port P09 - Port Data Register

I/O Port P10 - Port Data Register

Reserved

ADC0 - Control Status register Low

ADC0 - Control Status register High

ADC0 - Data Register Low

ADCSL

ADCSH

ADCRL

ADCRH

ADCS

ADCR

ADSR

R/W

R

ADC0 - Data Register High

R

ADC0 - Setting Register

R/W

-

ADC0 - Setting Register

ADC0 - Extended Configuration Register

Reserved

ADECR

FRT0 - Data register of free-running timer

FRT0 - Control status register of free-running timer Low

FRT0 - Control status register of free-running timer High

FRT1 - Data register of free-running timer

FRT1 - Control status register of free-running timer Low

FRT1 - Control status register of free-running timer High

OCU0 - Output Compare Control Status

OCU1 - Output Compare Control Status

OCU0 - Compare Register

TCDT0

TCCS0

TCDT1

TCCS1

R/W

TCCSL0

TCCSH0

TCCSL1

TCCSH1

OCS0

OCS1

OCCP0

Document Number: 002-04579 Rev. *A

Page 24 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00002B_H

00002C_H

00002D_H

00002E_H

00002F_H

000030_H

000031_H

000032_H

000033_H

000034_H

000035_H

000036_H

000037_H

000038_H

000039_H

00003A_H

00003B_H

00003C_H

00003D_H

00003E_H

00003F_H

000040_H

000041_H

000042_H

000043_H

000044_H

000045_H

000046_H

000047_H

000048_H

000049_H

00004A_H

OCU0 - Compare Register

R/W

OCU1 - Compare Register

OCCP1

R/W

R

OCU2 - Output Compare Control Status

OCU3 - Output Compare Control Status

OCU2 - Compare Register

OCS2

OCS3

OCCP2

OCCP3

OCU2 - Compare Register

OCU3 - Compare Register

OCU4 - Output Compare Control Status

OCU5 - Output Compare Control Status

OCU4 - Compare Register

OCS4

OCS5

OCCP4

OCCP5

OCU4 - Compare Register

OCU5 - Compare Register

OCU6 - Output Compare Control Status

OCU7 - Output Compare Control Status

OCU6 - Compare Register

OCS6

OCS7

OCCP6

OCCP7

OCU6 - Compare Register

OCU7 - Compare Register

ICU0/ICU1 - Control Status Register

ICU0/ICU1 - Edge register

ICS01

ICE01

ICU0 - Capture Register Low

ICU0 - Capture Register High

ICU1 - Capture Register Low

ICU1 - Capture Register High

ICU2/ICU3 - Control Status Register

ICU2/ICU3 - Edge register

IPCPL0

IPCPH0

IPCPL1

IPCPH1

ICS23

IPCP0

IPCP1

R

R/W

R

ICE23

ICU2 - Capture Register Low

ICU2 - Capture Register High

ICU3 - Capture Register Low

IPCPL2

IPCPH2

IPCPL3

IPCP2

IPCP3

R

Document Number: 002-04579 Rev. *A

Page 25 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00004B_H

00004C_H

00004D_H

00004E_H

00004F_H

000050_H

000051_H

000052_H

000053_H

000054_H

000055_H

000056_H

000057_H

000058_H

000059_H

00005A_H

00005B_H

00005C_H

00005D_H

00005E_H

00005F_H

000060_H

000061_H

000062_H

000063_H

000064_H

000065_H

000066_H

000067_H

ICU3 - Capture Register High

IPCPH3

ICS45

R

ICU4/ICU5 - Control Status Register

ICU4/ICU5 - Edge register

R/W

ICE45

ICU4 - Capture Register Low

IPCPL4

IPCPH4

IPCPL5

IPCPH5

ICS67

IPCP4

IPCP5

R

ICU4 - Capture Register High

ICU5 - Capture Register Low

R

ICU5 - Capture Register High

R

ICU6/ICU7 - Control Status Register

ICU6/ICU7 - Edge register

R/W

R

ICE67

ICU6 - Capture Register Low

IPCPL6

IPCPH6

IPCPL7

IPCPH7

ENIR0

IPCP6

IPCP7

ICU6 - Capture Register High

R

ICU7 - Capture Register Low

R

ICU7 - Capture Register High

R

EXTINT0 - External Interrupt Enable Register

EXTINT0 - External Interrupt Interrupt request Register

EXTINT0 - External Interrupt Level Select Low

EXTINT0 - External Interrupt Level Select High

EXTINT1 - External Interrupt Enable Register

EXTINT1 - External Interrupt Interrupt request Register

EXTINT1 - External Interrupt Level Select Low

EXTINT1 - External Interrupt Level Select High

RLT0 - Timer Control Status Register Low

RLT0 - Timer Control Status Register High

RLT0 - Reload Register - for writing

RLT0 - Reload Register - for reading

RLT0 - Reload Register - for writing

RLT0 - Reload Register - for reading

RLT1 - Timer Control Status Register Low

RLT1 - Timer Control Status Register High

RLT1 - Reload Register - for writing

RLT1 - Reload Register - for reading

RLT1 - Reload Register - for writing

R/W

W

EIRR0

ELVRL0

ELVRH0

ENIR1

ELVR0

EIRR1

ELVRL1

ELVRH1

TMCSRL0

TMCSRH0

ELVR1

TMCSR0

TMRLR0

TMR0

R

W

R

TMCSRL1

TMCSRH1

TMCSR1

R/W

W

TMRLR1

TMR1

R

W

Document Number: 002-04579 Rev. *A

Page 26 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000067_H

000068_H

000069_H

00006A_H

00006B_H

00006C_H

00006D_H

00006E_H

00006F_H

000070_H

000071_H

000072_H

000073_H

000074_H

000075_H

000076_H

000077_H

000078_H

000079_H

00007A_H

00007B_H

00007C_H

00007D_H

00007E_H

00007F_H

000080_H

RLT1 - Reload Register - for reading

RLT2 - Timer Control Status Register Low

RLT2 - Timer Control Status Register High

RLT2 - Reload Register - for writing

R

TMCSRL2

TMCSRH2

TMCSR2

R/W

W

TMRLR2

TMR2

RLT2 - Reload Register - for reading

RLT2 - Reload Register - for writing

R

W

RLT2 - Reload Register - for reading

RLT3 - Timer Control Status Register Low

RLT3 - Timer Control Status Register High

RLT3 - Reload Register - for writing

R

TMCSRL3

TMCSRH3

TMCSR3

R/W

W

TMRLR3

TMR3

RLT3 - Reload Register - for reading

RLT3 - Reload Register - for writing

R

W

RLT3 - Reload Register - for reading

RLT6 - Timer Control Status Register Low (dedic. RLT for PPG)

RLT6 - Timer Control Status Register High (dedic. RLT for PPG)

RLT6 - Reload Register (dedic. RLT for PPG) - for writing

RLT6 - Reload Register (dedic. RLT for PPG) - for reading

RLT6 - Reload Register (dedic. RLT for PPG) - for writing

RLT6 - Reload Register (dedic. RLT for PPG) - for reading

PPG3-PPG0 - General Control register 1 Low

PPG3-PPG0 - General Control register 1 High

PPG3-PPG0 - General Control register 2 Low

PPG3-PPG0 - General Control register 2 High

PPG0 - Timer register

R

TMCSRL6

TMCSRH6

TMCSR6

R/W

W

TMRLR6

TMR6

R

W

R

GCN1L0

GCN1H0

GCN2L0

GCN2H0

GCN10

GCN20

PTMR0

PCSR0

PDUT0

PCN0

R/W

R

PPG0 - Timer register

R

PPG0 - Period setting register

W

PPG0 - Period setting register

W

PPG0 - Duty cycle register

W

PPG0 - Duty cycle register

W

PPG0 - Control status register Low

PCNL0

PCNH0

R/W

R

PPG0 - Control status register High

PPG1 - Timer register

PTMR1

Document Number: 002-04579 Rev. *A

Page 27 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000081_H

000082_H

000083_H

000084_H

000085_H

000086_H

000087_H

000088_H

000089_H

00008A_H

00008B_H

00008C_H

00008D_H

00008E_H

00008F_H

000090_H

000091_H

000092_H

000093_H

000094_H

000095_H

000096_H

000097_H

000098_H

000099_H

00009A_H

00009B_H

00009C_H

00009D_H

00009E_H

00009F_H

0000A0_H

PPG1 - Timer register

PPG1 - Period setting register

R

PCSR1

PDUT1

PCN1

W

PPG1 - Period setting register

PPG1 - Duty cycle register

W

PPG1 - Duty cycle register

W

PPG1 - Control status register Low

PPG1 - Control status register High

PPG2 - Timer register

PCNL1

PCNH1

R/W

R

PTMR2

PCSR2

PDUT2

PCN2

PPG2 - Timer register

R

PPG2 - Period setting register

PPG2 - Duty cycle register

W

PPG2 - Duty cycle register

W

PPG2 - Control status register Low

PPG2 - Control status register High

PPG3 - Timer register

PCNL2

PCNH2

R/W

R

PTMR3

PCSR3

PDUT3

PCN3

PPG3 - Timer register

R

PPG3 - Period setting register

PPG3 - Duty cycle register

W

PPG3 - Duty cycle register

W

PPG3 - Control status register Low

PPG3 - Control status register High

PPG7-PPG4 - General Control register 1 Low

PPG7-PPG4 - General Control register 1 High

PPG7-PPG4 - General Control register 2 Low

PPG7-PPG4 - General Control register 2 High

PPG4 - Timer register

PCNL3

PCNH3

R/W

R

GCN1L1

GCN1H1

GCN2L1

GCN2H1

GCN11

GCN21

PTMR4

PCSR4

PDUT4

PPG4 - Timer register

R

PPG4 - Period setting register

PPG4 - Duty cycle register

W

Document Number: 002-04579 Rev. *A

Page 28 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0000A1_H

0000A2_H

0000A3_H

0000A4_H

0000A5_H

0000A6_H

0000A7_H

0000A8_H

0000A9_H

0000AA_H

0000AB_H

0000AC_H

0000AD_H

0000AE_H

0000AF_H

0000B0_H

0000B1_H

0000B2_H

0000B3_H

0000B4_H

0000B5_H

0000B6_H

0000B7_H

0000B8_H

0000B9_H

0000BA_H

0000BB_H

0000BC_H

0000BD_H

0000BE_H

0000BF_H

0000C0_H

PPG4 - Duty cycle register

W

PPG4 - Control status register Low

PPG4 - Control status register High

PPG5 - Timer register

PCNL4

PCNH4

PCN4

PTMR5

PCSR5

PDUT5

PCN5

R/W

R

PPG5 - Timer register

R

PPG5 - Period setting register

W

PPG5 - Period setting register

W

PPG5 - Duty cycle register

W

PPG5 - Duty cycle register

W

PPG5 - Control status register Low

PPG5 - Control status register High

I2C0 - Bus Status Register

PCNL5

PCNH5

IBSR0

IBCR0

ITBAL0

ITBAH0

ITMKL0

ITMKH0

ISBA0

R/W

R

I2C0 - Bus Control Register

R/W

R

I2C0 - Ten bit Slave address Register Low

I2C0 - Ten bit Slave address Register High

I2C0 - Ten bit Address mask Register Low

I2C0 - Ten bit Address mask Register High

I2C0 - Seven bit Slave address Register

I2C0 - Seven bit Address mask Register

I2C0 - Data Register

ITBA0

ITMK0

ISMK0

IDAR0

ICCR0

IBSR1

IBCR1

ITBAL1

ITBAH1

ITMKL1

ITMKH1

ISBA1

I2C0 - Clock Control Register

I2C1 - Bus Status Register

I2C1 - Bus Control Register

R/W

I2C1 - Ten bit Slave address Register Low

I2C1 - Ten bit Slave address Register High

I2C1 - Ten bit Address mask Register Low

I2C1 - Ten bit Address mask Register High

I2C1 - Seven bit Slave address Register

I2C1 - Seven bit Address mask Register

I2C1 - Data Register

ITBA1

ITMK1

ISMK1

IDAR1

ICCR1

SMR0

I2C1 - Clock Control Register

USART0 - Serial Mode Register

Document Number: 002-04579 Rev. *A

Page 29 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0000C1_H

0000C2_H

0000C3_H

0000C4_H

0000C5_H

0000C6_H

0000C7_H

0000C8_H

0000C9_H

0000CA_H

0000CB_H

0000CC_H

0000CD_H

0000CE_H

0000CF_H

0000D0_H

0000D1_H

0000D2_H

0000D3_H

0000D4_H

0000D5_H

0000D6_H

0000D7_H

0000D8_H

0000D9_H

0000DA_H

0000DB_H

0000DC_H

0000DD_H

USART0 - Serial Control Register

SCR0

TDR0

R/W

W

USART0 - TX Register

USART0 - RX Register

USART0 - Serial Status

RDR0

R

SSR0

R/W

USART0 - Control/Com. Register

USART0 - Ext. Status Register

USART0 - Baud Rate Generator Register Low

USART0 - Baud Rate Generator Register High

USART0 - Extended Serial Interrupt Register

Reserved

ECCR0

ESCR0

BGRL0

BGRH0

ESIR0

BGR0

BGR1

BGR2

R/W

-

USART1 - Serial Mode Register

USART1 - Serial Control Register

USART1 - TX Register

SMR1

SCR1

R/W

W

TDR1

USART1 - RX Register

RDR1

R

USART1 - Serial Status

SSR1

R/W

-

USART1 - Control/Com. Register

USART1 - Ext. Status Register

USART1 - Baud Rate Generator Register Low

USART1 - Baud Rate Generator Register High

USART1 - Extended Serial Interrupt Register

Reserved

ECCR1

ESCR1

BGRL1

BGRH1

ESIR1

USART2 - Serial Mode Register

USART2 - Serial Control Register

USART2 - TX Register

SMR2

SCR2

R/W

W

TDR2

USART2 - RX Register

RDR2

R

USART2 - Serial Status

SSR2

R/W

-

USART2 - Control/Com. Register

USART2 - Ext. Status Register

USART2 - Baud Rate Generator Register Low

USART2 - Baud Rate Generator Register High

USART2 - Extended Serial Interrupt Register

Reserved

ECCR2

ESCR2

BGRL2

BGRH2

ESIR2

Document Number: 002-04579 Rev. *A

Page 30 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0000DE_H

0000DF_H

0000E0_H

0000E1_H

0000E2_H

0000E3_H

0000E4_H

0000E5_H

0000E6_H

0000E7_H-0000EF_H

0000F0_H-0000FF_H

000100_H

USART3 - Serial Mode Register

USART3 - Serial Control Register

SMR3

SCR3

R/W

W

USART3 - TX Register

TDR3

USART3 - RX Register

RDR3

R

USART3 - Serial Status

SSR3

R/W

USART3 - Control/Com. Register

USART3 - Ext. Status Register

ECCR3

ESCR3

BGRL3

BGRH3

ESIR3

USART3 - Baud Rate Generator Register Low

USART3 - Baud Rate Generator Register High

USART3 - Extended Serial Interrupt Register

Reserved

BGR3

R/W

-

External Bus area

EXTBUS0

BAPL0

BAPM0

BAPH0

DMACS0

IOAL0

R/W

DMA0 - Buffer address pointer low byte

DMA0 - Buffer address pointer middle byte

DMA0 - Buffer address pointer high byte

DMA0 - DMA control register

000101_H

000102_H

000103_H

000104_H

DMA0 - I/O register address pointer low byte

DMA0 - I/O register address pointer high byte

DMA0 - Data counter low byte

IOA0

000105_H

IOAH0

000106_H

DCTL0

DCTH0

BAPL1

BAPM1

BAPH1

DMACS1

IOAL1

DCT0

000107_H

DMA0 - Data counter high byte

000108_H

DMA1 - Buffer address pointer low byte

DMA1 - Buffer address pointer middle byte

DMA1 - Buffer address pointer high byte

DMA1 - DMA control register

000109_H

00010A_H

00010B_H

00010C_H

00010D_H

00010E_H

00010F_H

000110_H

DMA1 - I/O register address pointer low byte

DMA1 - I/O register address pointer high byte

DMA1 - Data counter low byte

IOA1

IOAH1

DCTL1

DCTH1

BAPL2

BAPM2

BAPH2

DMACS2

DCT1

DMA1 - Data counter high byte

DMA2 - Buffer address pointer low byte

DMA2 - Buffer address pointer middle byte

DMA2 - Buffer address pointer high byte

DMA2 - DMA control register

000111_H

000112_H

000113_H

Document Number: 002-04579 Rev. *A

Page 31 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000114_H

000115_H

000116_H

000117_H

000118_H

000119_H

00011A_H

00011B_H

00011C_H

00011D_H

00011E_H

00011F_H

000120_H

000121_H

000122_H

000123_H

000124_H

000125_H

000126_H

000127_H

000128_H

000129_H

00012A_H

00012B_H

00012C_H

00012D_H

00012E_H

00012F_H

000130_H-00017F_H

000180_H-00037F_H

000380_H

000381_H

DMA2 - I/O register address pointer low byte

DMA2 - I/O register address pointer high byte

DMA2 - Data counter low byte

IOAL2

IOAH2

DCTL2

DCTH2

BAPL3

BAPM3

BAPH3

DMACS3

IOAL3

IOA2

R/W

-

DCT2

DMA2 - Data counter high byte

DMA3 - Buffer address pointer low byte

DMA3 - Buffer address pointer middle byte

DMA3 - Buffer address pointer high byte

DMA3 - DMA control register

DMA3 - I/O register address pointer low byte

DMA3 - I/O register address pointer high byte

DMA3 - Data counter low byte

IOA3

IOAH3

DCTL3

DCTH3

BAPL4

BAPM4

BAPH4

DMACS4

IOAL4

DCT3

DMA3 - Data counter high byte

DMA4 - Buffer address pointer low byte

DMA4 - Buffer address pointer middle byte

DMA4 - Buffer address pointer high byte

DMA4 - DMA control register

DMA4 - I/O register address pointer low byte

DMA4 - I/O register address pointer high byte

DMA4 - Data counter low byte

IOA4

IOAH4

DCTL4

DCTH4

BAPL5

BAPM5

BAPH5

DMACS5

IOAL5

DCT4

DMA4 - Data counter high byte

DMA5 - Buffer address pointer low byte

DMA5 - Buffer address pointer middle byte

DMA5 - Buffer address pointer high byte

DMA5 - DMA control register

DMA5 - I/O register address pointer low byte

DMA5 - I/O register address pointer high byte

DMA5 - Data counter low byte

IOA5

IOAH5

DCTL5

DCTH5

DCT5

DMA5 - Data counter high byte

Reserved

CPU - General Purpose registers (RAM access)

DMA0 - Interrupt select

GPR_RAM

DISEL0

R/W

DMA1 - Interrupt select

DISEL1

Document Number: 002-04579 Rev. *A

Page 32 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000382_H

000383_H

DMA2 - Interrupt select

DISEL2

DISEL3

DISEL4

DISEL5

R/W

-

DMA3 - Interrupt select

DMA4 - Interrupt select

DMA5 - Interrupt select

Reserved

000384_H

000385_H

000386_H-00038F_H

000390_H

DMA - Status register low byte

DSRL

DSRH

DSSRL

DSSRH

DERL

DSR

DSSR

DER

R/W

-

000391_H

DMA - Status register high byte

000392_H

DMA - Stop status register low byte

DMA - Stop status register high byte

DMA - Enable register low byte

000393_H

000394_H

000395_H

DMA - Enable register high byte

Reserved

DERH

000396_H-00039F_H

0003A0_H

Interrupt level register

ILR

IDX

ICR

R/W

-

0003A1_H

Interrupt index register

0003A2_H

Interrupt vector table base register Low

Interrupt vector table base register High

Delayed Interrupt register

TBRL

TBRH

DIRR

NMI

TBR

0003A3_H

0003A4_H

0003A5_H

Non Maskable Interrupt register

Reserved

0003A6_H-0003AB_H

0003AC_H

0003AD_H

0003AE_H

0003AF_H

0003B0_H

EDSU communication interrupt selection Low

EDSU communication interrupt selection High

ROM mirror control register

EDSU2L

EDSU2H

ROMM

EDSU2

R/W

EDSU configuration register

EDSU

Memory patch control/status register ch 0/1

Memory patch control/status register ch 2/3

Memory patch control/status register ch 4/5

Memory patch control/status register ch 6/7

Memory Patch function - Patch address 0 low

PFCS0

PFCS1

PFCS2

PFCS3

0003B1_H

0003B2_H

0003B3_H

0003B4_H

0003B5_H

0003B6_H

0003B7_H

0003B8_H

PFAL0

Document Number: 002-04579 Rev. *A

Page 33 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0003B9_H

0003BA_H

0003BB_H

0003BC_H

0003BD_H

0003BE_H

0003BF_H

0003C0_H

0003C1_H

0003C2_H

0003C3_H

0003C4_H

0003C5_H

0003C6_H

0003C7_H

0003C8_H

0003C9_H

0003CA_H

0003CB_H

0003CC_H

0003CD_H

0003CE_H

0003CF_H

0003D0_H

0003D1_H

0003D2_H

0003D3_H

0003D4_H

0003D5_H

0003D6_H

0003D7_H

0003D8_H

Memory Patch function - Patch address 0 middle

Memory Patch function - Patch address 0 high

Memory Patch function - Patch address 1 low

Memory Patch function - Patch address 1 middle

Memory Patch function - Patch address 1 high

Memory Patch function - Patch address 2 low

Memory Patch function - Patch address 2 middle

Memory Patch function - Patch address 2 high

Memory Patch function - Patch address 3 low

Memory Patch function - Patch address 3 middle

Memory Patch function - Patch address 3 high

Memory Patch function - Patch address 4 low

Memory Patch function - Patch address 4 middle

Memory Patch function - Patch address 4 high

Memory Patch function - Patch address 5 low

Memory Patch function - Patch address 5 middle

Memory Patch function - Patch address 5 high

Memory Patch function - Patch address 6 low

Memory Patch function - Patch address 6 middle

Memory Patch function - Patch address 6 high

Memory Patch function - Patch address 7 low

Memory Patch function - Patch address 7 middle

Memory Patch function - Patch address 7 high

Memory Patch function - Patch data 0 Low

Memory Patch function - Patch data 0 High

Memory Patch function - Patch data 1 Low

Memory Patch function - Patch data 1 High

Memory Patch function - Patch data 2 Low

Memory Patch function - Patch data 2 High

Memory Patch function - Patch data 3 Low

Memory Patch function - Patch data 3 High

Memory Patch function - Patch data 4 Low

PFAM0

PFAH0

PFAL1

PFAM1

PFAH1

PFAL2

PFAM2

PFAH2

PFAL3

PFAM3

PFAH3

PFAL4

PFAM4

PFAH4

PFAL5

PFAM5

PFAH5

PFAL6

PFAM6

PFAH6

PFAL7

PFAM7

PFAH7

PFDL0

PFDH0

PFDL1

PFDH1

PFDL2

PFDH2

PFDL3

PFDH3

PFDL4

R/W

PFD0

PFD1

PFD2

PFD3

PFD4

R/W

Document Number: 002-04579 Rev. *A

Page 34 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0003D9_H

0003DA_H

0003DB_H

0003DC_H

0003DD_H

0003DE_H

0003DF_H

0003E0_H

0003E1_H

0003E2_H

0003E3_H-0003F0_H

0003F1_H

Memory Patch function - Patch data 4 High

Memory Patch function - Patch data 5 Low

Memory Patch function - Patch data 5 High

Memory Patch function - Patch data 6 Low

Memory Patch function - Patch data 6 High

Memory Patch function - Patch data 7 Low

Memory Patch function - Patch data 7 High

Data Flash Control and Status register A

Data Flash Write command sequencer Control register A

Data Flash Write command sequencer Status register A

Reserved

PFDH4

PFDL5

PFDH5

PFDL6

PFDH6

PFDL7

PFDH7

DFCSA

DFWCA

DFWSA

R/W

PFD5

PFD6

PFD7

R/W

-

Memory Control Status Register A

Memory Timing Configuration Register A Low

Memory Timing Configuration Register A High

Reserved

MCSRA

MTCRAL

MTCRAH

R/W

-

0003F2_H

MTCRA

MTCRB

0003F3_H

0003F4_H

0003F5_H

Memory Control Status Register B

Memory Timing Configuration Register B Low

Memory Timing Configuration Register B High

Flash Memory Write Control register 0

Flash Memory Write Control register 1

Flash Memory Write Control register 2

Flash Memory Write Control register 3

Flash Memory Write Control register 4

Flash Memory Write Control register 5

Reserved

MCSRB

MTCRBL

MTCRBH

FMWC0

FMWC1

FMWC2

FMWC3

FMWC4

FMWC5

R/W

-

0003F6_H

0003F7_H

0003F8_H

0003F9_H

0003FA_H

0003FB_H

0003FC_H

0003FD_H

0003FE_H-0003FF_H

000400_H

Standby Mode control register

SMCR

CKSR

R/W

R

000401_H

Clock select register

000402_H

Clock Stabilization select register

CKSSR

CKMR

000403_H

Clock monitor register

000404_H

Clock Frequency control register Low

Clock Frequency control register High

PLL Control register Low

CKFCRL

CKFCRH

PLLCRL

CKFCR

PLLCR

R/W

000405_H

000406_H

Document Number: 002-04579 Rev. *A

Page 35 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000407_H

000408_H

PLL Control register High

RC clock timer control register

PLLCRH

RCTCR

MCTCR

SCTCR

RCCSRC

RCR

R/W

R

000409_H

Main clock timer control register

Sub clock timer control register

Reset cause and clock status register with clear function

Reset configuration register

00040A_H

00040B_H

00040C_H

00040D_H

00040E_H

R/W

R

Reset cause and clock status register

Watch dog timer configuration register

Watch dog timer clear pattern register

Reserved

RCCSR

WDTC

R/W

W

00040F_H

WDTCP

000410_H-000414_H

000415_H

-

Clock output activation register

Clock output configuration register 0

Clock output configuration register 1

Clock Modulator control register

Reserved

COAR

COCR0

COCR1

CMCR

R/W

-

000416_H

000417_H

000418_H

000419_H

00041A_H

Clock Modulator Parameter register Low

Clock Modulator Parameter register High

Reserved

CMPRL

CMPRH

CMPR

R/W

-

00041B_H

00041C_H-00042B_H

00042C_H

00042D_H

00042E_H-00042F_H

000430_H

Voltage Regulator Control register

Clock Input and LVD Control Register

Reserved

VRCR

CILCR

R/W

-

I/O Port P00 - Data Direction Register

I/O Port P01 - Data Direction Register

I/O Port P02 - Data Direction Register

I/O Port P03 - Data Direction Register

I/O Port P04 - Data Direction Register

I/O Port P05 - Data Direction Register

I/O Port P06 - Data Direction Register

I/O Port P07 - Data Direction Register

I/O Port P08 - Data Direction Register

I/O Port P09 - Data Direction Register

I/O Port P10 - Data Direction Register

DDR00

DDR01

DDR02

DDR03

DDR04

DDR05

DDR06

DDR07

DDR08

DDR09

DDR10

R/W

000431_H

000432_H

000433_H

000434_H

000435_H

000436_H

000437_H

000438_H

000439_H

00043A_H

Document Number: 002-04579 Rev. *A

Page 36 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00043B_H-000443_H

000444_H

Reserved

-

I/O Port P00 - Port Input Enable Register

I/O Port P01 - Port Input Enable Register

I/O Port P02 - Port Input Enable Register

I/O Port P03 - Port Input Enable Register

I/O Port P04 - Port Input Enable Register

I/O Port P05 - Port Input Enable Register

I/O Port P06 - Port Input Enable Register

I/O Port P07 - Port Input Enable Register

I/O Port P08 - Port Input Enable Register

I/O Port P09 - Port Input Enable Register

I/O Port P10 - Port Input Enable Register

Reserved

PIER00

PIER01

PIER02

PIER03

PIER04

PIER05

PIER06

PIER07

PIER08

PIER09

PIER10

R/W

-

000445_H

000446_H

000447_H

000448_H

000449_H

00044A_H

00044B_H

00044C_H

00044D_H

00044E_H

00044F_H-000457_H

000458_H

I/O Port P00 - Port Input Level Register

I/O Port P01 - Port Input Level Register

I/O Port P02 - Port Input Level Register

I/O Port P03 - Port Input Level Register

I/O Port P04 - Port Input Level Register

I/O Port P05 - Port Input Level Register

I/O Port P06 - Port Input Level Register

I/O Port P07 - Port Input Level Register

I/O Port P08 - Port Input Level Register

I/O Port P09 - Port Input Level Register

I/O Port P10 - Port Input Level Register

Reserved

PILR00

PILR01

PILR02

PILR03

PILR04

PILR05

PILR06

PILR07

PILR08

PILR09

PILR10

R/W

-

000459_H

00045A_H

00045B_H

00045C_H

00045D_H

00045E_H

00045F_H

000460_H

000461_H

000462_H

000463_H-00046B_H

00046C_H

00046D_H

00046E_H

00046F_H

I/O Port P00 - Extended Port Input Level Register

I/O Port P01 - Extended Port Input Level Register

I/O Port P02 - Extended Port Input Level Register

I/O Port P03 - Extended Port Input Level Register

I/O Port P04 - Extended Port Input Level Register

I/O Port P05 - Extended Port Input Level Register

I/O Port P06 - Extended Port Input Level Register

EPILR00

EPILR01

EPILR02

EPILR03

EPILR04

EPILR05

EPILR06

R/W

000470_H

000471_H

000472_H

Document Number: 002-04579 Rev. *A

Page 37 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000473_H

000474_H

I/O Port P07 - Extended Port Input Level Register

I/O Port P08 - Extended Port Input Level Register

I/O Port P09 - Extended Port Input Level Register

I/O Port P10 - Extended Port Input Level Register

Reserved

EPILR07

EPILR08

EPILR09

EPILR10

R/W

-

000475_H

000476_H

000477_H-00047F_H

000480_H

I/O Port P00 - Port Output Drive Register

I/O Port P01 - Port Output Drive Register

I/O Port P02 - Port Output Drive Register

I/O Port P03 - Port Output Drive Register

I/O Port P04 - Port Output Drive Register

I/O Port P05 - Port Output Drive Register

I/O Port P06 - Port Output Drive Register

I/O Port P07 - Port Output Drive Register

I/O Port P08 - Port Output Drive Register

I/O Port P09 - Port Output Drive Register

I/O Port P10 - Port Output Drive Register

Reserved

PODR00

PODR01

PODR02

PODR03

PODR04

PODR05

PODR06

PODR07

PODR08

PODR09

PODR10

R/W

-

000481_H

000482_H

000483_H

000484_H

000485_H

000486_H

000487_H

000488_H

000489_H

00048A_H

00048B_H-00049B_H

00049C_H

00049D_H

00049E_H

I/O Port P08 - Port High Drive Register

I/O Port P09 - Port High Drive Register

I/O Port P10 - Port High Drive Register

Reserved

PHDR08

PHDR09

PHDR10

R/W

-

00049F_H-0004A7_H

0004A8_H

I/O Port P00 - Pull-Up resistor Control Register

I/O Port P01 - Pull-Up resistor Control Register

I/O Port P02 - Pull-Up resistor Control Register

I/O Port P03 - Pull-Up resistor Control Register

I/O Port P04 - Pull-Up resistor Control Register

I/O Port P05 - Pull-Up resistor Control Register

I/O Port P06 - Pull-Up resistor Control Register

I/O Port P07 - Pull-Up resistor Control Register

I/O Port P08 - Pull-Up resistor Control Register

I/O Port P09 - Pull-Up resistor Control Register

I/O Port P10 - Pull-Up resistor Control Register

PUCR00

PUCR01

PUCR02

PUCR03

PUCR04

PUCR05

PUCR06

PUCR07

PUCR08

PUCR09

PUCR10

R/W

0004A9_H

0004AA_H

0004AB_H

0004AC_H

0004AD_H

0004AE_H

0004AF_H

0004B0_H

0004B1_H

0004B2_H

Document Number: 002-04579 Rev. *A

Page 38 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0004B3_H-0004BB_H

0004BC_H

0004BD_H

0004BE_H

0004BF_H

0004C0_H

0004C1_H

0004C2_H

0004C3_H

0004C4_H

0004C5_H

0004C6_H

0004C7_H-0004CF_H

0004D0_H

0004D1_H

0004D2_H

0004D3_H

0004D4_H

0004D5_H

0004D6_H

0004D7_H

0004D8_H

0004D9_H

0004DA_H

0004DB_H

0004DC_H

0004DD_H

0004DE_H

0004DF_H

0004E0_H

0004E1_H

0004E2_H

Reserved

-

I/O Port P00 - External Pin State Register

I/O Port P01 - External Pin State Register

I/O Port P02 - External Pin State Register

I/O Port P03 - External Pin State Register

I/O Port P04 - External Pin State Register

I/O Port P05 - External Pin State Register

I/O Port P06 - External Pin State Register

I/O Port P07 - External Pin State Register

I/O Port P08 - External Pin State Register

I/O Port P09 - External Pin State Register

I/O Port P10 - External Pin State Register

Reserved

EPSR00

EPSR01

EPSR02

EPSR03

EPSR04

EPSR05

EPSR06

EPSR07

EPSR08

EPSR09

EPSR10

R

-

ADC analog input enable register 0

ADC analog input enable register 1

ADC analog input enable register 2

ADC analog input enable register 3

ADC analog input enable register 4

Reserved

ADER0

ADER1

ADER2

ADER3

ADER4

R/W

-

Peripheral Resource Relocation Register 0

Peripheral Resource Relocation Register 1

Peripheral Resource Relocation Register 2

Peripheral Resource Relocation Register 3

Peripheral Resource Relocation Register 4

Peripheral Resource Relocation Register 5

Peripheral Resource Relocation Register 6

Peripheral Resource Relocation Register 7

Peripheral Resource Relocation Register 8

Peripheral Resource Relocation Register 9

RTC - Sub Second Register L

PRRR0

PRRR1

PRRR2

PRRR3

PRRR4

PRRR5

PRRR6

PRRR7

PRRR8

PRRR9

WTBRL0

WTBRH0

WTBR1

R/W

WTBR0

R/W

RTC - Sub Second Register M

RTC - Sub-Second Register H

Document Number: 002-04579 Rev. *A

Page 39 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0004E3_H

0004E4_H

0004E5_H

0004E6_H

0004E7_H

0004E8_H

0004E9_H

0004EA_H

0004EB_H

0004EC_H

0004ED_H

0004EE_H

0004EF_H

0004F0_H

0004F1_H

0004F2_H-0004F9_H

0004FA_H

0004FB_H-00053D_H

00053E_H

00053F_H

000540_H

RTC - Second Register

WTSR

WTMR

R/W

RTC - Minutes

RTC - Hour

WTHR

RTC - Timer Control Extended Register

RTC - Clock select register

WTCER

WTCKSR

WTCRL

WTCRH

CUCR

RTC - Timer Control Register Low

RTC - Timer Control Register High

CAL - Calibration unit Control register

Reserved

WTCR

R/W

-

CAL - Duration Timer Data Register Low

CAL - Duration Timer Data Register High

CAL - Calibration Timer Register 2 Low

CAL - Calibration Timer Register 2 High

CAL - Calibration Timer Register 1 Low

CAL - Calibration Timer Register 1 High

Reserved

CUTDL

CUTDH

CUTR2L

CUTR2H

CUTR1L

CUTR1H

CUTD

CUTR2

CUTR1

R/W

R

-

RLT - Timer input select (for Cascading)

Reserved

TMISR

R/W

-

USART7 - Serial Mode Register

USART7 - Serial Control Register

USART7 - Serial TX Register

SMR7

SCR7

R/W

W

TDR7

000540_H

USART7 - Serial RX Register

RDR7

R

000541_H

USART7 - Serial Status Register

USART7 - Ext. Control/Com. Register

USART7 - Ext. Status Com. Register

USART7 - Baud Rate Generator Register Low

USART7 - Baud Rate Generator Register High

USART7 - Extended Serial Interrupt Register

Reserved

SSR7

R/W

-

000542_H

ECCR7

ESCR7

BGRL7

BGRH7

ESIR7

000543_H

000544_H

BGR7

000545_H

000546_H

000547_H

000548_H

USART8 - Serial Mode Register

USART8 - Serial Control Register

USART8 - Serial TX Register

SMR8

SCR8

TDR8

R/W

W

000549_H

00054A_H

Document Number: 002-04579 Rev. *A

Page 40 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00054A_H

00054B_H

00054C_H

00054D_H

00054E_H

00054F_H

000550_H

000551_H

000552_H

000553_H

000554_H

000555_H

000556_H

000557_H

000558_H

000559_H

00055A_H

00055B_H-00055F_H

000560_H

000561_H

000562_H

000563_H

000564_H

000565_H

000566_H

000567_H

000568_H

000569_H

00056A_H

00056B_H

00056C_H

USART8 - Serial RX Register

USART8 - Serial Status Register

RDR8

SSR8

R

R/W

USART8 - Ext. Control/Com. Register

USART8 - Ext. Status Com. Register

USART8 - Baud Rate Generator Register Low

USART8 - Baud Rate Generator Register High

USART8 - Extended Serial Interrupt Register

Reserved

ECCR8

ESCR8

BGRL8

BGRH8

ESIR8

BGR8

R/W

-

USART9 - Serial Mode Register

USART9 - Serial Control Register

USART9 - Serial TX Register

SMR9

SCR9

R/W

W

TDR9

USART9 - Serial RX Register

RDR9

R

USART9 - Serial Status Register

USART9 - Ext. Control/Com. Register

USART9 - Ext. Status Com. Register

USART9 - Baud Rate Generator Register Low

USART9 - Baud Rate Generator Register High

USART9 - Extended Serial Interrupt Register

Reserved

SSR9

R/W

-

ECCR9

ESCR9

BGRL9

BGRH9

ESIR9

BGR9

ALARM0 - Control Status Register

ALARM0 - Extended Control Status Register

ALARM1 - Control Status Register

ALARM1 - Extended Control Status Register

PPG6 - Timer register

ACSR0

AECSR0

ACSR1

R/W

R

AECSR1

PTMR6

PCSR6

PDUT6

PCN6

PPG6 - Timer register

R

PPG6 - Period setting register

W

PPG6 - Period setting register

W

PPG6 - Duty cycle register

W

PPG6 - Duty cycle register

W

PPG6 - Control status register Low

PPG6 - Control status register High

PPG7 - Timer register

PCNL6

PCNH6

R/W

R

PTMR7

Document Number: 002-04579 Rev. *A

Page 41 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00056D_H

00056E_H

00056F_H

000570_H

000571_H

000572_H

000573_H

000574_H

000575_H

000576_H

000577_H

000578_H

000579_H

00057A_H

00057B_H

00057C_H

00057D_H

00057E_H

00057F_H

000580_H

000581_H

000582_H

000583_H

000584_H

000585_H

000586_H

000587_H

000588_H

000589_H

00058A_H

00058B_H

00058C_H

PPG7 - Timer register

PPG7 - Period setting register

R

PCSR7

PDUT7

PCN7

W

PPG7 - Period setting register

PPG7 - Duty cycle register

W

PPG7 - Duty cycle register

W

PPG7 - Control status register Low

PPG7 - Control status register High

PPG11-PPG8 - General Control register 1 Low

PPG11-PPG8 - General Control register 1 High

PPG11-PPG8 - General Control register 2 Low

PPG11-PPG8 - General Control register 2 High

PPG8 - Timer register

PCNL7

PCNH7

R/W

R

GCN1L2

GCN1H2

GCN2L2

GCN2H2

GCN12

GCN22

PTMR8

PCSR8

PDUT8

PCN8

PPG8 - Timer register

R

PPG8 - Period setting register

PPG8 - Duty cycle register

W

PPG8 - Duty cycle register

W

PPG8 - Control status register Low

PPG8 - Control status register High

PPG9 - Timer register

PCNL8

PCNH8

R/W

R

PTMR9

PCSR9

PDUT9

PCN9

PPG9 - Timer register

R

PPG9 - Period setting register

PPG9 - Duty cycle register

W

PPG9 - Duty cycle register

W

PPG9 - Control status register Low

PPG9 - Control status register High

PPG10 - Timer register

PCNL9

PCNH9

R/W

R

PTMR10

PCSR10

PDUT10

PPG10 - Timer register

R

PPG10 - Period setting register

PPG10 - Duty cycle register

W

Document Number: 002-04579 Rev. *A

Page 42 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00058D_H

00058E_H

00058F_H

000590_H

000591_H

000592_H

000593_H

000594_H

000595_H

000596_H

000597_H

000598_H

000599_H

00059A_H

00059B_H

00059C_H

00059D_H

00059E_H

00059F_H

0005A0_H

0005A1_H

0005A2_H

0005A3_H

0005A4_H

0005A5_H

0005A6_H

0005A7_H

0005A8_H

0005A9_H

0005AA_H

0005AB_H

0005AC_H

PPG10 - Duty cycle register

W

PPG10 - Control status register Low

PPG10 - Control status register High

PPG11 - Timer register

PCNL10

PCNH10

PCN10

PTMR11

PCSR11

PDUT11

PCN11

R/W

R

PPG11 - Timer register

R

PPG11 - Period setting register

PPG11 - Duty cycle register

W

PPG11 - Duty cycle register

W

PPG11 - Control status register Low

PPG11 - Control status register High

PPG15-PPG12 - General Control register 1 Low

PPG15-PPG12 - General Control register 1 High

PPG15-PPG12 - General Control register 2 Low

PPG15-PPG12 - General Control register 2 High

PPG12 - Timer register

PCNL11

PCNH11

GCN1L3

GCN1H3

GCN2L3

GCN2H3

R/W

R

GCN13

GCN23

PTMR12

PCSR12

PDUT12

PCN12

PPG12 - Timer register

R

PPG12 - Period setting register

PPG12 - Duty cycle register

W

PPG12 - Duty cycle register

W

PPG12 - Control status register Low

PPG12 - Control status register High

PPG13 - Timer register

PCNL12

PCNH12

R/W

R

PTMR13

PCSR13

PDUT13

PCN13

PPG13 - Timer register

R

PPG13 - Period setting register

PPG13 - Duty cycle register

W

PPG13 - Duty cycle register

W

PPG13 - Control status register Low

PPG13 - Control status register High

PPG14 - Timer register

PCNL13

PCNH13

R/W

R

PTMR14

Document Number: 002-04579 Rev. *A

Page 43 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0005AD_H

0005AE_H

0005AF_H

0005B0_H

0005B1_H

0005B2_H

0005B3_H

0005B4_H

0005B5_H

0005B6_H

0005B7_H

0005B8_H

0005B9_H

0005BA_H

0005BB_H

0005BC_H-00065F_H

000660_H

PPG14 - Timer register

PPG14 - Period setting register

R

PCSR14

PDUT14

PCN14

W

PPG14 - Period setting register

PPG14 - Duty cycle register

W

PPG14 - Duty cycle register

W

PPG14 - Control status register Low

PPG14 - Control status register High

PPG15 - Timer register

PCNL14

PCNH14

R/W

R

PTMR15

PCSR15

PDUT15

PCN15

PPG15 - Timer register

R

PPG15 - Period setting register

W

PPG15 - Period setting register

W

PPG15 - Duty cycle register

W

PPG15 - Duty cycle register

W

PPG15 - Control status register Low

PPG15 - Control status register High

Reserved

PCNL15

PCNH15

R/W

-

Peripheral Resource Relocation Register 10

Peripheral Resource Relocation Register 11

Peripheral Resource Relocation Register 12

Peripheral Resource Relocation Register 13

Reserved

PRRR10

PRRR11

PRRR12

PRRR13

R/W

W

000661_H

000662_H

000663_H

000664_H-0006DF_H

0006E0_H

0006E1_H

0006E2_H

0006E3_H

0006E4_H

0006E5_H

0006E6_H

0006E7_H

0006E8_H

0006E9_H

0006EA_H

-

External Bus - Area configuration register 0 Low

External Bus - Area configuration register 0 High

External Bus - Area configuration register 1 Low

External Bus - Area configuration register 1 High

External Bus - Area configuration register 2 Low

External Bus - Area configuration register 2 High

External Bus - Area configuration register 3 Low

External Bus - Area configuration register 3 High

External Bus - Area configuration register 4 Low

External Bus - Area configuration register 4 High

External Bus - Area configuration register 5 Low

EACL0

EACH0

EACL1

EACH1

EACL2

EACH2

EACL3

EACH3

EACL4

EACH4

EACL5

EAC0

EAC1

EAC2

EAC3

EAC4

EAC5

R/W

Document Number: 002-04579 Rev. *A

Page 44 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0006EB_H

0006EC_H

0006ED_H

0006EE_H

0006EF_H

0006F0_H

0006F1_H

0006F2_H

0006F3_H

0006F4_H

0006F5_H

0006F6_H-0006FF_H

000700_H

External Bus - Area configuration register 5 High

External Bus - Area select register 2

External Bus - Area select register 3

External Bus - Area select register 4

External Bus - Area select register 5

External Bus - Mode register

EACH5

EAS2

EAS3

EAS4

EAS5

EBM

R/W

-

External Bus - Clock and Function register

External Bus - Address output enable register 0

External Bus - Address output enable register 1

External Bus - Address output enable register 2

External Bus - Control signal register

Reserved

EBCF

EBAE0

EBAE1

EBAE2

EBCS

CAN0 - Control register Low

CTRLRL0

CTRLRH0

STATRL0

STATRH0

ERRCNTL0

ERRCNTH0

BTRL0

CTRLR0

STATR0

ERRCNT0

BTR0

R/W

R

000701_H

CAN0 - Control register High (reserved)

CAN0 - Status register Low

000702_H

R/W

R

000703_H

CAN0 - Status register High (reserved)

CAN0 - Error Counter Low (Transmit)

CAN0 - Error Counter High (Receive)

CAN0 - Bit Timing Register Low

000704_H

R

000705_H

R

000706_H

R/W

R

000707_H

CAN0 - Bit Timing Register High

BTRH0

000708_H

CAN0 - Interrupt Register Low

INTRL0

INTR0

000709_H

CAN0 - Interrupt Register High

INTRH0

R

00070A_H

00070B_H

00070C_H

00070D_H

00070E_H-00070F_H

000710_H

CAN0 - Test Register Low

TESTRL0

TESTRH0

BRPERL0

BRPERH0

TESTR0

BRPER0

R/W

R

CAN0 - Test Register High (reserved)

CAN0 - BRP Extension register Low

CAN0 - BRP Extension register High (reserved)

Reserved

R/W

R

-

CAN0 - IF1 Command request register Low

CAN0 - IF1 Command request register High

CAN0 - IF1 Command Mask register Low

CAN0 - IF1 Command Mask register High (reserved)

CAN0 - IF1 Mask 1 Register Low

IF1CREQL0

IF1CREQH0

IF1CMSKL0

IF1CMSKH0

IF1MSK1L0

IF1CREQ0

IF1CMSK0

IF1MSK10

R/W

R

000711_H

000712_H

000713_H

000714_H

R/W

Document Number: 002-04579 Rev. *A

Page 45 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000715_H

000716_H

000717_H

000718_H

000719_H

00071A_H

00071B_H

00071C_H

00071D_H

00071E_H

00071F_H

000720_H

000721_H

000722_H

000723_H

000724_H

000725_H

000726_H-00073F_H

000740_H

000741_H

000742_H

000743_H

000744_H

000745_H

000746_H

000747_H

000748_H

000749_H

00074A_H

00074B_H

00074C_H

00074D_H

CAN0 - IF1 Mask 1 Register High

CAN0 - IF1 Mask 2 Register Low

IF1MSK1H0

IF1MSK2L0

IF1MSK2H0

IF1ARB1L0

IF1ARB1H0

IF1ARB2L0

IF1ARB2H0

IF1MCTRL0

IF1MCTRH0

IF1DTA1L0

IF1DTA1H0

IF1DTA2L0

IF1DTA2H0

IF1DTB1L0

IF1DTB1H0

IF1DTB2L0

IF1DTB2H0

R/W

IF1MSK20

IF1ARB10

IF1ARB20

IF1MCTR0

IF1DTA10

IF1DTA20

IF1DTB10

IF1DTB20

R/W

-

CAN0 - IF1 Mask 2 Register High

CAN0 - IF1 Arbitration 1 Register Low

CAN0 - IF1 Arbitration 1 Register High

CAN0 - IF1 Arbitration 2 Register Low

CAN0 - IF1 Arbitration 2 Register High

CAN0 - IF1 Message Control Register Low

CAN0 - IF1 Message Control Register High

CAN0 - IF1 Data A1 Low

CAN0 - IF1 Data A1 High

CAN0 - IF1 Data A2 Low

CAN0 - IF1 Data A2 High

CAN0 - IF1 Data B1 Low

CAN0 - IF1 Data B1 High

CAN0 - IF1 Data B2 Low

CAN0 - IF1 Data B2 High

Reserved

CAN0 - IF2 Command request register Low

CAN0 - IF2 Command request register High

CAN0 - IF2 Command Mask register Low

CAN0 - IF2 Command Mask register High (reserved)

CAN0 - IF2 Mask 1 Register Low

CAN0 - IF2 Mask 1 Register High

CAN0 - IF2 Mask 2 Register Low

CAN0 - IF2 Mask 2 Register High

CAN0 - IF2 Arbitration 1 Register Low

CAN0 - IF2 Arbitration 1 Register High

CAN0 - IF2 Arbitration 2 Register Low

CAN0 - IF2 Arbitration 2 Register High

CAN0 - IF2 Message Control Register Low

CAN0 - IF2 Message Control Register High

IF2CREQL0

IF2CREQH0

IF2CMSKL0

IF2CMSKH0

IF2MSK1L0

IF2MSK1H0

IF2MSK2L0

IF2MSK2H0

IF2ARB1L0

IF2ARB1H0

IF2ARB2L0

IF2ARB2H0

IF2MCTRL0

IF2MCTRH0

IF2CREQ0

IF2CMSK0

IF2MSK10

IF2MSK20

IF2ARB10

IF2ARB20

IF2MCTR0

R/W

R

R/W

Document Number: 002-04579 Rev. *A

Page 46 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00074E_H

00074F_H

CAN0 - IF2 Data A1 Low

IF2DTA1L0

IF2DTA1H0

IF2DTA2L0

IF2DTA2H0

IF2DTB1L0

IF2DTB1H0

IF2DTB2L0

IF2DTB2H0

IF2DTA10

IF2DTA20

IF2DTB10

IF2DTB20

R/W

-

CAN0 - IF2 Data A1 High

CAN0 - IF2 Data A2 Low

CAN0 - IF2 Data A2 High

CAN0 - IF2 Data B1 Low

CAN0 - IF2 Data B1 High

CAN0 - IF2 Data B2 Low

CAN0 - IF2 Data B2 High

Reserved

000750_H

000751_H

000752_H

000753_H

000754_H

000755_H

000756_H-00077F_H

000780_H

CAN0 - Transmission Request 1 Register Low

CAN0 - Transmission Request 1 Register High

CAN0 - Transmission Request 2 Register Low

CAN0 - Transmission Request 2 Register High

Reserved

TREQR1L0

TREQR1H0

TREQR2L0

TREQR2H0

TREQR10

TREQR20

R

000781_H

R

000782_H

R

000783_H

R

000784_H-00078F_H

000790_H

-

CAN0 - New Data 1 Register Low

CAN0 - New Data 1 Register High

CAN0 - New Data 2 Register Low

CAN0 - New Data 2 Register High

Reserved

NEWDT1L0

NEWDT1H0

NEWDT2L0

NEWDT2H0

NEWDT10

NEWDT20

R

000791_H

R

000792_H

R

000793_H

R

000794_H-00079F_H

0007A0_H

-

CAN0 - Interrupt Pending 1 Register Low

CAN0 - Interrupt Pending 1 Register High

CAN0 - Interrupt Pending 2 Register Low

CAN0 - Interrupt Pending 2 Register High

Reserved

INTPND1L0

INTPND1H0

INTPND2L0

INTPND2H0

INTPND10

INTPND20

R

0007A1_H

R

0007A2_H

R

0007A3_H

R

0007A4_H-0007AF_H

0007B0_H

-

CAN0 - Message Valid 1 Register Low

CAN0 - Message Valid 1 Register High

CAN0 - Message Valid 2 Register Low

CAN0 - Message Valid 2 Register High

Reserved

MSGVAL1L0

MSGVAL1H0

MSGVAL2L0

MSGVAL2H0

MSGVAL10

MSGVAL20

R

0007B1_H

R

0007B2_H

R

0007B3_H

R

0007B4_H-0007CD_H

0007CE_H

-

CAN0 - Output enable register

Reserved

COER0

R/W

-

0007CF_H-0007FF_H

000800_H

CAN1 - Control register Low

CTRLRL1

CTRLR1

R/W

Document Number: 002-04579 Rev. *A

Page 47 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000801_H

000802_H

000803_H

000804_H

000805_H

000806_H

000807_H

000808_H

000809_H

00080A_H

00080B_H

00080C_H

00080D_H

00080E_H-00080F_H

000810_H

000811_H

000812_H

000813_H

000814_H

000815_H

000816_H

000817_H

000818_H

000819_H

00081A_H

00081B_H

00081C_H

00081D_H

00081E_H

00081F_H

000820_H

000821_H

CAN1 - Control register High (reserved)

CAN1 - Status register Low

CTRLRH1

STATRL1

STATRH1

ERRCNTL1

ERRCNTH1

BTRL1

R

STATR1

ERRCNT1

BTR1

R/W

R

CAN1 - Status register High (reserved)

CAN1 - Error Counter Low (Transmit)

CAN1 - Error Counter High (Receive)

CAN1 - Bit Timing Register Low

CAN1 - Bit Timing Register High

CAN1 - Interrupt Register Low

R

R/W

R

BTRH1

INTRL1

INTR1

CAN1 - Interrupt Register High

INTRH1

R

CAN1 - Test Register Low

TESTRL1

TESTRH1

BRPERL1

BRPERH1

TESTR1

BRPER1

R/W

R

CAN1 - Test Register High (reserved)

CAN1 - BRP Extension register Low

CAN1 - BRP Extension register High (reserved)

Reserved

R/W

R

-

CAN1 - IF1 Command request register Low

CAN1 - IF1 Command request register High

CAN1 - IF1 Command Mask register Low

CAN1 - IF1 Command Mask register High (reserved)

CAN1 - IF1 Mask 1 Register Low

CAN1 - IF1 Mask 1 Register High

CAN1 - IF1 Mask 2 Register Low

CAN1 - IF1 Mask 2 Register High

CAN1 - IF1 Arbitration 1 Register Low

CAN1 - IF1 Arbitration 1 Register High

CAN1 - IF1 Arbitration 2 Register Low

CAN1 - IF1 Arbitration 2 Register High

CAN1 - IF1 Message Control Register Low

CAN1 - IF1 Message Control Register High

CAN1 - IF1 Data A1 Low

IF1CREQL1

IF1CREQH1

IF1CMSKL1

IF1CMSKH1

IF1MSK1L1

IF1MSK1H1

IF1MSK2L1

IF1MSK2H1

IF1ARB1L1

IF1ARB1H1

IF1ARB2L1

IF1ARB2H1

IF1MCTRL1

IF1MCTRH1

IF1DTA1L1

IF1DTA1H1

IF1DTA2L1

IF1DTA2H1

IF1CREQ1

IF1CMSK1

IF1MSK11

IF1MSK21

IF1ARB11

IF1ARB21

IF1MCTR1

IF1DTA11

IF1DTA21

R/W

R

R/W

CAN1 - IF1 Data A1 High

CAN1 - IF1 Data A2 Low

CAN1 - IF1 Data A2 High

Document Number: 002-04579 Rev. *A

Page 48 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000822_H

000823_H

000824_H

000825_H

000826_H-00083F_H

000840_H

000841_H

000842_H

000843_H

000844_H

000845_H

000846_H

000847_H

000848_H

000849_H

00084A_H

00084B_H

00084C_H

00084D_H

00084E_H

00084F_H

000850_H

000851_H

000852_H

000853_H

000854_H

000855_H

000856_H-00087F_H

000880_H

000881_H

000882_H

000883_H

CAN1 - IF1 Data B1 Low

IF1DTB1L1

IF1DTB1H1

IF1DTB2L1

IF1DTB2H1

IF1DTB11

R/W

-

CAN1 - IF1 Data B1 High

CAN1 - IF1 Data B2 Low

CAN1 - IF1 Data B2 High

Reserved

IF1DTB21

CAN1 - IF2 Command request register Low

CAN1 - IF2 Command request register High

CAN1 - IF2 Command Mask register Low

CAN1 - IF2 Command Mask register High (reserved)

CAN1 - IF2 Mask 1 Register Low

CAN1 - IF2 Mask 1 Register High

CAN1 - IF2 Mask 2 Register Low

CAN1 - IF2 Mask 2 Register High

CAN1 - IF2 Arbitration 1 Register Low

CAN1 - IF2 Arbitration 1 Register High

CAN1 - IF2 Arbitration 2 Register Low

CAN1 - IF2 Arbitration 2 Register High

CAN1 - IF2 Message Control Register Low

CAN1 - IF2 Message Control Register High

CAN1 - IF2 Data A1 Low

IF2CREQL1

IF2CREQH1

IF2CMSKL1

IF2CMSKH1

IF2MSK1L1

IF2MSK1H1

IF2MSK2L1

IF2MSK2H1

IF2ARB1L1

IF2ARB1H1

IF2ARB2L1

IF2ARB2H1

IF2MCTRL1

IF2MCTRH1

IF2DTA1L1

IF2DTA1H1

IF2DTA2L1

IF2DTA2H1

IF2DTB1L1

IF2DTB1H1

IF2DTB2L1

IF2DTB2H1

IF2CREQ1

IF2CMSK1

IF2MSK11

IF2MSK21

IF2ARB11

IF2ARB21

IF2MCTR1

IF2DTA11

IF2DTA21

IF2DTB11

IF2DTB21

R/W

R

R/W

-

CAN1 - IF2 Data A1 High

CAN1 - IF2 Data A2 Low

CAN1 - IF2 Data A2 High

CAN1 - IF2 Data B1 Low

CAN1 - IF2 Data B1 High

CAN1 - IF2 Data B2 Low

CAN1 - IF2 Data B2 High

Reserved

CAN1 - Transmission Request 1 Register Low

CAN1 - Transmission Request 1 Register High

CAN1 - Transmission Request 2 Register Low

CAN1 - Transmission Request 2 Register High

TREQR1L1

TREQR1H1

TREQR2L1

TREQR2H1

TREQR11

TREQR21

R

Document Number: 002-04579 Rev. *A

Page 49 of 109

MB96340 Series

Table 4: I/O map MB96(F)34x

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000884_H-00088F_H

000890_H

Reserved

-

CAN1 - New Data 1 Register Low

CAN1 - New Data 1 Register High

CAN1 - New Data 2 Register Low

CAN1 - New Data 2 Register High

Reserved

NEWDT1L1

NEWDT1H1

NEWDT2L1

NEWDT2H1

NEWDT11

NEWDT21

R

000891_H

000892_H

R

000893_H

R

000894_H-00089F_H

0008A0_H

-

CAN1 - Interrupt Pending 1 Register Low

CAN1 - Interrupt Pending 1 Register High

CAN1 - Interrupt Pending 2 Register Low

CAN1 - Interrupt Pending 2 Register High

Reserved

INTPND1L1

INTPND1H1

INTPND2L1

INTPND2H1

INTPND11

INTPND21

R

0008A1_H

R

0008A2_H

R

0008A3_H

R

0008A4_H-0008AF_H

0008B0_H

-

CAN1 - Message Valid 1 Register Low

CAN1 - Message Valid 1 Register High

CAN1 - Message Valid 2 Register Low

CAN1 - Message Valid 2 Register High

Reserved

MSGVAL1L1

MSGVAL1H1

MSGVAL2L1

MSGVAL2H1

MSGVAL11

MSGVAL21

R

0008B1_H

R

0008B2_H

R

0008B3_H

R

0008B4_H-0008CD_H

0008CE_H

-

CAN1 - Output enable register

Reserved

COER1

R/W

-

0008CF_H-0009FF_H

000A00_H

DMA - IO address block register 0

DMA - IO address block register 1

DMA - IO address block register 2

DMA - IO address block register 3

DMA - IO address block register 4

DMA - IO address block register 5

Reserved

IOABK0

IOABK1

IOABK2

IOABK3

IOABK4

IOABK5

R/W

-

000A01_H

000A02_H

000A03_H

000A04_H

000A05_H

000A06_H-000BFF_H

Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results

in reading ‘X’.Registers of resources which are described in this table, but which are not supported by the device, should also be

handled as “Reserved”.

Document Number: 002-04579 Rev. *A

Page 50 of 109

MB96340 Series

12. Interrupt Vector Table

Table 5: Interrupt vector table MB96(F)34x

Offset in

Vector

Index in

ICR to pro-

gram

Cleared

by DMA

vector ta-

ble

Vector name

Description

number

0

3FC_H

3F8_H

3F4_H

3F0_H

3EC_H

3E8_H

3E4_H

3E0_H

3DC_H

3D8_H

3D4_H

3D0_H

3CC_H

3C8_H

3C4_H

3C0_H

3BC_H

3B8_H

3B4_H

3B0_H

3AC_H

3A8_H

3A4_H

3A0_H

39C_H

398_H

394_H

390_H

38C_H

388_H

CALLV0

CALLV1

CALLV2

CALLV3

CALLV4

CALLV5

CALLV6

CALLV7

RESET

No

-

1

-

2

No

-

3

No

-

4

No

-

5

No

-

6

No

-

7

No

-

8

No

-

9

INT9

No

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

EXCEPTION

NMI

No

-

No

-

Non-Maskable Interrupt

DLY

No

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

Delayed Interrupt

RC Timer

RC_TIMER

MC_TIMER

SC_TIMER

RESERVED

EXTINT0

EXTINT1

EXTINT2

EXTINT3

EXTINT4

EXTINT5

EXTINT6

EXTINT7

EXTINT8

EXTINT9

EXTINT10

EXTINT11

EXTINT12

No

Main Clock Timer

Sub Clock Timer

Reserved

No

Yes

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

External Interrupt 7

External Interrupt 8

External Interrupt 9

External Interrupt 10

External Interrupt 11

External Interrupt 12

Document Number: 002-04579 Rev. *A

Page 51 of 109

MB96340 Series

Table 5: Interrupt vector table MB96(F)34x

Offset in

Vector

Index in

ICR to pro-

gram

Cleared

by DMA

vector ta-

ble

Vector name

Description

number

30

31

32

384_H

380_H

37C_H

EXTINT13

EXTINT14

EXTINT15

Yes

30

31

32

External Interrupt 13

External Interrupt 14

External Interrupt 15

CAN Controller 0 (except MB96(F)34xAyy or

MB96(F)34xCyy)

33

34

378_H

374_H

CAN0

CAN1

No

33

34

CAN Controller 1 (except MB96(F)34xAyy,

MB96(F)34xCyy, MB96F345Dyy or

MB96F345Fyy)

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

370_H

36C_H

368_H

364_H

360_H

35C_H

358_H

354_H

350_H

34C_H

348_H

344_H

340_H

33C_H

338_H

334_H

330_H

32C_H

328_H

324_H

320_H

31C_H

318_H

314_H

310_H

PPG0

PPG1

PPG2

PPG3

PPG4

PPG5

PPG6

PPG7

PPG8

PPG9

PPG10

PPG11

PPG12

PPG13

PPG14

PPG15

RLT0

Yes

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

Programmable Pulse Generator 0

Programmable Pulse Generator 1

Programmable Pulse Generator 2

Programmable Pulse Generator 3

Programmable Pulse Generator 4

Programmable Pulse Generator 5

Programmable Pulse Generator 6

Programmable Pulse Generator 7

Programmable Pulse Generator 8

Programmable Pulse Generator 9

Programmable Pulse Generator 10

Programmable Pulse Generator 11

Programmable Pulse Generator 12

Programmable Pulse Generator 13

Programmable Pulse Generator 14

Programmable Pulse Generator 15

Reload Timer 0

RLT1

Reload Timer 1

RLT2

Reload Timer 2

RLT3

Reload Timer 3

PPGRLT

ICU0

Reload Timer 6 - dedicated for PPG

Input Capture Unit 0

ICU1

Input Capture Unit 1

ICU2

Input Capture Unit 2

ICU3

Input Capture Unit 3

Document Number: 002-04579 Rev. *A

Page 52 of 109

MB96340 Series

Table 5: Interrupt vector table MB96(F)34x

Offset in

Vector

Index in

ICR to pro-

gram

Cleared

by DMA

vector ta-

ble

Vector name

Description

number

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

30C_H

308_H

304_H

300_H

2FC_H

2F8_H

2F4_H

2F0_H

2EC_H

2E8_H

2E4_H

2E0_H

2DC_H

2D8_H

2D4_H

2D0_H

2CC_H

ICU4

ICU5

Yes

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

Input Capture Unit 4

Input Capture Unit 5

Input Capture Unit 6

Input Capture Unit 7

Output Compare Unit 0

Output Compare Unit 1

Output Compare Unit 2

Output Compare Unit 3

Output Compare Unit 4

Output Compare Unit 5

Output Compare Unit 6

Output Compare Unit 7

Free Running Timer 0

Free Running Timer 1

I2C interface

ICU6

ICU7

OCU0

OCU1

OCU2

OCU3

OCU4

OCU5

OCU6

OCU7

FRT0

FRT1

IIC0

IIC1

I2C interface

ADC0

A/D Converter

Alarm Comparator 0 (except MB96F345Dyy or

MB96F345Fyy)

77

78

2C8_H

2C4_H

ALARM0

ALARM1

No

77

78

Alarm Comparator 1 (except MB96F345Dyy or

MB96F345Fyy)

79

80

81

82

83

84

85

86

87

2C0_H

2BC_H

2B8_H

2B4_H

2B0_H

2AC_H

2A8_H

2A4_H

2A0_H

LINR0

LINT0

Yes

No

79

80

81

82

83

84

85

86

87

LIN USART 0 RX

LIN USART 0 TX

LINR1

LINT1

LIN USART 1 RX

LIN USART 1 TX

LINR2

LINT2

LIN USART 2 RX

LIN USART 2 TX

LINR3

LINT3

LIN USART 3 RX

LIN USART 3 TX

FLASH_A

Flash memory A (only Flash devices)

Flash memory B

(only MB96F348T/H/C)

88

89

29C_H

298_H

FLASH_B

LINR7

No

88

89

Yes

LIN USART 7 RX

Document Number: 002-04579 Rev. *A

Page 53 of 109

MB96340 Series

Table 5: Interrupt vector table MB96(F)34x

Offset in

Vector

Index in

ICR to pro-

gram

Cleared

by DMA

vector ta-

ble

Vector name

Description

number

90

91

92

93

94

95

96

294_H

290_H

28C_H

288_H

284_H

280_H

27C_H

LINT7

LINR8

LINT8

LINR9

LINT9

RTC0

CAL0

Yes

No

90

91

92

93

94

95

96

LIN USART 7 TX

LIN USART 8 RX

LIN USART 8 TX

LIN USART 9 RX

LIN USART 9 TX

Real Timer Clock

No

Clock Calibration Unit

Data Flash A

97

278_H

DFLASH_A

Yes

97

(only MB96F345Dyy, MB96F345Fyy)

Document Number: 002-04579 Rev. *A

Page 54 of 109

MB96340 Series

13. Handling Devices

Special care is required for the following when handling the device:

■ Latch-up prevention

■ Unused pins handling

■ External clock usage

■ Unused sub clock signal

■ Notes on PLL clock mode operation

■ Power supply pins (V_CC/V_SS

)

■ Crystal oscillator circuit

■ Turn on sequence of power supply to A/D converter and analog inputs

■ Pin handling when not using the A/D converter

■ Notes on energization

■ Stabilization of power supply voltage

■ Serial communication

■ Handling of Data Flash

13.1 Latch-up prevention

CMOS IC chips may suffer latch-up under the following conditions:

■ A voltage higher than V_CCor lower than V_SSis applied to an input or output pin.

■ A voltage higher than the rated voltage is applied between V_CCpins and V_SSpins.

■ The AV_CCpower supply is applied before the V_CCvoltage.

Latch-up may increase the power supply current dramatically, causing thermal damages to the device.

For the same reason, extra care is required to not let the analog power-supply voltage (AV_CC, AVRH) exceed the digital power-supply

voltage.

13.2 Unused pins handling

Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0).

Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device.

They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 k.

Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or

external pull-up/pull-down resistor as described above.

13.3 External clock usage

The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for

detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows:

Document Number: 002-04579 Rev. *A

Page 55 of 109

MB96340 Series

13.3.1 Single phase external clock

■ When using a single phase external clock, X0 pin must be driven and X1 pin left open.

X0

X1

13.3.2 Opposite phase external clock

■ When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the

X0 (X0A) pins.

X0

X1

13.4 Unused sub clock signal

If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin

must be left open.

13.5 Notes on PLL clock mode operation

If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts

to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.

13.6 Power supply pins (V /V )

SS

CC

It is required that all V_CC-level as well as all V_SS-level power supply pins are at the same potential. If there is more than one V_CCor

V_SSlevel, the device may operate incorrectly or be damaged even within the guaranteed operating range.

V_CCand V_SSmust be connected to the device from the power supply with lowest possible impedance.

As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 F between V_CCand V_SSas close

as possible to V_CCand V_SSpins.

Document Number: 002-04579 Rev. *A

Page 56 of 109

MB96340 Series

13.7 Crystal oscillator and ceramic resonator circuit

Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest

possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost

effort, that the lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area

for stabilizing the operation.

It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially

when using low-Q resonators at higher frequencies.

13.8 Turn on sequence of power supply to A/D converter and analog inputs

It is required to turn the A/D converter power supply (AV_CC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power

supply (V_CC) on.

It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage

must not exceed AVRH or AV_CC(turning the analog and digital power supplies simultaneously on or off is acceptable).

13.9 Pin handling when not using the A/D converter

It is required to connect the unused pins of the A/D converter as AV_CC= V_CC, AV_SS= AVRH = AVRL = V_SS

.

13.10 Notes on Power-on

To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than

50s from 0.2 V to 2.7 V.

13.11 Stabilization of power supply voltage

If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may

occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be

stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10%

of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for

power supply switching.

13.12 Serial communication

There is a possibility to receive wrong data due to noise or other causes on the serial communication.Therefore, design a printed

circuit board so as to avoid noise.Consider receiving of wrong data when designing the system. For example apply a checksum and

retransmit the data if an error occurs.

13.13 Handling of Data Flash

The Data Flash requires different and additional control signals for parallel programming. Please check with your programming

equipment maker for support of this interface.

Document Number: 002-04579 Rev. *A

Page 57 of 109

MB96340 Series

14. Electrical Characteristics

14.1 Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V_CC

V_SS- 0.3

V_SS+ 6.0

V

Power supply voltage

[1]

AV_CC

V_SS+ 6.0

V

_CC= AV_CC

AV_CCAVRH, AV_CCAVRL, AVRH

AVRL, AVRL AV_SS

V_SS- 0.3

AD Converter voltage references

AVRH, AVRL

V

V_IV_CC+ 0.3V ^[2]

V_O V_CC+ 0.3V ^[2]

V_I

V_O

V_SS- 0.3

V_SS+ 6.0

Input voltage

Output voltage

V

Applicable to general purposeI/O pins ^[3]

I_CLAMP

Maximum Clamp Current

-4.0

+4.0

40

mA

|I_CLAMP

|

Total Maximum Clamp Current

“L” level maximum output current

-

I_OL1

15

mA Normal outputs with driving strength set to

5mA

“L” level average output current

I_OLAV1

-

5

mA Normal outputs with driving strength set to

5mA

“L” level maximum overall output current

“L” level average overall output current

”H” level maximum output current

I_OL1

I_OLAV1

I_OH1

-

100

50

mA Normal outputs

-15

mA

Normal outputs with driving strength set to

5mA

”H” level average output current

I_OHAV1

-

-5

mA Normal outputs with driving strength set to

5mA

”H” level maximum overall output current

”H” level average overall output current

I_OH1

-

-100

-50

mA Normal outputs

I_OHAV1

T_A=105^oC

mW

430^[5]

750^[5]

540^[5]

375^[5]

750^[5]

470^[5]

560^[5]

335^[5]

670^[5]

840^[5]

420^[5]

590^[5]

-

Permitted Power dissipation (Flash devices in QFP

package) ^[4]

T_A=90^oC

mW

P_D

T_A=125^oC, no Flash program/erase ^[6]

mW

T_A=105^oC

mW

T_A=85^oC

mW

PermittedPowerdissipation(MB96F346/F347/F348

in LQFP package) ^[4]

P_D

T_A=125^oC, no Flash program/erase ^[6]

mW

T_A=120^oC, no Flash program/erase ^[6]

mW

T_A=105^oC

mW

T_A=85^oC

mW

Permitted Power dissipation (MB96F345 in LQFP

package) ^[4]

T_A=75^oC

mW

P_D

T_A=125^oC, no Flash program/erase ^[6]

mW

T_A=115^oC, no Flash program/erase ^[6]

mW

Document Number: 002-04579 Rev. *A

Page 58 of 109

MB96340 Series

Rating

Max

Parameter

Symbol

Unit

Remarks

Min

T_A=105^oC

-

350

360

mW

Permitted Power dissipation (Mask ROM devices)^[4]

P_D

T_A=125^oC ^[6]

MB96V300B

-

0

+70

+105

+125

^oC

-40

T_A

Operating ambient temperature

Storage temperature

[6]

T_STG

-55

+150

[1]: AV_CCand V_CCmust be set to the same voltage. It is required that AV_CCdoes not exceed V_CCand that the voltage at the analog

inputs does not exceed AV_CCneither when the power is switched on.

[2]: V_Iand V_Oshould not exceed V_CC+ 0.3 V. V_Ishould also not exceed the specified ratings. However if the maximum current

to/from a input is limited by some means with external components, the I_CLAMPrating supersedes the V_Irating. Input/output voltages

of standard ports depend on V_CC.

[3]:

■ Applicable to all general purpose I/O pins (Pnn_m)

■ Use within recommended operating conditions.

■ Use at DC voltage (current)

■ The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.

■ The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin

does not exceed rated values, either instantaneously or for prolonged periods.

■ Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through

the protective diode and increase the potential at the V_CCpin, and this may affect other devices.

■ Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from

the pins, so that incomplete operation may result.

■ Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may

not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode).

Sample recommended circuits:

Protective Diode

VCC

Limiting

resistance

P-ch

N-ch

+B input (0V to 16V)

R

Document Number: 002-04579 Rev. *A

Page 59 of 109

MB96340 Series

[4]: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal

conductance of the package on the PCB.The actual power dissipation depends on the customer application and can be calculated

as follows:

P_D= P_IO+ P_INT

P_IO= (V_OL* I_OL+ V_OH* I_OH) (IO load power dissipation, sum is performed on all IO ports)

P_INT= V_CC* (I_CC+ I_A) (internal power dissipation)

I

_CCis the total core current consumption into V_CCas described in the “DC characteristics” and depends on the selected operation

mode and clock frequency and the usage of functions like Flash programming or the clock modulator.I_Ais the analog current

consumption into AV_CC

.

[5]: Worst case value for a package mounted on single layer PCB at specified T_Awithout air flow.

[6]: Please contact Cypress for reliability limitations when using under these conditions.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in

excess of absolute maximum ratings. Do not exceed any of these ratings.

14.2 Recommended Operating Conditions

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

V_CC

C_S

Power supply voltage

3.0

-

5.5

V

Use a low inductance capacitor

(for example X7R ceramic capacitor)

Smoothing capacitor at C pin

3.5

4.7 - 10

15

F

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor

device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these

ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

Users considering application outside the listed conditions are advised to contact their representatives beforehand.

Document Number: 002-04579 Rev. *A

Page 60 of 109

MB96340 Series

14.3 DC characteristics

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Typ

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

Input H voltage

CMOS Hysteresis

0.8/0.2 input selected

0.8 V_CC

V_CC+ 0.3

-

V

0.7 V_CC

V_CC+ 0.3

V_CC4.5V

-

V

CMOS Hysteresis

0.7/0.3 input selected

Port inputs

Pnn_m

V_IH

0.74 V_CC

V_CC< 4.5V

AUTOMOTIVE Hys-

teresis input selected

0.8 V_CC

V_CC+ 0.3

-

V

TTL input selected

2.0

External clock in “Fast

Clock Input mode”

Not available in

MB96F34xY/R/AxA

V_IHX0F

V_IHX0S

0.8 V_CC

X0

X0,X1,

X0A,X1A

External clock in“oscil-

lation mode”

V

_CC+ 0.3

2.5

-

V

V_IHR

V_IHM

0.8 V_CC

V_CC+ 0.3

RSTX

-

V

CMOS Hysteresis input

V_CC- 0.3

MD2-MD0

Input L voltage

CMOS Hysteresis

V_SS- 0.3

0.2 V_CC

0.3 V_CC

-

V

0.8/0.2 input selected

CMOS Hysteresis

0.7/0.3 input selected

V

Port inputs

Pnn_m

V_IL

V

_SS- 0.3

0.5 V_CC

0.46 V_CC

0.8

V_CC4.5V

-

AUTOMOTIVE Hys-

teresis input selected

V_SS- 0.3

V_CC< 4.5V

TTL input selected

V

External clock in “Fast

Clock Input mode”

Not available in

MB96F34xY/R/AxA

V_ILX0F

V_ILX0S

V

_SS- 0.3

0.2 V_CC

0.4

X0

-

X0,X1,

X0A,X1A

External clock in

“oscillation mode”

V

V_ILR

V_ILM

V_SS- 0.3

0.2 V_CC

RSTX

-

V

CMOS Hysteresis input

V_SS+ 0.3

MD2-MD0

-

Output H voltage

4.5V V_CC 5.5V

I

_OH= -2mA

3.0V V_CC 4.5V

_OH= -1.6mA

4.5V V_CC 5.5V

_OH= -5mA

3.0V V_CC 4.5V

_OH= -3mA

4.5V V_CC 5.5V

_OH= -3mA

3.0V V_CC 4.5V

_OH= -2mA

Normal

outputs

V_OH2

V_OH5

V_OH3

V_CC- 0.5

-

V

Driving strength set to 2mA

I

Normal

outputs

Driving strength set to 5mA

I

3mA outputs

I

Document Number: 002-04579 Rev. *A

Page 61 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Typ

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

Output L voltage

4.5V V_CC 5.5V

I

_OL= +2mA

3.0V V_CC 4.5V

_OL= +1.6mA

4.5V V_CC 5.5V

_OL= +5mA

3.0V V_CC 4.5V

_OL= +3mA

3.0V V_CC 5.5V

_OL= +3mA

Normal

outputs

V_OL2

-

0.4

V

Driving strength set to 2mA

I

Normal

outputs

V_OL5

-

0.4

V

Driving strength set to 5mA

I

V_OL3

3mA outputs

Pnn_m

-

0.4

+1

I

V_SS< V_I< V_CC

I_IL

Input leak current

Pull-up resistance

-1

A Single port pin

AV_SS, AVRL < V_I<

AV_CC, AVRH

V_CC 3.3V  10

V_CC 5.0V  10

40

25

100

50

160

100

k

R_UP

Pnn_m, RSTX

Document Number: 002-04579 Rev. *A

Page 62 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Max

Condition (at T_A)

Parameter

Symbol

Remarks

Typ

Unit

+25°C

+125°C

+25°C

+125°C

+25°C

+125°C

+25°C

+125°C

+25°C

35

44

47

23

25

57

60

35

37

50

Flash devices at 0 Flash wait

states

mA

PLL Run mode with CLKS1/2 = 48MHz,

CLKB = CLKP1/2 = 24MHz

36

17

18

44

45

25

26

38

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

MB96345/346 at 0 ROM wait

states

mA

MB96F346/F347/F348 at 2

Flash wait states

PLL Run mode with CLKS1/2 = CLKB =

CLKP1= 56MHz,CLKP2 = 28MHz

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

MB96345/346 at 2 ROM wait

states

I_CCPLL

PLL Run mode with CLKS1/2 = 72MHz,

CLKB = CLKP1 = 36MHz, CLKP2 =

18MHz

MB96F346/F347/F348Y/R/Ayy

at 1 Flash wait state

mA

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

+125°C

+25°C

39

53

Power supply

current in Run

modes^[1]

PLL Run mode with CLKS1/2 = 80MHz,

CLKB = CLKP1 = 40MHz, CLKP2 =

20MHz

TBD

mA MB96F345 at 1 Flash wait state

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

+125°C

+25°C

+125°C

+25°C

49

50

62

65

MB96F348T/H/CyB/C at 1

mA

Flash wait state

PLL Run mode with CLKS1/2 = 96MHz,

CLKB = CLKP1= 48MHz, CLKP2 =

24MHz

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

26

36

MB96345/346 at 1 ROM wait

state

mA

+125°C

+25°C

27

38

4.5

5.1

2.5

3.1

5.5

8.5

3.5

5.5

Flash devices at 1 Flash wait

state

mA

+125°C

+25°C

Main Run mode with CLKS1/2 = CLKB =

CLKP1/2 = 4MHz

I_CCMAIN

(CLKPLL, CLKSC and CLKRC stopped)

MB96345/346 at 1 ROM wait

state

mA

+125°C

Document Number: 002-04579 Rev. *A

Page 63 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Max

Condition (at T_A)

Parameter

Symbol

Remarks

Typ

Unit

+25°C

+125°C

+25°C

2.9

4

6.5

2.7

4.7

0.6

3.5

0.3

3.3

0.6

2.4

0.25

3.2

0.25

2.1

0.2

3

Flash devices at 1 Flash wait

state

mA

3.5

1.7

RC Run mode with CLKS1/2 = CLKB =

CLKP1/2 = 2MHz

I_CCRCH

(CLKMC, CLKPLL and CLKSC stopped)

MB96345/346 at 1 ROM wait

state

mA

+125°C

+25°C

2.3

0.4

MB96F346/F347/F348 at 1

Flash wait state

+125°C

+25°C

0.9

RC Run mode with CLKS1/2 = CLKB =

CLKP1/2 = 100kHz,

0.18

0.68

0.4

SMCR:LPMS = 0

mA MB96F345 at 1 Flash wait state

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in high power mode)

+125°C

+25°C

Power supply

current in Run

modes^[1]

MB96345/346 at 1 ROM wait

state

I_CCRCL

mA

+125°C

+25°C

0.9

0.15

0.65

0.15

0.65

0.1

Flash devices at 1 Flash wait

state

mA

RC Run mode with CLKS1/2 = CLKB =

CLKP1/2 = 100kHz,

+125°C

+25°C

SMCR:LPMS = 1

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in low power mode, no

Flash programming/erasing allowed)

MB96345/346 at 1 ROM wait

state

mA

+125°C

+25°C

Flash devices at 1 Flash wait

state

mA

Sub Run mode with CLKS1/2 = CLKB =

CLKP1/2 = 32kHz

+125°C

+25°C

0.6

I_CCSUB

(CLKMC, CLKPLL and CLKRC stopped,

no Flash programming/erasing allowed)

0.1

0.2

2

MB96345/346 at 1 ROM wait

state

mA

+125°C

0.6

Document Number: 002-04579 Rev. *A

Page 64 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Max

Condition (at T_A)

Parameter

Symbol

Remarks

Typ

Unit

+25°C

+125°C

+25°C

+125°C

+25°C

+125°C

+25°C

+125°C

+25°C

9

10.5

13

mA Flash devices

PLL SleepmodewithCLKS1/2=48MHz,

CLKP1/2 = 24MHz

9.7

8

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

9.5

11.5

15.5

18

mA MB96345/346

8.7

14

mA MB96F346/F347/F348

mA MB96345/346

PLL Sleep mode with CLKS1/2 =

CLKP1= 56MHz, CLKP2 = 28MHz

14.8

13.5

14.3

10.5

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

15

17

I_CCSPLL

PLL SleepmodewithCLKS1/2=72MHz,

CLKP1 = 36MHz,

12

CLKP2 = 18MHz

mA MB96F346/F347/F348Y/R/Ayy

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

+125°C

+25°C

11.3

TBD

14.5

TBD

Power supply

current in Sleep

modes^[1]

PLL SleepmodewithCLKS1/2=80MHz,

CLKP1 = 40MHz,

CLKP2 = 20MHz

mA MB96F345

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

+125°C

+25°C

+125°C

+25°C

15

15.8

14

16.5

19

mA MB96F348T/H/CyB/C

mA MB96345/346

mA Flash devices

PLL SleepmodewithCLKS1/2=96MHz,

CLKP1= 48MHz,

CLKP2 = 24MHz

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

15.5

17.5

1.8

+125°C

+25°C

14.8

1.5

2

+125°C

+25°C

4.5

Main Sleep mode with CLKS1/2 =

CLKP1/2 = 4MHz

I_CCSMAIN

(CLKPLL, CLKSC and CLKRC stopped)

1.5

2

1.8

mA MB96345/346

+125°C

3.8

Document Number: 002-04579 Rev. *A

Page 65 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Max

Condition (at T_A)

Parameter

Symbol

Remarks

Typ

Unit

+25°C

+125°C

+25°C

0.9

1.4

4.1

1.4

3.1

0.5

3.4

0.2

3.1

0.5

2.3

0.15

3

mA Flash devices

mA MB96345/346

mA MB96F346/F347/F348

mA MB96F345

1.5

0.9

RCSleepmodewithCLKS1/2=CLKP1/2

= 2MHz

I_CCSRCH

(CLKMC, CLKPLL and CLKSC stopped)

+125°C

+25°C

1.5

0.3

+125°C

+25°C

0.8

RCSleepmodewithCLKS1/2=CLKP1/2

= 100kHz,

0.09

0.59

0.3

SMCR:LPMSS = 0

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in high power mode)

+125°C

+25°C

Power supply

I_CCSRCL

mA MB96345/346

mA Flash devices

mA MB96345/346

mA Flash devices

mA MB96345/346

current in Sleep

modes^[1]

+125°C

+25°C

0.8

0.06

0.56

0.06

0.56

0.04

0.54

0.04

0.54

RCSleepmodewithCLKS1/2=CLKP1/2

= 100kHz,

+125°C

+25°C

SMCR:LPMSS = 1

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in low power mode)

0.15

1.9

0.12

2.9

0.12

1.85

+125°C

+25°C

+125°C

+25°C

Sub Sleep mode with CLKS1/2 =

CLKP1/2 = 32kHz

I_CCSSUB

(CLKMC, CLKPLL and CLKRC stopped)

+125°C

Document Number: 002-04579 Rev. *A

Page 66 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Max

Condition (at T_A)

Parameter

Symbol

Remarks

Typ

Unit

+25°C

+125°C

+25°C

1.6

2

5

mA Flash devices

mA MB96345/346

mA MB96F346/F347/F348

mA MB96F345

PLL Timer mode with CLKMC = 4MHz,

CLKPLL = 48MHz

2.1

1.6

I_CCTPLL

(CLKRC and CLKSC stopped. Core volt-

age at 1.9V)

2

+125°C

+25°C

2.1

4

0.35

0.85

0.13

0.63

0.35

0.85

0.1

0.5

3.3

0.2

3

+125°C

+25°C

Main Timer mode with CLKMC = 4MHz,

SMCR:LPMSS = 0

(CLKPLL, CLKRC and CLKSC stopped.

Voltage regulator in high power mode)

+125°C

+25°C

0.5

2.3

0.15

2.9

0.15

1.9

0.5

3.3

0.2

3

I_CCTMAIN

mA MB96345/346

mA Flash devices

MB96345/346

+125°C

+25°C

Main Timer mode with CLKMC = 4MHz,

SMCR:LPMSS = 1

Power supply

+125°C

+25°C

0.6

current in Timer

modes^[1]

(CLKPLL, CLKRC and CLKSC stopped.

Voltage regulator in low power mode)

0.1

+125°C

+25°C

0.6

0.35

0.85

0.13

0.63

0.35

0.85

0.1

mA MB96F346/F347/F348

mA MB96F345

+125°C

+25°C

RC Timer mode with CLKRC = 2MHz,

SMCR:LPMSS = 0

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in high power mode)

+125°C

+25°C

0.5

2.3

0.15

2.9

0.15

1.9

I_CCTRCH

mA MB96345/346

mA Flash devices

mA MB96345/346

+125°C

+25°C

RC Timer mode with CLKRC = 2MHz,

SMCR:LPMSS = 1

+125°C

+25°C

0.6

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in low power mode)

0.1

+125°C

0.6

Document Number: 002-04579 Rev. *A

Page 67 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Max

Condition (at T_A)

Parameter

Symbol

Remarks

Typ

Unit

+25°C

+125°C

+25°C

0.3

0.45

3.2

mA MB96F346/F347/F348

mA MB96F345

0.8

0.08

0.58

0.3

RC Timer mode with CLKRC = 100kHz,

SMCR:LPMSS = 0

0.15

2.95

0.45

2.2

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in high power mode)

+125°C

+25°C

I_CCTRCL

mA MB96345/346

mA Flash devices

mA MB96345/346

mA Flash devices

mA MB96345/346

mA Flash devices

mA MB96345/346

mA Flash devices

+125°C

+25°C

0.8

Power supply

0.05

0.55

0.05

0.55

0.03

0.53

0.03

0.53

0.02

0.52

0.02

0.52

0.015

0.4

0.1

current in Timer

modes^[1]

RC Timer mode with CLKRC = 100kHz,

SMCR:LPMSS = 1

+125°C

+25°C

2.85

0.1

(CLKMC, CLKPLL and CLKSC stopped.

Voltage regulator in low power mode)

+125°C

+25°C

1.85

0.1

+125°C

+25°C

2.85

0.1

Sub Timer mode with CLKSC = 32kHz

(CLKMC, CLKPLL and CLKRC stopped)

I_CCTSUB

+125°C

+25°C

1.85

0.08

2.8

+125°C

+25°C

VRCR:LPMB[2:0] = 110_B

(Core voltage at 1.8V)

0.08

1.8

+125°C

+25°C

Power supply

I_CCH

current in Stop

Mode

0.06

2.3

+125°C

+25°C

VRCR:LPMB[2:0] = 000_B

(Core voltage at 1.2V)

0.015

0.4

0.06

1.4

mA MB96345/346

MB96F345

+125°C

-

5

10

A

Must be added to all current

above

Power supply

current for active

Low Voltage

Low voltage detector enabled

(RCR:LVDE = 1)

I_CCLVD

+25°C

90

140

150

Other devices

detector

A

Must be added to all current

above

+125°C

100

Document Number: 002-04579 Rev. *A

Page 68 of 109

MB96340 Series

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Max

Condition (at T_A)

Parameter

Symbol

Remarks

Typ

Unit

Power supply

Clock modulator enabled

(CMCR:PDX = 1)

Must be added to all current

above

I_CCCLOMO

current for active

Clock modulator

-

3

4.5

mA

Must be added to all current

above

I_CCFLASH

Current for one Flash module

15

10

40

20

mA

Flash

Write/Erase

current

Must be added to all current

above

I_CCDFLASH

Current for one Data Flash module

Other than C, AV_CC, AV_SS

AVRH, AVRL, V_CC, V_SS

,

Input

capacitance

C_IN

-

5

15

pF

[1]: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock

connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further

details about voltage regulator control.

Document Number: 002-04579 Rev. *A

Page 69 of 109

MB96340 Series

14.4 AC Characteristics

14.4.1 Source Clock timing

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

3

-

16

MHz When using a crystal oscillator, PLL off

When using an opposite phase external clock,

0

-

16

MHz

f_C

Clock frequency

X0, X1

PLL off

When using a crystal oscillator or opposite phase

external clock, PLL on

3.5

MHz

When using a single phase external clock in “Fast

MHz Clock Input mode” (not available in

MB96F34xY/R/AxA), PLL off

0

-

56

f_FCI

Clock frequency

X0

When using a single phase external clock in “Fast

MHz Clock Input mode” (not available in

MB96F34xY/R/AxA), PLL on

3.5

32

0

32.768

100

50

kHz When using an oscillation circuit

X0A, X1A

f_CL

Clock frequency

-

kHz When using an opposite phase external clock

kHz When using a single phase external clock

kHz When using slow frequency of RC oscillator

MHz When using fast frequency of RC oscillator

X0A

-

0

50

1

100

2

200

4

f_CR

Permitted VCO output frequency of PLL

f_CLKVCO

T_PSKEW

PLLClockfrequency

PLL Phase Jitter

-

64

-

200

 5

-

MHz

(CLKVCO)

ns

For CLKMC (PLL input clock) MHz

Input clock pulse

width

P

_WH, P_WL

X0,X1

8

Duty ratio is about 30% to 70%

Input clock pulse

width

P_WHL, P_WLL

X0A,X1A

5

-

s

t_CYL

V_IH

V_IL

X0

P_WH

P_WL

t_CYLL

V_IH

V_IL

X0A

P_WH

P_WL

L

Document Number: 002-04579 Rev. *A

Page 70 of 109

MB96340 Series

14.4.2 Internal Clock timing

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Core Voltage Settings

1.8V 1.9V

Parameter

Symbol

Unit

Remarks

Min

0

Max

92

Min

0

Max

96

MHz

Others than below

MB96F348T/H/CxB/C

MB96F345

0

86

0

96

Internal System clock frequency

(CLKS1 and CLKS2)

f

_CLKS1, f_CLKS2

0

72

0

80

0

68

0

74

MB96F34xY/R/Axx

Others than below

MB96F345

InternalCPUclockfrequency(CLKB),

internal peripheral clock frequency

(CLKP1)

0

52

0

56

f_CLKB, f_CLKP1

0

36

0

40

0

28

0

32

Others than below

MB96F34xY/R/Axx

Internal peripheral clock frequency

(CLKP2)

f_CLKP2

0

26

0

28

14.4.3 External Reset timing

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

t_RSTL

Reset input time

RSTX

500

-

ns

t_RSTL

RSTX

0.2 V_CC

Document Number: 002-04579 Rev. *A

Page 71 of 109

MB96340 Series

14.4.4 Power On Reset timing

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Parameter

Symbol

Unit

Remarks

Min

0.05

1

Typ

Max

30

-

t_R

Power on rise time

Power off time

Vcc

-

ms

t_OFF

tR

2.7V

V

CC

0.2 V

tOFF

If the power supply is changed too rapidly, a power-on reset may occur.

We recommend a smooth startup by restraining voltages when changing the

power supply voltage during operation, as shown in the figure below.

V

CC

Rising edge of 50 mV/ms

maximum is allowed

3 V

Document Number: 002-04579 Rev. *A

Page 72 of 109

MB96340 Series

14.4.5 External Input timing

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Min

Parameter Symbol

Condition

Unit Used Pin input function

Max

INTn(_R)

NMI(_R)

Pnn_m

External Interrupt

200

-

ns

NMI

General Purpose IO

Reload Timer

TINn(_R)

TTGn(_R)

ADTG(_R)

Input pulse

width

t_INH

t_INL

-

PPG Trigger input

2*t_CLKP1+ 200

(t_CLKP1=1/f_CLKP1

-

ns

AD Converter Trigger

)

FreeRunningTimerexternal

clock

FRCKn(_R)

INn(_R)

Input Capture

Note : Relocated Resource Inputs have same characteristics

V_IH

External Pin input

V_IL

t_INH

t_INL

14.4.6 External Bus timing

Note: The values given below are for an I/O driving strength IO_drive= 5mA. If IO_driveis 2mA, all the maximum output timing

described in the different tables must then be increased by 10ns.

Document Number: 002-04579 Rev. *A

Page 73 of 109

MB96340 Series

14.4.7 Basic Timing

(T_A 40°C to 125°C, V_CC 5.0 V  10, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

25

Max

t_CYC

t_CHCL

-

ECLK

-

t_CYC/2-5

-20

t_CYC/2+5

20

ns

t_CLCH

t_CHCBH

t_CHCBL

t_CLCBH

t_CLCBL

t_CHLH

-20

20

CSn, UBX, LBX,

ECLK

ECLK →UBX/ LBX / CSn time

-

ns

-20

20

-20

20

-10

10

t_CHLL

-10

10

ECLK → ALE time

ALE, ECLK

t_CLLH

-10

10

t_CLLL

-10

10

t_CHAV

-15

15

A[23:16], ECLK

AD[15:0], ECLK

-

ns

t_CLAV

-15

15

ECLK →address valid time

t_CLADV

t_CHADV

t_CHRWH

t_CHRWL

t_CLRWH

t_CLRWL

-15

15

-15

15

-10

10

RDX, WRX,

WRLX,WRHX,

ECLK

-10

10

ECLK → RDX /WRX time

-

ns

-10

10

-10

10

Document Number: 002-04579 Rev. *A

Page 74 of 109

MB96340 Series

(T_A 40°C to 125°C, V_CC 3.0 to 4.5V, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

30

Max

t_CYC

t_CHCL

-

ECLK

-

t_CYC/2-8

-25

t_CYC/2+8

25

ns

t_CLCH

t_CHCBH

t_CHCBL

t_CLCBH

t_CLCBL

t_CHLH

-25

25

CSn, UBX, LBX,

ECLK

ECLK →UBX/ LBX / CSn time

-

ns

-25

25

-25

25

-15

15

t_CHLL

-15

15

ECLK → ALE time

ALE, ECLK

t_CLLH

-15

15

t_CLLL

-15

15

t_CHAV

-20

20

A[23:16], ECLK

AD[15:0], ECLK

-

ns

t_CLAV

-20

20

ECLK →address valid time

t_CLADV

t_CHADV

t_CHRWH

t_CHRWL

t_CLRWH

t_CLRWL

-20

20

-20

20

-15

15

RDX, WRX,

WRLX, WRHX,

ECLK

-15

15

ECLK → RDX /WRX time

-

ns

-15

15

-15

15

Document Number: 002-04579 Rev. *A

Page 75 of 109

MB96340 Series

t_CYC

t_CHCL

t_CLCH

0.8*Vcc

ECLK

0.2*Vcc

t_CLAV

t_CHAV

A[23:16]

t_CHCBL

t_CLCBL

t_CHCBH

t_CLCBH

CSn

LBX UBX

t_CHRWL

t_CLRWL

t_CHRWH

t_CLRWH

RDX

WRX (WRLX, WRHX)

t_CHLL

t_CLLL

t_CLLH

t_CHLH

ALE

t_CHADV

t_CLADV

Address

AD[15:0]

Refer to the Hardware Manual for detailed Timing Charts

Document Number: 002-04579 Rev. *A

Page 76 of 109

MB96340 Series

14.4.8 Bus Timing (Read)

(T_A 40°C to 125°C, V_CC 5.0 V  10, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

EACL:STS=0 and

EACL:ACE=0

t

_CYC/2  5

t_CYC 5

-

ALE pulse width

t_LHLL

ALE

EACL:STS=1

ns

EACL:STS=0 and

EACL:ACE=1

3t_CYC/2  5

t_CYC 15

EACL:STS=0 and

EACL:ACE=0

-

EACL:STS=1 and

EACL:ACE=0

3t_CYC/2  15

2t_CYC 15

5t_CYC/2  15

t_AVLL

ALE, A[23:16],

ns

EACL:STS=0 and

EACL:ACE=1

EACL:STS=1 and

EACL:ACE=1

Valid address  ALE  time

EACL:STS=0 and

EACL:ACE=0

t

_CYC/2  15

t_CYC 15

EACL:STS=1 and

EACL:ACE=0

t_ADVLL

ALE,AD[15:0]

ns

EACL:STS=0 and

EACL:ACE=1

3t_CYC/2  15

2t_CYC 15

EACL:STS=1 and

EACL:ACE=1

EACL:STS=0

EACL:STS=1

EACL:ACE=0

t

_CYC/2  15

-

ALE   Address valid time

t_LLAX

ALE, AD[15:0]

RDX, A[23:16]

ns

-15

3t_CYC/2  15

-

t_AVRL

EACL:ACE=1

EACL:ACE=0

EACL:ACE=1

EACL:ACE=0

EACL:ACE=1

EACL:ACE=0

EACL:ACE=1

5t_CYC/2  15

Valid address  RDX  time

t_CYC 15

t_ADVRL

RDX, AD[15:0]

ns

2t_CYC 15

-

3t_CYC 55

4t_CYC 55

5t_CYC/2  55

7t_CYC/2  55

-

A[23:16],

AD[15:0]

w/o cycle

extension

t_AVDV

ns

-

Valid address  Valid data

input

-

w/o cycle

extension

t_ADVDV

AD[15:0]

-

w/o cycle

extension

RDX pulse width

t_RLRH

t_RLDV

RDX

-

3 t_CYC/2  5

ns

w/o cycle

extension

RDX   Valid data input

RDX, AD[15:0]

-

3 t_CYC/2  50

RDX   Data hold time

t_RHDX

t_AXDX

RDX, AD[15:0]

-

0

-

ns

Address valid  Data hold time

A[23:16], AD[15:0]

Document Number: 002-04579 Rev. *A

Page 77 of 109

MB96340 Series

(T_A 40°C to 125°C, V_CC 5.0 V  10, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

EACL:STS=1 and

EACL:ACE=1

3t_CYC/2  10

-

RDX   ALE  time

t_RHLH

RDX, ALE

ns

other ECL:STS, EA-

CL:ACE setting

t

_CYC/2  10

t_CYC 15

-

t_AVCH

t_ADVCH

t_RLCH

A[23:16], ECLK

AD[15:0], ECLK

RDX, ECLK

-

Valid address

 ECLK  time

-

ns

t_CYC/2  15

t_CYC/2  10

RDX   ECLK  time

ALE   RDX  time

ECLK  Valid data input

-

EACL:STS=0

EACL:STS=1

-

t

_CYC/2  10

t_LLRL

ALE, RDX

 10

t_CHDV

AD[15:0], ECLK

-

t_CYC 50

ns

(T_A 40°C to 125°C, V_CC 3.0 to 4.5V, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

EACL:STS=0 and

EACL:ACE=0

t

_CYC/2  8

t_CYC 8

-

ALE pulse width

t_LHLL

ALE

EACL:STS=1

ns

EACL:STS=0 and

EACL:ACE=1

3t_CYC/2  8

t_CYC 20

EACL:STS=0 and

EACL:ACE=0

-

EACL:STS=1 and

EACL:ACE=0

3t_CYC/2  20

2t_CYC 20

5t_CYC/2  20

t_AVLL

ALE, A[23:16],

ns

EACL:STS=0 and

EACL:ACE=1

EACL:STS=1 and

EACL:ACE=1

Valid address  ALE  time

EACL:STS=0 and

EACL:ACE=0

t

_CYC/2  20

t_CYC 20

EACL:STS=1 and

EACL:ACE=0

t_ADVLL

ALE, AD[15:0]

ns

EACL:STS=0 and

EACL:ACE=1

3t_CYC/2  20

2t_CYC 20

EACL:STS=1 and

EACL:ACE=1

EACL:STS=0

EACL:STS=1

EACL:ACE=0

t

_CYC/2  20

-

ALE   Address valid time

Valid address  RDX  time

t_LLAX

ALE, AD[15:0]

RDX, A[23:16]

ns

-20

3t_CYC/2  20

5t_CYC/2  20

t_CYC 20

-

t_AVRL

EACL:ACE=1

EACL:ACE=0

EACL:ACE=1

t_ADVRL

RDX, AD[15:0]

ns

2t_CYC 20

Document Number: 002-04579 Rev. *A

Page 78 of 109

MB96340 Series

(T_A 40°C to 125°C, V_CC 3.0 to 4.5V, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

EACL:ACE=0

-

3t_CYC 60

4t_CYC 60

5t_CYC/2  60

7t_CYC/2  60

-

A[23:16],

AD[15:0]

w/o cycle

extension

t_AVDV

ns

EACL:ACE=1

EACL:ACE=0

EACL:ACE=1

-

Valid address  Valid data

input

-

w/o cycle

extension

t_ADVDV

AD[15:0]

-

w/o cycle

extension

RDX pulse width

t_RLRH

t_RLDV

RDX

-

3t_CYC/2  8

ns

w/o cycle

extension

RDX   Valid data input

RDX, AD[15:0]

-

3t_CYC/2  55

RDX   Data hold time

t_RHDX

t_AXDX

RDX, AD[15:0]

A[23:16]

-

0

-

ns

Address valid  Data hold time

EACL:STS=1 and

EACL:ACE=1

3t_CYC/2  15

-

RDX   ALE  time

t_RHLH

RDX, ALE

ns

other ECL:STS, EA-

CL:ACE setting

t

_CYC/2  15

t_CYC 20

t_AVCH

t_ADVCH

t_RLCH

A[23:16], ECLK

AD[15:0], ECLK

RDX, ECLK

-

Valid address  ECLK  time

RDX   ECLK  time

ALE   RDX  time

-

ns

t_CYC/2  20

t_CYC/2  15

 15

-

EACL:STS=0

EACL:STS=1

-

t_LLRL

ALE, RDX

-

ECLK  Valid data input

t_CHDV

AD[15:0], ECLK

-

t_CYC 55

Document Number: 002-04579 Rev. *A

Page 79 of 109

MB96340 Series

t_AVCH

t_CHDV

t_RLCH

t_ADVCH

0.8*Vcc

ECLK

t_AVLL

t_LLAX

t_ADVLL

t_RHLH

ALE

0.2*V_CC

t_LHLL

t_AVRL

t_ADVRL

t_RLRH

RDX

t_LLRL

A[23:16]

t_RLDV

t_AXDX

t_AVDV

t_RHDX

t_ADVDV

V_IH

V_IL

AD[15:0]

Address

Read data

V_IL

Refer to the Hardware Manual for detailed Timing Charts

.

Document Number: 002-04579 Rev. *A

Page 80 of 109

MB96340 Series

14.4.9 Bus Timing (Write)

(T_A 40°C to 125°C, V_CC 5.0 V  10, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

EACL:ACE=0

3t_CYC/2  15

5t_CYC/2  15

t_CYC 15

-

WRX, WRLX,

WRHX, A[23:16]

t_AVWL

ns

EACL:ACE=1

EACL:ACE=0

EACL:ACE=1

-

Valid address  WRX  time

WRX, WRLX,

WRHX, AD[15:0]

t_ADVWL

ns

2t_CYC 15

WRX, WRXL,

WRHX

w/o cycle

extension

WRX pulse width

t_WLWH

-

t_CYC 5

Valid data output  WRX 

time

WRX, WRLX,

WRHX, AD[15:0]

w/o cycle

extension

t_DVWH

t_WHDX

t_WHAX

-

t_CYC 20

-

ns

WRX, WRLX,

WRHX, AD[15:0]

WRX   Data hold time

t

_CYC/2  15

WRX, WRLX,

WRHX, A[23:16]

WRX   Address valid time

EBM:ACE=1 and

EACL:STS=1

2t_CYC 10

t_CYC 10

-

WRX   ALE  time

WRX, WRLX,

WRHX, ALE

t_WHLH

ns

other EBM:ACE and

EACL:STS setting

WRX, WRLX,

WRHX, ECLK

WRX   ECLK  time

CSn  WRX time

t_WLCH

-

t

_CYC/2  10

-

EACL:ACE=0

-

3t_CYC/2  15

5t_CYC/2  15

-

WRX, WRLX,

WRHX, CSn

t_CSLWL

ns

EACL:ACE=1

-

WRX  CSn time

WRX, WRLX,

WRHX, CSn

t_WHCSH

t

_CYC/2  15

(T_A 40°C to 125°C, V_CC 3.0 to 4.5V, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

EACL:ACE=0

3t_CYC/2  20

-

WRX, WRLX,

WRHX, A[23:16]

t_AVWL

ns

EACL:ACE=1

EACL:ACE=0

EACL:ACE=1

5t_CYC/2  20

t_CYC 20

-

Valid address  WRX  time

WRX, WRLX,

WRHX, AD[15:0]

t_ADVWL

ns

2t_CYC 20

Document Number: 002-04579 Rev. *A

Page 81 of 109

MB96340 Series

(T_A 40°C to 125°C, V_CC 3.0 to 4.5V, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

WRX, WRXL,

WRHX

w/o cycle

extension

WRX pulse width

t_WLWH

-

t_CYC 8

-

ns

Valid data output  WRX 

time

WRX, WRLX,

WRHX, AD[15:0]

w/o cycle

extension

t_DVWH

t_WHDX

t_WHAX

-

t_CYC 25

-

ns

WRX, WRLX,

WRHX, AD[15:0]

WRX   Data hold time

t

_CYC/2  20

WRX   Address valid time

WRX, WRLX,

WRHX, A[23:16]

EBM:ACE=1 and

EACL:STS=1

2t_CYC 15

t_CYC 15

-

WRX, WRLX,

WRHX, ALE

WRX   ALE  time

WRX   ECLK  time

CSn  WRX time

t_WHLH

ns

other EBM:ACE and

EACL:STS setting

WRX, WRLX,

WRHX, ECLK

t_WLCH

-

t

_CYC/2  15

-

EACL:ACE=0

-

3t_CYC/2  20

5t_CYC/2  20

-

WRX, WRLX,

WRHX, CSn

t_CSLWL

ns

EACL:ACE=1

-

WRX  CSn time

WRX, WRLX,

WRHX, CSn

t_WHCSH

t

_CYC/2  20

Document Number: 002-04579 Rev. *A

Page 82 of 109

MB96340 Series

t_WLCH

0.8*V_CC

ECLK

t_WHLH

ALE

t_AVWL

t_WLWH

t_ADVWL

WRX (WRLX, WRHX)

0.2*V_CC

t_CSLWL

t_WHCS

CSn

t

WHAX

A[23:16]

t_DVWH

t

WHDX

AD[15:0]

Address

Write data

Refer to the Hardware Manual for detailed Timing Charts

.

14.4.10 Ready Input Timing

(T_A 40°C to 125°C, V_CC 5.0 V  10, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Rated Value

Test

Parameter

Symbol

Units

Remarks

Condition

Min

35

0

Max

RDY setup time

RDY hold time

t_RYHS

t_RYHH

RDY

-

ns

-

(T_A 40°C to 125°C, V_CC 3.0 to 4.5V, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Rated Value

Test

Parameter

Symbol

Units

Remarks

Condition

Min

45

0

Max

RDY setup time

RDY hold time

t_RYHS

t_RYHH

RDY

-

ns

-

Note: If the RDY setup time is insufficient, use the auto-ready function.

Document Number: 002-04579 Rev. *A

Page 83 of 109

MB96340 Series

0.8*V_CC

ECLK

t_RYHS

V_IH

t_RYHH

V_IH

RDY

When WAIT is not used.

RDY

V_IL

When WAIT is used.

Refer to the Hardware Manual for detailed Timing Charts

14.4.11 Hold Timing

(T_A 40°C to 125°C, V_CC 5.0 V  10, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Condition

Units

Remarks

Min

Max

Pin floating  HAKX  time

HAKX  time  Pin valid time

t_XHAL

t_HAHV

HAKX

t_CYC 20

t_CYC+ 20

ns

-

(T_A 40°C to 125°C, V_CC 3.0 to 4.5V, V_SS 0.0 V, IO_drive= 5mA, C_L= 50pF)

Value

Parameter

Symbol

Condition

Units

Remarks

Min

Max

Pin floating  HAKX  time

HAKX  time  Pin valid time

t_XHAL

t_HAHV

HAKX

t_CYC 25

t_CYC+ 25

ns

-

0.8*V_CC

HAKX

0.2*V_CC

t_HAHV

t_XHAL

High-Z

0.8*V_CC

0.2*V_CC

Each pin

Refer to the Hardware Manual for detailed Timing Charts

Document Number: 002-04579 Rev. *A

Page 84 of 109

MB96340 Series

14.4.12 USART timing

WARNING: The values given below are for an I/O driving strength IO_drive= 5mA. If IO_driveis 2mA, all the maximum output timing

described in the different tables must then be increased by 10ns.

(T_A= -40°C to 125°C, V_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V, IO_drive= 5mA, C_L= 50pF)

V_CC= AV_CC= 4.5V to 5.5V V_CC= AV_CC= 3.0V to 4.5V

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

Serial clock cycle time

t_SCYCI

t_SLOVI

SCKn

4 t_CLKP1

-

4 t_CLKP1

-

ns

SCKn,

SOTn

SCK ↓→ SOT delay time

-20

20

-30

N*t_CLKP1- 30 ^[1]

t_CLKP1+ 55

0

30

SCKn,

SOTn

SOT → SCK ↑ delay time

Valid SIN → SCK ↑

t_OVSHI

t_IVSHI

t_SHIXI

Internal Shift

Clock Mode

N*t_CLKP1- 20 ^[1]

-

ns

SCKn,

SINn

t

_CLKP1+ 45

0

SCKn,

SINn

SCK ↑→ Valid SIN hold time

Serial clock “L” pulse width

Serial clock “H” pulse width

t_SLSHE

t_SHSLE

SCKn

t

_CLKP1+ 10

-

t_CLKP1+ 10

-

ns

t_CLKP1+ 10

SCKn,

SOTn

SCK ↓→ SOT delay time

Valid SIN → SCK ↑

t_SLOVE

t_IVSHE

t_SHIXE

-

2 t_CLKP1+ 45

-

2 t_CLKP1+ 55

ns

SCKn,

SINn

External Shift

Clock Mode

t

_CLKP1/2 + 10

-

t_CLKP1/2 + 10

t_CLKP1+ 10

-

SCKn,

SINn

SCK ↑→ Valid SIN hold time

t

_CLKP1+ 10

SCK fall time

t_FE

t_RE

SCKn

-

20

-

20

ns

SCK rise time

Notes:

■ AC characteristic in CLK synchronized mode.

■ C_Lis the load capacity value of pins when testing.

■ Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These

parameters are shown in “MB96300 Super series HARDWARE MANUAL”.

■ t_CLKP1is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns

[1]: Parameter N depends on t_SCYCIand can be calculated as follows:

■ if t_SCYCI= 2*k*t_CLKP1, then N = k, where k is an integer > 2

■ if t_SCYCI= (2*k+1)*t_CLKP1, then N = k+1, where k is an integer > 1

Examples:

t_SCYCI

4*t_CLKP1

5*t_CLKP1,

7*t_CLKP1,

...

N

2

3

4

...

Document Number: 002-04579 Rev. *A

Page 85 of 109

MB96340 Series

t_SCYCI

SCK for

0.8*V_CC

ESCR:SCES = 0

0.2*V_CC

0.8*V_CC

SCK for

0.8*V_CC

ESCR:SCES = 1

0.2*V_CC

t_OVSHI

t_SLOVI

0.8*V_CC

0.2*V_CC

SOT

SIN

t_SHIXI

t_IVSHI

V_IH

V_IL

V_IH

V_IL

Internal Shift Clock Mode

t_SLSHE

t_SHSLE

SCK for

V

V_IH

IH

V_IL

ESCR:SCES = 0

V_IL

SCK for

V_IH

V_IL

V_IH

ESCR:SCES = 1

V_IL

tFE

tSLOVE

tRE

0.8*V_CC

0.2*V_CC

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

External Shift Clock Mode

Document Number: 002-04579 Rev. *A

Page 86 of 109

MB96340 Series

2

14.4.13 I C Timing

(T_A= -40°C to 125°C, V_CC= AV_CC= 3.0V to 5.5V,V_SS= AV_SS=0V)

Fast-mode^[4]

Unit

Standard-mode

Parameter

Symbol

Condition

Min

0

Max

Min

Max

SCL clock frequency

f_SCL

t_HDSTA

t_LOW

100

0

400

kHz

s

Hold time (repeated) START condition SDA↓→SCL

“L” width of the SCL clock

4.0

4.7

4.0

-

0.6

1.3

0.6

-

s

“H” width of the SCL clock

t_HIGH

s

Set-up time for a repeated START condition

SCL↓→SDA↑

R  1.7 k,

C  50 pF^[1]

t_SUSTA

4.7

-

0.6

-

s

Data hold timeSCL↑→SDA↑↓

t_HDDAT

t_SUDAT

t_SUSTO

t_BUS

0

3.45^[2]

0

0.9^[3]

s

ns

s

Data set-up timeSDA↑↓→SCL↑

250

4.0

4.7

-

100

0.6

1.3

-

Set-up time for STOP conditionSCL↑→SDA↑

Bus free time between a STOP and START condition

[1] : R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.

[2]: The maximum t_HDDAThave only to be met if the device does not stretch the “L” width (t_LOW) of the SCL signal.

[3] : A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t_SUDAT≥ 250 ns must then

be met.

[4] : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.

SDA

t

BUS

tSUDAT

t

HDSTA

tLOW

SCL

tHIGH

t

HDSTA

t

HDDAT

t

SUSTA

tSUSTO

Document Number: 002-04579 Rev. *A

Page 87 of 109

MB96340 Series

14.5 Analog Digital Converter

(T_A= -40 °C to +125 °C, 3.0 V AVRH - AVRL, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Parameter

Symbol Pin

Unit

Remarks

Min

-

Typ

Max

10

Resolution

-

bit

LSB

V

Total error

-

-3

+3

Nonlinearity error

-

-2.5

-1.9

+2.5

+1.9

Differential nonlinearity error

Zero reading voltage

V_OT

ANn

AVRL - 1.5 LSB AVRL+ 0.5 LSB AVRL + 2.5 LSB

V_FST

Full scale reading voltage

ANn AVRH - 3.5 LSB AVRH - 1.5 LSB AVRH + 0.5 LSB

V

4.5V V_CC 5.5V

3.0V V_CC 4.5V

4.5V V_CC 5.5V

3.0V V_CC 4.5V

1.0

2.0

0.5

1.2

-

16,500

s

Compare time

-

Sampling time

-

AV_SS, AVRL < V_I< AV_CC

AVRH

,

I_AIN

Analog port input curren

ANn

-3

-1

-

+3

+1

A

T_A= 25 °C, AV_SS, AVRL < V_I<

AV_CC, AVRH

I_AIN

Analog port input curren

ANn

T_A= 125 °C,AV_SS, AVRL < V_I

< AV_CC, AVRH

-3

-

+3

A

V_AIN

Analog input voltage range

Reference voltage range

AVRL

AVRH

V

AVRH/

AVRH

2

AVRH

0.75 AVcc

-

AVcc

V

AV_SS

0.25 AV_CC

AVRL

I_A

AVRL

AVcc

-

2.5

-

V

-

5

mA

A

A/D Converter active

Power supply current

I_AH

A/D Converter not operated

AVRH/

AVRL

I_R

I_RH

-

0.7

1

5

4

mA

A

A/D Converter active

Reference voltage current

AVRH/

AVRL

-

A/D Converter not operated

Offset between input

channels

ANn

LSB

Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.

Document Number: 002-04579 Rev. *A

Page 88 of 109

MB96340 Series

14.5.1

Definition of A/D Converter Terms

■ Resolution: Analog variation that is recognized by an A/D converter.

■ Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition

error and nonlinearity error.

■ Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”) and full-scale transition

line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.

■ Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

■ Zero reading voltage: Input voltage which results in the minimum conversion value.

■ Full scale reading voltage: Input voltage which results in the maximum conversion value.

Total error

3FF

1.5 LSB

3FE

3FD

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

V

NT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVRL

AVRH

Analog input

V_NT {1 LSB  (N  1)  0.5 LSB}

[LSB]

Total error of digital output “N” 

1 LSB  (Ideal value)

1 LSB

AVRH  AVRL

1024

[V]

N: A/D converter digital output value

V_OT(Ideal value)  AVRL  0.5 LSB [V]

V_FST(Ideal value)  AVRH  1.5 LSB [V]

V_NT: A voltage at which digital output transitions from (N  1) to N.

Document Number: 002-04579 Rev. *A

Page 89 of 109

MB96340 Series

Nonlinearity error

Differential nonlinearity error

Ideal

characteristics

3FF

3FE

3FD

Actual conversion

characteristics

N + 1

Actual conversion

characteristics

{1 LSB × (N − 1)

+ V^OT}

V^FST(actual

measurement

value)

N

V^NT(actual

measurement value)

004

003

002

001

V ^(N+ 1) T

(actual measurement

value)

Actual conversion

characteristics

N − 1

N − 2

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

V^OT(actual measurement value)

Analog input

AVRL

AVRH

AVRL

AVRH

Analog input

V_NT {1 LSB  (N  1)  V_OT

}

[LSB]

Nonlinearity error of digital output N 

1 LSB

V (_N+1) _T V_NT

 1LSB [LSB]

Differential nonlinearity error of digital output N 

1 LSB

V_FST V_OT

[V]

1 LSB 

1022

N: A/D converter digital output value

V_OT: Voltage at which digital output transits from “000_H” to “001_H.”

V_FST: Voltage at which digital output transits from “3FE_H” to “#FF_H.”

Document Number: 002-04579 Rev. *A

Page 90 of 109

MB96340 Series

14.5.2

Notes on A/D Converter Section

■ About the external impedance of the analog input and the sampling time of the A/D converter (with sample and hold circuit):

If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold

capacitor is insufficient, adversely affecting A/D conversion precision.

Analog input circuit model:

R

Comparator

Analog input

C

Sampling switch

Reference value:

C = 8.5 pF (Max)

To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum sampling time must

be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be

decreased so that the sampling time (T_samp) is longer than the minimum value. Usually, this value is set to 7where= RC. If the

external input resistance (R_ext) connected to the analog input is included, the sampling time is expressed as follows:

T_samp[min] = 7 (R_ext+ 2.6k) C for 4.5 AV_cc5.5

T_samp[min] = 7 (R_ext+ 12.1k) C for 3.0 AV_cc4.5

If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.

■ About the error

The accuracy gets worse as |AVRH - AVRL| becomes smaller.

Document Number: 002-04579 Rev. *A

Page 91 of 109

MB96340 Series

14.6 Alarm Comparator

(T_A= -40 °C to +125 °C, V_CC= AV_CC= 3.0V - 5.5V, V_SS= AV_SS= 0V)

Value

Typ

Parameter

Symbol

Unit

Remarks

Min

Max

Alarm comparator

I_A5ALMF

-

25

45

A

enabled in fast mode

(one channel)

Alarm comparator

AV_CC

Power supply current

I_A5ALMS

-

7

-

13

5

A

enabled in slow mode

(one channel)

Alarm comparator

disabled

I_A5ALMH

T

_A= 25 °C

-1

-3

-

+1

+3

A

I_ALIN

ALARM pin input current

T_A= 125 °C

ALARM pin input voltage

range

V_ALIN

AV_CC

-

0.36 * AV_CC+0.1 0.36* AV_CC+0.25

0.78 * AV_CC-0.25 0.78 * AV_CC-0.1

0.78 * AV_CC+0.1 0.78* AV_CC+0.25

0

-

V

External low threshold

high->low transition

V_EVTL(H->L)

V_EVTL(L->H)

V_EVTH(H->L)

V_EVTH(L->H)

V_IVTL(H->L)

V_IVTL(L->H)

V_IVTH(H->L)

V_IVTH(L->H)

0.36 * AV_CC-0.25 0.36 * AV_CC-0.1

External low threshold

low->high transition

-

INTREF = 0

External high threshold

high->low transition

-

External high threshold

low->high transition

Internal low threshold

high->low transition

0.9

-

1.1

1.3

2.4

2.6

-

ALARM0,

ALARM1

Internal low threshold

low->high transition

1.55

-

INTREF = 1

Internal high threshold

high->low transition

2.2

-

Internal high threshold

low->high transition

2.85

V

V_HYS

Switching hysteresis

50

-

0.1

1

300

1

mV

t_COMPF

t_COMPS

s CMD = 1 (fast)

s CMD = 0 (slow)

Comparison time

-

10

Power-up stabilization

time after enabling alarm

comparator

t_PD

Threshold levels

specified above are not

guaranteed within this

time

-

1

5

ms

Slow/Fastmodetransition

time

t_CMD

100

500

s

Document Number: 002-04579 Rev. *A

Page 92 of 109

MB96340 Series

Comparator

Output

H

L

V_ALIN

V_xVTx(H->L)

V_HYS

V_xVTx(L->H)

Document Number: 002-04579 Rev. *A

Page 93 of 109

MB96340 Series

14.7 Low Voltage Detector Characteristics

(T_A= -40 °C to +125 °C, V_cc= AV_cc= 3.0V - 5.5V, V_ss= AV_ss= 0V)

Value ^[1]

Value ^[2]

Parameter

Symbol

Unit

Remarks

Min

Max

Min

Max

After power-up or change of

detection level

T_LVDSTAB

Stabilization time

-

75

-

110

s

V_DL0

V_DL1

V_DL2

V_DL3

V_DL4

V_DL5

V_DL6

V_DL7

V_DL8

V_DL9

V_DL10

V_DL11

V_DL12

V_DL13

V_DL14

V_DL15

Level 0

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Level 8

Level 9

Level 10

Level 11

Level 12

Level 13

Level 14

Level 15

2.7

2.9

3.1

3.5

3.6

3.7

3.8

3.9

4.0

4.1

2.9

3.1

2.65

2.85

3.05

3.45

3.55

3.65

3.75

3.85

3.95

4.05

2.95

3.2

V

CILCR:LVL[3:0]=”0000”

CILCR:LVL[3:0]=”0001”

CILCR:LVL[3:0]=”0010”

CILCR:LVL[3:0]=”0011”

CILCR:LVL[3:0]=”0100”

CILCR:LVL[3:0]=”0101”

CILCR:LVL[3:0]=”0110”

CILCR:LVL[3:0]=”0111”

CILCR:LVL[3:0]=”1000”

CILCR:LVL[3:0]=”1001”

3.3

3.4

3.75

3.85

3.95

4.05

4.15

4.25

4.35

3.85

3.95

4.1

4.2

4.3

4.4

4.5

not used

[1]: valid for all devices except devices listed under “[2]”

[2]: valid for: MB96F345

CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.

Levels 10 to 15 are not used in this device.

V

s

dV

dt

-----

For correct detection, the slope of the voltage level must satisfy

 0.004

.

Faster variations are regarded as noise and may not be detected.

The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7V. The electrical

characteristics however are only valid in the specified range (usually down to 3.0V).

Document Number: 002-04579 Rev. *A

Page 94 of 109

MB96340 Series

14.7.1

Low Voltage Detector Operation

In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup

behavior, please refer to the corresponding hardware manual chapter.

Voltage [V]

V_CC

V_{DLx, Max}

V_{DLx, Min}

dV

dt

Time [s]

Power Reset Extension Time

Low Voltage Reset Assertion

Normal Operation

Document Number: 002-04579 Rev. *A

Page 95 of 109

MB96340 Series

14.8 Flash Memory Program/erase Characteristics

(T_A= -40°C to 105°C, V_CC= AV_CC= 3.0V to 5.5V, V_SS= AV_SS= 0V)

Value

Parameter

Unit

Remarks

Min

Typ

Max

Sector erase time

-

0.9

3.6

s

Without erasure pre-programming time

Program/Data Flash (Main Flash)

-

0.5

0.8

2

s

Without erasure pre-programming time

Including erasure pre-programming time

Sector erase time Data Flash

3.6

Without erasure pre-programming time

(n is the number of Flash sector of the

device)

Chip erase time Program/Data Flash (Main Flash)

Chip erase time Data Flash

-

n*0.9

n*3.6

s

-

2.5

3.7

10

s

Without erasure pre-programming time

Including erasure pre-programming time

16.4

Word (16-bit width) programming time

Program/Data Flash (Main Flash)

Without overhead time for submitting

write command

-

23

15

370

100

us

Without overhead time for submitting

write command

Byte (8-bit width) programming time Data Flash

100 000 Program/Erase cycles are under

evaluation by Cypress

Program/Erase cycle

10000

20

-

cycle

year

[1]

Flash data retention time

[1]: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high

temperature measurements into normalized value at 85^oC)

Document Number: 002-04579 Rev. *A

Page 96 of 109

MB96340 Series

15. Example Characteristics

The diagrams below show the characteristics of one measured sample with typical process parameters.

Run Mode

100.00

PLL clock (56 MHz)

10.00

Main osc. (4 MHz)

RC clock (2 MHz)

1.00

RC clock (100 kHz)

0.10

Sub osc.(32 kHz)

0.01

-50.00

0.00

50.00

100.00

150.00

Ta [ºC]

Sleep mode

100.00

PLL clock (56 MHz)

10.00

1.00

0.10

0.01

Main osc. (4 MHz)

RC clock (2 MHz)

RC clock (100 kHz)

Sub osc.(32 kHz)

-50.00

0.00

50.00

100.00

150.00

Ta [ºC]

Document Number: 002-04579 Rev. *A

Page 97 of 109

MB96340 Series

Timer mode

10.00

1.00

0.10

0.01

PLL clock (56 MHz)

Main osc. (4 MHz)

RC clock (2 MHz)

RC clock (100 kHz)

Sub osc. (32 kHz)

-50.00

0.00

50.00

100.00

150.00

Ta [ºC]

Stop mode

1.00

0.10

0.01

0.00

-50.00

0.00

50.00

100.00

150.00

Ta [ºC]

Document Number: 002-04579 Rev. *A

Page 98 of 109

MB96340 Series

Table 6: Used settings

Selected Source

Clock

Mode

Clock/Regulator Settings

Run mode

PLL

CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz

CLKP2 = 28 MHz

Regulator in High Power Mode

Core Voltage = 1.9 V

Main osc.

RC clock fast

RC clock slow

Sub osc.

CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz

Regulator in High Power Mode

Core Voltage = 1.8 V

CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz

Regulator in High Power Mode

Core Voltage = 1.8 V

CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz

Regulator in High Power Mode

Core Voltage = 1.8 V

CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz

Regulator in Low Power Mode A

Core Voltage = 1.8 V

Sleep mode

PLL

CLKS1 = CLKS2 = CLKP1 = 56 MHz

CLKP2 = 28 MHz

(CLKB is stopped in this mode)

Regulator in High Power Mode

Core Voltage = 1.9 V

Main osc.

CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz

(CLKB is stopped in this mode)

Regulator in High Power Mode

Core Voltage = 1.8 V

RC clock fast

RC clock slow

Sub osc.

CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz

(CLKB is stopped in this mode)

Regulator in High Power Mode

Core Voltage = 1.8 V

CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz

(CLKB is stopped in this mode)

Regulator in High Power Mode

Core Voltage = 1.8 V

CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz

(CLKB is stopped in this mode)

Regulator in Low Power Mode A

Core Voltage = 1.8 V

Document Number: 002-04579 Rev. *A

Page 99 of 109

MB96340 Series

Table 6: Used settings

Selected Source

Clock

Mode

Clock/Regulator Settings

Timer mode

PLL

CLKMC = 4 MHz, CLKPLL = 56 MHz

(System clocks are stopped in this mode)

Regulator in High Power Mode, Core Voltage = 1.9 V

Main osc.

CLKMC = 4 MHz

(System clocks are stopped in this mode)

Regulator in High Power Mode, Core Voltage = 1.8 V

RC clock fast

RC clock slow

Sub osc.

CLKRC = 2 MHz

(System clocks are stopped in this mode)

Regulator in High Power Mode, Core Voltage = 1.8 V

CLKRC = 100 kHz

(System clocks are stopped in this mode)

Regulator in High Power Mode, Core Voltage = 1.8 V

CLKSC = 100 kHz

(System clocks are stopped in this mode)

Regulator in Low Power Mode A, Core Voltage = 1.8 V

Stop mode

stopped

(All clocks are stopped in this mode)

Regulator in Low Power Mode B, Core Voltage = 1.8 V

Document Number: 002-04579 Rev. *A

Page 100 of 109

MB96340 Series

16. Package Dimension MB96(F)34x LQFP 100P

100-pin plastic LQFP

Lead pitch

0.50 mm

14.0 mm × 14.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm Max

0.65 g

Code

(Reference)

P-LFQFP100-14×14-0.50

(FPT-100P-M20)

100-pin plastic LQFP

(FPT-100P-M20)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

16.00 0.20(.630 .008)SQ

*

14.00 0.10(.551 .004)SQ

75

51

76

50

0.08(.003)

Details of "A" part

1.50 ^+0.20

–

^0.10.059 ^+.008

–.004

INDEX

(Mounting height)

0.10 0.10

(.004 .004)

(Stand off)

100

26

0°~8

°

"A"

0.50 0.20

(.020 .008

0.25(.010)

)

1

25

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

0.145 0.055

(.0057 .0022)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3

Document Number: 002-04579 Rev. *A

Page 101 of 109

MB96340 Series

17. Package Dimension MB96(F)34x QFP 100P

100-pin plastic QFP

Lead pitch

0.65 mm

14.00 mm × 20.00 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

Code

(Reference)

P-QFP100-14×20-0.65

(FPT-100P-M22)

100-pin plastic QFP

(FPT-100P-M22)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

23.90 0.40(.941 .016)

*

20.00 0.20(.787 .008)

80

51

81

50

0.10(.004)

17.90 0.40

(.705 .016)

*

14.00 0.20

(.551 .008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8

°

1

30

0.65(.026)

0.32 0.05

(.013 .002)

0.17 0.06

(.007 .002)

M

0.13(.005)

0.25 0.20

(.010 .008)

(Stand off)

0.80 0.20

(.031 .008)

"A"

0.88 0.15

(.035 .006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2006-2008 FUJITSU MICROELECTRONICS LIMITED F100033S-c-1-2

Document Number: 002-04579 Rev. *A

Page 102 of 109

MB96340 Series

18. Ordering Information

18.1 MCU with CAN Controller

Persistent

Low Volt-

age Reset

Part number

Flash/ROM

Subclock

Package

MB96345YSA PQC-GSE2 ^[1]

MB96345RSA PQC-GSE2 ^[1]

MB96345YWA PQC-GSE2 ^[1]

MB96345RWA PQC-GSE2 ^[1]

MB96345YSA PMC-GSE2^[1]

MB96345RSA PMC-GSE2 ^[1]

MB96345YWA PMC-GSE2 ^[1]

MB96345RWA PMC-GSE2^[1]

MB96346YSA PQC-GSE2^[1]

MB96346RSA PQC-GSE2^[1]

MB96346YWA PQC-GSE2 ^[1]

MB96346RWA PQC-GSE2 ^[1]

MB96346YSA PMC-GSE2 ^[1]

MB96346RSA PMC-GSE2^[1]

MB96346YWA PMC-GSE2 ^[1]

MB96346RWA PMC-GSE2 ^[1]

MB96F345FSA PQC-GSE2 ^[1]

MB96F345DSA PQC-GSE2 ^[1]

MB96F345FWA PQC-GSE2 ^[1]

MB96F345DWA PQC-GSE2 ^[1]

MB96F345FSA PMC-GSE2 ^[1]

MB96F345DSA PMC-GSE2 ^[1]

MB96F345FWA PMC-GSE2^[1]

MB96F345DWA PMC-GSE2 ^[1]

MB96F346YSB PQC-GSE2

MB96F346RSB PQC-GSE2

MB96F346YWB PQC-GSE2

MB96F346RWB PQC-GSE2

MB96F346YSB PMC-GSE2

MB96F346RSB PMC-GSE2

MB96F346YWB PMC-GSE2

MB96F346RWB PMC-GSE2

Yes

No

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

ROM (160KB)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

Yes

No

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Yes

No

ROM (288KB)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

Yes

No

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Yes

No

Flash A (160KB)

Data Flash A (64KB)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

Yes

No

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Yes

No

Flash A (288KB)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

Yes

Document Number: 002-04579 Rev. *A

Page 103 of 109

MB96340 Series

18.1 MCU with CAN Controller

Persistent

Low Volt-

age Reset

Part number

Flash/ROM

Subclock

Package

MB96F347YSB PQC-GSE2

MB96F347RSB PQC-GSE2

MB96F347YWB PQC-GSE2

MB96F347RWB PQC-GSE2

MB96F347YSB PMC-GSE2

MB96F347RSB PMC-GSE2

MB96F347YWB PMC-GSE2

MB96F347RWB PMC-GSE2

MB96F348YSB PQC-GSE2

MB96F348RSB PQC-GSE2

MB96F348YWB PQC-GSE2

MB96F348RWB PQC-GSE2

MB96F348YSB PMC-GSE2

MB96F348RSB PMC-GSE2

MB96F348YWB PMC-GSE2

MB96F348RWB PMC-GSE2

MB96F348TSC PQC-GSE2

MB96F348HSC PQC-GSE2

MB96F348TWC PQC-GSE2

MB96F348HWC PQC-GSE2

MB96F348TSC PMC-GSE2

MB96F348HSC PMC-GSE2

MB96F348TWC PMC-GSE2

MB96F348HWC PMC-GSE2

Yes

No

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Flash A (416KB)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

Yes

No

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Yes

No

Flash A (544KB)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

Yes

No

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Yes

No

Flash A (544KB)

Flash B (32KB)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

Yes

416 pin Plastic BGA

(BGA-416P-M02)

MB96V300BRB-ES(for evaluation)

Emulated by ext. RAM

No

Document Number: 002-04579 Rev. *A

Page 104 of 109

MB96340 Series

18.2 MCU without CAN Controller

Part number

MB96F346ASB PQC-GSE2

MB96F346AWB PQC-GSE2

MB96F346ASB PMC-GSE2

MB96F346AWB PMC-GSE2

MB96F347ASB PQC-GSE2

MB96F347AWB PQC-GSE2

MB96F347ASB PMC-GSE2

MB96F347AWB PMC-GSE2

MB96F348ASB PQC-GSE2

MB96F348AWB PQC-GSE2

MB96F348ASB PMC-GSE2

MB96F348AWB PMC-GSE2

MB96F348CSC PQC-GSE2

MB96F348CWC PQC-GSE2

MB96F348CSC PMC-GSE2

MB96F348CWC PMC-GSE2

Flash/ROM

Subclock

No

Package

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Flash A (288KB)

Flash A (416KB)

Flash A (544KB)

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

No

100 pin Plastic QFP

(FPT-100P-M22)

Yes

No

Flash A (544KB)

Flash B (32KB)

100 pin Plastic LQFP

(FPT-100P-M20)

Yes

[1]: These devices are under development and specification is preliminary. These products under development may change its

specification without notice.

This datasheet is also valid for the following outdated devices:

MB96F346YSA, MB96F346RSA, MB96F346YWA, MB96F346RWA,

MB96F347YSA, MB96F347RSA, MB96F347YWA, MB96F347RWA,

MB96F348YSA, MB96F348RSA, MB96F348YWA, MB96F348RWA,

MB96F348TSB, MB96F348HSB, MB96F348TWB, MB96F348HWB,

MB96F346ASA, MB96F346AWA,

MB96F347ASA, MB96F347AWA,

MB96F348ASA, MB96F348AWA,

MB96F348CSB, MB96F348CWB

Document Number: 002-04579 Rev. *A

Page 105 of 109

MB96340 Series

19. Revision History

Revision

Date

Modification

Prelim 1

Prelim 2

Prelim 3

Prelim 4

Prelim 5

2007-05-07

2007-05-10

2007-05-23

2007-08-02

2007-09-12

Creation

External bus hold timing update

Electrical characteristics updates

Electrical characteristics updates, Product lineup, changes and ordering information

Addition of the electrical characteristic examples and the LVD characteristics specifications,

updates of the DC characteristics. Pin circuit type drawing modifications.

Prelim 6

Prelim 7

2007-11-21

2007-12-04

LVD typo correction.

Update of the DC characteristics. Typos corrections.

Absolute maximum rating asterisks numbering corrected.

Typos page 59: Hardware -> Hardware.

IO map table regenerated.

Typos corrections.

IO circuit drawings modified.

Renaming of the Main/Satellite Flash into Flash memory A/B.

Memory map reworked.

Prelim 8

2008-02-04

■ Satellite Flash -> 32kB Data Flash

■ MB96345 added (under development)

■ MB96F348 TSA/HSA/TWA/HWA removed (outdated devices)

■ Block diagram and pin assignment corrected (existing resource pins)

■ Pin function table corrected

■ I/O circuit type diagrams corrected

■ Memory map cleaned up

■ "Flash sector configuration" replaced by corrected "User ROM Memory map for Flash devices",

“ROM configuration” replaced by “User ROM Memory map for Mask ROM devices”

■ Parallel Flash programming pinning removed

■ IO map table regenerated:

❐ Port register: Naming style corrected

❐ Memory control registers renamed (Main/Sat -> A/B)

❐ addresses after 000BFFh removed

■ Absolute maximum ratings: Pd and Ta specified more precisely

■ oscillator input levels in oscillation mode with external clock added

■ Run and Sleep mode currents: 96/48MHz and 72/36MHz settings added

■ Run mode current spec in 48/24MHz mode corrected

■ Maximum CLKS1/2 frequency for all devices correctly specified

■ Maximum CLKP2 for MB96F34xY/R/Axx corrected

■ External bus timings: missing conditions added and readability improved

■ Alarm comparator spec updated (transition voltages defined)

■ MB96V300A removed

■ Ordering information updated

■ Typos and formatting corrected

Document Number: 002-04579 Rev. *A

Page 106 of 109

MB96340 Series

Revision

9

Date

Modification

2009-01-09

■ Format adjusted to official Cypress datasheet standard (mainly style changes and official notes

and disclaimer added)

■ Numbering of Electrical Characteristics subchapters automated

■ Note about devices under development modified

■ I/O map: Note added about reserved addresses

■ ICCSPLL for CLKS1=96MHz mode: increased by 1mA

■ Serial programming interface: Note about handshaking pins improved

■ specified AD converter channel offset to 4LSB

■ package code of MB96V300 corrected in ordering information

■ Added voltage condition to pull-up resistance spec

■ Lineup: Term “Data Flash” replaced by “independent 32KB Flash”

■ Ordering information: column “Independent 32KB Data Flash” replaced by new column

“Flash/ROM”, column “Remarks” removed

■ Official package dimension drawing with additional notes added

■ Empty pages removed

■ Alarm comparator: Power supply current max values increased, comparison time reduced, mode

transition time and power-up stabilization time newly added

■ Handling devices: Notes added about Serial communication and about using ceramic resonators.

■ Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For

resonators, maximum frequency depends on Q-factor

■ AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz

■ VOL3 spec improved: spec valid for 3mA load for full Vcc range

■ MB96F345 added

■ Preliminary DC spec of MB96345/346 added

■ Permitted power dissipation of Flash devices in QFP package improved

■ C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted

■ “Preliminary” watermark removed

10

To be

■ I/O map: IOABK0-5 added at address 000A00H-000A05H

released

■ Ordering Information: Suffix “A” added to all MB96F345 device versions

■ AD converter I_AINspec improved: 1uA valid up to 105deg, 1.2uA above 105deg

Document Number: 002-04579 Rev. *A

Page 107 of 109

MB96340 Series

20. Main Changes in this Edition

Page

Section

Change Results

89

Electrical Characteristics

14.5. Analog Digital Converter

Corrected "Value" and "Unit" of Zero reading voltage.

(AVRL - 1.5  AVRL - 1.5 LSB

AVRL + 0.5  AVRL + 0.5 LSB

AVRL + 2.5  AVRL + 2.5 LSB

LSB  V)

Corrected "Value" and "Unit" of Full scale reading voltage.

(AVRH - 3.5  AVRH - 3.5 LSB

AVRH - 1.5  AVRH - 1.5 LSB

AVRH + 0.5  AVRH + 0.5 LSB

LSB  V)

NOTE: Please see “Document History” for later revised information.

Document History

Spansion Publication Number: DS07-13802-3E

Document Title: MB96345/346, MB96F345, MB96F346/F347/F348, F²MC-16FX, MB96340 Series, 16-bit Proprietary

Microcontroller Datasheet

Document Number: 002-04579

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

AKIH

06/17/2009 Migrated to Cypress and assigned document number 002-04579.

No change to document contents or format.



*A

5198948

AKIH

04/04/2016 Updated to Cypress template

Document Number: 002-04579 Rev. *A

Page 108 of 109

MB96340 Series

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

ARM^®Cortex^®Microcontrollers

®

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

PSoC Solutions

Automotive

cypress.com/psoc

Clocks & Buffers

Interface

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Lighting & Power Control

Memory

Community | Forums | Blogs | Video | Training

Technical Support

PSoC

cypress.com/support

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

ARM and Cortex are the trademarks of ARM Limited in the EU and other countries

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify

and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either

directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right

to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum

extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software

is prohibited.

CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not

assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or

programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application

made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of

weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or

hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any

component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole

or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify

and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress

products.

10

9

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United

States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-04579 Rev. *A

Revised April 4, 2016

Page 109 of 109


型号：	MB96F348YSBPQC-GSE2
厂家：	CYPRESS
描述：	8-byte instruction execution queue
文件：	总109页 (文件大小：1900K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB96F348YSBPQC-GSE2 [CYPRESS]

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MB96F348YWBPQC-GSE2

MB96F353ASBPMC-GSE2

MB96F353ASBPMC1-GSE2

MB96F353AWBPMC-GSE2

MB96F353AWBPMC1-GSE2

MB96F353RSBPMC-GSE2

MB96F353RSBPMC1-GSE2