MB96F386RWBPMC-GSE2 [CYPRESS]
F2MC-16FX 16-bit Proprietary Microcontroller;
| 型号： | MB96F386RWBPMC-GSE2 |
| 厂家： | 
CYPRESS |
| 描述： | F2MC-16FX 16-bit Proprietary Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总117页 (文件大小：9867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB96380 Series
F2MC-16FX 16-bit Proprietary
Microcontroller
MB96380 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance).
The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the
new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even
at the same operation frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to
56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going
together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency
spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock
tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed.
Note: MB96384/385/F385/F388/F389 devices are under development and specification is preliminary. These products under
development may change its specification without notice.
Features
Technology
On-chip voltage regulator
■ 0.18m CMOS
■ Internal voltage regulator supports reduced internal MCU
voltage, offering low EMI and low power consumption figures
CPU
■ F2MC-16FX CPU
Low voltage reset
■ Reset is generated when supply voltage is below minimum.
■ Up to 56 MHz internal, 17.8 ns instruction cycle time
Code Security
■ Optimized instruction set for controller applications (bit, byte,
word and long-word data types; 23 different addressing
modes; barrel shift; variety of pointers)
■ Protects ROM content from unintended read-out
Memory Patch Function
■ 8-byte instruction execution queue
■ Replaces ROM content
■ Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit)
instructions available
■ Can also be used to implement embedded debug support
System clock
DMA
■ On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
■ Automatic transfer function independent of CPU, can be
assigned freely to resources
■ 3 MHz - 16 MHz external crystal oscillator clock (maximum
frequency when using ceramic resonator depends on
Q-factor).
Interrupts
■ Fast Interrupt processing
■ 8 programmable priority levels
■ Non-Maskable Interrupt (NMI)
■ Up to 56 MHz external clock for devices with fast clock input
feature
■ 32-100 kHz subsystem quartz clock
■ 100kHz/2MHz internal RC clock for quick and safe startup,
oscillator stop detection, watchdog
Timers
■ Three independent clock timers (23-bit RC clock timer, 23-bit
Main clock timer, 17-bit Sub clock timer)
■ Clock source selectable from main- and subclock oscillator
(part number suffix “W”) and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals.
■ Watchdog Timer
■ Low Power Consumption - 13 operating modes : (different
Run, Sleep, Timer modes, Stop mode)
■ Clock modulator
Cypress Semiconductor Corporation
Document Number: 002-04582 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 28, 2016
MB96380 Series
CAN
Input Capture Units
■ Supports CAN protocol version 2.0 part A and B
■ ISO16845 certified
■ 16-bit wide
■ Signals an interrupt upon external event
■ Bit rates up to 1 Mbit/s
■ Rising edge, falling edge or rising & falling edge sensitive
■ 32 message objects
Output Compare Units
■ Each message object has its own identifier mask
■ 16-bit wide
■ Programmable FIFO mode (concatenation of message
objects)
■ Signals an interrupt when a match with 16-bit I/O Timer occurs
■ A pair of compare registers can be used to generate an output
signal.
■ Maskable interrupt
■ Disabled Automatic Retransmission mode for Time Triggered
CAN applications
Programmable Pulse Generator
■ 16-bit down counter, cycle and duty setting registers
■ Interrupt at trigger, counter borrow and/or duty match
■ PWM operation and one-shot operation
■ Programmable loop-back mode for self-test operation
USART
■ Full duplex USARTs (SCI/LIN)
■ Wide range of baud rate settings using a dedicated reload timer
■ Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock
as counter clock and Reload timer overflow as clock input
■ Special synchronous options for adapting to different
synchronous serial protocols
■ Can be triggered by software or reload timer
Stepper Motor Controller
■ LIN functionality working either as master or slave LIN device
■ Stepper Motor Controller with integrated high current output
drivers
2
I C
■ Up to 400 kbps
■ Four high current outputs for each channel
■ Two synchronized 8/10-bit PWMs per channel
■ Master and Slave functionality, 8-bit and 10-bit addressing
A/D converter
■ SAR-type
■ Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10,
1/12, 1/16 of peripheral clock
■ Separate power supply for high current output drivers
■ 10-bit resolution
LCD Controller
■ Signals interrupt on conversion end, single conversion mode,
continuousconversionmode,stopconversionmode,activation
by software, external trigger or reload timer
■ LCD controller with up to 4 COM × 65 SEG
■ Internal or external voltage generation
■ Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
■ Fixed 1/3 bias
A/D Converter Reference Voltage switch
■ 2 independent positive A/D converter reference voltages
available
■ Programmable frame period
Reload Timers
■ Clock source selectable from three options (peripheral clock,
subclock or RC oscillator clock)
■ 16-bit wide
■ Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral
clock frequency
■ On-chip drivers for internal divider resistors or external divider
resistors
■ Event count function
■ On-chip data memory for display
■ LCD display can be operated in Timer Mode
■ Blank display: selectable
Free Running Timers
■ Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22,
1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency
■ All SEG, COM and V pins can be switched between general
and specialized purposes
■ External divided resistors can be also used to shut off the
current when LCD is deactivated
Document Number: 002-04582 Rev. *A
Page 2 of 117
MB96380 Series
Sound Generator
Alarm comparator
■ 8-bit PWM signal is mixed with tone frequency from 16-bit
reload counter
■ Monitors an external voltageand generates an interruptin case
of a voltage lower or higher than the defined thresholds
■ PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral
clock
■ Threshold voltages defined externally or generated internally
■ Status is readable, interrupts can be masked separately
Real Time Clock
I/O Ports
■ Can be clocked either from sub oscillator (devices with part
■ Virtually all external pins can be used as general purpose I/O
■ All push-pull outputs (except when used as I2C SDA/SCL line)
■ Bit-wise programmable as input/output or peripheral signal
■ Bit-wise programmable input enable
number suffix “W”), main oscillator or from the RC oscillator
■ Facility to correct oscillation deviation of Sub clock or RC
oscillator clock (clock calibration)
■ Read/write accessible second/minute/hour registers
■ Can signal interrupts every half
second/second/minute/hour/day
■ Bit-wise programmable input levels: Automotive /
CMOS-Schmitt trigger / TTL
■ Internal clock divider and prescaler provide exact 1s clock
■ Bit-wise programmable pull-up resistor
■ Bit-wise programmable output driving strength for EMI
optimization
External Interrupts
■ Edge sensitive or level sensitive
■ Interrupt mask and pending bit per channel
Package
■ 120-pin plastic LQFP
■ Each available CAN channel RX has an external interrupt for
wake-up
Flash Memory
■ Selected USART channels SIN have an external interrupt for
wake-up
■ Supports automatic programming, Embedded Algorithm
■ Write/Erase/Erase-Suspend/Resume commands
■ A flag indicating completion of the algorithm
■ Number of erase cycles: 10,000 times
■ Data retention time: 20 years
Non Maskable Interrupt
■ Disabled after reset
■ Once enabled, can not be disabled other than by reset.
■ Level high or level low sensitive
■ Pin shared with external interrupt 0.
■ Erase can be performed on each sector individually
■ Sector protection
External bus interface
■ 8-bit or 16-bit bidirectional data
■ Up to 24-bit addresses
■ Flash Security feature to protect the content of the Flash
■ Low voltage detection during Flash erase
■ 6 chip select signals
■ Multiplexed address/data lines
■ Non-multiplexed address/data lines
■ Wait state request
■ External bus master possible
■ Timing programmable
Document Number: 002-04582 Rev. *A
Page 3 of 117
MB96380 Series
Contents
Product Lineup .................................................................5
Block Diagram ..................................................................7
Pin Assignment ................................................................8
Pin Function Description .................................................9
Pin Circuit Type ..............................................................12
I/O Circuit Type ...............................................................14
Memory Map ....................................................................19
RAMSTART/END and External Bus End Addresses ...20
User ROM Memory Map for Flash Devices ..................21
User ROM Memory Map for Mask Rom Devices ..........23
Serial Programming Communication Interface ...........24
I/O Map .............................................................................25
Interrupt Vector Table ....................................................55
Handling Devices ............................................................58
Latch-up prevention ...................................................58
Unused pins handling ................................................58
External clock usage .................................................58
Unused sub clock signal ............................................59
Notes on PLL clock mode operation .........................59
Power supply pins (VCC/VSS) ..................................59
Crystal oscillator and ceramic resonator circuit .........59
Turn on sequence of power supply to
A/D converter and analog inputs ...............................59
Pin handling when not using the A/D converter ........59
Notes on Power-on ....................................................59
Stabilization of power supply voltage ........................59
SMC power supply pins .............................................60
Serial communication ................................................60
Electrical Characteristics ...............................................61
Absolute Maximum Ratings .......................................61
Recommended Operating Conditions .......................64
DC characteristics .....................................................65
AC Characteristics .....................................................77
Analog Digital Converter ...........................................99
Alarm Comparator ...................................................103
Low Voltage Detector characteristics ......................105
FLASH memory program/erase characteristics ......107
Example Characteristics ..............................................108
Package Dimension MB96(F)38x LQFP 120P ............112
Ordering Information ....................................................113
Revision History ...........................................................114
Document History .........................................................116
Document Number: 002-04582 Rev. *A
Page 4 of 117
MB96380 Series
1. Product Lineup
Features
MB96V300B
MB96(F)38x
Flash product: MB96F38x
Mask ROM product: MB9638x
Product type
Evaluation sample
Product options
YS
RS
Low voltage reset persistently on / Single clock
Low voltage reset can be disabled / Single clock
YW
Low voltage reset persistently on / Dual clock
RW
Low voltage reset can be disabled / Dual clock
NA
TS
indep. 32KB Flash / Low voltage reset persistently on / Single clock
indep. 32KB Flash / Low voltage reset can be disabled / Single clock
indep. 32KB Flash / Low voltage reset persistently on / Dual clock
indep. 32KB Flash / Low voltage reset can be disabled / Dual clock
HS
TW
HW
Flash/ROM
128KB
RAM
6KB
MB96384Y*1, MB96384R*1
MB96385Y*1, MB96385R*1, MB96F385Y*1, MB96F385R*1
MB96F386Y, MB96F386R
160KB
288KB
416KB
8KB
16KB
16KB
ROM/Flash memory
emulation by
MB96F387Y, MB96F387R
external RAM,
92KB internal RAM
576KB
[Flash A: 544KB,
Flash B: 32KB]
MB96F388T*1, MB96F388H*1
MB96F389Y*1, MB96F389R*1,
28KB
32KB
832KB
[Flash A: 544KB,
Flash B: 288KB]
Package
DMA
BGA416
FPT-120P-M21
7 channels
5 channels
1 channel
16 channels
10 channels
2 channels
40 channels
USART
I2C
A/D Converter
16 channels
A/D Converter Reference
Voltage switch
yes
Only for MB96F386Y, MB96F386R, MB96F387Y, MB96F387R
4 channels + 1 channel (for PPG)
6 channels + 1
channel (for PPG)
16-bit Reload Timer
16-bit Free-Running Timer
16-bit Output Compare
4 channels
2 channels
4 channels
12 channels
Document Number: 002-04582 Rev. *A
Page 5 of 117
MB96380 Series
Features
MB96V300B
MB96(F)38x
16-bit Input Capture
12 channels
8 channels
16-bit Programmable Pulse
Generator
20 channels
5 channels
8 channels
Other than below: 2 channels
MB96384Y*1, MB96384R*1, MB96(F)385Y*1, MB96(F)385R*1,:
CAN Interface
1 channel
Stepping Motor Controller
External Interrupts
Non-Maskable Interrupt
Sound generator
LCD Controller
6 channels
5 channels
16 channels
8 channels
1 channel
2 channels
2 channels
4 COM x 72 SEG
4 COM x 65 SEG
Real Time Clock
I/O Ports
1
136
94 for part number with suffix "W", 96 for part number with suffix "S"
Other than below: 2 channels
MB96384Y*1, MB96384R*1, MB96(F)385Y*1, MB96(F)385R*1,:
1 channel
Alarm comparator
2 channels
External bus interface
Chip select
Yes
6 signals
2 channels
Yes
Clock output function
Low voltage reset
On-chip RC-oscillator
Yes
*1: These devices are under development and specification is preliminary. These products under development may change its
specification without notice.
Document Number: 002-04582 Rev. *A
Page 6 of 117
MB96380 Series
2. Block Diagram
Block diagram of MB96(F)38x
AD00 ... AD15
CKOT0, CKOT1, CKOT1_R
A00 ... A23
ALE
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
RDX
WR(L)X, WRHX
HRQ
X0A, X1A *1
RSTX
MD0...MD2
HAKX
NMI
RDY
ECLK
LBX, UBX
CS0 ... CS5, CS3_R
Clock &
Mode Controller
Memory Patch
Flash
External Bus
Interface
Interrupt
Controller
Flash
Memory A
16FX
CPU
Memory B *2
Unit
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Controller
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
RAM
Boot ROM
SDA0
SCL0
I2C
1 ch.
VCC
VSS
C
TX0, TX1 *3
RX0, RX1 *3
CAN
AVCC
AVSS
Interface
2 ch. *3
AVRH
10-bit ADC
16 ch.
AVRL/AVRH2 *4
AN0 ... AN15
ADTG
SGO0, SGO1, SGO0_R, SGO1_R
SGA0, SGA1, SGA0_R, SGA1_R
Sound
Generator
2 ch.
TIN2_R
TIN0 ... TIN3
TOT1_R, TOT2_R
TOT0 ... TOT3
16-bit Reload
Timer
SIN0...SIN2,SIN4,SIN5
SOT0...SOT2,SOT4,SOT5
SCK0...SCK2,SCK4,SCK5
USART
5 ch.
4 ch.
FRCK0
FRCK0_R
IN0, IN1
ALARM0
Alarm
Comparator
2 ch. *3
ALARM1 *3
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
IN0_R ... IN3_R
OUT0 ... OUT3
OUT0_R...OUT3_R
16-bit PPG
8 ch.
TTG0 ... TTG7
PPG0 ... PPG7
PPG0_R ... PPG5_R
RLT6
FRCK1
IN6 ... IN7
IN4_R ... IN7_R
I/O Timer 1
ICU 4/5/6/7
PWM1M0 ... PWM1M4
PWM1P0 ... PWM1P4
PWM2M0 ... PWM2M4
PWM2P0 ... PWM2P4
Stepper
Motor
Controller
INT0 ... INT7
External
Interrupt
5 ch.
DVCC
DVSS
INT1_R ... INT7_R
V0 ... V3
COM0 ... COM3
SEG0 ... SEG64
LCD
controller/
driver
Real Time
Clock
WOT
*1: X0A, X1A only available on devices with suffix “W”
*2: Flash B only available on MB96F388 and MB96F389
*3: CAN1 and ALARM1 not available on MB96384 and MB96(F)385
*4: AVRH2 only available on MB96F386 and MB96F387
Document Number: 002-04582 Rev. *A
Page 7 of 117
MB96380 Series
3. Pin Assignment
Pin assignment of MB96(F)38x
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
91
92
60
Vcc
Vss
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P10_3/PWM2M4/PPG7
P10_2/PWM2P4/SCK2/PPG6
P10_1/PWM1M4/SOT2/TOT3
P10_0/PWM1P4/SIN2/TIN3
P09_7/PWM2M3
DVss
P00_3/INT6_R/A00/CS3_R/SEG15
P00_4/INT7_R/ALE/SEG16
P00_5/TTG2/TTG6/IN6/RDX/SEG17
P00_6/TTG3/IN7/WR(L)X/TTG7/SEG18
P00_7/SGO0/ECLK/SEG19
P01_0/SGA0/AD00/SEG20
P01_1/OUT0/CKOT1/AD01/SEG21
P01_2/OUT1/CKOTX1/AD02/SEG22
P01_3/PPG5/AD03/SEG23
P01_4/AD04/SIN4/SEG24
P01_5/AD05/SOT4/SEG25
P01_6/AD06/SCK4/SEG26
P01_7/CKOTX1_R/AD07/SEG27
P02_0/CKOT1_R/AD08/SEG28
P02_1/IN6_R/AD09/SEG29
P02_2/IN7_R/AD10/SEG30
P02_3/SGO0_R/AD11/SEG31
P02_4/SGA0_R/AD12/SEG32
P02_5/OUT0_R/AD13/SEG33
P02_6/OUT1_R/AD14/SEG34
P02_7/PPG5_R/AD15/SEG35
P03_0/V0/A16/SEG36
93
94
95
96
97
98
DVcc
99
P09_6/PWM2P3
P09_5/PWM1M3
P09_4/PWM1P3
P09_3/PWM2M2
P09_2/PWM2P2
P09_1/PWM1M2
P09_0/PWM1P2
P08_7/PWM2M1
P08_6/PWM2P1
P08_5/PWM1M1
DVss
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
LQFP - 120
Package code (mold)
FPT-120P-M21
DVcc
P08_4/PWM1P1
P08_3/PWM2M0
P08_2/PWM2P0
P08_1/PWM1M0
P08_0/PWM1P0
P05_7/AN15/TOT2/SGA1_R/SEG64
P05_6/AN14/TIN2/SGO1_R/SEG63
P03_1/V1/A17/SEG37
P03_2/V2/A18/SEG38
P03_3/V3/A19/SEG39
P03_4/INT4/RX0
*3
P03_5/TX0
P05_5/AN13/TX1/SEG62
*3
P03_6/NMI/INT0
P05_4/AN12/RX1/INT2_R/SEG61
Vcc
Vss
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
*2: Alarm1 not available on MB96384 and MB96(F)385
*3: TX1 resp. RX1 not available on MB96384 and MB96(F)385
*4: AVRH2 only available on MB96F386 and MB96F387
(FPT-120P-M21)
Document Number: 002-04582 Rev. *A
Page 8 of 117
MB96380 Series
4. Pin Function Description
Pin Function description (1 of 3)
Pin name
Feature
Description
External bus interface (non multiplexed mode) data input/output.
External bus interface (multiplexed mode) address output and data
input/output
ADn
External bus
ADTG
ALARMn
ALE
ADC
Alarm comparator
External bus
External bus
ADC
A/D converter trigger input
Alarm Comparator n input
External bus Address Latch Enable output
External bus non-multiplexed address output
A/D converter channel n input
An
ANn
AVCC
Supply
Analog circuits power supply
AVRH
AVRH2
AVRL
AVSS
ADC
A/D converter high reference voltage input
Alternative A/D converter high reference voltage input
A/D converter low reference voltage input
Analog circuits power supply
ADC
ADC
Supply
C
Voltage regulator
Clock output function
Clock output function
Clock output function
Clock output function
LCD
Internally regulated power supply stabilization capacitor pin
Clock Output function n output
CKOTn
CKOTn_R
CKOTXn
CKOTXn_R
COMn
Relocated Clock Output function n output
Clock Output function n inverted output
Relocated Clock Output function n inverted output
LCD COM pins
ECLK
External bus
External bus
External bus
Supply
External bus clock output
CSn
External bus chip select n output
Relocated External bus chip select n output
SMC pins power supply
CSn_R
DVCC
FRCKn
FRCKn_R
HAKX
HRQ
Free Running Timer
Free Running Timer
External bus
External bus
ICU
Free Running Timer n input
Relocated Free Running Timer n input
External bus Hold Acknowledge
External bus Hold Request
INn
Input Capture Unit n input
INn_R
INTn
ICU
Relocated Input Capture Unit n input
External Interrupt n input
External Interrupt
Document Number: 002-04582 Rev. *A
Page 9 of 117
MB96380 Series
Pin Function description (2 of 3)
Pin name
Feature
Description
INTn_R
LBX
External Interrupt
External bus
Core
Relocated External Interrupt n input
External Bus Interface Lower Byte select strobe output
Input pins for specifying the operating mode.
Non-Maskable Interrupt input
MDn
NMI
External Interrupt
OCU
OUTn
OUTn_R
Pxx_n
PPGn
PPGn_R
PWMn
RDX
Output Compare Unit n waveform output
Relocated Output Compare Unit n waveform output
General purpose IO
OCU
GPIO
PPG
Programmable Pulse Generator n output
Relocated Programmable Pulse Generator n output
SMC PWM high current
PPG
SMC
External bus
External bus
Core
External bus interface read strobe output
External bus interface external wait state request input
Reset input
RDY
RSTX
RXn
CAN
CAN interface n RX input
SCKn
SCLn
SDAn
SEGn
SGA
USART
USART n serial clock input/output
I2C interface n clock I/O input/output
I2C interface n serial data I/O input/output
LCD segment n
I2C
I2C
LCD
Sound Generator
Sound Generator
Sound Generator
Sound Generator
USART
SG amplitude output
SGO
SG sound/tone output
SGA_R
SGO_R
SINn
Relocated SG amplitude output
Relocated SG sound/tone output
USART n serial data input
SOTn
TINn
USART
USART n serial data output
Reload Timer
Reload Timer
Reload Timer
Reload Timer
PPG
Reload Timer n event input
TINn_R
TOTn
TOTn_R
TTGn
TXn
Relocated Reload Timer n event input
Reload Timer n output
Relocated Reload Timer n output
Programmable Pulse Generator n trigger input
CAN interface n TX output
CAN
UBX
External bus
External Bus Interface Upper Byte select strobe output
Document Number: 002-04582 Rev. *A
Page 10 of 117
MB96380 Series
Pin Function description (3 of 3)
Pin name
Feature
Description
Vn
LCD
LCD voltage references
Power supply
VCC
Supply
VSS
Supply
RTC
Power supply
Real Timer clock output
WOT
WRHX
WRLX/WRX
X0
External bus
External bus
Clock
External bus High byte write strobe output
External bus Low byte / Word write strobe output
Oscillator input
X0A
Clock
Subclock Oscillator input (only for devices with suffix “W”)
Oscillator output
X1
Clock
X1A
Clock
Subclock Oscillator output (only for devices with suffix “W”)
Document Number: 002-04582 Rev. *A
Page 11 of 117
MB96380 Series
5. Pin Circuit Type
Pin circuit types (1 of 2)
FPT-120P-M21
Circuit
type *1
Pin no.
1
Supply
2
F
3 to 11
12,13
J
N
K
14 to 21
22
Supply
G
23 to 24
25
Supply
K
26 to 29
30,31
Supply
K
32 to 35
36 to 40
41,42
M
Supply
M
43 to 52
53,54
Supply
M
55 to 59
60, 61
62 to 64
65, 66
67
Supply
C
A
Supply
B *2
68,69
H *3
68,69
70
E
71 to 89
90 to 91
92 to 112
113 to 116
J
Supply
J
L
Document Number: 002-04582 Rev. *A
Page 12 of 117
MB96380 Series
Pin circuit types (2 of 2)
FPT-120P-M21
Circuit
type *1
Pin no.
117 to 119
120
H
Supply
*1: Please refer to 6.“I/O Circuit Type” for details on the I/O circuit types
*2: Devices with suffix “W”
*3: Devices without suffix “W”
Document Number: 002-04582 Rev. *A
Page 13 of 117
MB96380 Series
6. I/O Circuit Type
Type
Circuit
Remarks
X1
High-speed oscillation circuit:
R
• Programmable between oscillation mode (external
crystal or resonator connected to X0/X1 pins) and
Fast external Clock Input (FCI) mode (external clock
connected to X0 pin)
0
1
Xout
A
MRFBE
• Programmable feedback resistor = approx.
2 * 0.5 M. Feedback resistor is grounded in the
center when the oscillator is disabled or in FCI mode
FCI
R
X0
FCI or osc disable
Xout
X1A
R
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
2 * 5 M. Feedback resistor is grounded in the center
when the oscillator is disabled
B
SRFBE
R
X0A
osc disable
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
R
C
Hysteresis
inputs
CMOS input pin
Pull-up
Resistor
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 k
E
R
Hysteresis
inputs
Document Number: 002-04582 Rev. *A
Page 14 of 117
MB96380 Series
Type
Circuit
Remarks
F
• Power supply input protection circuit
• A/D converter ref+ (AVRH/AVRH2) power supply in-
put pin with protection circuit
• Flash devices do not have a protection circuit against
VCC for pins AVRH/AVRH2
ANE
AVR
G
• Devices without AVRH reference switch do not have
an analog switch for the AVRL pin
ANE
pull-up control
Pout
Nout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
R
• 2 different CMOS hysteresis inputs with input
shutdown function
Hysteresis input
H
Standby control
for input shutdown
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50k approx.
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Document Number: 002-04582 Rev. *A
Page 15 of 117
MB96380 Series
Type
Circuit
Remarks
pull-up control
Pout
Nout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
R
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50k approx.
• SEG or COM output
Hysteresis input
Standby control
J
for input shutdown
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
SEG, COM output
pull-up control
Pout
Nout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
R
• 2 different CMOS hysteresis inputs with input
shutdown function
Hysteresis input
Standby control
K
• Automotive input with input shutdown function
• TTL input with input shutdown function.
• Programmable pull-up resistor: 50k approx.
• Analog input
for input shutdown
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
• SEG output
Standby control
for input shutdown
Standby control
for input shutdown
Analog input
SEG output
Document Number: 002-04582 Rev. *A
Page 16 of 117
MB96380 Series
Type
Circuit
Remarks
pull-up control
Pout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
Nout
R
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50k approx.
• Analog input
Hysteresis input
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
L
Standby control
for input shutdown
• Vx input
• SEG output
Standby control
for input shutdown
Standby control
for input shutdown
Analog input
SEG output
Vx input
pull-up control
Pout
Nout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL = 30mA,
IOH = -30mA)
R
Hysteresis input
Standby control
for input shutdown
• 2 different CMOS hysteresis inputs with input
shutdown function
M
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50k approx.
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
Document Number: 002-04582 Rev. *A
Page 17 of 117
MB96380 Series
Type
Circuit
Remarks
pull-up control
Pout
Nout
• CMOS level output (IOL = 3mA, IOH = -3mA)
R
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50k approx.
Hysteresis input
N
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Document Number: 002-04582 Rev. *A
Page 18 of 117
MB96380 Series
7. Memory Map
MB96V300B
MB96(F)38x
FF:FFFF
H
USER ROM /
External Bus*4
Emulation ROM
DE:0000
H
External Bus
External Bus
Boot-ROM
Reserved
10:0000
0F:E000
H
H
Boot-ROM
Reserved
0E:0000
02:0000
H
External RAM
H
Reserved
Internal RAM
*2
RAM availability
depending on the
device
Internal RAM
bank 1
RAMEND1
2
RAMSTART1
bank 1
01:0000
00:8000
Reserved
H
H
ROM/RAM MIRROR
ROM/RAM MIRROR
Internal RAM
bank 0
*2
RAMSTART0
Internal RAM
bank 0
Reserved
External Bus end
address*2
*
RAMSTART0
External Bus
External Bus
Peripherals
00:0C00
H
Peripherals
00:0380
00:0180
00:0100
00:00F0
00:0000
H
H
H
H
H
GPR*1
DMA
GPR*1
DMA
External Bus
Peripheral
External Bus
Peripheral
*1: Unused GPR banks can be used as RAM area
*2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, see the 9.“User ROM Memory Map for Flash Devices” and
10.“User ROM Memory Map for Mask Rom Devices” on the following pages.
The External Bus area and DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
Document Number: 002-04582 Rev. *A
Page 19 of 117
MB96380 Series
8. RAMSTART/END and External Bus End Addresses
Bank 1
RAM size
Bank0RAM
size
External Bus end
address
Devices
RAMSTART0
RAMSTART1
RAMEND1
MB96384
6KByte
8KByte
-
-
00:61FFH
00:61FFH
00:6A40H
00:6240H
-
-
-
-
MB96385/F385
MB96F386,
MB96F387
16KByte
-
00:41FFH
00:4240H
-
-
MB96F388
MB96F389
28KByte
28KByte
-
00:11FFH
00:11FFH
00:1240H
00:1240H
-
-
4KByte
01:8000H
01:8FFFH
Document Number: 002-04582 Rev. *A
Page 20 of 117
MB96380 Series
9. User ROM Memory Map for Flash Devices
MB96F385R
MB96F385Y
MB96F386R
MB96F386Y
MB96F387R
MB96F387Y
Flash size
160kByte
Flash size
288kByte
Flash size
416kByte
Alternative mode Flash memory
CPU address mode address
FF:FFFF
3F:FFFF
H
H
S39 - 64K
S38 - 64K
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
FF:0000
3F:0000
H
H
FE:FFFF
3E:FFFF
H
H
FE:0000
3E:0000
H
H
FD:FFFF
3D:FFFF
H
H
FD:0000
3D:0000
H
H
Flash A
FC:FFFF
3C:FFFF
H
H
H
FC:0000
3C:0000
H
FB:FFFF
3B:FFFF
H
H
H
H
FB:0000
3B:0000
FA:FFFF
3A:FFFF
H
H
H
H
FA:0000
3A:0000
F9:FFFF
F9:0000
39:FFFF
39:0000
H
H
H
H
F8:FFFF
F8:0000
38:FFFF
38:0000
H
H
H
H
F7:FFFF
F7:0000
37:FFFF
37:0000
H
H
H
H
F6:FFFF
F6:0000
36:FFFF
36:0000
H
H
H
H
External bus
F5:FFFF
F5:0000
35:FFFF
35:0000
H
H
H
H
External bus
F4:FFFF
34:FFFF
H
H
F4:0000
F3:FFFF
F3:0000
34:0000
H
H
External bus
33:FFFF
H
H
H
33:0000
H
F2:FFFF
32:FFFF
32:0000
H
H
H
F2:0000
H
F1:FFFF
31:FFFF
31:0000
H
H
H
F1:0000
H
F0:FFFF
30:FFFF
30:0000
H
H
H
F0:0000
H
E0:FFFF
H
E0:0000
H
H
DF:FFFF
Reserved
Reserved
Reserved
DF:8000
DF:7FFF
DF:6000
H
1F:7FFF
H
H
H
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
1F:6000
H
DF:5FFF
1F:5FFF
H
H
DF:4000
1F:4000
H
H
Flash A
DF:3FFF
1F:3FFF
H
H
DF:2000
1F:2000
H
H
DF:1FFF
DF:0000
DE:FFFF
1F:1FFF
H
H
H
*1
*1
*1
SA0 - 8K
SA0 - 8K
SA0 - 8K
1F:0000
H
H
Reserved
Reserved
Reserved
DE:0000
H
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
Document Number: 002-04582 Rev. *A
Page 21 of 117
MB96380 Series
MB96F388T
MB96F388H
MB96F389R
MB96F389Y
Flash size
576kByte
Flash size
832kByte
Alternative mode Flash memory
CPU address mode address
FF:FFFF
3F:FFFF
H
H
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
S33 - 64K
S32 - 64K
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
S33 - 64K
S32 - 64K
S31 - 64K
S30 - 64K
S29 - 64K
S28 - 64K
FF:0000
3F:0000
H
H
FE:FFFF
3E:FFFF
H
H
FE:0000
3E:0000
H
H
FD:FFFF
3D:FFFF
H
H
FD:0000
3D:0000
H
H
FC:FFFF
3C:FFFF
H
H
H
FC:0000
3C:0000
H
Flash A
FB:FFFF
3B:FFFF
H
H
H
H
FB:0000
3B:0000
FA:FFFF
3A:FFFF
H
H
H
H
FA:0000
3A:0000
F9:FFFF
39:FFFF
H
H
H
H
F9:0000
39:0000
F8:FFFF
38:FFFF
H
H
H
H
F8:0000
38:0000
F7:FFFF
37:FFFF
H
H
F7:0000
37:0000
H
H
F6:FFFF
36:FFFF
H
H
H
F6:0000
36:0000
H
Flash B
F5:FFFF
35:FFFF
H
H
H
F5:0000
35:0000
H
F4:FFFF
34:FFFF
H
H
F4:0000
34:0000
H
H
F3:FFFF
33:FFFF
33:0000
H
H
H
F3:0000
H
External bus
F2:FFFF
32:FFFF
32:0000
H
H
H
F2:0000
H
F1:FFFF
31:FFFF
31:0000
H
H
H
F1:0000
H
External bus
F0:FFFF
30:FFFF
30:0000
H
H
H
F0:0000
H
E0:FFFF
H
E0:0000
H
H
DF:FFFF
Reserved
Reserved
DF:8000
DF:7FFF
DF:6000
H
1F:7FFF
H
H
H
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
1F:6000
H
DF:5FFF
1F:5FFF
H
H
DF:4000
1F:4000
H
H
Flash A
DF:3FFF
1F:3FFF
H
H
DF:2000
1F:2000
H
H
DF:1FFF
1F:1FFF
H
H
*1
*1
SA0 - 8K
SA0 - 8K
DF:0000
1F:0000
H
H
DE:FFFF
H
Reserved
Reserved
DE:8000
H
DE:7FFF
DE:6000
1E:7FFF
H
H
H
SB3 - 8K
SB2 - 8K
SB1 - 8K
SB3 - 8K
SB2 - 8K
SB1 - 8K
1E:6000
H
DE:5FFF
1E:5FFF
H
H
DE:4000
1E:4000
H
H
Flash B
DE:3FFF
1E:3FFF
H
H
DE:2000
1E:2000
H
H
DE:1FFF
1E:1FFF
H
H
*2
*2
SB0 - 8K
SB0 - 8K
DE:0000
1E:0000
H
H
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
*2: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000H - DE:002FH
Document Number: 002-04582 Rev. *A
Page 22 of 117
MB96380 Series
10. User ROM Memory Map for Mask Rom Devices
MB96384
MB96385
ROM size
128kByte
ROM size
160kByte
CPU address
FF:FFFF
H
FF:0000
H
128K ROM
128K ROM
FE:FFFF
H
FE:0000
H
FD:FFFF
H
External bus
External bus
Reserved
DF:FFFF
H
H
DF:8000
DF:7FFF
Reserved
H
32K ROM
DF:0080
H
DF:007F
DF:0000
H
ROM configuration
block RCB
ROM configuration
block RCB
H
DE:FFFF
H
Reserved
Reserved
DE:0000
H
Document Number: 002-04582 Rev. *A
Page 23 of 117
MB96380 Series
11. Serial Programming Communication Interface
USART pins for Flash serial programming (MD[2:0] = 010, Serial Communication mode)
MB96F38x
Pin number
Normal function
USART Number
USART0
LQFP-120
8
9
SIN0
SOT0
SCK0
SIN1
10
3
4
USART1
USART2
SOT1
SCK1
SIN2
5
56
57
58
SOT2
SCK2
Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor to support at least
port P00_1 on pin 88.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Cypress suggests to the customer to
check the tool manual or to contact the tool vendor for alternative handshaking pins.
Document Number: 002-04582 Rev. *A
Page 24 of 117
MB96380 Series
12. I/O Map
I/O map MB96(F)38x (Sheet 1 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
00000DH
I/O Port P00 - Port Data Register
I/O Port P01 - Port Data Register
I/O Port P02 - Port Data Register
I/O Port P03 - Port Data Register
I/O Port P04 - Port Data Register
I/O Port P05 - Port Data Register
I/O Port P06 - Port Data Register
Reserved
PDR00
PDR01
PDR02
PDR03
PDR04
PDR05
PDR06
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
I/O Port P08 - Port Data Register
I/O Port P09 - Port Data Register
I/O Port P10 - Port Data Register
I/O Port P11 - Port Data Register
I/O Port P12 - Port Data Register
I/O Port P13 - Port Data Register
PDR08
PDR09
PDR10
PDR11
PDR12
PDR13
R/W
R/W
R/W
R/W
R/W
R/W
00000EH-
000017H
Reserved
-
-
-
000018H
000019H
00001AH
00001BH
00001CH
00001DH
00001EH
00001FH
000020H
000021H
000022H
000023H
000024H
000025H
ADC0 - Control Status register Low
ADC0 - Control Status register High
ADC0 - Data Register Low
ADCSL
ADCS
R/W
R/W
R
ADCSH
-
ADCRL
ADCR
ADC0 - Data Register High
ADCRH
-
R
ADC0 - Setting Register
-
ADSR
R/W
R/W
R/W
-
ADC0 - Setting Register
-
-
ADC0 - Extended Configuration Register
Reserved
ADECR
-
-
-
FRT0 - Data register of free-running timer
FRT0 - Data register of free-running timer
FRT0 - Control status register of free-running timer Low
FRT0 - Control status register of free-running timer High
FRT1 - Data register of free-running timer
FRT1 - Data register of free-running timer
-
TCDT0
R/W
R/W
R/W
R/W
R/W
R/W
-
-
TCCSL0
TCCS0
TCCSH0
-
-
-
TCDT1
-
Document Number: 002-04582 Rev. *A
Page 25 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 2 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
000026H
000027H
000028H
000029H
00002AH
00002BH
00002CH
00002DH
00002EH
00002FH
000030H
000031H
000032H
000033H
FRT1 - Control status register of free-running timer Low
FRT1 - Control status register of free-running timer High
OCU0 - Output Compare Control Status
OCU1 - Output Compare Control Status
OCU0 - Compare Register
TCCSL1
TCCS1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCCSH1
-
OCS0
-
OCS1
-
-
OCCP0
OCU0 - Compare Register
-
-
OCU1 - Compare Register
-
OCCP1
OCU1 - Compare Register
-
-
OCU2 - Output Compare Control Status
OCU3 - Output Compare Control Status
OCU2 - Compare Register
OCS2
-
OCS3
-
-
-
-
-
OCCP2
OCU2 - Compare Register
OCU3 - Compare Register
OCCP3
-
OCU3 - Compare Register
000034H-
00003FH
Reserved
-
-
-
000040H
000041H
000042H
000043H
000044H
000045H
000046H
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
ICU0/ICU1 - Control Status Register
ICU0/ICU1 - Edge register
ICS01
ICE01
-
R/W
R/W
R
-
ICU0 - Capture Register Low
ICU0 - Capture Register High
ICU1 - Capture Register Low
ICU1 - Capture Register High
ICU2/ICU3 - Control Status Register
ICU2/ICU3 - Edge register
IPCPL0
IPCPH0
IPCPL1
IPCPH1
ICS23
IPCP0
-
R
IPCP1
R
-
R
-
R/W
R/W
R
ICE23
-
ICU2 - Capture Register Low
ICU2 - Capture Register High
ICU3 - Capture Register Low
ICU3 - Capture Register High
ICU4/ICU5 - Control Status Register
ICU4/ICU5 - Edge register
IPCPL2
IPCPH2
IPCPL3
IPCPH3
ICS45
IPCP2
-
R
IPCP3
R
-
R
-
-
R/W
R/W
R
ICE45
ICU4 - Capture Register Low
IPCPL4
IPCP4
Document Number: 002-04582 Rev. *A
Page 26 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 3 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
000059H
00005AH
00005BH
ICU4 - Capture Register High
IPCPH4
IPCPL5
IPCPH5
ICS67
-
R
R
ICU5 - Capture Register Low
IPCP5
ICU5 - Capture Register High
-
R
ICU6/ICU7 - Control Status Register
ICU6/ICU7 - Edge register
-
R/W
R/W
R
ICE67
-
ICU6 - Capture Register Low
IPCPL6
IPCPH6
IPCPL7
IPCPH7
ENIR0
IPCP6
ICU6 - Capture Register High
-
R
ICU7 - Capture Register Low
IPCP7
R
ICU7 - Capture Register High
-
R
EXTINT0 - External Interrupt Enable Register
EXTINT0 - External Interrupt Interrupt request Register
EXTINT0 - External Interrupt Level Select Low
EXTINT0 - External Interrupt Level Select High
-
R/W
R/W
R/W
R/W
EIRR0
-
ELVRL0
ELVRH0
ELVR0
-
00005CH-
00005FH
Reserved
-
-
-
000060H
000061H
000062H
000062H
000063H
000063H
000064H
000065H
000066H
000066H
000067H
000067H
000068H
000069H
00006AH
00006AH
RLT0 - Timer Control Status Register Low
RLT0 - Timer Control Status Register High
RLT0 - Reload Register - for writing
RLT0 - Reload Register - for reading
RLT0 - Reload Register - for writing
RLT0 - Reload Register - for reading
RLT1 - Timer Control Status Register Low
RLT1 - Timer Control Status Register High
RLT1 - Reload Register - for writing
RLT1 - Reload Register - for reading
RLT1 - Reload Register - for writing
RLT1 - Reload Register - for reading
RLT2 - Timer Control Status Register Low
RLT2 - Timer Control Status Register High
RLT2 - Reload Register - for writing
RLT2 - Reload Register - for reading
TMCSRL0
TMCSR0
R/W
R/W
W
TMCSRH0
-
-
TMRLR0
-
TMR0
R
-
-
W
-
-
R
TMCSRL1
TMCSR1
R/W
R/W
W
TMCSRH1
-
-
TMRLR1
-
TMR1
R
-
-
W
-
-
R
TMCSRL2
TMCSR2
-
R/W
R/W
W
TMCSRH2
-
-
TMRLR2
TMR2
R
Document Number: 002-04582 Rev. *A
Page 27 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 4 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
00006BH
00006BH
00006CH
00006DH
00006EH
00006EH
00006FH
00006FH
RLT2 - Reload Register - for writing
RLT2 - Reload Register - for reading
RLT3 - Timer Control Status Register Low
RLT3 - Timer Control Status Register High
RLT3 - Reload Register - for writing
RLT3 - Reload Register - for reading
RLT3 - Reload Register - for writing
RLT3 - Reload Register - for reading
-
-
W
R
TMCSRL3
TMCSR3
R/W
R/W
W
TMCSRH3
-
-
-
-
TMRLR3
TMR3
R
-
-
W
R
RLT6 - Timer Control Status Register Low (dedic. RLT for
PPG)
000070H
000071H
TMCSRL6
TMCSRH6
TMCSR6
-
R/W
R/W
RLT6 - Timer Control Status Register High (dedic. RLT for
PPG)
000072H
000072H
000073H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
RLT6 - Reload Register (dedic. RLT for PPG) - for writing
RLT6 - Reload Register (dedic. RLT for PPG) - for reading
RLT6 - Reload Register (dedic. RLT for PPG) - for writing
RLT6 - Reload Register (dedic. RLT for PPG) - for reading
PPG3-PPG0 - General Control register 1 Low
PPG3-PPG0 - General Control register 1 High
PPG3-PPG0 - General Control register 2 Low
PPG3-PPG0 - General Control register 2 High
PPG0 - Timer register
-
TMRLR6
W
R
-
TMR6
-
-
W
-
-
R
GCN1L0
GCN10
R/W
R/W
R/W
R/W
R
GCN1H0
-
GCN2L0
GCN20
GCN2H0
-
-
PTMR0
PPG0 - Timer register
-
-
R
PPG0 - Period setting register
-
PCSR0
W
PPG0 - Period setting register
-
-
W
PPG0 - Duty cycle register
-
PDUT0
W
PPG0 - Duty cycle register
-
-
PCN0
-
W
PPG0 - Control status register Low
PPG0 - Control status register High
PPG1 - Timer register
PCNL0
R/W
R/W
R
PCNH0
-
-
-
PTMR1
-
PPG1 - Timer register
R
PPG1 - Period setting register
PCSR1
W
Document Number: 002-04582 Rev. *A
Page 28 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 5 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
000090H
000091H
000092H
000093H
000094H
000095H
000096H
000097H
000098H
000099H
00009AH
00009BH
00009CH
00009DH
00009EH
00009FH
0000A0H
PPG1 - Period setting register
-
-
W
W
PPG1 - Duty cycle register
-
PDUT1
PPG1 - Duty cycle register
-
-
W
PPG1 - Control status register Low
PPG1 - Control status register High
PPG2 - Timer register
PCNL1
PCN1
R/W
R/W
R
PCNH1
-
-
PTMR2
PPG2 - Timer register
-
-
R
PPG2 - Period setting register
PPG2 - Period setting register
PPG2 - Duty cycle register
-
PCSR2
W
-
-
W
-
PDUT2
W
PPG2 - Duty cycle register
-
-
W
PPG2 - Control status register Low
PPG2 - Control status register High
PPG3 - Timer register
PCNL2
PCN2
R/W
R/W
R
PCNH2
-
-
PTMR3
PPG3 - Timer register
-
-
R
PPG3 - Period setting register
PPG3 - Period setting register
PPG3 - Duty cycle register
-
PCSR3
W
-
-
W
-
PDUT3
W
PPG3 - Duty cycle register
-
-
W
PPG3 - Control status register Low
PPG3 - Control status register High
PPG7-PPG4 - General Control register 1 Low
PPG7-PPG4 - General Control register 1 High
PPG7-PPG4 - General Control register 2 Low
PPG7-PPG4 - General Control register 2 High
PPG4 - Timer register
PCNL3
PCN3
R/W
R/W
R/W
R/W
R/W
R/W
R
PCNH3
-
GCN1L1
GCN11
GCN1H1
-
GCN2L1
GCN21
GCN2H1
-
-
-
-
-
-
PTMR4
-
PPG4 - Timer register
R
PPG4 - Period setting register
PPG4 - Period setting register
PPG4 - Duty cycle register
PCSR4
-
W
W
PDUT4
W
Document Number: 002-04582 Rev. *A
Page 29 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 6 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
0000A1H
0000A2H
0000A3H
0000A4H
0000A5H
0000A6H
0000A7H
0000A8H
0000A9H
0000AAH
0000ABH
0000ACH
0000ADH
0000AEH
0000AFH
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
PPG4 - Duty cycle register
-
-
W
R/W
R/W
R
PPG4 - Control status register Low
PPG4 - Control status register High
PPG5 - Timer register
PCNL4
PCNH4
-
PCN4
-
PTMR5
PPG5 - Timer register
-
-
R
PPG5 - Period setting register
PPG5 - Period setting register
PPG5 - Duty cycle register
-
PCSR5
W
-
-
W
-
PDUT5
W
PPG5 - Duty cycle register
-
-
W
PPG5 - Control status register Low
PPG5 - Control status register High
I2C0 - Bus Status Register
PCNL5
PCNH5
IBSR0
IBCR0
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
ISMK0
IDAR0
ICCR0
PCN5
R/W
R/W
R
-
-
I2C0 - Bus Control Register
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2C0 - Ten bit Slave address Register Low
I2C0 - Ten bit Slave address Register High
I2C0 - Ten bit Address mask Register Low
I2C0 - Ten bit Address mask Register High
I2C0 - Seven bit Slave address Register
I2C0 - Seven bit Address mask Register
I2C0 - Data Register
ITBA0
-
ITMK0
-
-
-
-
-
I2C0 - Clock Control Register
0000B6H-
0000BFH
Reserved
-
-
-
0000C0H
0000C1H
0000C2H
0000C2H
0000C3H
0000C4H
0000C5H
0000C6H
USART0 - Serial Mode Register
USART0 - Serial Control Register
USART0 - TX Register
SMR0
SCR0
-
R/W
R/W
W
-
TDR0
-
USART0 - RX Register
RDR0
SSR0
-
R
USART0 - Serial Status
-
R/W
R/W
R/W
R/W
USART0 - Control/Com. Register
USART0 - Ext. Status Register
USART0 - Baud Rate Generator Register Low
ECCR0
ESCR0
BGRL0
-
-
BGR0
Document Number: 002-04582 Rev. *A
Page 30 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 7 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
0000C7H
0000C8H
0000C9H
0000CAH
0000CBH
0000CCH
0000CCH
0000CDH
0000CEH
0000CFH
0000D0H
0000D1H
0000D2H
0000D3H
0000D4H
0000D5H
0000D6H
0000D6H
0000D7H
0000D8H
0000D9H
0000DAH
0000DBH
0000DCH
USART0 - Baud Rate Generator Register High
USART0 - Extended Serial Interrupt Register
Reserved
BGRH0
ESIR0
-
-
R/W
R/W
-
-
-
USART1 - Serial Mode Register
USART1 - Serial Control Register
USART1 - TX Register
SMR1
SCR1
TDR1
RDR1
SSR1
ECCR1
ESCR1
BGRL1
BGRH1
ESIR1
-
-
R/W
R/W
W
-
-
USART1 - RX Register
-
R
USART1 - Serial Status
-
R/W
R/W
R/W
R/W
R/W
R/W
-
USART1 - Control/Com. Register
USART1 - Ext. Status Register
USART1 - Baud Rate Generator Register Low
USART1 - Baud Rate Generator Register High
USART1 - Extended Serial Interrupt Register
Reserved
-
-
BGR1
-
-
-
USART2 - Serial Mode Register
USART2 - Serial Control Register
USART2 - TX Register
SMR2
SCR2
TDR2
RDR2
SSR2
ECCR2
ESCR2
BGRL2
BGRH2
ESIR2
-
R/W
R/W
W
-
-
USART2 - RX Register
-
R
USART2 - Serial Status
-
R/W
R/W
R/W
R/W
R/W
R/W
USART2 - Control/Com. Register
USART2 - Ext. Status Register
USART2 - Baud Rate Generator Register Low
USART2 - Baud Rate Generator Register High
USART2 - Extended Serial Interrupt Register
-
-
BGR2
-
-
0000DDH-
0000EFH
Reserved
-
-
-
-
0000F0H-
0000FFH
External Bus area
EXTBUS0
R/W
000100H
000101H
000102H
DMA0 - Buffer address pointer low byte
DMA0 - Buffer address pointer middle byte
DMA0 - Buffer address pointer high byte
BAPL0
BAPM0
BAPH0
-
-
-
R/W
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 31 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 8 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
000103H
000104H
000105H
000106H
000107H
000108H
000109H
00010AH
00010BH
00010CH
00010DH
00010EH
00010FH
000110H
000111H
000112H
000113H
000114H
000115H
000116H
000117H
000118H
000119H
00011AH
00011BH
00011CH
00011DH
00011EH
00011FH
000120H
DMA0 - DMA control register
DMACS0
IOAL0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA0 - I/O register address pointer low byte
DMA0 - I/O register address pointer high byte
DMA0 - Data counter low byte
IOA0
IOAH0
DCTL0
DCTH0
BAPL1
BAPM1
BAPH1
DMACS1
IOAL1
-
DCT0
DMA0 - Data counter high byte
-
DMA1 - Buffer address pointer low byte
DMA1 - Buffer address pointer middle byte
DMA1 - Buffer address pointer high byte
DMA1 - DMA control register
-
-
-
-
DMA1 - I/O register address pointer low byte
DMA1 - I/O register address pointer high byte
DMA1 - Data counter low byte
IOA1
IOAH1
DCTL1
DCTH1
BAPL2
BAPM2
BAPH2
DMACS2
IOAL2
-
DCT1
DMA1 - Data counter high byte
-
DMA2 - Buffer address pointer low byte
DMA2 - Buffer address pointer middle byte
DMA2 - Buffer address pointer high byte
DMA2 - DMA control register
-
-
-
-
DMA2 - I/O register address pointer low byte
DMA2 - I/O register address pointer high byte
DMA2 - Data counter low byte
IOA2
IOAH2
DCTL2
DCTH2
BAPL3
BAPM3
BAPH3
DMACS3
IOAL3
-
DCT2
DMA2 - Data counter high byte
-
DMA3 - Buffer address pointer low byte
DMA3 - Buffer address pointer middle byte
DMA3 - Buffer address pointer high byte
DMA3 - DMA control register
-
-
-
-
DMA3 - I/O register address pointer low byte
DMA3 - I/O register address pointer high byte
DMA3 - Data counter low byte
IOA3
IOAH3
DCTL3
DCTH3
BAPL4
-
DCT3
DMA3 - Data counter high byte
-
-
DMA4 - Buffer address pointer low byte
Document Number: 002-04582 Rev. *A
Page 32 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 9 of 30)
Address
Abbreviation
8-bit access
Abbreviation
Access
Register
16-bit access
000121H
000122H
000123H
000124H
000125H
000126H
000127H
000128H
000129H
00012AH
00012BH
00012CH
00012DH
00012EH
00012FH
000130H
000131H
000132H
000133H
000134H
000135H
000136H
000137H
DMA4 - Buffer address pointer middle byte
DMA4 - Buffer address pointer high byte
DMA4 - DMA control register
BAPM4
BAPH4
DMACS4
IOAL4
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
DMA4 - I/O register address pointer low byte
DMA4 - I/O register address pointer high byte
DMA4 - Data counter low byte
IOA4
IOAH4
-
DCTL4
DCTH4
BAPL5
BAPM5
BAPH5
DMACS5
IOAL5
DCT4
DMA4 - Data counter high byte
-
DMA5 - Buffer address pointer low byte
DMA5 - Buffer address pointer middle byte
DMA5 - Buffer address pointer high byte
DMA5 - DMA control register
-
-
-
-
DMA5 - I/O register address pointer low byte
DMA5 - I/O register address pointer high byte
DMA5 - Data counter low byte
IOA5
IOAH5
-
DCTL5
DCTH5
BAPL6
BAPM6
BAPH6
DMACS6
IOAL6
DCT5
DMA5 - Data counter high byte
-
DMA6 - Buffer address pointer low byte
DMA6 - Buffer address pointer middle byte
DMA6 - Buffer address pointer high byte
DMA6 - DMA control register
-
-
-
-
DMA6 - I/O register address pointer low byte
DMA6 - I/O register address pointer high byte
DMA6 - Data counter low byte
IOA6
IOAH6
-
DCT6
-
DCTL6
DCTH6
DMA6 - Data counter high byte
000138H-
00017FH
Reserved
-
-
-
-
000180H-
00037FH
CPU - General Purpose registers (RAM access)
GPR_RAM
R/W
000380H
000381H
000382H
000383H
DMA0 - Interrupt select
DMA1 - Interrupt select
DMA2 - Interrupt select
DMA3 - Interrupt select
DISEL0
DISEL1
DISEL2
DISEL3
-
-
-
-
R/W
R/W
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 33 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 10 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000384H
000385H
000386H
DMA4 - Interrupt select
DMA5 - Interrupt select
DMA6 - Interrupt select
DISEL4
DISEL5
DISEL6
-
-
-
R/W
R/W
R/W
000387H-
00038FH
Reserved
-
-
-
000390H
000391H
000392H
000393H
000394H
000395H
DMA - Status register low byte
DMA - Status register high byte
DMA - Stop status register low byte
DMA - Stop status register high byte
DMA - Enable register low byte
DMA - Enable register high byte
DSRL
DSRH
DSSRL
DSSRH
DERL
DSR
R/W
R/W
R/W
R/W
R/W
R/W
-
DSSR
-
DER
-
DERH
000396H-
00039FH
Reserved
-
-
-
0003A0H
0003A1H
0003A2H
0003A3H
0003A4H
0003A5H
Interrupt level register
ILR
IDX
ICR
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt index register
-
Interrupt vector table base register Low
Interrupt vector table base register High
Delayed Interrupt register
TBRL
TBRH
DIRR
NMI
TBR
-
-
-
Non Maskable Interrupt register
0003A6H-
0003ABH
Reserved
-
-
-
0003ACH
0003ADH
0003AEH
0003AFH
0003B0H
0003B1H
0003B2H
0003B3H
0003B4H
0003B5H
0003B6H
EDSU communication interrupt selection Low
EDSU communication interrupt selection High
ROM mirror control register
EDSU2L
EDSU2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EDSU2H
-
ROMM
-
EDSU configuration register
EDSU
-
Memory patch control/status register ch 0/1
Memory patch control/status register ch 0/1
Memory patch control/status register ch 2/3
Memory patch control/status register ch 2/3
Memory patch control/status register ch 4/5
Memory patch control/status register ch 4/5
Memory patch control/status register ch 6/7
-
-
-
-
-
-
-
PFCS0
-
PFCS1
-
PFCS2
-
PFCS3
Document Number: 002-04582 Rev. *A
Page 34 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 11 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
0003B7H
0003B8H
0003B9H
0003BAH
0003BBH
0003BCH
0003BDH
0003BEH
0003BFH
0003C0H
0003C1H
0003C2H
0003C3H
0003C4H
0003C5H
0003C6H
0003C7H
0003C8H
0003C9H
0003CAH
0003CBH
0003CCH
0003CDH
0003CEH
0003CFH
0003D0H
0003D1H
0003D2H
0003D3H
0003D4H
Memory patch control/status register ch 6/7
Memory Patch function - Patch address 0 low
Memory Patch function - Patch address 0 middle
Memory Patch function - Patch address 0 high
Memory Patch function - Patch address 1 low
Memory Patch function - Patch address 1 middle
Memory Patch function - Patch address 1 high
Memory Patch function - Patch address 2 low
Memory Patch function - Patch address 2 middle
Memory Patch function - Patch address 2 high
Memory Patch function - Patch address 3 low
Memory Patch function - Patch address 3 middle
Memory Patch function - Patch address 3 high
Memory Patch function - Patch address 4 low
Memory Patch function - Patch address 4 middle
Memory Patch function - Patch address 4 high
Memory Patch function - Patch address 5 low
Memory Patch function - Patch address 5 middle
Memory Patch function - Patch address 5 high
Memory Patch function - Patch address 6 low
Memory Patch function - Patch address 6 middle
Memory Patch function - Patch address 6 high
Memory Patch function - Patch address 7 low
Memory Patch function - Patch address 7 middle
Memory Patch function - Patch address 7 high
Memory Patch function - Patch data 0 Low
Memory Patch function - Patch data 0 High
Memory Patch function - Patch data 1 Low
Memory Patch function - Patch data 1 High
Memory Patch function - Patch data 2 Low
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFAL0
PFAM0
PFAH0
PFAL1
PFAM1
PFAH1
PFAL2
PFAM2
PFAH2
PFAL3
PFAM3
PFAH3
PFAL4
PFAM4
PFAH4
PFAL5
PFAM5
PFAH5
PFAL6
PFAM6
PFAH6
PFAL7
PFAM7
PFAH7
PFDL0
PFDH0
PFDL1
PFDH1
PFDL2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PFD0
-
PFD1
-
PFD2
Document Number: 002-04582 Rev. *A
Page 35 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 12 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
0003D5H
0003D6H
0003D7H
0003D8H
0003D9H
0003DAH
0003DBH
0003DCH
0003DDH
0003DEH
0003DFH
Memory Patch function - Patch data 2 High
Memory Patch function - Patch data 3 Low
Memory Patch function - Patch data 3 High
Memory Patch function - Patch data 4 Low
Memory Patch function - Patch data 4 High
Memory Patch function - Patch data 5 Low
Memory Patch function - Patch data 5 High
Memory Patch function - Patch data 6 Low
Memory Patch function - Patch data 6 High
Memory Patch function - Patch data 7 Low
Memory Patch function - Patch data 7 High
PFDH2
PFDL3
PFDH3
PFDL4
PFDH4
PFDL5
PFDH5
PFDL6
PFDH6
PFDL7
PFDH7
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFD3
-
PFD4
-
PFD5
-
PFD6
-
PFD7
-
0003E0H-
0003F0H
Reserved
-
-
-
0003F1H
0003F2H
0003F3H
0003F4H
0003F5H
0003F6H
0003F7H
0003F8H
0003F9H
0003FAH
0003FBH
0003FCH
0003FDH
Memory Control Status Register A
MCSRA
MTCRAL
MTCRAH
-
-
R/W
R/W
R/W
-
Memory Timing Configuration Register A Low
Memory Timing Configuration Register A High
Reserved
MTCRA
-
-
Memory Control Status Register B
MCSRB
MTCRBL
MTCRBH
FMWC0
FMWC1
FMWC2
FMWC3
FMWC4
FMWC5
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Memory Timing Configuration Register B Low
Memory Timing Configuration Register B High
Flash Memory Write Control register 0
Flash Memory Write Control register 1
Flash Memory Write Control register 2
Flash Memory Write Control register 3
Flash Memory Write Control register 4
Flash Memory Write Control register 5
MTCRB
-
-
-
-
-
-
-
0003FEH-
0003FFH
Reserved
-
-
-
000400H
000401H
000402H
Standby Mode control register
Clock select register
SMCR
CKSR
-
-
-
R/W
R/W
R/W
Clock Stabilisation select register
CKSSR
Document Number: 002-04582 Rev. *A
Page 36 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 13 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000403H
000404H
000405H
000406H
000407H
000408H
000409H
00040AH
00040BH
00040CH
00040DH
00040EH
00040FH
Clock monitor register
CKMR
CKFCRL
CKFCRH
PLLCRL
PLLCRH
RCTCR
MCTCR
SCTCR
RCCSRC
RCR
-
R
Clock Frequency control register Low
Clock Frequency control register High
PLL Control register Low
CKFCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
-
PLLCR
PLL Control register High
-
-
-
-
-
-
-
-
-
RC clock timer control register
Main clock timer control register
Sub clock timer control register
Reset cause and clock status register with clear function
Reset configuration register
R/W
R
Reset cause and clock status register
Watch dog timer configuration register
Watch dog timer clear pattern register
RCCSR
WDTC
R/W
W
WDTCP
000410H-
000414H
Reserved
-
-
-
000415H
000416H
000417H
000418H
000419H
00041AH
00041BH
Clock output activation register
Clock output configuration register 0
Clock output configuration register 1
Clock Modulator control register
Reserved
COAR
COCR0
COCR1
CMCR
-
-
R/W
R/W
R/W
R/W
-
-
-
-
-
Clock Modulator Parameter register Low
Clock Modulator Parameter register High
CMPRL
CMPRH
CMPR
-
R/W
R/W
00041CH-
00042BH
Reserved
-
-
-
00042CH
00042DH
Voltage Regulator Control register
VRCR
CILCR
-
-
R/W
R/W
Clock Input and LVD Control Register
00042EH-
00042FH
Reserved
-
-
-
000430H
000431H
000432H
000433H
I/O Port P00 - Data Direction Register
I/O Port P01 - Data Direction Register
I/O Port P02 - Data Direction Register
I/O Port P03 - Data Direction Register
DDR00
DDR01
DDR02
DDR03
-
-
-
-
R/W
R/W
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 37 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 14 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000434H
000435H
000436H
000437H
000438H
000439H
00043AH
00043BH
00043CH
00043DH
I/O Port P04 - Data Direction Register
I/O Port P05 - Data Direction Register
I/O Port P06 - Data Direction Register
Reserved
DDR04
DDR05
DDR06
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
-
I/O Port P08 - Data Direction Register
I/O Port P09 - Data Direction Register
I/O Port P10 - Data Direction Register
I/O Port P11 - Data Direction Register
I/O Port P12 - Data Direction Register
I/O Port P13 - Data Direction Register
DDR08
DDR09
DDR10
DDR11
DDR12
DDR13
R/W
R/W
R/W
R/W
R/W
R/W
00043EH-
000443H
Reserved
-
-
-
000444H
000445H
000446H
000447H
000448H
000449H
00044AH
00044BH
00044CH
00044DH
00044EH
00044FH
000450H
000451H
I/O Port P00 - Port Input Enable Register
I/O Port P01 - Port Input Enable Register
I/O Port P02 - Port Input Enable Register
I/O Port P03 - Port Input Enable Register
I/O Port P04 - Port Input Enable Register
I/O Port P05 - Port Input Enable Register
I/O Port P06 - Port Input Enable Register
Reserved
PIER00
PIER01
PIER02
PIER03
PIER04
PIER05
PIER06
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
I/O Port P08 - Port Input Enable Register
I/O Port P09 - Port Input Enable Register
I/O Port P10 - Port Input Enable Register
I/O Port P11 - Port Input Enable Register
I/O Port P12 - Port Input Enable Register
I/O Port P13 - Port Input Enable Register
PIER08
PIER09
PIER10
PIER11
PIER12
PIER13
R/W
R/W
R/W
R/W
R/W
R/W
000452H-
000457H
Reserved
-
-
-
000458H
000459H
00045AH
I/O Port P00 - Port Input Level Register
I/O Port P01 - Port Input Level Register
I/O Port P02 - Port Input Level Register
PILR00
PILR01
PILR02
-
-
-
R/W
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 38 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 15 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
00045BH
00045CH
00045DH
00045EH
00045FH
000460H
000461H
000462H
000463H
000464H
000465H
I/O Port P03 - Port Input Level Register
I/O Port P04 - Port Input Level Register
I/O Port P05 - Port Input Level Register
I/O Port P06 - Port Input Level Register
Reserved
PILR03
PILR04
PILR05
PILR06
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
-
I/O Port P08 - Port Input Level Register
I/O Port P09 - Port Input Level Register
I/O Port P10 - Port Input Level Register
I/O Port P11 - Port Input Level Register
I/O Port P12 - Port Input Level Register
I/O Port P13 - Port Input Level Register
PILR08
PILR09
PILR10
PILR11
PILR12
PILR13
R/W
R/W
R/W
R/W
R/W
R/W
000466H-
00046BH
Reserved
-
-
-
00046CH
00046DH
00046EH
00046FH
000470H
000471H
000472H
000473H
000474H
000475H
000476H
000477H
000478H
000479H
I/O Port P00 - Extended Port Input Level Register
I/O Port P01 - Extended Port Input Level Register
I/O Port P02 - Extended Port Input Level Register
I/O Port P03 - Extended Port Input Level Register
I/O Port P04 - Extended Port Input Level Register
I/O Port P05 - Extended Port Input Level Register
I/O Port P06 - Extended Port Input Level Register
Reserved
EPILR00
EPILR01
EPILR02
EPILR03
EPILR04
EPILR05
EPILR06
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
I/O Port P08 - Extended Port Input Level Register
I/O Port P09 - Extended Port Input Level Register
I/O Port P10 - Extended Port Input Level Register
I/O Port P11 - Extended Port Input Level Register
I/O Port P12 - Extended Port Input Level Register
I/O Port P13 - Extended Port Input Level Register
EPILR08
EPILR09
EPILR10
EPILR11
EPILR12
EPILR13
R/W
R/W
R/W
R/W
R/W
R/W
00047AH-
00047FH
Reserved
-
-
-
000480H
000481H
I/O Port P00 - Port Output Drive Register
I/O Port P01 - Port Output Drive Register
PODR00
PODR01
-
-
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 39 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 16 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000482H
000483H
000484H
000485H
000486H
000487H
000488H
000489H
00048AH
00048BH
00048CH
00048DH
I/O Port P02 - Port Output Drive Register
I/O Port P03 - Port Output Drive Register
I/O Port P04 - Port Output Drive Register
I/O Port P05 - Port Output Drive Register
I/O Port P06 - Port Output Drive Register
Reserved
PODR02
PODR03
PODR04
PODR05
PODR06
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
-
I/O Port P08 - Port Output Drive Register
I/O Port P09 - Port Output Drive Register
I/O Port P10 - Port Output Drive Register
I/O Port P11 - Port Output Drive Register
I/O Port P12 - Port Output Drive Register
I/O Port P13 - Port Output Drive Register
PODR08
PODR09
PODR10
PODR11
PODR12
PODR13
R/W
R/W
R/W
R/W
R/W
R/W
00048EH-
00049BH
Reserved
-
-
-
00049CH
00049DH
00049EH
I/O Port P08 - Port High Drive Register
I/O Port P09 - Port High Drive Register
I/O Port P10 - Port High Drive Register
PHDR08
PHDR09
PHDR10
-
-
-
R/W
R/W
R/W
00049FH-
0004A7H
Reserved
-
-
-
0004A8H
0004A9H
0004AAH
0004ABH
0004ACH
0004ADH
0004AEH
0004AFH
0004B0H
0004B1H
0004B2H
0004B3H
I/O Port P00 - Pull-Up resistor Control Register
I/O Port P01 - Pull-Up resistor Control Register
I/O Port P02 - Pull-Up resistor Control Register
I/O Port P03 - Pull-Up resistor Control Register
I/O Port P04 - Pull-Up resistor Control Register
I/O Port P05 - Pull-Up resistor Control Register
I/O Port P06 - Pull-Up resistor Control Register
Reserved
PUCR00
PUCR01
PUCR02
PUCR03
PUCR04
PUCR05
PUCR06
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
I/O Port P08 - Pull-Up resistor Control Register
I/O Port P09 - Pull-Up resistor Control Register
I/O Port P10 - Pull-Up resistor Control Register
I/O Port P11 - Pull-Up resistor Control Register
PUCR08
PUCR09
PUCR10
PUCR11
R/W
R/W
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 40 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 17 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
0004B4H
0004B5H
I/O Port P12 - Pull-Up resistor Control Register
I/O Port P13 - Pull-Up resistor Control Register
PUCR12
PUCR13
-
-
R/W
R/W
0004B6H-
0004BBH
Reserved
-
-
-
0004BCH
0004BDH
0004BEH
0004BFH
0004C0H
0004C1H
0004C2H
0004C3H
0004C4H
0004C5H
0004C6H
0004C7H
0004C8H
0004C9H
I/O Port P00 - External Pin State Register
I/O Port P01 - External Pin State Register
I/O Port P02 - External Pin State Register
I/O Port P03 - External Pin State Register
I/O Port P04 - External Pin State Register
I/O Port P05 - External Pin State Register
I/O Port P06 - External Pin State Register
Reserved
EPSR00
EPSR01
EPSR02
EPSR03
EPSR04
EPSR05
EPSR06
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R
R
R
R
R
R
R
-
I/O Port P08 - External Pin State Register
I/O Port P09 - External Pin State Register
I/O Port P10 - External Pin State Register
I/O Port P11 - External Pin State Register
I/O Port P12 - External Pin State Register
I/O Port P13 - External Pin State Register
EPSR08
EPSR09
EPSR10
EPSR11
EPSR12
EPSR13
R
R
R
R
R
R
0004CAH-
0004CFH
Reserved
-
-
-
0004D0H
0004D1H
0004D2H
0004D3H
0004D4H
0004D5H
0004D6H
0004D7H
0004D8H
0004D9H
0004DAH
ADC analog input enable register 0
ADC analog input enable register 1
ADC analog input enable register 2
ADC analog input enable register 3
ADC analog input enable register 4
Reserved
ADER0
ADER1
ADER2
ADER3
ADER4
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
-
Peripheral Resource Relocation Register 0
Peripheral Resource Relocation Register 1
Peripheral Resource Relocation Register 2
Peripheral Resource Relocation Register 3
Peripheral Resource Relocation Register 4
PRRR0
PRRR1
PRRR2
PRRR3
PRRR4
R/W
R/W
R/W
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 41 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 18 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
0004DBH
0004DCH
0004DDH
0004DEH
0004DFH
0004E0H
0004E1H
0004E2H
0004E3H
0004E4H
0004E5H
0004E6H
0004E7H
0004E8H
0004E9H
0004EAH
0004EBH
0004ECH
0004EDH
0004EEH
0004EFH
0004F0H
0004F1H
Peripheral Resource Relocation Register 5
Peripheral Resource Relocation Register 6
Peripheral Resource Relocation Register 7
Peripheral Resource Relocation Register 8
Peripheral Resource Relocation Register 9
RTC - Sub Second Register L
PRRR5
PRRR6
PRRR7
PRRR8
PRRR9
WTBRL0
WTBRH0
WTBR1
WTSR
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
WTBR0
RTC - Sub Second Register M
-
RTC - Sub-Second Register H
-
RTC - Second Register
-
RTC - Minutes
WTMR
-
RTC - Hour
WTHR
-
RTC - Timer Control Extended Register
RTC - Clock select register
WTCER
WTCKSR
WTCRL
WTCRH
CUCR
-
-
RTC - Timer Control Register Low
RTC - Timer Control Register High
CAL - Calibration unit Control register
Reserved
WTCR
-
-
-
-
CAL - Duration Timer Data Register Low
CAL - Duration Timer Data Register High
CAL - Calibration Timer Register 2 Low
CAL - Calibration Timer Register 2 High
CAL - Calibration Timer Register 1 Low
CAL - Calibration Timer Register 1 High
CUTDL
CUTDH
CUTR2L
CUTR2H
CUTR1L
CUTR1H
CUTD
R/W
R/W
R
-
CUTR2
-
R
CUTR1
-
R
R
0004F2H-
0004F9H
Reserved
-
-
-
-
-
R/W
-
0004FAH
RLT - Timer input select (for Cascading)
Reserved
TMISR
-
0004FBH-
00051FH
000520H
000521H
000522H
USART4 - Serial Mode Register
USART4 - Serial Control Register
USART4 - TX Register
SMR4
SCR4
TDR4
-
-
-
R/W
R/W
W
Document Number: 002-04582 Rev. *A
Page 42 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 19 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000522H
000523H
000524H
000525H
000526H
000527H
000528H
000529H
00052AH
00052BH
00052CH
00052CH
00052DH
00052EH
00052FH
000530H
000531H
000532H
USART4 - RX Register
RDR4
SSR4
-
R
USART4 - Serial Status
-
R/W
R/W
R/W
R/W
R/W
R/W
-
USART4 - Control/Com. Register (internal)
USART4 - Ext. Status Register
USART4 - Baud Rate Generator Register Low
USART4 - Baud Rate Generator Register High
USART4 - Extended Serial Interrupt Register
Reserved
ECCR4
ESCR4
BGRL4
BGRH4
ESIR4
-
-
-
BGR4
-
-
-
USART5 - Serial Mode Register
USART5 - Serial Control Register
USART5 - RX Register
SMR5
SCR5
TDR5
-
R/W
R/W
W
-
-
USART5 - TX Register
RDR5
SSR5
-
R
USART5 - Serial Status
-
R/W
R/W
R/W
R/W
R/W
R/W
USART5 - Control/Com. Register
USART5 - Ext. Status Register
USART5 - Baud Rate Generator Register Low
USART5 - Baud Rate Generator Register High
USART5 - Extended Serial Interrupt Register
ECCR5
ESCR5
BGRL5
BGRH5
ESIR5
-
-
BGR5
-
-
000533H-
00055FH
Reserved
-
-
-
000560H
000561H
000562H
000563H
000564H
000565H
000566H
000567H
000568H
000569H
00056AH
ALARM0 - Control Status Register
ALARM0 - Extended Control Status Register
ALARM1 - Control Status Register
ALARM1 - Extended Control Status Register
PPG6 - Timer register
ACSR0
-
R/W
R/W
R/W
R/W
R
AECSR0
-
ACSR1
-
AECSR1
-
-
PTMR6
PPG6 - Timer register
-
-
PCSR6
-
R
PPG6 - Period setting register
PPG6 - Period setting register
PPG6 - Duty cycle register
-
W
-
W
-
PDUT6
-
W
PPG6 - Duty cycle register
-
W
PPG6 - Control status register Low
PCNL6
PCN6
R/W
Document Number: 002-04582 Rev. *A
Page 43 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 20 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
00056BH
00056CH
00056DH
00056EH
00056FH
000570H
000571H
000572H
000573H
PPG6 - Control status register High
PPG7 - Timer register
PCNH6
-
R/W
R
-
PTMR7
-
PPG7 - Timer register
-
R
PPG7 - Period setting register
PPG7 - Period setting register
PPG7 - Duty cycle register
PPG7 - Duty cycle register
PPG7 - Control status register Low
PPG7 - Control status register High
-
PCSR7
W
-
W
-
PDUT7
W
-
-
PCN7
-
W
PCNL7
PCNH7
R/W
R/W
000574H-
0005DFH
Reserved
-
-
-
0005E0H
0005E1H
0005E2H
0005E3H
0005E4H
0005E5H
0005E6H
0005E7H
SMC0 - PWM control register
PWC0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMC0 - Extended control register (Output enable)
SMC0 - PWM compare register PWM 1
SMC0 - PWM compare register PWM 1
SMC0 - PWM compare register PWM 2
SMC0 - PWM compare register PWM 2
SMC0 - PWM Select register
PWEC0
-
-
PWC10
-
-
-
PWC20
-
-
-
-
PWS10
PWS20
SMC0 - PWM Select register
0005E8H-
0005E9H
Reserved
-
-
-
0005EAH
0005EBH
0005ECH
0005EDH
0005EEH
0005EFH
0005F0H
0005F1H
SMC1 - PWM control register
PWC1
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMC1 - Extended control register (Output enable)
SMC1 - PWM compare register PWM 1
SMC1 - PWM compare register PWM 1
SMC1 - PWM compare register PWM 2
SMC1 - PWM compare register PWM 2
SMC1 - PWM Select register
PWEC1
-
-
PWC11
-
-
-
PWC21
-
-
-
-
PWS11
PWS21
SMC1 - PWM Select register
0005F2H-
0005F3H
Reserved
-
-
-
-
0005F4H
SMC2 - PWM control register
PWC2
R/W
Document Number: 002-04582 Rev. *A
Page 44 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 21 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
0005F5H
0005F6H
0005F7H
0005F8H
0005F9H
0005FAH
0005FBH
SMC2 - Extended control register (Output enable)
SMC2 - PWM compare register PWM 1
SMC2 - PWM compare register PWM 1
SMC2 - PWM compare register PWM 2
SMC2 - PWM compare register PWM 2
SMC2 - PWM Select register
PWEC2
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
PWC12
-
-
-
PWC22
-
-
-
-
PWS12
PWS22
SMC2 - PWM Select register
0005FCH-
0005FDH
Reserved
-
-
-
0005FEH
0005FFH
000600H
000601H
000602H
000603H
000604H
000605H
SMC3 - PWM control register
PWC3
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMC3 - Extended control register (Output enable)
SMC3 - PWM compare register PWM 1
SMC3 - PWM compare register PWM 1
SMC3 - PWM compare register PWM 2
SMC3 - PWM compare register PWM 2
SMC3 - PWM Select register
PWEC3
-
-
PWC13
-
-
-
PWC23
-
-
-
-
PWS13
PWS23
SMC3 - PWM Select register
000606H-
000607H
Reserved
-
-
-
000608H
000609H
00060AH
00060BH
00060CH
00060DH
00060EH
00060FH
SMC4 - PWM control register
PWC4
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMC4 - Extended control register (Output enable)
SMC4 - PWM compare register PWM 1
SMC4 - PWM compare register PWM 1
SMC4 - PWM compare register PWM 2
SMC4 - PWM compare register PWM 2
SMC4 - PWM Select register
PWEC4
-
-
PWC14
-
-
-
PWC24
-
-
-
-
PWS14
PWS24
SMC4 - PWM Select register
000610H-
00061BH
Reserved
-
-
-
00061CH
00061DH
00061EH
LCD - Output Enable Register 0 (Seg 7-0)
LCD - Output Enable Register 1 (Seg 15-8)
LCD - Output Enable Register 2 (Seg 23-16)
LCDER0
LCDER1
LCDER2
-
-
-
R/W
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 45 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 22 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
00061FH
000620H
000621H
000622H
000623H
000624H
000625H
000626H
000627H
000628H
000629H
00062AH
00062BH
00062CH
00062DH
00062EH
00062FH
000630H
000631H
000632H
000633H
000634H
000635H
000636H
000637H
000638H
000639H
00063AH
00063BH
00063CH
LCD - Output Enable Register 3 (Seg 31-24)
LCD - Output Enable Register 4 (Seg 39-32)
LCD - Output Enable Register 5 (Seg 47-40)
LCD - Output Enable Register 6 (Seg 55-48)
LCD - Output Enable Register 7 (Seg 63-56)
LCD - Output Enable Register 8 (Seg 71-64)
Reserved
LCDER3
LCDER4
LCDER5
LCDER6
LCDER7
LCDER8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
-
LCD - Output Enable Register V (Vx)
LCD - Extended Control Register
LCDVER
LECR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCD - Common pin switching register
LCD - Control Register
LCDCMR
LCR
LCD - Data register for Segment 1-0
LCD - Data register for Segment 3-2
LCD - Data register for Segment 5-4
LCD - Data register for Segment 7-6
LCD - Data register for Segment 9-8
LCD - Data register for Segment 11-10
LCD - Data register for Segment 13-12
LCD - Data register for Segment 15-14
LCD - Data register for Segment 17-16
LCD - Data register for Segment 19-18
LCD - Data register for Segment 21-20
LCD - Data register for Segment 23-22
LCD - Data register for Segment 25-24
LCD - Data register for Segment 27-26
LCD - Data register for Segment 29-28
LCD - Data register for Segment 31-30
LCD - Data register for Segment 33-32
LCD - Data register for Segment 35-34
LCD - Data register for Segment 37-36
VRAM0
VRAM1
VRAM2
VRAM3
VRAM4
VRAM5
VRAM6
VRAM7
VRAM8
VRAM9
VRAM10
VRAM11
VRAM12
VRAM13
VRAM14
VRAM15
VRAM16
VRAM17
VRAM18
Document Number: 002-04582 Rev. *A
Page 46 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 23 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
00063DH
00063EH
00063FH
000640H
000641H
000642H
000643H
000644H
000645H
000646H
000647H
000648H
000649H
00064AH
LCD - Data register for Segment 39-38
LCD - Data register for Segment 41-40
LCD - Data register for Segment 43-42
LCD - Data register for Segment 45-44
LCD - Data register for Segment 47-46
LCD - Data register for Segment 49-48
LCD - Data register for Segment 51-50
LCD - Data register for Segment 53-52
LCD - Data register for Segment 55-54
LCD - Data register for Segment 57-56
LCD - Data register for Segment 59-58
LCD - Data register for Segment 61-60
LCD - Data register for Segment 63-62
LCD - Data register for Segment 65-64
VRAM19
VRAM20
VRAM21
VRAM22
VRAM23
VRAM24
VRAM25
VRAM26
VRAM27
VRAM28
VRAM29
VRAM30
VRAM31
VRAM32
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00064BH-
00065FH
Reserved
-
-
-
000660H
000661H
000662H
000663H
Peripheral Resource Relocation Register 10
Peripheral Resource Relocation Register 11
Peripheral Resource Relocation Register 12
Peripheral Resource Relocation Register 13
PRRR10
PRRR11
PRRR12
PRRR13
-
-
-
-
R/W
R/W
R/W
W
000664H-
0006DFH
Reserved
-
-
-
0006E0H
0006E1H
0006E2H
0006E3H
0006E4H
0006E5H
0006E6H
0006E7H
0006E8H
External Bus - Area configuration register 0 Low
External Bus - Area configuration register 0 High
External Bus - Area configuration register 1 Low
External Bus - Area configuration register 1 High
External Bus - Area configuration register 2 Low
External Bus - Area configuration register 2 High
External Bus - Area configuration register 3 Low
External Bus - Area configuration register 3 High
External Bus - Area configuration register 4 Low
EACL0
EACH0
EACL1
EACH1
EACL2
EACH2
EACL3
EACH3
EACL4
EAC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
EAC1
-
EAC2
-
EAC3
-
EAC4
Document Number: 002-04582 Rev. *A
Page 47 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 24 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
0006E9H
0006EAH
0006EBH
0006ECH
0006EDH
0006EEH
0006EFH
0006F0H
0006F1H
0006F2H
0006F3H
0006F4H
0006F5H
External Bus - Area configuration register 4 High
External Bus - Area configuration register 5 Low
External Bus - Area configuration register 5 High
External Bus - Area select register 2
EACH4
EACL5
EACH5
EAS2
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EAC5
-
-
-
-
-
-
-
-
-
-
-
External Bus - Area select register 3
EAS3
External Bus - Area select register 4
EAS4
External Bus - Area select register 5
EAS5
External Bus - Mode register
EBM
External Bus - Clock and Function register
External Bus - Address output enable register 0
External Bus - Address output enable register 1
External Bus - Address output enable register 2
External Bus - Control signal register
EBCF
EBAE0
EBAE1
EBAE2
EBCS
0006F6H-
0006FFH
Reserved
-
-
-
000700H
000701H
000702H
000703H
000704H
000705H
000706H
000707H
000708H
000709H
00070AH
00070BH
00070CH
00070DH
CAN0 - Control register Low
CTRLRL0
CTRLRH0
STATRL0
STATRH0
ERRCNTL0
ERRCNTH0
BTRL0
CTRLR0
R/W
R
CAN0 - Control register High (reserved)
CAN0 - Status register Low
-
STATR0
R/W
R
CAN0 - Status register High (reserved)
CAN0 - Error Counter Low (Transmit)
CAN0 - Error Counter High (Receive)
CAN0 - Bit Timing Register Low
CAN0 - Bit Timing Register High
CAN0 - Interrupt Register Low
-
ERRCNT0
R
-
R
BTR0
R/W
R/W
R
BTRH0
-
INTRL0
INTR0
CAN0 - Interrupt Register High
INTRH0
-
R
CAN0 - Test Register Low
TESTRL0
TESTRH0
BRPERL0
BRPERH0
TESTR0
R/W
R
CAN0 - Test Register High (reserved)
CAN0 - BRP Extension register Low
CAN0 - BRP Extension register High (reserved)
-
BRPER0
-
R/W
R
00070EH-
00070FH
Reserved
-
-
-
Document Number: 002-04582 Rev. *A
Page 48 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 25 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000710H
000711H
000712H
000713H
000714H
000715H
000716H
000717H
000718H
000719H
00071AH
00071BH
00071CH
00071DH
00071EH
00071FH
000720H
000721H
000722H
000723H
000724H
000725H
CAN0 - IF1 Command request register Low
CAN0 - IF1 Command request register High
CAN0 - IF1 Command Mask register Low
CAN0 - IF1 Command Mask register High (reserved)
CAN0 - IF1 Mask 1 Register Low
CAN0 - IF1 Mask 1 Register High
CAN0 - IF1 Mask 2 Register Low
CAN0 - IF1 Mask 2 Register High
CAN0 - IF1 Arbitration 1 Register Low
CAN0 - IF1 Arbitration 1 Register High
CAN0 - IF1 Arbitration 2 Register Low
CAN0 - IF1 Arbitration 2 Register High
CAN0 - IF1 Message Control Register Low
CAN0 - IF1 Message Control Register High
CAN0 - IF1 Data A1 Low
IF1CREQL0
IF1CREQH0
IF1CMSKL0
IF1CMSKH0
IF1MSK1L0
IF1MSK1H0
IF1MSK2L0
IF1MSK2H0
IF1ARB1L0
IF1ARB1H0
IF1ARB2L0
IF1ARB2H0
IF1MCTRL0
IF1MCTRH0
IF1DTA1L0
IF1DTA1H0
IF1DTA2L0
IF1DTA2H0
IF1DTB1L0
IF1DTB1H0
IF1DTB2L0
IF1DTB2H0
IF1CREQ0
R/W
R/W
R/W
R
-
IF1CMSK0
-
IF1MSK10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
IF1MSK20
-
IF1ARB10
-
IF1ARB20
-
IF1MCTR0
-
IF1DTA10
CAN0 - IF1 Data A1 High
-
CAN0 - IF1 Data A2 Low
IF1DTA20
CAN0 - IF1 Data A2 High
-
CAN0 - IF1 Data B1 Low
IF1DTB10
CAN0 - IF1 Data B1 High
-
CAN0 - IF1 Data B2 Low
IF1DTB20
-
CAN0 - IF1 Data B2 High
000726H-
00073FH
Reserved
-
-
-
000740H
000741H
000742H
CAN0 - IF2 Command request register Low
CAN0 - IF2 Command request register High
CAN0 - IF2 Command Mask register Low
IF2CREQL0
IF2CREQH0
IF2CMSKL0
IF2CREQ0
-
R/W
R/W
R/W
IF2CMSK0
CAN0 - IF2 Command Mask register High
(reserved)
000743H
IF2CMSKH0
-
R
000744H
000745H
CAN0 - IF2 Mask 1 Register Low
CAN0 - IF2 Mask 1 Register High
IF2MSK1L0
IF2MSK1H0
IF2MSK10
-
R/W
R/W
Document Number: 002-04582 Rev. *A
Page 49 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 26 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000746H
000747H
000748H
000749H
00074AH
00074BH
00074CH
00074DH
00074EH
00074FH
000750H
000751H
000752H
000753H
000754H
000755H
CAN0 - IF2 Mask 2 Register Low
CAN0 - IF2 Mask 2 Register High
CAN0 - IF2 Arbitration 1 Register Low
CAN0 - IF2 Arbitration 1 Register High
CAN0 - IF2 Arbitration 2 Register Low
CAN0 - IF2 Arbitration 2 Register High
CAN0 - IF2 Message Control Register Low
CAN0 - IF2 Message Control Register High
CAN0 - IF2 Data A1 Low
IF2MSK2L0
IF2MSK2H0
IF2ARB1L0
IF2ARB1H0
IF2ARB2L0
IF2ARB2H0
IF2MCTRL0
IF2MCTRH0
IF2DTA1L0
IF2DTA1H0
IF2DTA2L0
IF2DTA2H0
IF2DTB1L0
IF2DTB1H0
IF2DTB2L0
IF2DTB2H0
IF2MSK20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
IF2ARB10
-
IF2ARB20
-
IF2MCTR0
-
IF2DTA10
CAN0 - IF2 Data A1 High
-
CAN0 - IF2 Data A2 Low
IF2DTA20
CAN0 - IF2 Data A2 High
-
CAN0 - IF2 Data B1 Low
IF2DTB10
CAN0 - IF2 Data B1 High
-
CAN0 - IF2 Data B2 Low
IF2DTB20
-
CAN0 - IF2 Data B2 High
000756H-
00077FH
Reserved
-
-
-
000780H
000781H
000782H
000783H
CAN0 - Transmission Request 1 Register Low
CAN0 - Transmission Request 1 Register High
CAN0 - Transmission Request 2 Register Low
CAN0 - Transmission Request 2 Register High
TREQR1L0
TREQR1H0
TREQR2L0
TREQR2H0
TREQR10
R
R
R
R
-
TREQR20
-
000784H-
00078FH
Reserved
-
-
-
000790H
000791H
000792H
000793H
CAN0 - New Data 1 Register Low
CAN0 - New Data 1 Register High
CAN0 - New Data 2 Register Low
CAN0 - New Data 2 Register High
NEWDT1L0
NEWDT1H0
NEWDT2L0
NEWDT2H0
NEWDT10
R
R
R
R
-
NEWDT20
-
000794H-
00079FH
Reserved
-
-
-
0007A0H
0007A1H
CAN0 - Interrupt Pending 1 Register Low
CAN0 - Interrupt Pending 1 Register High
INTPND1L0
INTPND1H0
INTPND10
-
R
R
Document Number: 002-04582 Rev. *A
Page 50 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 27 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
0007A2H
0007A3H
CAN0 - Interrupt Pending 2 Register Low
CAN0 - Interrupt Pending 2 Register High
INTPND2L0
INTPND2H0
INTPND20
-
R
R
0007A4H-
0007AFH
Reserved
-
-
-
0007B0H
0007B1H
0007B2H
0007B3H
CAN0 - Message Valid 1 Register Low
CAN0 - Message Valid 1 Register High
CAN0 - Message Valid 2 Register Low
CAN0 - Message Valid 2 Register High
MSGVAL1L0
MSGVAL1H0
MSGVAL2L0
MSGVAL2H0
MSGVAL10
R
R
R
R
-
MSGVAL20
-
0007B4H-
0007CDH
Reserved
-
-
-
0007CEH
0007CFH
0007D0H
0007D1H
0007D2H
0007D3H
0007D4H
0007D5H
0007D6H
0007D7H
0007D8H
0007D9H
0007DAH
0007DBH
CAN0 - Output enable register
COER0
-
-
R/W
-
Reserved
-
SG0 - Sound Generator Control Register Low
SG0 - Sound Generator Control Register High
SG0 - Sound Generator Frequency Register
SG0 - Sound Generator Amplitude Register
SG0 - Sound Generator Decrement Register
SG0 - Sound Generator Tone Register
SG1 - Sound Generator Control Register Low
SG1 - Sound Generator Control Register High
SG1 - Sound Generator Frequency Register
SG1 - Sound Generator Amplitude Register
SG1 - Sound Generator Decrement Register
SG1 - Sound Generator Tone Register
SGCRL0
SGCRH0
SGFR0
SGAR0
SGDR0
SGTR0
SGCRL1
SGCRH1
SGFR1
SGAR1
SGDR1
SGTR1
SGCR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
SGCR1
-
-
-
-
-
0007DCH-
0007FFH
Reserved
-
-
-
000800H
000801H
000802H
000803H
000804H
000805H
CAN1 - Control register Low
CTRLRL1
CTRLRH1
STATRL1
CTRLR1
R/W
R
CAN1 - Control register High (reserved)
CAN1 - Status register Low
-
STATR1
R/W
R
CAN1 - Status register High (reserved)
CAN1 - Error Counter Low (Transmit)
CAN1 - Error Counter High (Receive)
STATRH1
ERRCNTL1
ERRCNTH1
-
ERRCNT1
-
R
R
Document Number: 002-04582 Rev. *A
Page 51 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 28 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000806H
000807H
000808H
000809H
00080AH
00080BH
00080CH
00080DH
CAN1 - Bit Timing Register Low
CAN1 - Bit Timing Register High
CAN1 - Interrupt Register Low
BTRL1
BTRH1
BTR1
R/W
R/W
R
-
INTRL1
INTR1
CAN1 - Interrupt Register High
INTRH1
-
R
CAN1 - Test Register Low
TESTRL1
TESTRH1
BRPERL1
BRPERH1
TESTR1
R/W
R
CAN1 - Test Register High (reserved)
CAN1 - BRP Extension register Low
CAN1 - BRP Extension register High (reserved)
-
BRPER1
-
R/W
R
00080EH-
00080FH
Reserved
-
-
-
000810H
000811H
000812H
CAN1 - IF1 Command request register Low
CAN1 - IF1 Command request register High
CAN1 - IF1 Command Mask register Low
IF1CREQL1
IF1CREQH1
IF1CMSKL1
IF1CREQ1
-
R/W
R/W
R/W
IF1CMSK1
CAN1 - IF1 Command Mask register High
(reserved)
000813H
IF1CMSKH1
-
R
000814H
000815H
000816H
000817H
000818H
000819H
00081AH
00081BH
00081CH
00081DH
00081EH
00081FH
000820H
000821H
000822H
000823H
CAN1 - IF1 Mask 1 Register Low
CAN1 - IF1 Mask 1 Register High
CAN1 - IF1 Mask 2 Register Low
CAN1 - IF1 Mask 2 Register High
CAN1 - IF1 Arbitration 1 Register Low
CAN1 - IF1 Arbitration 1 Register High
CAN1 - IF1 Arbitration 2 Register Low
CAN1 - IF1 Arbitration 2 Register High
CAN1 - IF1 Message Control Register Low
CAN1 - IF1 Message Control Register High
CAN1 - IF1 Data A1 Low
IF1MSK1L1
IF1MSK1H1
IF1MSK2L1
IF1MSK2H1
IF1ARB1L1
IF1ARB1H1
IF1ARB2L1
IF1ARB2H1
IF1MCTRL1
IF1MCTRH1
IF1DTA1L1
IF1DTA1H1
IF1DTA2L1
IF1DTA2H1
IF1DTB1L1
IF1DTB1H1
IF1MSK11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
IF1MSK21
-
IF1ARB11
-
IF1ARB21
-
IF1MCTR1
-
IF1DTA11
CAN1 - IF1 Data A1 High
-
CAN1 - IF1 Data A2 Low
IF1DTA21
CAN1 - IF1 Data A2 High
-
CAN1 - IF1 Data B1 Low
IF1DTB11
-
CAN1 - IF1 Data B1 High
Document Number: 002-04582 Rev. *A
Page 52 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 29 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000824H
000825H
CAN1 - IF1 Data B2 Low
CAN1 - IF1 Data B2 High
IF1DTB2L1
IF1DTB2H1
IF1DTB21
-
R/W
R/W
000826H-
00083FH
Reserved
-
-
-
000840H
000841H
000842H
CAN1 - IF2 Command request register Low
CAN1 - IF2 Command request register High
CAN1 - IF2 Command Mask register Low
IF2CREQL1
IF2CREQH1
IF2CMSKL1
IF2CREQ1
-
R/W
R/W
R/W
IF2CMSK1
CAN1 - IF2 Command Mask register High
(reserved)
000843H
IF2CMSKH1
-
R
000844H
000845H
000846H
000847H
000848H
000849H
00084AH
00084BH
00084CH
00084DH
00084EH
00084FH
000850H
000851H
000852H
000853H
000854H
000855H
CAN1 - IF2 Mask 1 Register Low
CAN1 - IF2 Mask 1 Register High
CAN1 - IF2 Mask 2 Register Low
CAN1 - IF2 Mask 2 Register High
CAN1 - IF2 Arbitration 1 Register Low
CAN1 - IF2 Arbitration 1 Register High
CAN1 - IF2 Arbitration 2 Register Low
CAN1 - IF2 Arbitration 2 Register High
CAN1 - IF2 Message Control Register Low
CAN1 - IF2 Message Control Register High
CAN1 - IF2 Data A1 Low
IF2MSK1L1
IF2MSK1H1
IF2MSK2L1
IF2MSK2H1
IF2ARB1L1
IF2ARB1H1
IF2ARB2L1
IF2ARB2H1
IF2MCTRL1
IF2MCTRH1
IF2DTA1L1
IF2DTA1H1
IF2DTA2L1
IF2DTA2H1
IF2DTB1L1
IF2DTB1H1
IF2DTB2L1
IF2DTB2H1
IF2MSK11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
IF2MSK21
-
IF2ARB11
-
IF2ARB21
-
IF2MCTR1
-
IF2DTA11
CAN1 - IF2 Data A1 High
-
CAN1 - IF2 Data A2 Low
IF2DTA21
CAN1 - IF2 Data A2 High
-
CAN1 - IF2 Data B1 Low
IF2DTB11
CAN1 - IF2 Data B1 High
-
CAN1 - IF2 Data B2 Low
IF2DTB21
-
CAN1 - IF2 Data B2 High
000856H-
00087FH
Reserved
-
-
-
000880H
000881H
000882H
CAN1 - Transmission Request 1 Register Low
CAN1 - Transmission Request 1 Register High
CAN1 - Transmission Request 2 Register Low
TREQR1L1
TREQR1H1
TREQR2L1
TREQR11
-
R
R
R
TREQR21
Document Number: 002-04582 Rev. *A
Page 53 of 117
MB96380 Series
I/O map MB96(F)38x (Sheet 30 of 30)
Abbreviation
8-bit access
Abbreviation
Access
Address
Register
16-bit access
000883H
CAN1 - Transmission Request 2 Register High
Reserved
TREQR2H1
-
-
-
R
-
000884H-
00088FH
000890H
000891H
000892H
000893H
CAN1 - New Data 1 Register Low
CAN1 - New Data 1 Register High
CAN1 - New Data 2 Register Low
CAN1 - New Data 2 Register High
NEWDT1L1
NEWDT1H1
NEWDT2L1
NEWDT2H1
NEWDT11
R
R
R
R
-
NEWDT21
-
000894H-
00089FH
Reserved
-
-
-
0008A0H
0008A1H
0008A2H
0008A3H
CAN1 - Interrupt Pending 1 Register Low
CAN1 - Interrupt Pending 1 Register High
CAN1 - Interrupt Pending 2 Register Low
CAN1 - Interrupt Pending 2 Register High
INTPND1L1
INTPND1H1
INTPND2L1
INTPND2H1
INTPND11
R
R
R
R
-
INTPND21
-
0008A4H-
0008AFH
Reserved
-
-
-
0008B0H
0008B1H
0008B2H
0008B3H
CAN1 - Message Valid 1 Register Low
CAN1 - Message Valid 1 Register High
CAN1 - Message Valid 2 Register Low
CAN1 - Message Valid 2 Register High
MSGVAL1L1
MSGVAL1H1
MSGVAL2L1
MSGVAL2H1
MSGVAL11
R
R
R
R
-
MSGVAL21
-
0008B4H-
0008CDH
Reserved
-
-
-
-
-
R/W
-
0008CEH
CAN1 - Output enable register
Reserved
COER1
-
0008CFH-
000BFFH
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results
in reading ‘X’.
Registers of resources which are described in this table, but which are not supported by the device, should also be handled
as “Reserved”.
Document Number: 002-04582 Rev. *A
Page 54 of 117
MB96380 Series
13. Interrupt Vector Table
Interrupt vector table MB96(F)38x (Sheet 1 of 3)
Vector
number
Offset in
vector table
Cleared by
DMA
Index in ICR to
program
Vector name
Description
0
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
378H
374H
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
INT9
No
No
-
1
-
2
No
-
3
No
-
4
No
-
5
No
-
6
No
-
7
No
-
8
No
-
9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Delayed Interrupt
RC_TIMER
MC_TIMER
SC_TIMER
RESERVED
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
CAN0
No
RC Timer
No
Main Clock Timer
No
Sub Clock Timer
No
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
CAN Controller 0
CAN1*
No
CAN Controller 1
PPG0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
Document Number: 002-04582 Rev. *A
Page 55 of 117
MB96380 Series
Interrupt vector table MB96(F)38x (Sheet 2 of 3)
Vector
number
Offset in
vector table
Cleared by
DMA
Index in ICR to
program
Vector name
Description
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
370H
36CH
368H
364H
360H
35CH
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
RLT0
RLT1
RLT2
RLT3
PPGRLT
ICU0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Reload Timer 0
Reload Timer 1
Reload Timer 2
Reload Timer 3
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
Input Capture Unit 1
Input Capture Unit 2
Input Capture Unit 3
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
Output Compare Unit 0
Output Compare Unit 1
Output Compare Unit 2
Output Compare Unit 3
Free Running Timer 0
Free Running Timer 1
Real Timer Clock
ICU1
ICU2
ICU3
ICU4
ICU5
ICU6
ICU7
OCU0
OCU1
OCU2
OCU3
FRT0
FRT1
RTC0
CAL0
SG0
No
Clock Calibration Unit
Sound Generator 0
Sound Generator 1
I2C interface
No
SG1
No
IIC0
Yes
Yes
No
ADC0
ALARM0
ALARM1*
LINR0
LINT0
LINR1
LINT1
LINR2
LINT2
LINR4
LINT4
LINR5
LINT5
A/D Converter
Alarm Comparator 0
Alarm Comparator 1
LIN USART 0 RX
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LIN USART 0 TX
LIN USART 1 RX
LIN USART 1 TX
LIN USART 2 RX
LIN USART 2 TX
LIN USART 4 RX
LIN USART 4 TX
LIN USART 5 RX
LIN USART 5 TX
Document Number: 002-04582 Rev. *A
Page 56 of 117
MB96380 Series
Interrupt vector table MB96(F)38x (Sheet 3 of 3)
Vector
number
Offset in
vector table
Cleared by
DMA
Index in ICR to
program
Vector name
Description
Flash memory A (only Flash devic-
es)
72
73
2DCH
2D8H
FLASH_A
No
No
72
73
Flash memory B (only
MB96F388/F389)
FLASH_B
*: ALARM1 and CAN1 are not included on MB96384 and MB96(F)385 devices
Document Number: 002-04582 Rev. *A
Page 57 of 117
MB96380 Series
14. Handling Devices
Special care is required for the following when handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Unused sub clock signal
• Notes on PLL clock mode operation
• Power supply pins (VCC/VSS
)
• Crystal oscillator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on energization
• Stabilization of power supply voltage
• SMC power supply pins
• Serial communication
14.1 Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply
voltage.
14.2 Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device.
They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 k.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or
external pull-up/pull-down resistor as described above.
14.3 External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for
detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 pin must be driven and X1 pin left open.
X0
X1
Document Number: 002-04582 Rev. *A
Page 58 of 117
MB96380 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to
the X0 (X0A) pins.
X0
X1
14.4 Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin
must be left open.
14.5 Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts
to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.
14.6 Power supply pins (V /V
)
SS
CC
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or
VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 F between VCC and VSS as close
as possible to VCC and VSS pins.
14.7 Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest
possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost
effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area
for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially
when using low-Q resonators at higher frequencies.
14.8 Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power
supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage
must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable).
14.9 Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS
.
14.10 Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than
50s from 0.2 V to 2.7 V.
14.11 Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may
occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be
stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10%
of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for
power supply switching.
Document Number: 002-04582 Rev. *A
Page 59 of 117
MB96380 Series
14.12 SMC power supply pins
All DVSS pins must be set to the same level as the VSS pins.
The DVCC power supply level can be set independently of the VCC power supply level. However note that the SMC I/O pin state is
undefined if DVCC is powered on and VCC is below 3V. To avoid this, we recommend to always power VCC before DVCC
.
14.13 Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error
occurs.
Document Number: 002-04582 Rev. *A
Page 60 of 117
MB96380 Series
15. Electrical Characteristics
15.1 Absolute Maximum Ratings
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
VCC
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
Power supply voltage
*1
AVCC
VCC = AVCC
AVCC AVRH, AVCC AVRL, AVRH
AVRL, AVRL AVSS
AVRH,
AVRL
VSS - 0.3 VSS + 6.0
AD Converter voltage references
V
DVCC
V0 to V3
VI
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
SMC Power supply
LCD power supply voltage
Input voltage
V
V
V
See *7
V0 to V3 must not exceed VCC
*2
VI (D)VCC + 0.3V
VO (D)VCC + 0.3V *2
VO
VSS - 0.3 VSS + 6.0
Output voltage
V
Applicable to general purpose
I/O pins *3
ICLAMP
Maximum Clamp Current
-4.0
+4.0
mA
Applicable to general purpose
I/O pins *3
|ICLAMP
IOL1
IOLSMC
IOLAV1
|
Total Maximum Clamp Current
-
-
-
-
-
40
15
40
5
mA
mA
mA
mA
mA
Normal outputs with driving strength
set to 5mA
High current outputs with driving
strength set to 30mA
“L” level maximum output current
Normal outputs with driving strength
set to 5mA
High current outputs with driving
strength set to 30mA
“L” level average output current
IOLAVSMC
30
IOL1
IOLSMC
IOLAV1
-
-
-
-
100
330
50
mA Normal outputs
“L” level maximum overall output current
“L” level average overall output current
mA High current outputs
mA Normal outputs
IOLAVSMC
250
mA High current outputs
Normal outputs with driving strength
IOH1
IOHSMC
IOHAV1
-
-
-
-
-15
-40
-5
mA
set to 5mA
High current outputs with driving
strength set to 30mA
”H” level maximum output current
mA
Normal outputs with driving strength
set to 5mA
mA
High current outputs with driving
strength set to 30mA
”H” level average output current
IOHAVSMC
-30
mA
IOH1
-
-
-
-
-100
-330
-50
mA Normal outputs
”H” level maximum overall output current
”H” level average overall output current
IOHSMC
IOHAV1
IOHASMC
mA High current outputs
mA Normal outputs
-250
mA High current outputs
Document Number: 002-04582 Rev. *A
Page 61 of 117
MB96380 Series
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
TA=105oC
TA=85oC
TA=70oC
295*5
595*5
820*5
-
mW
mW
mW
-
-
Permitted Power dissipation (MB96F385) *4
PD
TA=125oC, no Flash program/erase
370*5
670*5
-
-
mW
mW
*6
TA=105oC, no Flash program/erase
*6
TA=105oC
TA=85oC
TA=70oC
370*5
740*5
-
-
-
mW
mW
mW
1000*5
Permitted Power dissipation
PD
(MB96F386/F387/F388/F389) *4
TA=125oC, no Flash program/erase
*6
460*5
800*5
-
-
mW
mW
TA=105oC, no Flash program/erase
*6
TA=105oC
TA=85oC
310*5
625*5
800*5
390*5
-
-
-
-
-
mW
mW
mW
mW
mW
TA=70oC
Permitted Power dissipation (MB96384/385) *4
PD
TA=125oC *6
TA=105oC*6
MB96V300B
700*5
+70
0
oC
oC
-40
-40
+105
+125
TA
Operating ambient temperature
Storage temperature
*6
TSTG
-55
+150
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog
inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current
to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output
voltages of high current ports depend on DVCC. Input/output voltages of standard ports depend on VCC.
*3: Applicable to all general purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality.
Use within recommended operating conditions.
Use at DC voltage (current)
The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller
pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided
from the pins, so that incomplete operation may result.
Document Number: 002-04582 Rev. *A
Page 62 of 117
MB96380 Series
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage
may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode).
No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins).
Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0V to 16V)
R
*4: The maximum permitted power dissipationdepends onthe ambient temperature, theair flow velocity and the thermal conductance
of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation
mode and clock frequency and the usage of functions like Flash programming or the clock modulator.
IA is the analog current consumption into AVCC
.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Cypress for reliability limitations when using under these conditions.
*7: If DVCC is powered before VCC, then SMC I/O pins state is undefined. To avoid this, we recommend to always power VCC before
DVCC. It is not necessary to set VCC and DVCC to the same value.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04582 Rev. *A
Page 63 of 117
MB96380 Series
15.2 Recommended Operating Conditions
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
Max
VCC, DVCC
CS
Power supply voltage
3.0
5.5
V
Use a low inductance capacitor (for
example X7R ceramic capacitor)
Smoothing capacitor at C pin
3.5
4.7 - 10
15
F
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-04582 Rev. *A
Page 64 of 117
MB96380 Series
15.3 DC characteristics
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
CMOS Hysteresis
0.8/0.2 input
selected
0.8
VCC
(D)VCC
+ 0.3
-
V
0.7
(D)VCC
+ 0.3
(D)VCC 4.5V
-
-
V
V
VCC
CMOS Hysteresis
0.7/0.3 input
selected
Port inputs
Pnn_m
0.74
VCC
(D)VCC
+ 0.3
VIH
(D)VCC < 4.5V
AUTOMOTIVE
Hysteresis input
selected
0.8
(D)VCC
+ 0.3
-
-
-
V
V
V
VCC
(D)VCC
+ 0.3
TTL input selected
2.0
Input H voltage
External clock in
“Fast Clock Input
mode”
0.8
VCC
VCC
0.3
+
Not available in
MB96F386xxA/F387xxA
VIHX0F
X0
VCC
0.3
+
+
+
X0,X1,
External clock in
“oscillation mode”
VIHX0S
VIHR
2.5
-
-
-
V
V
V
X0A,X1A
0.8
VCC
VCC
0.3
RSTX
-
-
CMOS Hysteresis input
VCC
0.3
-
VCC
0.3
VIHM
MD2-MD0
CMOS Hysteresis
0.8/0.2 input
selected
VSS
0.3
-
-
0.2
-
-
V
(D)VCC
CMOS Hysteresis
0.7/0.3 input
selected
VSS
0.3
0.3
(D)VCC
V
V
Port inputs
Pnn_m
VIL
VSS
0.3
-
-
-
0.5
(D)VCC
(D)VCC 4.5V
-
-
-
AUTOMOTIVE
Hysteresis input
selected
VSS
0.3
0.46
(D)VCC
(D)VCC < 4.5V
VSS
0.3
TTL input selected
0.8
V
V
Input L voltage
External clock in
“Fast Clock Input
mode”
VSS
0.3
-
Not available in
MB96F386xxA/F387xxA
VILX0F
0.2 VCC
X0
-
VSS
0.3
-
-
-
X0,X1,
External clock in
“oscillation mode”
VILX0S
VILR
-
-
-
0.4
V
V
V
X0A,X1A
VSS
0.3
0.2 VCC
RSTX
-
-
CMOS Hysteresis input
VSS
0.3
VSS
0.3
+
VILM
MD2-MD0
Document Number: 002-04582 Rev. *A
Page 65 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
4.5V (D)VCC
5.5V
IOH = -2mA
Normal and
High Current
outputs
(D)VCC
- 0.5
VOH2
-
-
V
Driving strength set to 2mA
3.0V (D)VCC
4.5V
IOH = -1.6mA
4.5V (D)VCC
5.5V
IOH = -5mA
Normal and
High Current
outputs
(D)VCC
- 0.5
VOH5
-
-
V
Driving strength set to 5mA
3.0V (D)VCC
4.5V
IOH = -3mA
Output H voltage
4.5V DVCC
5.5V
IOH = -30mA
DVCC
0.5
-
High current
outputs
Driving strength set to
30mA
VOH30
-
-
-
-
V
V
3.0V DVCC
4.5V
IOH = -20mA
4.5V VCC 5.5V
OH = -3mA
I
VCC
0.5
-
VOH3
3mA outputs
3.0V VCC 4.5V
IOH = -2mA
Document Number: 002-04582 Rev. *A
Page 66 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
4.5V (D)VCC
5.5V
IOL = +2mA
Normal and
High Current
outputs
VOL2
-
-
0.4
V
Driving strength set to 2mA
3.0V (D)VCC
4.5V
IOL = +1.6mA
4.5V (D)VCC
5.5V
IOL = +5mA
Normal and
High Current
outputs
VOL5
-
-
-
-
0.4
0.5
V
Driving strength set to 5mA
3.0V (D)VCC
4.5V
Output L voltage
IOL = +3mA
4.5V DVCC
5.5V
IOL = +30mA
High current
outputs
Driving strength set to
30mA
VOL30
V
V
3.0V DVCC
4.5V
IOL = +20mA
3.0V VCC 5.5V
VOL3
3mA outputs
Pnn_m
-
-
-
0.4
+1
I
OL = +3mA
VSS < VI < VCC
IIL
Input leak current
-1
A Single port pin
AVSS, AVRL < VI <
AVCC, AVRH
all
SEG/COM
pins
Total LCD leak cur-
rent
Maximum leakage current
of all LCD pins
|IILCD
RLCD
RUP
|
VCC = 5.0V
VCC = 5.0V
-
0.5
40
10
65
A
k
Between V3
and VSS
Internal LCD divide
resistance
25
VCC 3.3V 10
VCC 5.0V 10
40
25
100
50
160
100
k
k
Pnn_m,
RSTX
Pull-up resistance
Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC.
Document Number: 002-04582 Rev. *A
Page 67 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
35
44
MB96F385/F386/F387at
0 Flash wait states
mA
36
38
39
16
17
44
45
24
25
38
47
46
PLL Run mode with
CLKS1/2 = 48MHz,
MB96F388/F389 at 0
Flash wait states
CLKB = CLKP1/2 = 24MHz
mA
mA
mA
mA
49
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
22
MB96384/385 at 0 ROM
wait states
23.5
57
MB96F386/F387 at 2
Flash wait states
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1= 56MHz,
CLKP2 = 28MHz
60
34
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
MB96384/385 at 2 ROM
wait states
35.5
50
Power supply
current in Run
modes*
ICCPLL
PLL Run mode with
CLKS1/2 = 72MHz,
CLKB = CLKP1 = 36MHz,
CLKP2 = 18MHz
MB96F386/F387 at 1
Flash wait state
mA
+125°C
39
53
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
+25°C
+125°C
+25°C
+125°C
+25°C
43
44
48
49
25
55
57
60
63
35
MB96F385 at 1 Flash
wait state
PLL Run mode with
CLKS1/2 = 80MHz,
CLKB = CLKP1 = 40MHz,
CLKP2 = 20MHz
mA
mA
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
MB96F388/F389 at 1
Flash wait state
PLL Run mode with
CLKS1/2 = 96MHz,
CLKB = CLKP1= 48MHz,
CLKP2 = 24MHz
MB96384/385 at 1 ROM
wait state
mA
+125°C
26
36.5
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
Document Number: 002-04582 Rev. *A
Page 68 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
4.5
5.5
MB96F385 at 1 Flash
wait state
mA
5.1
4.5
7.5
5.5
8.5
6
MB96F386/F387 at 1
Flash wait state
mA
mA
mA
mA
mA
mA
mA
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
+125°C
+25°C
5.1
ICCMAIN
4.8
(CLKPLL,CLKSCandCLKRC
stopped)
MB96F388/F389 at 1
Flash wait state
+125°C
+25°C
5.4
8.5
3.5
5
2.5
MB96384/385 at 1 ROM
wait state
+125°C
+25°C
3.1
2.5
3.6
5.1
4
MB96F385 at 1 Flash
wait state
+125°C
+25°C
3.1
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
2.9
MB96F386/F387/F388/F
389 at 1 Flash wait state
ICCRCH
+125°C
+25°C
3.5
6.5
2.7
4.2
0.6
3.5
0.6
2.9
0.6
2
(CLKMC, CLKPLL and
CLKSC stopped)
1.7
Power supply
current in Run
modes*
MB96384/385 at 1 ROM
wait state
+125°C
+25°C
2.3
0.4
MB96F386/F387 at 1
Flash wait state
+125°C
+25°C
0.9
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
0.4
MB96F388/F389 at 1
Flash wait state
+125°C
+25°C
0.9
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
0.4
MB96384/385/F385 at 1
ROM/Flash wait state
+125°C
+25°C
0.9
ICCRCL
0.15
0.65
0.15
0.65
0.15
0.65
0.25
3.2
0.25
2.6
0.25
1.75
MB96F386/F387 at 1
Flash wait state
mA
mA
mA
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
+125°C
+25°C
MB96F388/F389 at 1
Flash wait state
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode,
no Flash programming/
erasing allowed)
+125°C
+25°C
MB96384/385/F385 at 1
ROM/Flash wait state
+125°C
Document Number: 002-04582 Rev. *A
Page 69 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
0.1
0.2
MB96F386/F387 at 1
Flash wait state
mA
0.6
0.1
0.6
0.1
0.6
3
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
0.2
2.4
0.2
1.7
Power supply
current in Run
modes*
MB96F388/F389 at 1
Flash wait state
ICCSUB
mA
mA
(CLKMC, CLKPLL and
CLKRC stopped, no Flash
programming/erasing
allowed)
+125°C
+25°C
MB96384/385/F385 at 1
ROM/Flash wait state
+125°C
Document Number: 002-04582 Rev. *A
Page 70 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
7.5
9
mA MB96F385
8.2
9
10.5
10.5
13
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385
mA MB96F386/F387
mA MB96384/385
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
9.7
11
13
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
11.7
7
15.5
8.5
10
7.7
14
15.5
18
PLL Sleep mode with
CLKS1/2 = CLKP1= 56MHz,
CLKP2 = 28MHz
14.8
12
Power supply
current in Sleep
modes*
ICCSPLL
13.5
15
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
12.8
10.5
PLL Sleep mode with
CLKS1/2 = 72MHz,
CLKP1 = 36MHz,
CLKP2 = 18MHz
12
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
+125°C
+25°C
11.3
14
14.5
17
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
PLL Sleep mode with
CLKS1/2 = 80MHz,
CLKP1 = 40MHz,
CLKP2 = 20MHz
+125°C
+25°C
14.8
13
19.5
14.5
16
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
PLL Sleep mode with
CLKS1/2 = 96MHz,
CLKP1= 48MHz,
CLKP2 = 24MHz
+125°C
13.8
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
Document Number: 002-04582 Rev. *A
Page 71 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
1.5
1.8
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
2
4.5
2
Main Sleep mode with
1.6
2.1
1.5
2
CLKS1/2 = CLKP1/2 = 4MHz
ICCSMAIN
(CLKPLL,CLKSCandCLKRC
stopped)
+125°C
+25°C
4.2
1.8
3.3
1.4
4
+125°C
+25°C
Power supply
current in Sleep
modes*
0.9
1.5
0.9
1.5
0.9
1.5
+125°C
+25°C
RC Sleep mode with
CLKS1/2 = CLKP1/2 = 2MHz
1.4
3.5
1.4
2.8
ICCSRCH
(CLKMC, CLKPLL and
CLKSC stopped)
+125°C
+25°C
+125°C
Document Number: 002-04582 Rev. *A
Page 72 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
0.3
0.5
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
0.8
0.3
3.4
0.5
2.8
0.5
2
RC Sleep mode with CLKS1/2
= CLKP1/2 = 100kHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
+125°C
+25°C
0.8
0.3
+125°C
+25°C
0.8
ICCSRCL
0.06
0.56
0.06
0.56
0.06
0.56
0.04
0.54
0.04
0.54
0.04
0.54
1.6
0.15
3
+125°C
+25°C
RC Sleep mode with CLKS1/2
= CLKP1/2 = 100kHz,
SMCR:LPMSS = 1
0.15
2.4
0.15
1.6
0.12
2.9
0.12
2.3
0.12
1.55
2
Power supply
current in Sleep
modes*
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode)
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
Sub Sleep mode with
CLKS1/2 = CLKP1/2 = 32kHz
ICCSSUB
(CLKMC, CLKPLL and
CLKRC stopped)
+125°C
+25°C
+125°C
+25°C
+125°C
+25°C
2.1
4.8
2
PLL Timer mode with CLKMC
= 4MHz, CLKPLL = 48MHz
1.6
Power supply
current in Timer
modes*
ICCTPLL
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
+125°C
+25°C
2.1
4.2
2
1.6
+125°C
2.1
3.5
Document Number: 002-04582 Rev. *A
Page 73 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
0.35
0.5
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
MB96384/385/F385
0.85
0.35
0.85
0.35
0.85
0.1
3.3
0.5
2.7
0.5
2
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
(CLKPLL,CLKRCandCLKSC
stopped. Voltage regulator in
high power mode)
+125°C
+25°C
+125°C
+25°C
ICCTMAIN
0.15
2.9
0.15
2.3
0.18
1.6
0.5
3.3
0.5
2.7
0.5
2
+125°C
+25°C
0.6
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 1
0.1
(CLKPLL,CLKRCandCLKSC
stopped. Voltage regulator in
low power mode)
+125°C
+25°C
0.6
0.1
+125°C
+25°C
0.6
Power supply
current in Timer
modes*
0.35
0.85
0.35
0.85
0.35
0.85
0.1
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
+125°C
+25°C
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
+125°C
+25°C
+125°C
+25°C
ICCTRCH
0.15
2.9
0.15
2.3
0.15
1.6
+125°C
+25°C
0.6
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 1
0.1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode)
+125°C
+25°C
0.6
0.1
+125°C
0.6
Document Number: 002-04582 Rev. *A
Page 74 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
0.3
0.45
mA MB96F386/F387
mA MB96F386/F387
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
0.8
0.3
3.2
0.45
2.6
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
+125°C
+25°C
0.8
0.3
0.45
1.95
0.1
+125°C
+25°C
0.8
ICCTRCL
0.05
0.55
0.05
0.55
0.05
0.55
0.03
0.53
0.03
0.53
0.03
0.53
+125°C
+25°C
2.8
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
0.1
Power supply
current in Timer
modes*
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode)
+125°C
+25°C
2.2
0.1
+125°C
+25°C
1.55
0.1
+125°C
+25°C
2.8
Sub Timer mode with
CLKSC = 32kHz
0.1
ICCTSUB
(CLKMC, CLKPLL and
CLKRC stopped)
+125°C
+25°C
2.2
0.1
+125°C
1.55
Document Number: 002-04582 Rev. *A
Page 75 of 117
MB96380 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Condition (at TA)
Parameter
Symbol
Remarks
Typ
Max
Unit
+25°C
+125°C
+25°C
0.02
0.08
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
mA MB96F386/F387
mA MB96F388/F389
mA MB96384/385/F385
0.52
0.02
0.52
0.02
0.52
0.015
0.4
2.8
0.08
2.2
VRCR:LPMB[2:0] = 110B
(Core voltage at 1.8V)
+125°C
+25°C
0.08
1.5
+125°C
+25°C
Power supply
current in Stop Mode
ICCH
0.06
2.3
+125°C
+25°C
0.015
0.4
0.06
1.65
0.06
1.2
VRCR:LPMB[2:0] = 000B
(Core voltage at 1.2V)
+125°C
+25°C
0.015
0.4
+125°C
+25°C
90
140
150
Power supply
current for active
Low Voltage detector
This current must be
A addedtoallPowersupply
currents above
Low voltage detector enabled
(RCR:LVDE = 1)
ICCLVD
+125°C
100
Power supply
Clock modulator enabled
(CMCR:PDX = 1)
Must be added to all
mA
ICCCLOMO
current for active
Clock modulator
-
-
3
4.5
current above
Flash Write/Erase
current
Must be added to all
mA
ICCFLASH
CIN
Current for one Flash module
-
15
15
40
30
current above
Input capacitance
pF High current outputs
Other than C, AVCC
AVSS, AVRH,AVRL, VCC
SS, DVCC, DVSS, High
current outputs
,
,
CIN
Input capacitance
-
-
5
15
pF
V
*: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for
further details about voltage regulator control.
Document Number: 002-04582 Rev. *A
Page 76 of 117
MB96380 Series
15.4 AC Characteristics
Source Clock timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
3
-
16
MHz When using a crystal oscillator, PLL off
When using an opposite phase external clock,
0
-
-
16
16
MHz
fC
Clock frequency
X0, X1
PLL off
When using a crystal oscillator or opposite
phase external clock, PLL on
3.5
MHz
When using a single phase external clock in
MHz “Fast Clock Input mode” (not available in
MB96F386xxA and MB96F387xxA), PLL off
0
-
-
56
56
fFCI
Clock frequency
X0
When using a single phase external clock in
MHz “Fast Clock Input mode” (not available in
MB96F386xxA and MB96F387xxA), PLL on
3.5
32
0
32.768
100
100
50
kHz When using an oscillation circuit
X0A, X1A
fCL
Clock frequency
Clock frequency
-
-
kHz When using an opposite phase external clock
kHz When using a single phase external clock
kHz When using slow frequency of RC oscillator
MHz When using fast frequency of RC oscillator
X0A
-
0
50
1
100
2
200
4
fCR
PLL Clock
frequency
Permitted VCO output frequency of PLL
fCLKVCO
TPSKEW
-
-
64
-
-
-
-
200
5
-
MHz
(CLKVCO)
PLL Phase Jitter
ns For CLKMC (PLL input clock) MHz
Input clock pulse
width
PWH, PWL
X0,X1
8
ns Duty ratio is about 30% to 70%
Input clock pulse
width
PWHL, PWLL
X0A,X1A
5
-
-
s
t
CYL
V
IH
X0
V
IL
P
P
WH
WL
t
CYLL
V
IH
X0A
V
IL
P
P
WH
WL
Document Number: 002-04582 Rev. *A
Page 77 of 117
MB96380 Series
Internal Clock timing
Parameter
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Core Voltage Settings
Symbol
1.8V
1.9V
Unit
Remarks
Min
Max
Min
Max
Internal System clock
frequency (CLKS1 and
CLKS2)
fCLKS1, fCLKS2
0
92
0
96
MHz
Others than below
0
0
72
68
0
0
80
74
MHz
MHz
MB96F385/F388/F389
MB96F386/F387
Internal CPU clock frequency
(CLKB), internal peripheral
clock frequency (CLKP1)
fCLKB, fCLKP1
0
52
0
56
MHz
Others than below
0
0
0
36
28
26
0
0
0
40
32
28
MHz
MHz
MHz
MB96F385/F388/F389
Others than below
MB96F386/F387
Internal peripheral clock
frequency (CLKP2)
fCLKP2
Document Number: 002-04582 Rev. *A
Page 78 of 117
MB96380 Series
External Reset timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
tRSTL
Reset input time
RSTX
500
-
-
ns
tRSTL
RSTX
0.2 VCC
0.2 VCC
Document Number: 002-04582 Rev. *A
Page 79 of 117
MB96380 Series
Power On Reset timing
Parameter
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Symbol
Pin
Unit
Remarks
Min
0.05
1
Typ
Max
30
-
tR
Power on rise time
Power off time
Vcc
Vcc
-
-
ms
ms
tOFF
tR
2.7V
V
CC
0.2 V
0.2 V
0.2 V
tOFF
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
V
CC
Rising edge of 50 mV/ms
maximum is allowed
3 V
Document Number: 002-04582 Rev. *A
Page 80 of 117
MB96380 Series
External Input timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit Used Pin input function
Min
Max
INTn(_R)
NMI(_R)
Pnn_m
External Interrupt
200
—
ns
NMI
General Purpose IO
Reload Timer
TINn(_R)
TTGn(_R)
ADTG(_R)
Input pulse
width
tINH
tINL
—
PPG Trigger input
2*tCLKP1 + 200
(tCLKP1=1/fCLK
—
ns
AD Converter Trigger
)
P1
Free Running Timer
external clock
FRCKn(_R)
INn(_R)
Input Capture
Note : Relocated Resource Inputs have same characteristics
VIH
VIH
External Pin input
VIL
VIL
tINH
tINL
Document Number: 002-04582 Rev. *A
Page 81 of 117
MB96380 Series
Slew Rate High Current Outputs
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
Output driv-
ing strength
set to “30mA”
Output
rise/fall time
tR30
tF30
I/O circuit type M
15
—
ns
Note : Relocated Resource Inputs have same characteristics
Slew rate output timing
VH = VOL30 + 0.9 (VOH30 - VOL30
VL = VOL30 + 0.1 (VOH30 - VOL30
)
VH
VH
)
VL
VL
tF3
tR30
Document Number: 002-04582 Rev. *A
Page 82 of 117
MB96380 Series
External Bus timing
Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described
in the different tables must then be increased by 10ns.
Basic Timing
(TA 40°C to 125°C, VCC 5.0 V 10, VSS 0.0 V, IO
= 5mA, C = 50pF)
L
drive
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
25
Max
—
tCYC
tCHCL
ECLK
ECLK
—
tCYC/2-5
tCYC/2-5
-20
tCYC/2+5
tCYC/2+5
20
ns
tCLCH
tCHCBH
tCHCBL
tCLCBH
tCLCBL
tCHLH
-20
20
ECLK →
CSn, UBX, LBX,
ECLK
—
—
ns
ns
UBX/ LBX / CSn time
-20
20
-20
20
-10
10
tCHLL
-10
10
ECLK → ALE time
ALE, ECLK
tCLLH
-10
10
tCLLL
-10
10
tCHAV
tCLAV
tCHAV
tCLAV
-15
15
ECLK →address valid time
(non-multiplexed)
A[23:0], ECLK
A[23:16], ECLK
EBM:NMS=1
EBM:NMS=0
ns
ns
ns
-15
15
-15
15
-15
15
ECLK →address valid time
(multiplexed)
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
-15
15
AD[15:0], ECLK EBM:NMS=0
-15
15
-10
10
RDX, WRX,
WRLX,WRHX,
ECLK
-10
10
ECLK → RDX /WRX time
—
ns
-10
10
-10
10
Document Number: 002-04582 Rev. *A
Page 83 of 117
MB96380 Series
(TA 40°C to 125°C, VCC 3.0 to 4.5V, VSS 0.0 V, IO
= 5mA, C = 50pF)
L
drive
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
—
tCYC
tCHCL
30
ECLK
ECLK
—
tCYC/2-8
tCYC/2-8
-25
tCYC/2+8
tCYC/2+8
25
ns
tCLCH
tCHCBH
tCHCBL
tCLCBH
tCLCBL
tCHLH
-25
25
ECLK →
CSn, UBX, LBX,
ECLK
—
—
ns
ns
UBX/ LBX / CSn time
-25
25
-25
25
-15
15
tCHLL
-15
15
ECLK → ALE time
ALE, ECLK
tCLLH
-15
15
tCLLL
-15
15
tCHAV
tCLAV
tCHAV
tCLAV
-20
20
ECLK →address valid time
(non-multiplexed)
A[23:0], ECLK EBM:NMS=1
ns
ns
ns
-20
20
-20
20
A[23:16], ECLK
EBM:NMS=0
-20
20
ECLK →address valid time
(multiplexed)
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
-20
20
AD[15:0], ECLK EBM:NMS=0
-20
20
-15
15
RDX, WRX,
-15
15
ECLK → RDX /WRX time
WRLX, WRHX,
ECLK
—
ns
-15
15
-15
15
Document Number: 002-04582 Rev. *A
Page 84 of 117
MB96380 Series
tCYC
tCHCL
tCLCH
0.8*Vcc
ECLK
0.2*Vcc
tCLAV
tCHAV
A[23:0]
tCHCBL
tCLCBL
tCHCBH
tCLCBH
CSn
LBX UBX
tCHRWL
tCLRWL
tCHRWH
tCLRWH
RDX
WRX (WRLX, WRHX)
tCHLL
tCLLL
tCLLH
tCHLH
ALE
tCHADV
tCLADV
Address
AD[15:0]
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04582 Rev. *A
Page 85 of 117
MB96380 Series
Bus Timing (Read)
Parameter
(TA 40°C to 125°C, VCC 5.0 V 10, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Symbol
Pin
Conditions
Unit Remarks
Min
Max
—
EACL:STS=0 and
EACL:ACE=0
t
CYC/2 5
tCYC 5
ALE pulse width
(multiplexed)
tLHLL
ALE
EACL:STS=1
—
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 5
tCYC 15
—
EACL:STS=0 and
EACL:ACE=0
—
—
—
—
—
—
—
—
EACL:STS=1 and
EACL:ACE=0
3tCYC/2 15
2tCYC 15
5tCYC/2 15
tCYC/2 15
tCYC 15
tAVLL
ALE, A[23:16],
ns
EACL:STS=0 and
EACL:ACE=1
EBM:NMS
= 0
EACL:STS=1 and
EACL:ACE=1
Valid address
ALE time
(multiplexed)
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL
ALE,AD[15:0]
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 15
2tCYC 15
EACL:STS=1 and
EACL:ACE=1
ALE
Address valid time
(multiplexed)
EACL:STS=0
EACL:STS=1
t
CYC/2 15
—
—
tLLAX
ALE, AD[15:0]
RDX, A[23:0]
ns
ns
-15
Valid address
RDX time
(non-multiplexed)
tAVRL
EBM:NMS= 1
tCYC/2 15
—
EACL:ACE=0
EBM:NMS=0
3tCYC/2 15
5tCYC/2 15
tCYC 15
—
—
—
—
tAVRL
RDX, A[23:16]
RDX, AD[15:0]
ns
ns
EACL:ACE=1
EBM:NMS=0
Valid address
RDX time
(multiplexed)
EACL:ACE=0
EBM:NMS=0
tADVRL
EACL:ACE=1
EBM:NMS=0
2tCYC 15
Valid address
Valid data input
(non-multiplexed)
A[23:0],
AD[15:0]
w/o cycle
ns
tAVDV
EBM:NMS= 1
—
2tCYC 55
extension
Document Number: 002-04582 Rev. *A
Page 86 of 117
MB96380 Series
(TA 40°C to 125°C, VCC 5.0 V 10, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Conditions
Unit Remarks
Min
Max
EACL:ACE=0
EBM:NMS=0
—
3tCYC 55
A[23:16],
AD[15:0]
w/o cycle
ns
tAVDV
extension
EACL:ACE=1
EBM:NMS=0
—
4tCYC 55
5tCYC/2 55
7tCYC/2 55
—
Valid address
Valid data input
(multiplexed)
EACL:ACE=0
EBM:NMS=0
—
—
w/o cycle
ns
tADVDV
AD[15:0]
RDX
extension
EACL:ACE=1
EBM:NMS=0
w/o cycle
ns
RDX pulse width
tRLRH
—
3 tCYC/2 5
extension
w/o cycle
extension
RDX Valid data input
RDX Data hold time
tRLDV
tRHDX
tAXDX
RDX, AD[15:0]
RDX, AD[15:0]
A[23:0], AD[15:0]
—
—
—
—
0
3 tCYC/2 50 ns
—
—
ns
ns
Address valid Data hold
time
0
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 10
tCYC/2 10
—
—
RDX ALE time
tRHLH
RDX, ALE
ns
other ECL:STS,
EACL:ACE setting
tAVCH
A[23:0], ECLK
tCYC 15
tCYC/2 15
tCYC/2 10
—
Valid address
ECLK time
—
ns
ns
ns
ns
tADVCH AD[15:0], ECLK
—
RDX ECLK time
ALE RDX time
ECLK Valid data input
tRLCH
RDX, ECLK
—
EACL:STS=0
EACL:STS=1
—
—
—
tCYC/2 10
tLLRL
ALE, RDX
10
—
tCHDV
AD[15:0], ECLK
—
tCYC 50
Document Number: 002-04582 Rev. *A
Page 87 of 117
MB96380 Series
(TA 40°C to 125°C, VCC 3.0 to 4.5V, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Parameter
Pin
Conditions
Unit Remarks
Min
Max
—
EACL:STS=0 and
EACL:ACE=0
tCYC/2 8
tCYC 8
ALE pulse width
(multiplexed)
tLHLL ALE
EACL:STS=1
—
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 8
—
EACL:STS=0 and
EACL:ACE=0
tCYC 20
3tCYC/2 20
2tCYC 20
5tCYC/2 20
tCYC/2 20
tCYC 20
—
—
—
—
—
—
—
—
EACL:STS=1 and
EACL:ACE=0
tAVLL ALE, A[23:16],
ns
EACL:STS=0 and
EACL:ACE=1
EBM:NMS
= 0
EACL:STS=1 and
EACL:ACE=1
Valid address
ALE time
(multiplexed)
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL ALE, AD[15:0]
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 20
2tCYC 20
EACL:STS=1 and
EACL:ACE=1
ALE
Address valid time
(multiplexed)
EACL:STS=0
EACL:STS=1
tCYC/2 20
—
—
tLLAX ALE, AD[15:0]
tAVRL RDX, A[23:0]
ns
ns
-20
Valid address
RDX time
(non-multiplexed)
EBM:NMS= 1
tCYC/2 20
—
EACL:ACE=0
EBM:NMS=0
3tCYC/2 20
5tCYC/2 20
tCYC 20
—
—
—
—
tAVRL RDX, A[23:16]
ns
ns
EACL:ACE=1
EBM:NMS=0
Valid address
RDX time
(multiplexed)
EACL:ACE=0
EBM:NMS=0
tADVRL RDX, AD[15:0]
EACL:ACE=1
EBM:NMS=0
2tCYC 20
Valid address
Valid data input
(non-multiplexed)
A[23:0],
tAVDV
w/o cycle
ns
EBM:NMS= 1
—
2tCYC 60
AD[15:0]
extension
Document Number: 002-04582 Rev. *A
Page 88 of 117
MB96380 Series
(TA 40°C to 125°C, VCC 3.0 to 4.5V, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Parameter
Pin
Conditions
Unit Remarks
Min
Max
EACL:ACE=0
EBM:NMS=0
—
3tCYC 60
A[23:16],
AD[15:0]
w/o cycle
ns
tAVDV
extension
EACL:ACE=1
EBM:NMS=0
—
4tCYC 60
5tCYC/2 60
7tCYC/2 60
—
Valid address
Valid data input
(multiplexed)
EACL:ACE=0
EBM:NMS=0
—
tAD-
w/o cycle
ns
AD[15:0]
extension
VDV
EACL:ACE=1
EBM:NMS=0
—
3tCYC/2 8
—
w/o cycle
ns
RDX pulse width
tRLRH RDX
—
—
extension
w/o cycle
extension
RDX Valid data input
RDX Data hold time
tRLDV RDX, AD[15:0]
tRHDX RDX, AD[15:0]
3tCYC/2 55 ns
—
—
0
0
—
—
ns
ns
Address valid Data hold time tAXDX A[23:0]
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 15
—
RDX ALE time
tRHLH RDX, ALE
ns
ns
other ECL:STS,
EACL:ACE setting
tCYC/2 15
tCYC 20
—
—
—
tAVCH A[23:0], ECLK
Valid address
ECLK time
—
tAD-
AD[15:0], ECLK
tCYC/2 20
VCH
RDX ECLK time
ALE RDX time
ECLK Valid data input
tRLCH RDX, ECLK
—
EACL:STS=0
EACL:STS=1
—
tCYC/2 15
—
—
ns
ns
ns
tCYC/2 15
tLLRL ALE, RDX
15
—
tCHDV AD[15:0], ECLK
—
tCYC 55
Document Number: 002-04582 Rev. *A
Page 89 of 117
MB96380 Series
.
tAVCH
tCHDV
tRLCH
tADVCH
0.8*Vcc
ECLK
tAVLL
tLLAX
tADVLL
tRHLH
ALE
0.2*VC
tLHLL
tAVRL
tADVRL
tRLRH
RDX
tLLRL
A[23:0]
tRLDV
tAXD
tAVDV
tRHDX
tADVDV
VIH
VIL
VIH
VIL
AD[15:0]
Address
Read data
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04582 Rev. *A
Page 90 of 117
MB96380 Series
Bus Timing (Write)
Parameter
(TA 40°C to 125°C, VCC 5.0 V 10, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Symbol
Pin
Condition
Unit
Remarks
Min
Max
EACL:STS=0
EBM:NMS=1
tCYC/2 15
—
Valid address
WRX time
(non-multiplexed)
WRX, WRLX,
tAVWL WRHX,
A[23:0]
ns
EACL:STS=1
EBM:NMS=1
tCYC 15
3tCYC/2 15
5tCYC/2 15
tCYC 15
—
—
—
EACL:ACE=0
EBM:NMS=0
WRX, WRLX,
WRHX, A[23:16]
tAVWL
ns
ns
EACL:ACE=1
EBM:NMS=0
Valid address
WRX time
(multiplexed)
EACL:ACE=0
EBM:NMS=0
—
—
—
—
—
WRX, WRLX,
WRHX, AD[15:0]
tADVWL
EACL:ACE=1
EBM:NMS=0
2tCYC 15
tCYC 5
WRX, WRXL,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
tDVWH
tWHDX
—
—
—
ns
ns
ns
Valid data output
WRX time
WRX, WRLX,
WRHX, AD[15:0]
w/o cycle
extension
tCYC 20
WRX
Data hold time
WRX, WRLX,
WRHX, AD[15:0]
t
CYC/2 15
15
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
—
—
ns
ns
WRX
Address valid time
(non-multiplexed)
WRX, WRLX,
WRHX, A[23:0]
tWHAX
tCYC/2 15
tCYC/2 15
WRX
Address valid time
(multiplexed)
WRX, WRLX,
WRHX, A[23:16]
tWHAX
EBM:NMS=0
—
ns
ns
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
2tCYC 10
tCYC 10
—
—
WRX ALE time
(multiplexed)
WRX, WRLX,
WRHX, ALE
tWHLH
EBM:NMS=0
EACL:STS setting
WRX, WRLX,
WRHX, ECLK
WRX ECLK time
tWLCH
—
tCYC/2 10
—
ns
ns
EACL:STS=0
EBM:NMS=1
—
—
—
—
tCYC/2 15
tCYC 15
CSn WRX time
(non-multiplexed)
WRX, WRLX,
WRHX, CSn
tCSLWL
EACL:STS=1
EBM:NMS=1
EACL:ACE=0
EBM:NMS=0
3tCYC/2 15
5tCYC/2 15
CSn WRX time
(multiplexed)
WRX, WRLX,
WRHX, CSn
tCSLWL
ns
EACL:ACE=1
EBM:NMS=0
Document Number: 002-04582 Rev. *A
Page 91 of 117
MB96380 Series
(TA 40°C to 125°C, VCC 5.0 V 10, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
15
—
ns
ns
WRX CSn time
(non-multiplexed)
WRX, WRLX,
WRHX, CSn
tWHCSH
tCYC/2 15
—
—
WRX CSn time
(multiplexed)
WRX, WRLX,
WRHX, CSn
tWHCSH
EBM:NMS=0
t
CYC/2 15
ns
(TA 40°C to 125°C, VCC 3.0 to 4.5V, VSS 0.0 V, IO
= 5mA, C = 50pF)
L
drive
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
EACL:STS=0
EBM:NMS=1
tCYC/2 20
—
Valid address
WRX time
(non-multiplexed)
WRX, WRLX,
tAVWL WRHX,
A[23:0]
ns
EACL:STS=1
EBM:NMS=1
tCYC 20
3tCYC/2 20
5tCYC/2 20
tCYC 20
—
—
—
—
—
—
—
—
EACL:ACE=0
EBM:NMS=0
WRX, WRLX,
WRHX, A[23:16]
tAVWL
ns
ns
EACL:ACE=1
EBM:NMS=0
Valid address
WRX time
(multiplexed)
EACL:ACE=0
EBM:NMS=0
WRX, WRLX,
WRHX, AD[15:0]
tADVWL
EACL:ACE=1
EBM:NMS=0
2tCYC 20
tCYC 8
WRX, WRXL,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
tDVWH
tWHDX
—
—
—
ns
ns
ns
Valid data output
WRX time
WRX, WRLX,
WRHX, AD[15:0]
w/o cycle
extension
tCYC 25
WRX
Data hold time
WRX, WRLX,
WRHX, AD[15:0]
t
CYC/2 20
20
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
—
—
ns
ns
WRX
Address valid time
(non-multiplexed)
WRX, WRLX,
WRHX, A[23:0]
tWHAX
tCYC/2 20
tCYC/2 20
WRX
Address valid time
(multiplexed)
WRX, WRLX,
WRHX, A[23:16]
tWHAX
EBM:NMS=0
—
ns
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
2tCYC 15
tCYC 15
—
—
WRX ALE time
(multiplexed)
WRX, WRLX,
WRHX, ALE
tWHLH
ns
ns
EBM:NMS=0
EACL:STS setting
WRX, WRLX,
WRHX, ECLK
WRX ECLK time
tWLCH
—
t
CYC/2 15
—
Document Number: 002-04582 Rev. *A
Page 92 of 117
MB96380 Series
(TA 40°C to 125°C, VCC 3.0 to 4.5V, VSS 0.0 V, IO
= 5mA, C = 50pF)
L
drive
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
EACL:STS=0
EBM:NMS=1
—
tCYC/2 20
tCYC 20
CSn WRX time
(non-multiplexed)
WRX, WRLX,
WRHX, CSn
tCSLWL
ns
EACL:STS=1
EBM:NMS=1
—
—
—
EACL:ACE=0
EBM:NMS=0
3tCYC/2 20
5tCYC/2 20
CSn WRX time
(multiplexed)
WRX, WRLX,
WRHX, CSn
tCSLWL
ns
EACL:ACE=1
EBM:NMS=0
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
20
—
—
ns
ns
WRX CSn time
(non-multiplexed)
WRX, WRLX,
WRHX, CSn
tWHCSH
tCYC/2 20
WRX CSn time
(multiplexed)
WRX, WRLX,
WRHX, CSn
tWHCSH
EBM:NMS=0
t
CYC/2 20
—
ns
tWLCH
0.8*VC
ECLK
ALE
tWHLH
.
tAVWL
tWLWH
tADVWL
WRX (WRLX, WRHX)
0.2*VCC
tCSLWL
tWHCSH
CSn
tWHAX
A[23:0]
tDVWH
tWHDX
AD[15:0]
Address
Write data
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04582 Rev. *A
Page 93 of 117
MB96380 Series
Ready Input Timing
Parameter
(TA 40°C to 125°C, VCC 5.0 V 10, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Rated Value
Test
Symbol
Pin
Units
Remarks
Condition
Min
35
0
Max
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
—
ns
ns
—
—
(TA 40°C to 125°C, VCC 3.0 to 4.5V, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Rated Value
Test
Parameter
Symbol
Pin
Units
Remarks
Condition
Min
45
0
Max
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
—
ns
ns
—
—
Note : If the RDY setup time is insufficient, use the auto-ready function.
0.8*VC
ECLK
tRYHS
VIH
tRYHH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04582 Rev. *A
Page 94 of 117
MB96380 Series
Hold Timing
(TA 40°C to 125°C, VCC 5.0 V 10, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min
Max
Pin floating HAKX time
HAKX time Pin valid time
tXHAL
tHAHV
HAKX
HAKX
tCYC 20 tCYC + 20
tCYC 20 tCYC + 20
ns
ns
—
(TA 40°C to 125°C, VCC 3.0 to 4.5V, VSS 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min
Max
Pin floating HAKX time
HAKX time Pin valid time
tXHAL
tHAHV
HAKX
HAKX
tCYC 25 tCYC + 25
tCYC 25 tCYC + 25
ns
ns
—
0.8*VCC
HAKX
0.2*VCC
tHAHV
tXHAL
High-Z
0.8*VCC
0.2*VCC
Each pin
Refer to the Hardware Manual for detailed Timing Charts
Document Number: 002-04582 Rev. *A
Page 95 of 117
MB96380 Series
USART timing
WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing
described in the different tables must then be increased by 10ns.
(TA = -40°C to 125°C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
VCC = AVCC= 4.5V VCC = AVCC= 3.0V to
to 5.5V
4.5V
Parameter
Symbol
Pin
Condition
Unit
Min
4 tCLKP1
Max
Min
4 tCLKP1
Max
Serial clock cycle time
tSCYCI
tSLOVI
tOVSHI
tIVSHI
SCKn
—
—
ns
ns
SCKn,
SOTn
SCK ↓ → SOT delay time
-20
20
—
-30
30
—
SCKn,
SOTn
N*tCLKP1
- 20 *1
N*tCLKP1
30 *1
-
SOT → SCK ↑ delay time
Valid SIN → SCK ↑
Internal Shift
Clock Mode
ns
ns
ns
ns
ns
ns
ns
ns
SCKn,
SINn
tCLKP1
45
+
tCLKP1
55
+
—
—
SCK ↑ → Valid SIN hold
time
SCKn,
SINn
tSHIXI
0
—
0
—
tCLKP1
10
+
+
tCLKP1
10
+
+
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLSHE
tSHSLE
tSLOVE
tIVSHE
tSHIXE
SCKn
SCKn
—
—
tCLKP1
10
tCLKP1
10
—
—
SCKn,
SOTn
2 tCLKP1
+ 45
2 tCLKP1
+ 55
—
—
External Shift
Clock Mode
SCKn,
SINn
tCLKP1/2
+ 10
tCLKP1/2 +
10
—
—
—
—
SCK ↑ → Valid SIN hold
time
SCKn,
SINn
tCLKP1
10
+
tCLKP1
10
+
SCK fall time
SCK rise time
tFE
tRE
SCKn
SCKn
—
—
20
20
—
—
20
20
ns
ns
Notes: • AC characteristic in CLK synchronized mode.
•
CL is the load capacity value of pins when testing.
•
Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters.
These parameters are shown in “MB96300 Super series Hardware Manual”
•
tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
2
4*tCLKP1
5*tCLKP1, 6*tCLKP1
7*tCLKP1, 8*tCLKP1
...
3
4
...
Document Number: 002-04582 Rev. *A
Page 96 of 117
MB96380 Series
tSCYCI
0.8*VCC
SCK for
ESCR:SCES = 0
0.2*VCC
0.2*VCC
SCK for
0.8*VCC
0.8*VCC
ESCR:SCES = 1
0.2*VCC
tOVSHI
tSLOVI
0.8*VCC
0.2*VCC
tIVSHI
SOT
SIN
tSHIXI
VIH
VIL
VIH
VIL
Internal Shift Clock Mode
tSLSHE
tSHSLE
SCK for
V
VIH
VIH
IH
VIL
ESCR:SCES = 0
VIL
SCK for
VIH
VIH
ESCR:SCES = 1
VIL
VIL
VIL
tFE
tSLOVE
tRE
0.8*VCC
0.2*VCC
SOT
SIN
tSHIXE
tIVSHE
VIH
VIL
VIH
VIL
External Shift Clock Mode
Document Number: 002-04582 Rev. *A
Page 97 of 117
MB96380 Series
2
I C Timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Fast-mode*4
Standard-mode
Parameter
Symbol
Condition
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA↓→SCL↓
tHDSTA
4.0
—
0.6
—
s
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
—
—
1.3
0.6
—
—
s
s
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
—
3.45*2
—
0.6
0
—
0.9*3
—
s
s
ns
s
s
R 1.7 k,
C 50 pF*1
Data hold time
SCL↓→SDA↓↑
Data set-up time
SDA↓↑→SCL↑
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL↑→SDA↑
—
—
Bus free time between a STOP and START
condition
—
—
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then
be met.
*4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
SDA
t
BUS
tSUDAT
t
HDSTA
tLOW
SCL
tHIGH
t
HDSTA
t
HDDAT
t
SUSTA
tSUSTO
Document Number: 002-04582 Rev. *A
Page 98 of 117
MB96380 Series
15.5 Analog Digital Converter
(TA = -40 °C to +125 °C, 3.0 V AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min
-
Typ
Max
10
-
-
-
-
-
-
-
-
-
-
-
-
bit
Total error
-3
+3
LSB
LSB
LSB
Nonlinearity error
Differential nonlinearity error
-2.5
-1.9
+2.5
+1.9
AVRL-
AVRL+
AVRL+
VOT
Zero reading voltage
ANn
ANn
V
V
1.5 LSB
0.5 LSB
2.5 LSB
Full scale reading
voltage
AVRH-
3.5 LSB
AVRH-
1.5 LSB
AVRH+
0.5 LSB
VFST
4.5V VCC 5.5V
3.0V VCC 4.5V
4.5V VCC 5.5V
3.0V VCC 4.5V
1.0
2.0
0.5
1.2
-
-
-
-
16,500
s
s
s
s
Compare time
-
-
-
-
-
Sampling time
-
-
AVSS, AVRL < VI < AVCC
AVRH
,
,
,
IAIN
Analog port input current
ANn
-3
-1
-
-
+3
+1
A
TA = 25 C,
A AVSS, AVRL < VI < AVCC
AVRH
Analog input leakage current
(during conversion)
IAIN
ANn
ANn
TA = 125 C,
A AVSS, AVRL < VI < AVCC
AVRH
-3
-
+3
VAIN
AVRH
AVRL
IA
Analog input voltage range
Reference voltage range
AVRL
-
-
AVRH
AVcc
V
AVRH/AVRH2 0.75 AVcc
V
AVSS
-
0.25 AVCC
AVRL
AVcc
-
V
2.5
5
5
1
5
mA A/D Converter active
Power supply current
A/D Converter not
operated
IAH
IR
AVcc
-
-
-
-
0.7
-
A
AVRH/AVRL
AVRH/AVRL
mA A/D Converter active
Reference voltage current
A/D Converter not
operated
IRH
A
Offset between input
channels
-
ANn
-
-
4
LSB
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Document Number: 002-04582 Rev. *A
Page 99 of 117
MB96380 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition
error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”) and full-scale transition
line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
1.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
V
NT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
V
NT {1 LSB × (N 1) 0.5 LSB}
[LSB]
Total error of digital output “N”
1 LSB
AVRH AVRL
1 LSB (Ideal value)
[V]
1024
N: A/D converter digital output value
V
V
V
(Ideal value) AVRL 0.5 LSB [V]
(Ideal value) AVRH 1.5 LSB [V]
: A voltage at which digital output transitions from (N 1) to N.
OT
FST
NT
Document Number: 002-04582 Rev. *A
Page 100 of 117
MB96380 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
3FE
3FD
Actual conversion
characteristics
N + 1
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004
003
002
001
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
V
NT {1 LSB × (N 1) V
}
OT
[LSB]
Nonlinearity error of digital output N
1 LSB
V ( ) V
N+1
T
NT
1 LSB [LSB]
[V]
Differential nonlinearity error of digital output N
1 LSB
1 LSB
V
FST V
OT
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Notes on A/D Converter Section
• ² About the external impedance of the analog input and the sampling time of the A/D converter (with sample and hold circuit):
If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and
hold capacitor is insufficient, adversely affecting A/D conversion precision.
analog input circuit model:
R
Comparator
Analog input
C
Sampling switch
Reference value:
• C = 8.5 pF (Max)
Document Number: 002-04582 Rev. *A
Page 101 of 117
MB96380 Series
To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum sampling time must
be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be
decreased so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7where= RC. If the
external input resistance (Rext) connected to the analog input is included, the sampling time is expressed as follows:
T
samp [min] = 7 × (Rext + 2.6k) × C for 4.5 AVcc 5.5
Tsamp [min] = 7 × (Rext + 12.1k) × C for 3.0 AVcc 4.5
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.
• ² About the error
The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Document Number: 002-04582 Rev. *A
Page 102 of 117
MB96380 Series
15.6 Alarm Comparator
Parameter
(TA = -40 °C to +125 °C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
Symbol
Pin
Unit
Remarks
Min
Typ
Max
Alarm comparator
enabled in fast mode
(one channel)
IA5ALMF
-
25
45
A
Alarm comparator
AVCC
Power supply current
IA5ALMS
IA5ALMH
IALIN
-
-
7
-
13
5
A enabled in slow mode
(one channel)
Alarm comparator
A
disabled
TA = 25 °C
-1
-3
-
-
+1
+3
A
A
ALARM pin input current
TA = 125 °C
ALARM pin input voltage
range
VALIN
AVCC
0
-
V
V
V
V
0.36 * AVCC 0.36 * AVCC
External low threshold
high->low transition
VEVTL(H->L)
VEVTL(L->H)
VEVTH(H->L)
-
-0.25
-0.1
0.36 * AVCC 0.36 * AVCC
External low threshold
low->high transition
-
+0.1
+0.25
-
INTREF = 0
0.78 * AVCC 0.78 * AVCC
External high threshold
high->low transition
-0.25
-0.1
0.78 * AVCC 0.78 * AVCC
External high threshold
low->high transition
VEVTH(L->H)
VIVTL(H->L)
VIVTL(L->H)
VIVTH(H->L)
VIVTH(L->H)
V
V
V
V
V
+0.1
+0.25
Internal low threshold
high->low transition
0.9
-
1.1
-
ALARM0,
ALARM1
Internal low threshold
low->high transition
1.3
2.4
2.6
1.55
-
INTREF = 1
Internal high threshold
high->low transition
2.2
-
Internal high threshold
low->high transition
2.85
VHYS
Switching hysteresis
50
-
-
0.1
1
300
1
mV
s
tCOMPF
tCOMPS
CMD = 1 (fast)
CMD = 0 (slow)
Comparison time
-
10
s
Power-up stabilization time
after enabling alarm
comparator
Threshold levels
specifiedabovearenot
guaranteed within this
time
tPD
-
-
1
5
ms
Slow/Fast mode transition
time
tCMD
100
500
s
Document Number: 002-04582 Rev. *A
Page 103 of 117
MB96380 Series
Comparator
Output
H
L
VALIN
VxVTx(H->L)
VHYS
VxVTx(L->H)
Document Number: 002-04582 Rev. *A
Page 104 of 117
MB96380 Series
15.7 Low Voltage Detector characteristics
(TA = -40 °C to +125 °C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Value
Parameter
Symbol
Unit
Remarks
Min
-
Max
75
TLVDSTAB
VDL0
Stabilization time
Level 0
s
V
V
V
V
V
V
V
V
V
V
After power-up or change of detection level
CILCR:LVL[3:0]=”0000”
CILCR:LVL[3:0]=”0001”
CILCR:LVL[3:0]=”0010”
CILCR:LVL[3:0]=”0011”
CILCR:LVL[3:0]=”0100”
CILCR:LVL[3:0]=”0101”
CILCR:LVL[3:0]=”0110”
CILCR:LVL[3:0]=”0111”
CILCR:LVL[3:0]=”1000”
CILCR:LVL[3:0]=”1001”
2.7
2.9
3.1
3.5
3.6
3.7
3.8
3.9
4.0
4.1
2.9
VDL1
Level 1
3.1
VDL2
Level 2
3.3
VDL3
Level 3
3.75
3.85
3.95
4.05
4.15
4.25
4.35
VDL4
Level 4
VDL5
Level 5
VDL6
Level 6
VDL7
Level 7
VDL8
Level 8
VDL9
Level 9
VDL10
VDL11
VDL12
VDL13
VDL14
VDL15
Level 10
Level 11
Level 12
Level 13
Level 14
Level 15
not used
not used
not used
not used
not used
not used
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
Levels 10 to 15 are not used in this device.
dV
dt
V
μs
≤0.004
For correct detection, the slope of the voltage level must satisfy
.
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7V. The electrical
characteristics however are only valid in the specified range (usually down to 3.0V).
Document Number: 002-04582 Rev. *A
Page 105 of 117
MB96380 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup
behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
VDLx, Max
VDLx, Min
dV
dt
Time [s]
Power Reset Extension Time
Low Voltage Reset Assertion
Normal Operation
Document Number: 002-04582 Rev. *A
Page 106 of 117
MB96380 Series
15.8 FLASH memory program/erase characteristics
(TA = -40°C to 105°C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Unit
s
Remarks
Min
Typ
Max
Without erasure pre-programming
time
Sector erase time
-
0.9
3.6
Without erasure pre-programming
time (n is the number of Flash sector
of the device)
Chip erase time
-
-
n*0.9
23
n*3.6
370
s
Without overhead time for submitting
write command
Word (16-bit width) programming time
us
Program/Erase cycle
10 000
20
-
-
-
-
cycle
year
Flash data retention time
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high
temperature measurements into normalized value at 85oC)
Document Number: 002-04582 Rev. *A
Page 107 of 117
MB96380 Series
16. Example Characteristics
The diagrams below show the characteristics of one measured sample with typical process parameters.
Run Mode
100.00
PLL clock (56 MHz)
10.00
Main osc. (4 MHz)
RC clock (2 MHz)
1.00
RC clock (100 kHz)
0.10
Sub osc.(32 kHz)
0.01
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
Sleep mode
100.00
PLL clock (56 MHz)
10.00
1.00
0.10
0.01
Main osc. (4 MHz)
RC clock (2 MHz)
RC clock (100 kHz)
Sub osc.(32 kHz)
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
Document Number: 002-04582 Rev. *A
Page 108 of 117
MB96380 Series
Timer mode
10.00
1.00
0.10
0.01
PLL clock (56 MHz)
Main osc. (4 MHz)
RC clock (2 MHz)
RC clock (100 kHz)
Sub osc. (32 kHz)
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
Stop mode
1.00
0.10
0.01
0.00
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
Document Number: 002-04582 Rev. *A
Page 109 of 117
MB96380 Series
Used settings
Selected Source
Clock
Mode
Clock/Regulator Settings
CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz
CLKP2 = 28 MHz
Regulator in High Power Mode
Core Voltage = 1.9 V
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz
Regulator in High Power Mode
Main osc.
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz
Regulator in High Power Mode
Core Voltage = 1.8 V
Run mode
RC clock fast
RC clock slow
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz
Regulator in Low Power Mode A
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKP1 = 56 MHz
CLKP2 = 28 MHz
PLL
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.9 V
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
Main osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
Sleep mode
RC clock fast
RC clock slow
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz
(CLKB is stopped in this mode)
Regulator in Low Power Mode A
Core Voltage = 1.8 V
Document Number: 002-04582 Rev. *A
Page 110 of 117
MB96380 Series
Used settings
Selected Source
Clock
Mode
Clock/Regulator Settings
CLKMC = 4 MHz, CLKPLL = 56 MHz
PLL
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.9 V
CLKMC = 4 MHz
Main osc.
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
CLKRC = 2 MHz
Timer mode
RC clock fast
RC clock slow
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
CLKRC = 100 kHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
CLKSC = 100 kHz
Sub osc.
stopped
(System clocks are stopped in this mode)
Regulator in Low Power Mode A, Core Voltage = 1.8 V
(All clocks are stopped in this mode)
Regulator in Low Power Mode B, Core Voltage = 1.8 V
Stop mode
Document Number: 002-04582 Rev. *A
Page 111 of 117
MB96380 Series
17. Package Dimension MB96(F)38x LQFP 120P
120-pin plastic LQFP
Lead pitch
0.50 mm
16.0 × 16.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.88 g
Code
(Reference)
(FPT-120P-M21)
P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 0.20(.709 .008)SQ
+0.40
16.00 –0.10 .630 –+..000146 SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 –+..000048
INDEX
0~8
˚
"A"
120
31
0.10 0.05
(.004 .002)
(Stand off)
1
30
LEAD No.
0.145 +–00..0035
0.60 0.15
(.024 .006)
0.22 0.05
(.009 .002)
M
0.50(.020)
0.08(.003)
.006 –+..000012
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
2002 FUJITSU LIMITED F120033S-c-4-4
Document Number: 002-04582 Rev. *A
Page 112 of 117
MB96380 Series
18. Ordering Information
Persistent
Low Voltage
Reset
Part number
Flash/ROM
Subclock
No
Package
MB96384YSB PMC-GSE2 *1
MB96384RSB PMC-GSE2 *1
MB96384YWB PMC-GSE2 *1
MB96384RWB PMC-GSE2 *1
MB96385YSB PMC-GSE2 *1
MB96385RSB PMC-GSE2 *1
MB96385YWB PMC-GSE2 *1
MB96385RWB PMC-GSE2 *1
MB96F385YSA PMC-GSE2 *1
MB96F385RSA PMC-GSE2 *1
MB96F385YWA PMC-GSE2 *1
MB96F385RWA PMC-GSE2 *1
MB96F386YSB PMC-GSE2
MB96F386RSB PMC-GSE2
MB96F386YWB PMC-GSE2
MB96F386RWB PMC-GSE2
MB96F387YSB PMC-GSE2
MB96F387RSB PMC-GSE2
MB96F387YWB PMC-GSE2
MB96F387RWB PMC-GSE2
MB96F388TSA PMC-GSE2 *1
MB96F388HSA PMC-GSE2 *1
MB96F388TWA PMC-GSE2 *1
MB96F388HWA PMC-GSE2 *1
MB96F389YSA PMC-GSE2 *1
MB96F389RSA PMC-GSE2 *1
MB96F389YWA PMC-GSE2 *1
MB96F389RWA PMC-GSE2 *1
Yes
No
120 pin Plastic LQFP
(FPT-120P-M21)
ROM (128KB)
Yes
No
Yes
No
Yes
No
120 pin Plastic LQFP
(FPT-120P-M21)
ROM (160KB)
Flash A (160KB)
Flash A (288KB)
Flash A (416KB)
Yes
No
Yes
No
Yes
No
120 pin Plastic LQFP
(FPT-120P-M21)
Yes
No
Yes
No
Yes
No
120 pin Plastic LQFP
(FPT-120P-M21)
Yes
No
Yes
No
Yes
No
120 pin Plastic LQFP
(FPT-120P-M21)
Yes
No
Yes
No
Yes
No
Flash A (544KB)
Flash B (32KB)
120 pin Plastic LQFP
(FPT-120P-M21)
Yes
No
Yes
No
Yes
No
Flash A (544KB)
Flash B (288kB)
120 pin Plastic LQFP
(FPT-120P-M21)
Yes
No
Yes
Yes
MB96V300BRB-ES
(for evaluation)
416 pin Plastic BGA
(BGA-416P-M02)
Emulated by ext. RAM
No
*1: These devices are under development and specification is preliminary. These products under development may change its
specification without notice.
This datasheet is also valid for the following outdated devices:
MB96F386YSA, MB96F386RSA, MB96F386YWA, MB96F386RWA,
MB96F387YSA, MB96F387RSA, MB96F387YWA, MB96F387RWA
Document Number: 002-04582 Rev. *A
Page 113 of 117
MB96380 Series
19. Revision History
Spansion Publication Number: DS07-13803-2E
Revision
Date
Modification
Prelim 1
Prelim 2
Prelim 3
2007-05-2
2007-05-24
2007-08-09
Creation
Electrical characteristics and memory description updates
Typo errors corrections, Flash memory programming interface update
Update of DC characteristics. new MB96F388 and MB96F389 added. LVD chapter added as
well as an example characteristics chapter
Prelim 4
Prelim 5
2007-08-31
2007-09-06
Updates of the DC characteristics, interrupt vector table update, update of the LVD
characteristics
Memory map for external bus modified. Modifications of the drawing of the pin circuits. Electrical
characteristics updates. Rephrasing and typos corrections. Add Slew rate high current outputs
chapter.
Modification of the block diagram.
Memory map modified for Flash. RAM memory map added.
Pin circuit type corrected. Type L IO is now included.
Prelim 6
Prelim 7
2007-11-14
2007-12-12
Memory IO map modified
New Flash/ROM configuration presentation
Ordering information: MB96300B used as reference.
Block diagram modified to included relocated pins.
Main Flash becomes Flash memory A and Satellite flash becomes Flash memory B
• Devices under development added: MB96384/385/F385/F388/F389
• Block diagram corrected (existing resource pins)
• Pin assignment: TTG8 -> TTG7
• Pin function table corrected
• I/O circuit type diagrams corrected
• Memory map cleaned up
• "Flash sector configuration" replaced by corrected "User ROM Memory map for Flash devices",
“ROM configuration” replaced by “User ROM Memory map for Mask ROM devices”
• IO map table regenerated:
- Port register: Naming style corrected
- Memory control registers renamed (Main/Sat -> A/B)
- addresses after 000BFFh removed
Prelim 8
2008-02-04
• Absolute maximum ratings: Pd and Ta specified more precisely
• Run and Sleep mode currents: more conditions added (1WS settings)
• Run mode current spec in 48/24MHz mode corrected
• Maximum CLKP2 frequency for MB96F386/F387 corrected
• High current port input capacitance added
• External bus timings: missing conditions added and readability improved
• Alarm comparator spec updated (transition voltages defined)
• MB96V300A removed
• Ordering information updated
• Typos and formatting corrected
Document Number: 002-04582 Rev. *A
Page 114 of 117
MB96380 Series
Revision
Date
Modification
• Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly style changes
and official notes and disclaimer added)
• Numbering of Electrical Characteristics subchapters automated
• Note about devices under development modified
• I/O map: Note added about reserved addresses
• Serial programming interface: Note about handshaking pins improved
• ICCPLL for CLKS1/2=80MHz, CLKB=40MHz (F388/F389) increased by 5mA
• ICCSPLL for CLKS1/2=80MHz, CLKB=40MHz (F388/F389) increased by 0.8mA (typ) and
1.3mA (max)
• Updated ordering information: MB96384/385**A -> MB96384/385**B
• Package code of MB96V300 corrected in ordering information
• Internal LCD divider resistance value corrected: Typ 35kOhm -> 40kOhm, Max 50kOhm ->
65kOhm
• Run and Sleep mode currents of ROM devices (MB96384/385) reduced
• Added voltage condition to pull-up resistance and LCD divide resistance spec
• Lineup: Term “Data Flash” replaced by “independent 32KB Flash”
• Ordering information: column “Independent 32KB Data Flash” replaced by new column
“Flash/ROM”, column “Remarks” removed
9
2009-01-09
• Official package dimension drawing with additional notes added
• Empty pages removed
• MB96384/385 and MB96F385/F388/F389 separated in DC spec and currents of these devices
adjusted according to first evaluation results
• Alarmcomparator:Powersupplycurrentmaxvaluesincreased, comparisontimereduced, mode
transition time and power-up stabilization time newly added
• Handling devices: Notes added about Serial communication and about using ceramic resona-
tors.
• Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators.
For resonators, maximum frequency depends on Q-factor
• AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz
• VOL3 spec improved: spec valid for 3mA load for full Vcc range
• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted
• “Preliminary” watermark removed
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04582 Rev. *A
Page 115 of 117
MB96380 Series
Document History
Document Title: MB96380 Series F2MC-16FX 16-bit Proprietary Microcontroller
Document Number: 002-04582
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-04582.
No change to document contents or format.
**
AKIH
AKIH
05/02/2007
*A
5243006
04/28/2016 Updated to Cypress template
Document Number: 002-04582 Rev. *A
Page 116 of 117
MB96380 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | Projects | Video | Blogs | Training | Components
Technical Support
Lighting & Power Control
Memory
cypress.com/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04582 Rev. *A
Revised April 28, 2016
Page 117 of 117
相关型号：
MB96F386YSAPMC-GSE2
Microcontroller, 16-Bit, FLASH, 56MHz, CMOS, PQFP120, 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-120
CYPRESS
MB96F386YSBPMC-GSE2
Microcontroller, 16-Bit, FLASH, F2MC-16F CPU, 56MHz, CMOS, PQFP120, 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
CYPRESS
©2020 ICPDF网 联系我们和版权申明