MB9BF328SAPMC-GK7E2 [CYPRESS]
32-bit Arm® Cortex®-M3 FM3 Microcontroller;
| 型号： | MB9BF328SAPMC-GK7E2 |
| 厂家： | 
CYPRESS |
| 描述： | 32-bit Arm® Cortex®-M3 FM3 Microcontroller 微控制器 外围集成电路 |
| 文件： | 总143页 (文件大小：4554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
1. Go to www.cypress.com/pcn.
2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9B320TA Series
32-bit Arm® Cortex®-M3
FM3 Microcontroller
The MB9B320TA Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the Arm® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, DACs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE12 product categories in "FM3 Family PERIPHERAL
MANUAL".
Features
32-bit Arm® Cortex®-M3 Core
Processor version: r2p1
External Bus Interface
Supports SRAM, NOR NAND Flash memory device
Up to 8 chip selects
Up to 60 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
USB Interface
The USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
Dual operation Flash memory
Main area:
• Up to 1.5 Mbytes (1008 Kbytes(ROM0) + 512 Kbytes
(ROM1) of Upper bank and 16 Kbytes(ROM0) of Lower
[USB Device]
bank.)
Work area
USB2.0 Full-Speed supported
Max 6 EndPoint supported
EndPoint 0 is control transfer
EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or
Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 are comprised of Double Buffers.
The size of each EndPoint is as follows.
• EndPoint 0, 2 to 5:64 bytes
• 64 Kbytes(ROM1) of Lower bank
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
• EndPoint 1: 256 bytes
SRAM0: Up to 96 Kbytes
SRAM1: Up to 96 Kbytes
[USB host]
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatic detection
Automatic processing of the IN/OUT token handshake
packet
Max 256-byte packet-length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-05665 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2018
MB9B320TA Series
Multi-function Serial Interface (Max 16channels)
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
16 channels with 16 steps×9-bit FIFO
Operation mode is selectable from the followings for each
8 independently configured and operated channels
channel.
UART
CSIO
LIN
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
I2C
Transfer mode: Block transfer/Burst transfer/Demand
transfer
[UART]
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Number of transfers: 1 to 65536
A/D Converter (Max 24channels)
Hardware Flow control: Automatically control the
transmission/reception by CTS/RTS (only ch.4)
[12-bit A/D Converter]
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Successive Approximation type
Built-in 2 units
Conversion time: 1.0 μs @ 2.7 V to 5.5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
[LIN]
D/A Converter (Max 2channels)
R-2R type
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
10-bit resolution
Base Timer (Max 16channels)
Operation mode is selectable from the followings for each
channel.
LIN break field generation (can be changed to 13 to 16-bit
length)
LIN break delimiter generation (can be changed to 1 to 4-bit
length)
16-bit PWM timer
16-bit PPG timer
Various error detection functions available (parity errors,
framing errors, and overrun errors)
16-/32-bit reload timer
16-/32-bit PWC timer
[I2C]
Standard - mode (Max 100 kbps) / Fast - mode (Max 400 kbps)
supported
Document Number: 002-05665 Rev. *D
Page 2 of 142
MB9B320TA Series
General-Purpose I/O Port
Multi-function Timer
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Output compare × 6 ch./unit
A/D activation compare × 2 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
Up to 154 high-speed general-purpose I/O Ports@176 pin
Package
The following function can be used to achieve the motor
control.
Some ports are 5V tolerant.
See "List of Pin Functions" and "I/O Circuit Type" to confirm
the corresponding pins.
PWM signal output function
DC chopper waveform output function
Dead time function
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Free-running
Periodic (=Reload)
One-shot
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Quadrature Position/Revolution Counter (QPRC)
(Max 2channels)
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute.) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
The detection edge of the three external event input pins AIN,
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Watch Counter
The Watch counter is used for wake up from sleep and timer
mode.
HDMI-CEC/Remote Control Reception (Up to
2channels)
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
HDMI-CEC transmission
Header block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
External Interrupt Controller Unit
Up to 32 external interrupt input pins @ 176 pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Generating transmission status interrupt when transmitting
1 block (1 byte data and EOM/ACK)
HDMI-CEC reception
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
Automatic ACK reply function available
Line error detection function available
The "Hardware" watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except RTC,
STOP, Deep standby RTC, Deep standby STOP modes.
Remote control reception
4 bytes reception buffer
Repeat code detection function available
Document Number: 002-05665 Rev. *D
Page 3 of 142
MB9B320TA Series
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
Low-Power Consumption Mode
Six low-power consumption modes supported.
SLEEP
TIMER
RTC
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
STOP
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Deep standby RTC (selectable between keeping the value of
RAM and not)
Clock and Reset
Deep standby STOP (selectable between keeping the value
[Clocks]
of RAM and not)
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
Debug
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocell (ETM)
Built-in high-speed CR Clock:4 MHz
Built-in low-speed CR Clock: 100 kHz
Main PLL Clock
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage:
[Resets]
VCC
= 2.7 V to 5.5 V
Reset requests from INITX pin
Power-on reset
USBVCC = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is
asserted.
If external frequency anomaly is detected, interrupt or reset is
asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-05665 Rev. *D
Page 4 of 142
MB9B320TA Series
Contents
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 53
6. Handling Precautions ..................................................................................................................................................... 58
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 58
Precautions for Package Mounting.............................................................................................................................. 59
Precautions for Use Environment................................................................................................................................ 60
7. Handling Devices ............................................................................................................................................................ 61
8. Block Diagram................................................................................................................................................................. 64
9. Memory Size .................................................................................................................................................................... 64
10. Memory Map .................................................................................................................................................................... 65
11. Pin Status in Each CPU State ........................................................................................................................................ 68
12. Electrical Characteristics ............................................................................................................................................... 76
12.1 Absolute Maximum Ratings......................................................................................................................................... 76
12.2 Recommended Operating Conditions.......................................................................................................................... 78
12.3 DC Characteristics....................................................................................................................................................... 79
12.3.1 Current Rating.............................................................................................................................................................. 79
12.3.2 Pin Characteristics ....................................................................................................................................................... 83
12.4 AC Characteristics....................................................................................................................................................... 85
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 85
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 86
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 87
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)................................... 88
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of main PLL).............. 89
12.4.6 Reset Input Characteristics.......................................................................................................................................... 90
12.4.7 Power-on Reset Timing................................................................................................................................................ 90
12.4.8 External Bus Timing..................................................................................................................................................... 91
12.4.9 Base Timer Input Timing............................................................................................................................................ 102
12.4.10 CSIO/UART Timing ................................................................................................................................................ 103
12.4.11 External Input Timing.............................................................................................................................................. 111
12.4.12 Quadrature Position/Revolution Counter timing...................................................................................................... 112
12.4.13 I2C Timing............................................................................................................................................................... 114
12.4.14 ETM Timing ............................................................................................................................................................ 115
12.4.15 JTAG Timing........................................................................................................................................................... 116
12.5 12-bit A/D Converter.................................................................................................................................................. 117
12.6 10-bit D/A Converter.................................................................................................................................................. 120
12.7 USB Characteristics .................................................................................................................................................. 121
12.8 Low-Voltage Detection Characteristics...................................................................................................................... 125
12.8.1 Low-Voltage Detection Reset..................................................................................................................................... 125
12.8.2 Interrupt of Low-Voltage Detection............................................................................................................................. 126
12.9 Flash Memory Write/Erase Characteristics ............................................................................................................... 127
12.9.1 Write / Erase time....................................................................................................................................................... 127
12.9.2 Write cycles and data hold time ................................................................................................................................. 127
12.10 Return Time from Low-Power Consumption Mode.................................................................................................... 128
Document Number: 002-05665 Rev. *D
Page 5 of 142
MB9B320TA Series
12.10.1 Return Factor: Interrupt/WKUP............................................................................................................................... 128
12.10.2 Return Factor: Reset .............................................................................................................................................. 130
13. Ordering Information .................................................................................................................................................... 132
14. Package Dimensions .................................................................................................................................................... 133
15. Errata.............................................................................................................................................................................. 136
15.1 Part Numbers Affected............................................................................................................................................ 136
15.2 Qualification Status................................................................................................................................................. 136
15.3 Errata Summary....................................................................................................................................................... 136
15.4 Errata Detail .............................................................................................................................................................. 136
15.4.1 HDMI-CEC polling message issue............................................................................................................................. 136
16. Major Changes .............................................................................................................................................................. 138
Document History............................................................................................................................................................... 140
Sales, Solutions, and Legal Information........................................................................................................................... 142
Document Number: 002-05665 Rev. *D
Page 6 of 142
MB9B320TA Series
1. Product Lineup
Memory size
Product name
MB9BF328SA/TA
1 Mbytes
MB9BF329SA/TA
1.5 Mbytes
Main area
On-chip
Flash memory
Work area
64 Kbytes
64 Kbytes
96 Kbytes
SRAM0
On-chip
SRAM
80 Kbytes
80 Kbytes
160 Kbytes
SRAM1
96 Kbytes
Total
192 Kbytes
Function
Product name
Pin count
MB9BF328SA
MB9BF329SA
MB9BF328TA
MB9BF329TA
144
176/192
Cortex-M3
60 MHz
CPU
Freq.
Power supply voltage range
USB2.0 (Device/Host)
DMAC
2.7 V to 5.5 V
1 ch.
8 ch.
Addr: 25-bit (Max)
R/Wdata : 8-/16-bit (Max)
CS: 8 (Max)
External Bus Interface
SRAM , NOR Flash memory , NAND Flash memory
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
16 ch. (Max) with 16steps×9-bit FIFO
Base Timer
(PWC/Reload timer/PWM/PPG)
16 ch. (Max)
A/D activation
compare
2 ch.
Input capture
4 ch.
3 ch.
6 ch.
MF-
Timer
Free-run timer
Output compare
Waveform
generator
1 unit
3 ch.
3 ch.
PPG
QPRC
1 ch.(Max)
1 unit
2 ch. (Max)
Dual Timer
HDMI-CEC/ Remote Control Reception
2 ch. (Max)
Real-Time Clock
1 unit
Watch Counter
1 unit
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
Yes
1 ch. (SW) + 1 ch. (HW)
32 pins (Max) + NMI × 1
122 pins (Max)
24 ch. (2 units)
2 ch. (Max)
Yes
154 pins (Max)
2 ch.
High-speed
Low-speed
4 MHz
100 kHz
Built-in CR
Debug Function
Unique ID
SWJ-DP / ETM
Yes
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See "Electrical Characteristics 12.4 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics" for accuracy of built-in
CR.
Document Number: 002-05665 Rev. *D
Page 7 of 142
MB9B320TA Series
2. Packages
Product name
MB9BF328SA
MB9BF329SA
MB9BF328TA
MB9BF329TA
Package
-
LQFP:
LQFP:
BGA:
LQS144 (0.5 mm pitch)
LQP176 (0.5 mm pitch)
LBE192 (0.8 mm pitch)
-
-
: Supported
Note:
−
See "Package Dimensions" for detailed information on each package.
Document Number: 002-05665 Rev. *D
Page 8 of 142
MB9B320TA Series
3. Pin Assignment
LQP176
(TOP VIEW)
VCC
1
132 VSS
PA0/SIN8_0/TIOA08_0/MAD21_0
PA1/SOT8_0/TIOA09_0/MAD22_0
PA2/SCK8_0/TIOA10_0/MAD23_0
PA3/SIN9_0/TIOA11_0/MAD24_0
PA4/SOT9_0/TIOA12_0/INT03_0
PA5/SCK9_0/TIOA13_0/INT10_2
P05/TRACED0/SIN4_2/TIOA05_2/INT00_1
P06/TRACED1/SOT4_2/TIOB05_2/INT01_1
P07/TRACED2/ADTG_0/SCK4_2
2
131 VCC
3
130 P83/MCSX6_0
4
129 P82/MCSX7_0
5
128 PF6/NMIX/WKUP0
6
127 P20/AIN1_1/INT05_0/CROUT_0
126 P21/SIN0_0/BIN1_1/INT06_1
125 P22/AN23/SOT0_0/ZIN1_1/TIOB07_1
124 P23/AN22/SCK0_0/RTO00_1/TIOA07_1
123 P24/AN21/SIN2_1/RTO01_1/INT01_2
122 P25/AN20/SOT2_1/RTO02_1
121 P26/AN19/SCK2_1/RTO03_1
120 P27/AN18/SCK12_0/RTO04_1/INT02_2
119 P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0
118 P29/AN16/SIN12_0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P08/TRACED3/CTS4_2/TIOA00_2
P09/TRACECLK/RTS4_2/TIOB00_2
P50/SIN3_1/AIN0_2/INT00_0/MOEX_0
P51/SOT3_1/BIN0_2/INT01_0/MWEX_0
P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0
P54/SOT6_0/TIOB01_2/MALE_0
P55/ADTG_1/SCK6_0/MRDY_0
117 AVRH
116 AVRL
115 AVSS
P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
P5C/TIOA06_2/INT28_0
114 AVCC
113 PB7/TIOB12_1/INT23_0
112 PB6/SCK0_2/TIOA12_1/INT22_0
111 PB5/SOT0_2/TIOB11_1/INT21_0
110 PB4/SIN0_2/TIOA11_1/INT20_0
109 PB3/TIOB10_1/INT19_0
LQFP - 176
108 PB2/SCK7_2/TIOA10_1/INT18_0
107 PB1/SOT7_2/TIOB09_1/INT17_0
106 PB0/SIN7_2/TIOA09_1/INT16_0
105 P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1
104 P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1
103 P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1
102 P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1
101 P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1
100 P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1
P5D/TIOB06_2/INT29_0
VSS
P30/AIN0_0/TIOB00_1/INT03_2/WKUP4
P31/SCK6_1/BIN0_0/TIOB01_1/INT04_2
P32/SOT6_1/ZIN0_0/TIOB02_1/INT05_2
P33/ADTG_6/SIN6_1/TIOB03_1/INT04_0
P34/FRCK0_0/TIOB04_1
P35/IC03_0/TIOB05_1/INT08_1
P36/SIN5_2/IC02_0/TIOA12_2/INT09_1
P37/SOT5_2/IC01_0/TIOB12_2/INT10_1
P38/SCK5_2/IC00_0/INT11_1
99
98
97
96
95
94
93
92
91
90
89
P19/AN09/SCK2_2/INT22_1
P18/AN08/SOT2_2/INT21_1
P17/AN07/SIN2_2/INT04_1
P16/AN06/SCK0_1/INT20_1
P15/AN05/SOT0_1/IC03_2
P14/AN04/SIN0_1/IC02_2/INT03_1
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P12/AN02/SOT1_1/IC00_2
P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1
P10/AN00
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
P3A/RTO00_0/TIOA00_1
P3B/RTO01_0/TIOA01_1
P3C/RTO02_0/TIOA02_1
P3D/RTO03_0/TIOA03_1
P3E/RTO04_0/TIOA04_1
P3F/RTO05_0/TIOA05_1
VSS
VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05665 Rev. *D
Page 9 of 142
MB9B320TA Series
LQS144
(TOP VIEW)
VCC
PA0/SIN8_0/TIOA08_0/MAD21_0
PA1/SOT8_0/TIOA09_0/MAD22_0
PA2/SCK8_0/TIOA10_0/MAD23_0
PA3/SIN9_0/TIOA11_0/MAD24_0
PA4/SOT9_0/TIOA12_0/INT03_0
PA5/SCK9_0/TIOA13_0/INT10_2
P05/TRACED0/SIN4_2/TIOA05_2/INT00_1
P06/TRACED1/SOT4_2/TIOB05_2/INT01_1
P07/TRACED2/ADTG_0/SCK4_2
1
108 VSS
2
107 VCC
3
106 P83/MCSX6_0
4
105 P82/MCSX7_0
5
104 PF6/NMIX/WKUP0
6
103 P20/AIN1_1/INT05_0/CROUT_0
102 P21/SIN0_0/BIN1_1/INT06_1
101 P22/AN23/SOT0_0/ZIN1_1/TIOB07_1
100 P23/AN22/SCK0_0/RTO00_1/TIOA07_1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P24/AN21/SIN2_1/RTO01_1/INT01_2
P25/AN20/SOT2_1/RTO02_1
P26/AN19/SCK2_1/RTO03_1
P27/AN18/SCK12_0/RTO04_1/INT02_2
P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0
P29/AN16/SIN12_0
P08/TRACED3/CTS4_2/TIOA00_2
P09/TRACECLK/RTS4_2/TIOB00_2
P50/SIN3_1/AIN0_2/INT00_0/MOEX_0
P51/SOT3_1/BIN0_2/INT01_0/MWEX_0
P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0
P54/SOT6_0/TIOB01_2/MALE_0
P55/ADTG_1/SCK6_0/MRDY_0
AVRH
AVRL
AVSS
LQFP - 144
P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
VSS
AVCC
P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1
P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1
P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1
P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1
P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1
P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1
P19/AN09/SCK2_2/INT22_1
P18/AN08/SOT2_2/INT21_1
P17/AN07/SIN2_2/INT04_1
P16/AN06/SCK0_1/INT20_1
P15/AN05/SOT0_1/IC03_2
P36/SIN5_2/IC02_0/TIOA12_2/INT09_1
P37/SOT5_2/IC01_0/TIOB12_2/INT10_1
P38/SCK5_2/IC00_0/INT11_1
P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2
P3A/RTO00_0/TIOA00_1
P3B/RTO01_0/TIOA01_1
P14/AN04/SIN0_1/IC02_2/INT03_1
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P12/AN02/SOT1_1/IC00_2
P3C/RTO02_0/TIOA02_1
P3D/RTO03_0/TIOA03_1
P3E/RTO04_0/TIOA04_1
P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1
P10/AN00
P3F/RTO05_0/TIOA05_1
VSS
VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05665 Rev. *D
Page 10 of 142
MB9B320TA Series
LBE192
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
USB
VCC
UDP0 UDM0
VSS
P61
P60
PA3
P50
P55
P5A
P32
P34
P4A
P49
P48
INITX
X0A
PCD
PD1
PD2
PD3
P62
P56
P5B
P33
P70
P4E
P4D
P4C
P4B
X1A
PCB
PCA
PCC
PCE
PCF
PD0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PC1
PC5
PC6
PC7
PC9
VSS
VSS
P76
P74
P73
P72
P71
P75
VCC
P95
PC0
PC2
PC3
PC4
PB7
P1F
P1D
P7B
P7A
P79
P78
P77
PC8
P92
P93
P94
P25
P29
PB6
P1E
P1C
P7F
P7E
PF0
P7D
P7C
VSS
TDO
P90
P91
P24
P28
PB5
PB2
P1B
P18
P14
PF2
PF1
VSS
TCK
VCC
A
B
C
D
E
F
VSS
VCC
PA5
VSS
P51
PA0
PA1
PA4
P07
P52
P57
P5D
P37
P39
P3D
P3F
P40
C
PF5
PA2
P05
P08
P53
P58
P30
P36
P3A
P3E
P42
P41
VSS
PF3
PF4
P06
P09
P54
P59
P31
P35
P3B
P43
P44
P45
VCC
TMS TRSTX VSS
TDI
P21
P23
P27
PB4
PB1
P1A
P16
P13
P11
MD0
X0
PF6
P20
P22
P26
PB3
PB0
P19
P15
P12
P10
MD1
X1
VCC
P83
P82
AVRH
AVRL
AVSS
AVCC
P17
VSS
P5C
VSS
P38
G
H
J
K
L
P3C
VSS
VCC
VSS
VCC
VSS
M
N
P
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05665 Rev. *D
Page 11 of 142
MB9B320TA Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
BGA-192
C1
1
2
1
2
VCC
-
PA0
SIN8_0
TIOA08_0
MAD21_0
PA1
B2
C2
C3
D5
D2
D1
I*
J
SOT8_0
TIOA09_0
MAD22_0
PA2
3
4
5
6
7
3
4
5
6
7
I*
I*
I*
I*
I*
J
SCK8_0
TIOA10_0
MAD23_0
PA3
J
SIN9_0
TIOA11_0
MAD24_0
PA4
J
SOT9_0
TIOA12_0
INT03_0
PA5
K
K
SCK9_0
TIOA13_0
INT10_2
P05
TRACED0
SIN4_2
TIOA05_2
8
9
8
9
D3
D4
E
E
Q
Q
INT00_1
P06
TRACED1
SOT4_2
TIOB05_2
INT01_1
Document Number: 002-05665 Rev. *D
Page 12 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
BGA-192
P07
TRACED2
ADTG_0
SCK4_2
P08
10
10
E2
E
P
P
P
TRACED3
CTS4_2
TIOA00_2
P09
11
12
11
12
E3
E4
E
E
TRACECLK
RTS4_2
TIOB00_2
P50
SIN3_1
AIN0_2
INT00_0
MOEX_0
P51
13
14
15
13
14
15
E5
F1
F2
E
E
E
K
K
K
SOT3_1
BIN0_2
INT01_0
MWEX_0
P52
SCK3_1
ZIN0_2
INT02_0
MDQM0_0
Document Number: 002-05665 Rev. *D
Page 13 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
BGA-192
P53
SIN6_0
TIOA01_2
INT07_2
MDQM1_0
P54
16
16
F3
E
K
SOT6_0
TIOB01_2
MALE_0
P55
17
18
17
18
F4
F5
E
E
J
J
ADTG_1
SCK6_0
MRDY_0
P56
SIN1_0
TIOA09_2
INT08_2
CEC1_1
MNALE_0
P57
19
19
F6
I*
S
SOT1_0
TIOB09_2
INT16_1
MNCLE_0
P58
20
21
22
20
21
22
G2
G3
G4
I*
I*
E
K
K
K
SCK1_0
TIOA11_2
INT17_1
MNWEX_0
P59
SIN7_0
TIOB11_2
INT09_2
MNREX_0
Document Number: 002-05665 Rev. *D
Page 14 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P5A
SOT7_0
TIOA13_1
INT18_1
MCSX0_0
P5B
23
23
G5
E
K
K
SCK7_0
TIOB13_1
INT19_1
MCSX1_0
P5C
24
25
24
-
G6
H1
E
E
TIOA06_2
INT28_0
P5D
K
K
26
27
-
H2
A5
TIOB06_2
INT29_0
VSS
E
-
25
P30
AIN0_0
TIOB00_1
INT03_2
WKUP4
P31
28
29
30
31
-
-
-
-
H3
H4
H5
H6
E
E
E
E
U
K
K
K
SCK6_1
BIN0_0
TIOB01_1
INT04_2
P32
SOT6_1
ZIN0_0
TIOB02_1
INT05_2
P33
ADTG_6
SIN6_1
TIOB03_1
INT04_0
Document Number: 002-05665 Rev. *D
Page 15 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
32
BGA-192
J5
P34
-
-
FRCK0_0
TIOB04_1
P35
E
J
IC03_0
TIOB05_1
INT08_1
P36
33
34
J4
J3
E
E
K
SIN5_2
IC02_0
TIOA12_2
INT09_1
P37
26
K
SOT5_2
IC01_0
TIOB12_2
INT10_1
P38
35
36
37
27
28
29
J2
E
E
E
K
K
J
SCK5_2
IC00_0
INT11_1
P39
K1
K2
ADTG_2
DTTI0X_0
RTCCO_2
SUBOUT_2
P3A
38
39
40
30
31
32
K3
K4
L1
RTO00_0
TIOA00_1
P3B
F
F
F
J
J
J
RTO01_0
TIOA01_1
P3C
RTO02_0
TIOA02_1
Document Number: 002-05665 Rev. *D
Page 16 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
41
BGA-192
L2
P3D
33
RTO03_0
TIOA03_1
P3E
F
J
J
J
42
43
34
35
L3
RTO04_0
TIOA04_1
P3F
F
F
M2
RTO05_0
TIOA05_1
VSS
44
45
36
37
A8
N1
-
-
VCC
P40
SIN10_0
TIOA00_0
INT12_1
MCSX2_0
P41
46
47
38
39
N2
N3
E
E
K
K
SOT10_0
TIOA01_0
INT13_1
MCSX3_0
P42
SCK10_0
TIOA02_0
48
49
40
41
M3
L4
E
I*
J
J
MCLKOUT_0
P43
ADTG_7
SIN11_0
TIOA03_0
P44
50
51
42
43
M4
N4
SOT11_0
TIOA04_0
P45
I*
I*
J
J
SCK11_0
TIOA05_0
C
52
53
54
44
45
46
P2
-
-
-
A11
P4
VSS
VCC
P46
55
47
P5
D
F
X0A
P47
56
57
48
49
P6
N5
D
B
G
C
X1A
INITX
P48
58
50
M5
SIN3_2
INT14_1
E
K
Document Number: 002-05665 Rev. *D
Page 17 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P49
SOT3_2
AIN0_1
TIOB00_0
P4A
59
51
L5
E
J
J
SCK3_2
BIN0_1
TIOB01_0
60
61
62
63
52
53
54
55
K5
N6
M6
L6
E
E
E
E
MADATA00_0
P4B
IGTRG0_0
ZIN0_1
J
J
J
TIOB02_0
MADATA01_0
P4C
SCK7_1
AIN1_2
TIOB03_0
MADATA02_0
P4D
SOT7_1
BIN1_2
TIOB04_0
MADATA03_0
P4E
SIN7_1
ZIN1_2
64
56
K6
E
K
TIOB05_0
INT06_2
MADATA04_0
P70
65
66
57
58
J6
TIOA04_2
MADATA05_0
P71
E
E
J
TIOB04_2
INT13_2
MADATA06_0
N8
K
Document Number: 002-05665 Rev. *D
Page 18 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P72
SIN2_0
INT14_2
WKUP2
67
59
M8
E
U
MADATA07_0
P73
SOT2_0
INT15_2
MADATA08_0
P74
68
69
60
61
L8
K8
E
E
K
J
SCK2_0
MADATA09_0
P75
ADTG_8
SIN3_0
70
71
62
63
P8
J8
E
E
K
K
INT07_1
MADATA10_0
P76
SOT3_0
TIOA07_2
INT11_2
MADATA11_0
P77
SCK3_0
TIOB07_2
INT12_2
MADATA12_0
P78
72
73
74
64
65
66
P9
N9
M9
E
E
E
K
J
AIN1_0
TIOA15_0
MADATA13_0
P79
BIN1_0
TIOB15_0
INT23_1
MADATA14_0
VSS
K
-
-
-
-
M1
P3
-
-
VSS
Document Number: 002-05665 Rev. *D
Page 19 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P7A
ZIN1_0
INT24_1
75
67
L9
E
K
MADATA15_0
P7B
76
77
78
79
80
-
-
-
-
-
K9
TIOB07_0
INT10_0
P7C
E
E
E
E
E
K
K
K
K
K
P10
N10
L10
K10
TIOA07_0
INT11_0
P7D
TIOA14_1
INT12_0
P7E
TIOB14_1
INT24_0
P7F
TIOA15_1
INT25_0
PF0
SIN1_2
TIOB15_1
INT13_0
CEC0_0
PF1
81
-
M10
I*
S
SOT1_2
TIOA08_1
INT14_0
PF2
82
83
-
-
N11
M11
I*
I*
K
K
SCK1_2
TIOB08_1
INT15_0
PE0
84
85
86
68
69
70
N13
N12
P12
C
J
E
D
A
MD1
MD0
PE2
A
X0
PE3
87
71
P13
A
B
X1
88
89
-
72
73
-
E1
VSS
-
-
-
-
M14
P7
VCC
VSS
-
-
N7
VSS
Document Number: 002-05665 Rev. *D
Page 20 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
90
BGA-192
P10
74
M13
G
L
AN00
P11
AN01
SIN1_1
FRCK0_2
INT02_1
WKUP1
P12
91
92
93
75
76
77
M12
L13
L12
G
G
G
N
AN02
L
L
SOT1_1
IC00_2
P13
AN03
SCK1_1
IC01_2
RTCCO_1
SUBOUT_1
P14
AN04
94
78
L11
SIN0_1
IC02_2
INT03_1
P15
G
M
AN05
95
96
97
79
80
81
K13
K12
K14
G
G
G
L
SOT0_1
IC03_2
P16
AN06
M
M
SCK0_1
INT20_1
P17
AN07
SIN2_2
INT04_1
VSS
-
-
-
-
-
-
M7
L7
-
-
-
VSS
K7
VSS
Document Number: 002-05665 Rev. *D
Page 21 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P18
AN08
98
82
K11
G
M
M
SOT2_2
INT21_1
P19
AN09
99
83
84
J13
J12
G
G
SCK2_2
INT22_1
P1A
AN10
SIN4_1
IC00_1
TIOA13_2
INT05_1
P1B
100
M
M
M
M
AN11
SOT4_1
IC01_1
TIOB13_2
INT25_1
P1C
101
102
103
85
86
87
J11
J10
J9
G
G
G
AN12
SCK4_1
IC02_1
TIOA14_2
INT26_1
P1D
AN13
CTS4_1
IC03_1
TIOB14_2
INT27_1
P1E
AN14
RTS4_1
DTTI0X_1
TIOA15_2
INT28_1
104
88
H10
G
M
Document Number: 002-05665 Rev. *D
Page 22 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P1F
AN15
ADTG_5
FRCK0_1
TIOB15_2
INT29_1
PB0
105
89
H9
G
M
SIN7_2
TIOA09_1
INT16_0
PB1
106
107
-
-
H13
H12
E
E
K
K
SOT7_2
TIOB09_1
INT17_0
PB2
SCK7_2
TIOA10_1
INT18_0
PB3
108
109
110
-
-
-
H11
G13
G12
E
E
E
K
K
K
TIOB10_1
INT19_0
PB4
SIN0_2
TIOA11_1
INT20_0
PB5
SOT0_2
TIOB11_1
INT21_0
PB6
111
-
G11
E
K
SCK0_2
TIOA12_1
INT22_0
PB7
112
113
-
-
G10
G9
E
E
K
K
TIOB12_1
INT23_0
AVCC
114
90
91
-
J14
H14
J7
-
-
-
-
115
AVSS
-
-
VSS
-
P11
VSS
Document Number: 002-05665 Rev. *D
Page 23 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
116
BGA-192
G14
92
AVRL
-
117
93
94
F14
AVRH
-
P29
118
F10
AN16
G
L
SIN12_0
P28
AN17
ADTG_4
SOT12_0
RTO05_1
INT09_0
P27
119
120
95
96
F11
F12
G
G
M
AN18
SCK12_0
RTO04_1
INT02_2
P26
M
AN19
121
122
97
98
F13
E10
G
G
L
L
SCK2_1
RTO03_1
P25
AN20
SOT2_1
RTO02_1
P24
AN21
123
99
E11
SIN2_1
RTO01_1
INT01_2
G
M
Document Number: 002-05665 Rev. *D
Page 24 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
P23
AN22
124
100
E12
SCK0_0
RTO00_1
TIOA07_1
P22
G
L
AN23
125
126
101
102
E13
D12
SOT0_0
ZIN1_1
TIOB07_1
P21
G
E
L
SIN0_0
BIN1_1
INT06_1
P20
K
AIN1_1
INT05_0
CROUT_0
PF6
127
128
103
104
D13
C13
E
I*
K
H
NMIX
WKUP0
P82
129
130
105
106
E14
D14
E
E
J
J
MCSX7_0
P83
MCSX6_0
VCC
131
132
133
107
108
109
C14
G7
-
-
-
VSS
A13
VCC
P00
134
135
136
137
110
111
112
113
B13
A12
C12
B12
E
E
E
E
I
I
I
I
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
138
114
B11
TDO
E
I
SWO
P90
139
-
-
-
C11
N14
TIOB08_0
INT30_0
VSS
E
-
K
Document Number: 002-05665 Rev. *D
Page 25 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
140
BGA-192
D11
P91
-
-
-
TIOB09_0
INT31_0
P92
E
K
J
141
142
B10
C10
SIN5_1
TIOB10_0
P93
E
E
SOT5_1
TIOB11_0
P94
J
SCK5_1
TIOB12_0
INT26_0
P95
143
144
145
-
-
D10
B9
E
E
H
K
K
O
TIOB13_0
INT27_0
PC0
DA0_0
115
116
C9
SIN13_0
MCSX5_0
PC1
DA1_0
146
B8
H
O
SOT13_0
MCSX4_0
PC2
147
148
117
118
D9
E9
SCK13_0
MAD00_0
PC3
E
E
J
J
TIOA06_1
MAD01_0
PC4
SIN14_0
TIOA08_2
CEC0_1
MAD02_0
PC5
149
119
F9
I*
R
J
SOT14_0
TIOA10_2
MAD03_0
VSS
150
-
120
-
C8
I*
-
L14
Document Number: 002-05665 Rev. *D
Page 26 of 142
MB9B320TA Series
Pin No
LQFP-144
I/O circuit
type
Pin state
type
Pin name
LQFP-176
BGA-192
PC6
SCK14_0
TIOA14_0
MAD04_0
PC7
151
121
D8
I*
J
CROUT_1
RTCCO_0
152
122
E8
E
J
SUBOUT_0
MAD05_0
PC8
153
154
155
123
124
125
A10
F8
SIN15_0
MAD06_0
PC9
E
E
E
J
J
J
SOT15_0
MAD07_0
PCA
B7
SCK15_0
MAD08_0
VCC
156
157
126
127
A9
G8
-
-
VSS
PCB
158
159
160
128
129
130
A7
C7
A6
E
E
E
J
J
J
MAD09_0
PCC
MAD10_0
PCD
MAD11_0
PCE
RTS4_0
TIOB06_1
MAD12_0
PCF
161
162
131
132
D7
E7
E
E
J
J
CTS4_0
TIOB08_2
MAD13_0
PD0
SCK4_0
TIOB10_2
INT30_1
MAD14_0
PD1
163
164
133
134
F7
B6
E
E
K
K
SOT4_0
TIOB14_0
INT31_1
MAD15_0
VSS
-
-
-
-
-
-
-
-
B14
H7
B1
-
-
-
-
VSS
VSS
G1
VSS
Document Number: 002-05665 Rev. *D
Page 27 of 142
MB9B320TA Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
PD2
SIN4_0
TIOA03_2
INT00_2
MAD16_0
PD3
165
135
C6
E
K
166
167
136
137
D6
E6
TIOB03_2
MAD17_0
P62
E
E
J
J
ADTG_3
SCK5_0
MAD18_0
P61
UHCONX
SOT5_0
TIOB02_2
MAD19_0
P60
168
169
138
139
B5
C5
E
E
J
SIN5_0
TIOA02_2
INT15_1
WKUP5
MAD20_0
PF3
U
SIN6_2
TIOA06_0
INT06_0
PF4
170
171
-
-
B4
C4
I*
I*
K
K
SOT6_2
TIOB06_0
INT07_0
PF5
IGTRG0_1
INT08_0
WKUP3
CEC1_0
SCK6_2
USBVCC
P80
140
172
B3
I*
T
-
173
174
141
A4
A3
-
142
143
K
V
V
UDM0
P81
175
A2
K
UDP0
176
-
144
-
H8
J1
VSS
-
-
VSS
* : 5V tolerant I/O
Document Number: 002-05665 Rev. *D
Page 28 of 142
MB9B320TA Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Pin
Pin name
ADTG_0
Function description
function
LQFP-176
10
LQFP-144
BGA-192
E2
ADC
10
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
18
18
29
137
95
89
-
F5
37
K2
167
119
105
31
E6
A/D converter external trigger input
pin
F11
H9
H6
49
41
62
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
100
101
L4
70
P8
90
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
AN01
91
AN02
92
AN03
93
AN04
94
AN05
95
AN06
96
AN07
97
AN08
98
AN09
99
AN10
100
101
102
103
104
105
118
119
120
121
122
123
124
125
AN11
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN12
AN13
AN14
H10
H9
AN15
AN16
F10
F11
F12
F13
E10
E11
E12
E13
AN17
AN18
AN19
AN20
AN21
AN22
AN23
Document Number: 002-05665 Rev. *D
Page 29 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
function
Pin name
TIOA00_0
Function description
LQFP-176
46
BGA-192
N2
Base Timer
0
38
30
11
51
-
TIOA00_1
TIOA00_2
TIOB00_0
TIOB00_1
TIOB00_2
TIOA01_0
TIOA01_1
TIOA01_2
TIOB01_0
TIOB01_1
TIOB01_2
TIOA02_0
TIOA02_1
TIOA02_2
TIOB02_0
TIOB02_1
TIOB02_2
TIOA03_0
TIOA03_1
TIOA03_2
TIOB03_0
TIOB03_1
TIOB03_2
TIOA04_0
TIOA04_1
TIOA04_2
TIOB04_0
TIOB04_1
TIOB04_2
TIOA05_0
TIOA05_1
TIOA05_2
TIOB05_0
TIOB05_1
TIOB05_2
TIOA06_0
TIOA06_1
TIOA06_2
TIOB06_0
Base timer ch.0 TIOA pin
38
11
K3
E3
L5
H3
E4
N3
K4
F3
K5
H4
F4
M3
L1
C5
N6
H5
B5
L4
L2
C6
M6
H6
D6
M4
L3
J6
59
28
12
47
39
16
60
29
17
48
40
169
61
30
168
49
41
165
62
31
166
50
42
65
63
32
66
51
43
8
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
12
39
31
16
52
-
Base Timer
1
17
40
32
139
53
-
Base Timer
2
138
41
33
135
54
-
Base Timer
3
136
42
34
57
55
-
Base Timer
4
L6
J5
58
43
35
8
N8
N4
M2
D3
K6
J4
Base Timer
5
64
33
9
56
-
9
D4
B4
E9
H1
C4
Base Timer
6
170
148
25
171
-
118
-
-
TIOB06_1
TIOB06_2
Base timer ch.6 TIOB pin
161
26
131
-
D7
H2
Document Number: 002-05665 Rev. *D
Page 30 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
TIOA07_0
Function description
function
LQFP-176
77
BGA-192
P10
Base Timer
7
-
TIOA07_1
TIOA07_2
TIOB07_0
TIOB07_1
TIOB07_2
TIOA08_0
TIOA08_1
TIOA08_2
TIOB08_0
TIOB08_1
TIOB08_2
TIOA09_0
TIOA09_1
TIOA09_2
TIOB09_0
TIOB09_1
TIOB09_2
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
Base timer ch.7 TIOA pin
124
71
100
63
-
E12
J8
76
K9
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
Base timer ch.10 TIOA pin
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
125
72
101
64
2
E13
P9
Base Timer
8
2
B2
82
-
N11
F9
149
139
83
119
-
C11
M11
E7
-
162
3
132
3
Base Timer
9
C2
106
19
-
H13
F6
19
-
140
107
20
D11
H12
G2
-
20
4
Base Timer
10
4
C3
108
150
141
109
163
5
-
H11
C8
120
-
B10
G13
F7
-
133
5
Base Timer
11
D5
110
21
-
G12
G3
21
-
142
111
22
C10
G11
G4
-
22
6
Base Timer
12
6
D2
112
34
-
G10
J3
26
-
143
113
35
D10
G9
-
27
7
J2
Base Timer
13
7
D1
23
23
84
-
G5
100
144
24
J12
B9
24
85
G6
101
J11
Document Number: 002-05665 Rev. *D
Page 31 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
TIOA14_0
Function description
function
LQFP-176
151
78
BGA-192
D8
Base Timer
14
121
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
SWCLK
Base timer ch.14 TIOA pin
-
N10
J10
B6
102
164
79
86
134
-
Base timer ch.14 TIOB pin
Base timer ch.15 TIOA pin
L10
J9
103
73
87
65
-
Base Timer
15
N9
80
K10
H10
M9
104
74
88
66
-
Base timer ch.15 TIOB pin
81
M10
H9
105
135
89
111
Debugger
Serial wire debug interface clock input
A12
Serial wire debug interface data input /
output
SWDIO
137
113
B12
SWO
Serial wire viewer output
JTAG test clock input
138
135
136
138
137
12
114
111
112
114
113
12
B11
A12
C12
B11
B12
E4
TCK
TDI
JTAG test data input
TDO
JTAG debug data output
JTAG test mode state input/output
Trace CLK output of ETM
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
8
8
D3
9
9
D4
Trace data output of ETM
JTAG test reset Input
10
10
E2
11
11
E3
134
110
B13
Document Number: 002-05665 Rev. *D
Page 32 of 142
MB9B320TA Series
Pin No
Pin
Pin name
MAD00_0
Function description
function
LQFP-176
147
LQFP-144
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
137
138
139
2
BGA-192
External
Bus
D9
E9
F9
C8
D8
E8
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
167
168
169
2
A10
F8
B7
A7
C7
A6
D7
E7
F7
External bus interface address bus
B6
C6
D6
E6
B5
C5
B2
C2
C3
D5
G5
G6
N2
N3
B8
C9
D14
E14
F2
3
3
4
4
5
5
23
23
24
24
46
38
47
39
External bus interface chip select
output pin
146
145
130
129
15
116
115
106
105
15
External bus interface byte mask
signal output
16
16
F3
External bus interface read enable
signal for SRAM
MOEX_0
MWEX_0
13
14
13
14
E5
F1
External bus interface write enable
signal for SRAM
Document Number: 002-05665 Rev. *D
Page 33 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
MNALE_0
Function description
function
LQFP-176
19
BGA-192
External
Bus
External bus interface ALE signal to
control NAND Flash output pin
19
F6
External bus interface CLE signal to
control NAND Flash output pin
MNCLE_0
MNREX_0
MNWEX_0
20
22
21
20
22
21
G2
G4
G3
External bus interface read enable
signal to control NAND Flash
External bus interface write enable
signal to control NAND Flash
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
K5
N6
M6
L6
K6
J6
N8
M8
L8
K8
P8
J8
External bus interface data bus
(Address / data multiplex bus)
P9
N9
M9
L9
External bus interface Address Latch
enable output signal for multiplex
MALE_0
17
18
48
17
18
40
F4
F5
M3
External bus interface external RDY
input signal
MRDY_0
External bus interface external clock
output
MCLKOUT_0
Document Number: 002-05665 Rev. *D
Page 34 of 142
MB9B320TA Series
Pin No
LQFP-144
13
Pin
Pin name
INT00_0
Function description
function
LQFP-176
13
BGA-192
External
Interrupt
E5
D3
C6
F1
D4
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
External interrupt request 00 input pin
8
8
165
14
9
135
14
9
External interrupt request 01 input pin
123
15
99
15
75
96
6
E11
F2
External interrupt request 02 input pin 91
120
M12
F12
D2
L11
H3
H6
K14
H4
D13
J12
H5
B4
6
External interrupt request 03 input pin 94
78
-
28
31
External interrupt request 04 input pin 97
29
-
81
-
127
103
84
-
External interrupt request 05 input pin 100
30
170
-
External interrupt request 06 input pin 126
102
56
-
D12
K6
64
171
C4
P8
External interrupt request 07 input pin 70
62
16
140
-
16
F3
172
B3
External interrupt request 08 input pin 33
J4
19
19
95
26
22
-
F6
119
F11
J3
External interrupt request 09 input pin 34
22
G4
K9
76
External interrupt request 10 input pin 35
27
7
J2
7
D1
P10
K1
77
-
External interrupt request 11 input pin 36
28
63
-
71
J8
78
N10
N2
P9
External interrupt request 12 input pin 46
38
64
-
72
81
M10
N3
N8
N11
M5
M8
External interrupt request 13 input pin 47
39
58
-
66
82
External interrupt request 14 input pin 58
67
50
59
Document Number: 002-05665 Rev. *D
Page 35 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
INT15_0
Function description
function
LQFP-176
83
BGA-192
M11
External
Interrupt
-
INT15_1
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
External interrupt request 15 input pin 169
68
139
60
-
C5
L8
106
H13
G2
External interrupt request 16 input pin
20
20
-
107
H12
G3
External interrupt request 17 input pin
21
21
-
108
H11
G5
External interrupt request 18 input pin
23
23
-
109
G13
G6
External interrupt request 19 input pin
24
24
-
110
G12
K12
G11
K11
G10
J13
G9
External interrupt request 20 input pin
96
80
-
111
External interrupt request 21 input pin
98
82
-
112
External interrupt request 22 input pin
99
83
-
113
External interrupt request 23 input pin
74
66
-
M9
79
External interrupt request 24 input pin
75
L10
L9
67
-
80
External interrupt request 25 input pin
101
K10
J11
D10
J10
B9
85
-
143
External interrupt request 26 input pin
102
86
-
144
External interrupt request 27 input pin
103
87
-
J9
25
External interrupt request 28 input pin
104
H1
88
-
H10
H2
26
External interrupt request 29 input pin
105
89
-
H9
139
External interrupt request 30 input pin
163
C11
F7
133
-
140
External interrupt request 31 input pin
164
D11
B6
134
104
Non-Maskable Interrupt input
128
C13
Document Number: 002-05665 Rev. *D
Page 36 of 142
MB9B320TA Series
Pin No
LQFP-144
110
Pin
Pin name
Function description
function
LQFP-176
134
135
136
137
138
8
BGA-192
B13
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
111
112
113
114
8
A12
C12
B12
B11
D3
General-purpose I/O port 0
9
9
D4
10
10
11
E2
11
E3
12
12
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
103
102
101
100
99
98
97
96
95
94
E4
90
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
91
92
93
94
95
96
97
General-purpose I/O port 1
98
99
100
101
102
103
104
105
127
126
125
124
123
122
121
120
119
118
H10
H9
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
General-purpose I/O port 2
Document Number: 002-05665 Rev. *D
Page 37 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
Function description
function
LQFP-176
28
BGA-192
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
-
H3
H4
H5
H6
J5
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
48
49
50
51
55
56
58
59
60
61
62
63
64
13
14
15
16
17
18
19
20
21
22
23
24
25
26
-
-
-
-
-
J4
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
13
14
15
16
17
18
19
20
21
22
23
24
-
J3
J2
General-purpose I/O port 3
K1
K2
K3
K4
L1
L2
L3
M2
N2
N3
M3
L4
M4
N4
P5
P6
M5
L5
General-purpose I/O port 4
K5
N6
M6
L6
K6
E5
F1
F2
F3
F4
F5
F6
G2
G3
G4
G5
G6
H1
H2
General-purpose I/O port 5
-
Document Number: 002-05665 Rev. *D
Page 38 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
Function description
function
LQFP-176
169
BGA-192
GPIO
P60
P61
P62
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P7F
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
139
138
137
57
58
59
60
61
62
63
64
65
66
67
-
C5
B5
E6
J6
General-purpose I/O port 6
168
167
65
66
N8
M8
L8
K8
P8
J8
67
68
69
70
71
72
P9
N9
M9
L9
K9
General-purpose I/O port 7
73
74
75
76
77
-
P10
N10
L10
K10
A3
78
-
79
-
80
-
174
175
129
130
139
140
141
142
143
144
2
142
143
105
106
-
A2
General-purpose I/O port 8
General-purpose I/O port 9
E14
D14
C11
D11
B10
C10
D10
B9
-
-
-
-
-
2
B2
3
3
C2
4
4
C3
General-purpose I/O port A
5
5
D5
6
6
D2
7
7
D1
106
107
108
109
110
111
112
113
-
H13
H12
H11
G13
G12
G11
G10
G9
-
-
-
General-purpose I/O port B
-
-
-
-
Document Number: 002-05665 Rev. *D
Page 39 of 142
MB9B320TA Series
Pin No
Pin
Pin name
Function description
function
LQFP-176
145
LQFP-144
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
68
BGA-192
C9
GPIO
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PD3
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
84
B8
D9
E9
F9
C8
D8
E8
General-purpose I/O port C
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
General-purpose I/O port D
General-purpose I/O port E
C6
D6
N13
P12
P13
M10
N11
M11
B4
86
70
87
71
81
-
82
-
83
-
General-purpose I/O port F*
170
171
172
128
-
-
C4
B3
140
104
C13
Document Number: 002-05665 Rev. *D
Page 40 of 142
MB9B320TA Series
Pin No.
LQFP-144
Pin
Pin name
SIN0_0
Function description
function
LQFP-176
126
BGA-192
D12
Multi
102
78
-
Multifunction serial interface ch.0
input pin
Function
Serial
0
SIN0_1
SIN0_2
94
L11
110
G12
SOT0_0
(SDA0_0)
Multifunction serial interface ch.0
output pin.
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA0 when it is
used in an I2C (operation mode 4).
125
95
101
79
-
E13
K13
G11
E12
K12
G10
SOT0_1
(SDA0_1)
SOT0_2
(SDA0_2)
111
124
96
SCK0_0
(SCL0_0)
Multifunction serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL0 when it is
used in an I2C (operation mode 4).
100
80
-
SCK0_1
(SCL0_1)
SCK0_2
(SCL0_2)
112
Multi
Function
Serial
1
SIN1_0
SIN1_1
SIN1_2
19
91
81
19
75
-
F6
Multifunction serial interface ch.1
input pin
M12
M10
SOT1_0
(SDA1_0)
Multifunction serial interface ch.1
output pin.
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA1 when it is
used in an I2C (operation mode 4).
20
92
82
21
93
83
20
76
-
G2
SOT1_1
(SDA1_1)
L13
N11
G3
SOT1_2
(SDA1_2)
SCK1_0
(SCL1_0)
Multifunction serial interface ch.1
clock I/O pin.
This pin operates as SCK1 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL1 when it is
used in an I2C (operation mode 4).
21
77
-
SCK1_1
(SCL1_1)
L12
M11
SCK1_2
(SCL1_2)
Document Number: 002-05665 Rev. *D
Page 41 of 142
MB9B320TA Series
Pin No.
LQFP-144
59
Pin
Pin name
SIN2_0
Function description
function
LQFP-176
67
BGA-192
M8
Multi
Multifunction serial interface ch.2
input pin
Function
Serial
2
SIN2_1
SIN2_2
123
97
99
81
E11
K14
SOT2_0
(SDA2_0)
Multifunction serial interface ch.2
output pin.
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA2 when it is
used in an I2C (operation mode 4).
68
60
98
82
61
97
83
L8
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
122
98
E10
K11
K8
SCK2_0
(SCL2_0)
Multifunction serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL2 when it is
used in an I2C (operation mode 4).
69
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
121
99
F13
J13
Multi
Function
Serial
3
SIN3_0
SIN3_1
SIN3_2
70
13
58
62
13
50
P8
E5
M5
Multifunction serial interface ch.3
input pin
SOT3_0
(SDA3_0)
Multifunction serial interface ch.3
output pin.
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA3 when it is
used in an I2C (operation mode 4).
71
14
59
72
15
60
63
14
51
64
15
52
J8
F1
L5
P9
F2
K5
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
Multifunction serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL3 when it is
used in an I2C (operation mode 4).
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Document Number: 002-05665 Rev. *D
Page 42 of 142
MB9B320TA Series
Pin No.
LQFP-176 LQFP-144
Pin
Pin name
SIN4_0
Function description
function
BGA-192
C6
Multi
165
100
8
135
84
8
Multifunction serial interface ch.4
input pin
Function
Serial
4
SIN4_1
SIN4_2
J12
D3
SOT4_0
(SDA4_0)
Multifunction serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA4 when it is
used in an I2C (operation mode 4).
164
101
9
134
85
9
B6
J11
D4
F7
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
Multifunction serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL4 when it is
used in an I2C (operation mode 4).
163
102
10
133
86
10
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
J10
E2
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_1
SIN5_2
161
104
12
131
88
12
132
87
11
D7
H10
E4
E7
J9
Multifunction serial interface ch.4 RTS
output pin
162
103
11
Multifunction serial interface ch.4 CTS
input pin
E3
C5
B10
J3
Multi
Function
Serial
5
169
141
34
139
-
Multifunction serial interface ch.5
input pin
26
SOT5_0
(SDA5_0)
Multifunction serial interface ch.5
output pin.
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA5 when it is
used in an I2C (operation mode 4).
168
142
35
138
-
B5
SOT5_1
(SDA5_1)
C10
J2
SOT5_2
(SDA5_2)
27
137
-
SCK5_0
(SCL5_0)
Multifunction serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL5 when it is
used in an I2C (operation mode 4).
167
143
36
E6
SCK5_1
(SCL5_1)
D10
K1
SCK5_2
(SCL5_2)
28
Document Number: 002-05665 Rev. *D
Page 43 of 142
MB9B320TA Series
Pin No.
LQFP-144
16
Pin
Pin name
SIN6_0
Function description
function
LQFP-176
16
BGA-192
Multi
F3
H6
B4
Multifunction serial interface ch.6
input pin
Function
Serial
6
SIN6_1
SIN6_2
31
-
-
170
SOT6_0
(SDA6_0)
Multifunction serial interface ch.6
output pin.
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA6 when it is
used in an I2C (operation mode 4).
17
17
-
F4
H5
C4
F5
H4
B3
SOT6_1
(SDA6_1)
SOT6_2
(SDA6_2)
30
171
18
-
SCK6_0
(SCL6_0)
Multifunction serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL6 when it is
used in an I2C (operation mode 4).
18
-
SCK6_1
(SCL6_1)
SCK6_2
(SCL6_2)
29
172
-
Multi
Function
Serial
7
SIN7_0
SIN7_1
SIN7_2
22
22
56
-
G4
K6
Multifunction serial interface ch.7
input pin
64
106
H13
SOT7_0
(SDA7_0)
Multifunction serial interface ch.7
output pin.
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA7 when it is
used in an I2C (operation mode 4).
23
23
55
-
G5
SOT7_1
(SDA7_1)
63
L6
SOT7_2
(SDA7_2)
107
24
H12
G6
SCK7_0
(SCL7_0)
Multifunction serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL7 when it is
used in an I2C (operation mode 4).
24
54
-
SCK7_1
(SCL7_1)
62
M6
H11
SCK7_2
(SCL7_2)
108
Document Number: 002-05665 Rev. *D
Page 44 of 142
MB9B320TA Series
Pin No.
LQFP-144
Pin
Pin name
SIN8_0
Function description
function
LQFP-176
BGA-192
Multi
Multifunction serial interface ch.8
input pin
2
2
B2
C2
Function
Serial
8
Multifunction serial interface ch.6
output pin.
SOT8_0
(SDA8_0)
This pin operates as SOT8 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA8 when it is
used in an I2C (operation mode 4).
3
3
Multifunction serial interface ch.7
clock I/O pin.
SCK8_0
(SCL8_0)
This pin operates as SCK8 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL8 when it is
used in an I2C (operation mode 4).
4
5
6
4
5
6
C3
D5
D2
Multi
Function
Serial
9
Multifunction serial interface ch.9
input pin
SIN9_0
Multifunction serial interface ch.9
output pin.
This pin operates as SOT9 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA9 when it is
used in an I2C (operation mode 4).
SOT9_0
(SDA9_0)
Multifunction serial interface ch.9
clock I/O pin.
SCK9_0
(SCL9_0)
This pin operates as SCK9 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL9 when it is
used in an I2C (operation mode 4).
7
7
D1
Document Number: 002-05665 Rev. *D
Page 45 of 142
MB9B320TA Series
Pin No.
LQFP-144
Pin
Pin name
SIN10_0
Function description
function
LQFP-176
46
BGA-192
Multi
Multifunction serial interface ch.10
input pin
38
N2
N3
Function
Serial
10
Multifunction serial interface ch.10
output pin.
SOT10_0
(SDA10_0)
This pin operates as SOT10 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA10 when it
is used in an I2C (operation mode 4).
47
39
Multifunction serial interface ch.10
clock I/O pin.
SCK10_0
(SCL10_0)
This pin operates as SCK10 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL10 when it
is used in an I2C (operation mode 4).
48
49
50
40
41
42
M3
L4
Multi
Multifunction serial interface ch.11
input pin
SIN11_0
Function
Serial
11
Multifunction serial interface ch.11
output pin.
This pin operates as SOT11 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA11 when it
is used in an I2C (operation mode 4).
SOT11_0
(SDA11_0)
M4
Multifunction serial interface ch.11
clock I/O pin.
SCK11_0
(SCL11_0)
This pin operates as SCK11 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL11 when it
is used in an I2C (operation mode 4).
51
43
N4
Document Number: 002-05665 Rev. *D
Page 46 of 142
MB9B320TA Series
Pin No.
LQFP-144
Pin
Pin name
SIN12_0
Function description
function
LQFP-176
BGA-192
F10
Multi
Multifunction serial interface ch.12
input pin
118
94
Function
Serial
12
Multifunction serial interface ch.12
output pin.
SOT12_0
(SDA12_0)
This pin operates as SOT12 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA12 when it
is used in an I2C (operation mode 4).
119
95
F11
Multifunction serial interface ch.12
clock I/O pin.
SCK12_0
(SCL12_0)
This pin operates as SCK12 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL12 when it
is used in an I2C (operation mode 4).
120
145
146
96
F12
C9
Multi
Multifunction serial interface ch.13
input pin
SIN13_0
115
116
Function
Serial
13
Multifunction serial interface ch.13
output pin.
This pin operates as SOT13 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA13 when it
is used in an I2C (operation mode 4).
SOT13_0
(SDA13_0)
B8
Multifunction serial interface ch.13
clock I/O pin.
SCK13_0
(SCL13_0)
This pin operates as SCK13 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL13 when it
is used in an I2C (operation mode 4).
147
117
D9
Document Number: 002-05665 Rev. *D
Page 47 of 142
MB9B320TA Series
Pin No.
Pin
Pin name
SIN14_0
Function description
function
LQFP-176
LQFP-144
BGA-192
Multi
Multifunction serial interface ch.14
input pin
149
119
F9
C8
Function
Serial
14
Multifunction serial interface ch.14
output pin.
SOT14_0
(SDA14_0)
This pin operates as SOT14 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA14 when it
is used in an I2C (operation mode 4).
150
120
Multifunction serial interface ch.14
clock I/O pin.
SCK14_0
(SCL14_0)
This pin operates as SCK14 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL14 when it
is used in an I2C (operation mode 4).
151
153
154
121
123
124
D8
Multi
Multifunction serial interface ch.15
input pin
SIN15_0
A10
F8
Function
Serial
15
Multifunction serial interface ch.15
output pin.
This pin operates as SOT15 when it is
used in a UART/CSIO/LIN (operation
modes 0 to 3) and as SDA15 when it
is used in an I2C (operation mode 4).
SOT15_0
(SDA15_0)
Multifunction serial interface ch.15
clock I/O pin.
SCK15_0
(SCL15_0)
This pin operates as SCK15 when it is
used in a UART/CSIO (operation
modes 0 to 2) and as SCL15 when it
is used in an I2C (operation mode 4).
155
125
B7
Document Number: 002-05665 Rev. *D
Page 48 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
DTTI0X_0
Function description
function
LQFP-176
37
BGA-192
K2
Multi
Input signal controlling wave form
generator outputs RTO00 to RTO05
of multi-function timer 0.
29
Function
Timer
0
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
104
32
88
-
H10
J5
16-bit free-run timer ch.0 external
clock input pin
105
91
89
75
28
84
76
27
85
77
26
86
78
-
H9
M12
K1
36
100
92
J12
L13
J2
35
101
93
J11
L12
J3
16-bit input capture ch.0 input pin of
multi-function timer 0.
ICxx describes channel number.
34
102
94
J10
L11
J4
33
103
95
87
79
J9
K13
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
Wave form generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
38
30
100
31
99
32
98
33
97
34
96
35
95
K3
124
39
E12
K4
RTO01_0
(PPG00_0)
Wave form generator output of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
RTO01_1
(PPG00_1)
123
40
E11
L1
RTO02_0
(PPG02_0)
Wave form generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
RTO02_1
(PPG02_1)
122
41
E10
L2
RTO03_0
(PPG02_0)
Wave form generator output of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
RTO03_1
(PPG02_1)
121
42
F13
L3
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
Wave form generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
120
43
F12
M2
F11
RTO05_0
(PPG04_0)
Wave form generator output of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
RTO05_1
(PPG04_1)
IGTRG0_0
119
61
53
N6
B3
PPG IGBT mode external trigger input
pin
IGTRG0_1
172
140
Document Number: 002-05665 Rev. *D
Page 49 of 142
MB9B320TA Series
Pin No
LQFP-144
Pin
Pin name
AIN0_0
Function description
function
LQFP-176
BGA-192
Quadrature
Position/
Revolution
Counter
0
28
-
H3
L5
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
ZIN1_1
ZIN1_2
UDM0
QPRC ch.0 AIN input pin
59
51
13
-
13
E5
H4
K5
F1
H5
N6
F2
N9
29
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
60
52
14
-
14
30
61
53
15
65
103
54
66
102
55
67
101
56
142
143
15
Quadrature
Position/
Revolution
Counter
1
73
127
62
D13
M6
M9
D12
L6
74
126
63
75
L9
125
64
E13
K6
USB
USB ch.0 Device/Host D – pin
174
175
A3
UDP0
USB ch.0 Device/Host D + pin
A2
USB ch.0
USB external pull-up control pin
UHCONX
168
138
B5
Real-time
clock
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
152
93
122
77
E8
0.5 seconds pulse output pin of
Real-time clock
L12
K2
37
29
152
93
122
77
E8
Sub clock output pin
L12
K2
37
29
Document Number: 002-05665 Rev. *D
Page 50 of 142
MB9B320TA Series
Pin No
Pin
Pin name
INITX
Function description
function
LQFP-176
LQFP-144
BGA-192
N5
Reset
External Reset Input. A reset is valid
when INITX="L".
57
49
Mode
Mode 0 Pin.
During normal operation, MD0="L"
must be input. During serial
programming to Flash memory,
MD0="H" must be input.
MD0
MD1
85
84
69
68
N12
N13
Mode 1 Pin.
During serial programming to Flash
memory, MD1="L" must be input.
Power
1
1
C1
45
54
89
37
46
73
N1
P4
M14
VCC
Power supply Pin
131
133
107
109
126
141
C14
A13
A9
156
173
USBVCC
WKUP0
3.3V Power supply port for USB I/O
A4
Low-Power
Consumption
Mode
Deep standby mode return signal
input pin 0
128
91
104
75
C13
M12
M8
B3
Deep standby mode return signal
input pin 1
WKUP1
WKUP2
WKUP3
WKUP4
WKUP5
Deep standby mode return signal
input pin 2
67
59
Deep standby mode return signal
input pin 3
172
28
140
-
Deep standby mode return signal
input pin 4
H3
Deep standby mode return signal
input pin 5
169
139
C5
HDMI-
CEC/
Remote
Control
Reception
CEC0_0
CEC0_1
CEC1_0
81
-
M10
F9
HDMI-CEC/Remote Control
Reception ch.0 input/output pin
149
172
119
140
B3
HDMI-CEC/Remote Control
Reception ch.1 input/output pin
CEC1_1
DA0_0
DA1_0
19
19
F6
C9
B8
DAC
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
145
146
115
116
Document Number: 002-05665 Rev. *D
Page 51 of 142
MB9B320TA Series
Pin No
LQFP-144
25
Pin
Pin name
Function description
function
LQFP-176
BGA-192
GND
27
44
A5
A8
36
45
A11
E1
53
72
88
108
G7
G8
H8
M1
P3
132
127
157
144
176
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P7
N7
M7
L7
VSS
GND Pin
K7
J7
P11
N14
L14
B14
H7
B1
G1
J1
Clock
X0
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
86
70
P12
P5
X0A
X1
55
47
87
71
P13
P6
X1A
56
48
CROUT_0
CROUT_1
127
152
103
122
D13
E8
Built-in high-speed CR-osc clock
output port
Analog
Power
A/D converter, D/A converter analog
power pin
AVCC
114
117
90
J14
A/D converter analog reference
voltage input pin
AVRH
AVSS
AVRL
93
91
92
F14
H14
G14
Analog
GND
A/D converter, D/A converter GND pin 115
A/D converter analog reference
voltage input pin
116
C pin
Power supply stabilization capacity
pin
C
52
44
P2
*: 5V tolerant I/O
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05665 Rev. *D
Page 52 of 142
MB9B320TA Series
5. I/O Circuit Type
Type
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
A
Pull-up
resistor
When the main oscillation is selected.
P-ch
P-ch
Digital output
Digital output
• Oscillation feedback resistor
: Approximately 1 MΩ
• With Standby mode control
X1
When the GPIO is selected.
N-ch
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-05665 Rev. *D
Page 53 of 142
MB9B320TA Series
Type
Circuit
Remarks
C
• Open drain output
• CMOS level hysteresis input
Digital input
Digital output
N-ch
It is possible to select the sub
oscillation / GPIO function
D
Pull-up
resistor
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 5 MΩ
P-ch
P-ch
Digital output
X1A
• With Standby mode control
When the GPIO is selected.
• CMOS level output.
N-ch
Digital output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05665 Rev. *D
Page 54 of 142
MB9B320TA Series
Type
Circuit
Remarks
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
P-ch
P-ch
Digital output
Digital output
• +B input available
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -12 mA, IOL= 12 mA
• +B input available
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05665 Rev. *D
Page 55 of 142
MB9B320TA Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Digital output
Digital output
P-ch
P-ch
N-ch
• +B input available
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
H
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog output
P-ch
P-ch
Digital output
Digital output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
N-ch
Pull-up resistor control
Digital input
R
Standby mode Control
Analog output
Document Number: 002-05665 Rev. *D
Page 56 of 142
MB9B320TA Series
Type
Circuit
Remarks
I
• CMOS level output
• CMOS level hysteresis input
• 5V tolerant
• With pull-up resistor control
• With standby mode control
P-ch
P-ch
Digital output
Digital output
• Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
CMOS level hysteresis input
J
Mode input
It is possible to select the USB I/O /
GPIO function.
K
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
When the USB I/O is selected.
• Full-speed, Low-speed control
GPIO Digital input circuit control
When the GPIO is selected.
UDP output
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
UDP0/P81
USB Full-speed/Low-speed control
UDP input
Differential
UDM0/P80
Differential input
USB/GPIO select
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-05665 Rev. *D
Page 57 of 142
MB9B320TA Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. (Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05665 Rev. *D
Page 58 of 142
MB9B320TA Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05665 Rev. *D
Page 59 of 142
MB9B320TA Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05665 Rev. *D
Page 60 of 142
MB9B320TA Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to
fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size :
More than 3.2 mm × 1.5 mm
Load capacitance : Approximately 6 pF to 7 pF
Lead type
Load capacitance : Approximately 6 pF to 7 pF
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as
External clock
input
Can be used as
general-purpose
I/O ports.
X1(PE3),
X1A (P47)
Document Number: 002-05665 Rev. *D
Page 61 of 142
MB9B320TA Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → USBVCC
VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
USBVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Document Number: 002-05665 Rev. *D
Page 62 of 142
MB9B320TA Series
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Adjoining wiring on circuit board
If wiring of the crystal oscillation circuit (X0/X1 and X0A/X1A) adjoins and also runs in parallel with the wiring of GPIO, there is a
possibility that the oscillation erroneously counts because oscillation wave has noise with the change of GPIO. Keep as much
distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility.
Document Number: 002-05665 Rev. *D
Page 63 of 142
MB9B320TA Series
8. Block Diagram
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
TPIU
ETM
SRAM0
80/96 Kbytes
ROM
Table
TRACEDx,
TRACECLK
I
SRAM1
80/96 Kbytes
D
NVIC
Sys
Flash I/F
Security
On-Chip Flash
1 Mbytes+64 Kbytes/
1.5 Mbytes+64 Kbytes
Dual-Timer
WatchDog Timer
(Software)
USB2.0
(Host
/Device)
UDP0/UDM0
UHCONX
PHY
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
X0
X1
Main
Source Clock
CR
PLL
CR
Osc
Sub
Osc
X0A
X1A
4 MHz 100 kHz
CROUT
MADx
AVCC,
AVSS,
AVRH
MADATAx
External Bus I/F
12-bit A/D Converter
Unit 0
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT
ANxx
Unit 1
ADTGx
USB Clock Ctrl
LVD Ctrl
PLL
TIOAx
TIOBx
Base Timer
16-bit 16ch./
32-bit 8ch.
Power-On
Reset
LVD
Regulator
C
IRQ-Monitor
CRC Accelerator
Watch Counter
AINx
BINx
ZINx
QPRC
2ch.
WKUPx
Deep Standby Ctrl
A/D Activation Compare
2ch.
CEC0_x,
CEC1_x
HDMI-CEC/
Remote Reciver Control
16-bit Input Capture
4ch.
IC0x
RTCCO,
SUBOUT
Real-Time Clock
External Interrupt
Controller
32pin + NMI
16-bit Free-run Timer
3ch.
FRCK0
INTx
NMIX
16-bit Output Compare
6ch.
MD0,
MD1
P0x,
P1x,
DTTI0X
RTO0x
MODE-Ctrl
GPIO
Waveform Generator
3ch.
.
.
.
PIN-Function-Ctrl
PFx
SCKx
SINx
SOTx
CTS4
RTS4
16-bit PPG
3ch.
IGTRGx
Multi-function Serial I/F
16ch.
HW flow control(ch.4)
Multi-function Timer × 1
9. Memory Size
See "Memory size" in "Product Lineup" to confirm the memory size.
Document Number: 002-05665 Rev. *D
Page 64 of 142
MB9B320TA Series
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
DMAC
Reserved
USB ch.0
EXT-bus I/F
Reserved
Reserved
RTC
Watch Counter
CRC
0x7000_0000
0x6000_0000
External Device
Area
MFS
Reserved
Reserved
USB Clock Ctrl
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
GPIO
0x4400_0000
32Mbytes
Bit band alias
0x4200_0000
0x4000_0000
0x2400_0000
0x2200_0000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
Peripherals
Reserved
Reserved
Int-Req.Read
EXTI
32Mbytes
Bit band alias
Reserved
CR Trim
Reserved
Reserved
D/AC
A/DC
0x2001_8000
0x2000_0000
0x1FFE_8000
SRAM1
SRAM0
QPRC
Base Timer
PPG
Reserved
0x0051_8000
0x0050_8000
0x0040_4000
0x0040_0000
Flash(Work area)
Reserved
Reserved
See "lMemory map(2)" for
the memory size details.
Security/CR Trim
0x4002_1000
0x4002_0000
MFT unit0
Reserved
0x4001_6000
0x4001_5000
Flash(Main area)
Dual Timer
Reserved
0x0000_0000
0x4001_3000
0x4001_2000
SW WDT
HW WDT
0x4001_1000
0x4001_0000
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-05665 Rev. *D
Page 65 of 142
MB9B320TA Series
Memory Map (2)
MB9BF329SA/TA
MB9BF328SA/TA
0x2008_0000
0x2001_8000
0x2008_0000
0x2001_4000
Reserved
Reserved
SRAM1
80Kbytes
SRAM1
64Kbytes
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_4000
0x2000_0000
0x1FFF_C000
SRAM1ꢀ16Kbytes*
SRAM0ꢀ16Kbytes*
SRAM1ꢀ16Kbytes*
SRAM0ꢀ16Kbytes*
SRAM0
64Kbytes
SRAM0
80Kbytes
0x1FFE_C000
0x1FFE_8000
Reserved
Reserved
ROM1_SA0-7(8KBx8)
Reserved
0x0051_8000
0x0050_8000
0x0051_8000
0x0050_8000
ROM1_SA0-7(8KBx8)
Reserved
0x0040_4000
0x0040_2000
0x0040_0000
0x0040_4000
0x0040_2000
0x0040_0000
CR trimming
Security
CR trimming
Security
Reserved
Reserved
0x0018_0000
0x0010_0000
ROM1_SA8_15(64KBx8)
0x0010_0000
ROM0_SA9-23(64KBx15)
ROM0_SA9-23(64KBx15)
ROM0_SA8(48KB)
ROM0_SA8(48KB)
ROM0_SA2-3(8KBx2)
ROM0_SA2-3(8KBx2)
0x0000_0000
0x0000_0000
The content of SRAM can be retained at the deep standby modes by the setting of Deep Standby RAM Retention Register
(DSRAMR).
See "MB9B520T/420T/320T/120T Series Flash Programming Manual" for sector structure of Flash.
Document Number: 002-05665 Rev. *D
Page 66 of 142
MB9B320TA Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
Flash Memory I/F register
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_F000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_8FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_EFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x400F_FFFF
AHB
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Reserved
PPG
Base Timer
Quadrature Position/Revolution Counter (QPRC)
A/D Converter
APB1
D/A Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Resister
Reserved
GPIO
HDMI-CEC/Remote control Reception
Low-Voltage Detector
Deep standby mode Controller
USB clock generator
Reserved
APB2
Multi-function serial Interface
CRC
Watch Counter
Real-time clock
Reserved
External bus interface
USB ch.0
Reserved
AHB
DMAC register
Reserved
Document Number: 002-05665 Rev. *D
Page 67 of 142
MB9B320TA Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05665 Rev. *D
Page 68 of 142
MB9B320TA Series
List of Pin Status
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from Deep
standby
Run mode
or SLEEP
mode state
Timer mode,
RTC mode, or
STOP mode state
INITX
input state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 0
-
INITX = 1
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
GPIO
selected
A
Main crystal
oscillator
input pin/
External
main clock
input
Input
Input
Input
Input
Input
Input
Input
Input
Input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
selected
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
External
main clock
input
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
selected
B
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Whe
n
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Hi-Z /
Internal
input
fixed at
"0"
Main crystal
oscillator
output pin
Internal input
fixed at "0"/
or Input
Hi-Z /
Internal input
fixed at "0"
oscillatio
oscillatio
oscillatio
n stops*1, n stops*1, n stops*1,
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
enable
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
INITX
input pin
C
D
Input
enabled
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Document Number: 002-05665 Rev. *D
Page 69 of 142
MB9B320TA Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from Deep
standby
Run mode
or SLEEP
mode state
Timer mode,
RTC mode, or
STOP mode state
INITX
input state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 0
-
INITX = 1
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
GPIO
selected
F
Sub crystal
oscillator
input pin /
External sub
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z/
External sub
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
Maintain
previous
state/When
oscillation
stops*2,
Hi-Z/
Internal
input fixed
at "0"
G
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Wh
en
Maintain
previous
state/Whe
n
oscillation
stops*2,
Hi-Z/
Internal
input fixed
at "0"
Hi-Z /
Hi-Z /
Internal
input
fixed at
"0"
Sub crystal
oscillator
output pin
Internal input
fixed at "0"/
or Input
Hi-Z /
Internal input
fixed at "0"
Maintain
previous
state
oscillatio
oscillatio
oscillatio
n stops*2, n stops*2, n stops*2,
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z/
Internal
input
fixed at
"0"
enable
Document Number: 002-05665 Rev. *D
Page 70 of 142
MB9B320TA Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from Deep
standby
Run mode
or SLEEP
mode state
Timer mode,
RTC mode, or
STOP mode state
INITX
input state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 0
-
INITX = 1
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Maintain
previous
state
NMIX
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
WKUP
input
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
H
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
enabled
Hi-Z
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input
fixed at
"0"
I
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
GPIO
selected
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Resource
selected
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Internal
input fixed
at "0"
GPIO
selected
J
Hi-Z
GPIO
selected
External
interrupt
enabled
selected
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
Internal
input fixed
at "0"
GPIO
selected
K
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z
selected
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Internal
input fixed
at "0" /
Analog
input
Internal input
fixed at "0" /
Analog input
enabled
Analog input
selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
L
Resource
other than
above
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
GPIO
selected
selected
GPIO
selected
Document Number: 002-05665 Rev. *D
Page 71 of 142
MB9B320TA Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from Deep
standby
Run mode
or SLEEP
mode state
Timer mode,
RTC mode, or
STOP mode state
INITX
input state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 0
-
INITX = 1
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Internal
input fixed
at "0" /
Analog
input
Internal input
fixed at "0" /
Analog input
enabled
Analog input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
enabled
External
interrupt
enabled
selected
M
Maintain
previous
state
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
GPIO
selected
Hi-Z /
Internal
input
selected
fixed at
"0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
Internal
input fixed
at "0" /
Analog
input
Internal input
fixed at "0" /
Analog input
enabled
Analog input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
WKUP
input
WKUP
input
enabled
WKUP
enabled
N
Maintain
previous
state
enabled
External
interrupt
enabled
selected
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Resource
other than
above
Internal
input fixed
at "0"
Hi-Z /
Internal
input
selected
fixed at
"0"
GPIO
selected
Document Number: 002-05665 Rev. *D
Page 72 of 142
MB9B320TA Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from Deep
standby
Run mode
or SLEEP
mode state
Timer mode,
RTC mode, or
STOP mode state
INITX
input state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 0
-
INITX = 1
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Analog
output
selected
Setting
disabled
Setting
disabled
Setting
disabled
*3
*4
GPIO
selected
Internal
input
fixed at
"0"
Resource
other than
above
Hi-Z /
Maintain
previous
state
Internal
input fixed
at "0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
O
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
selected
Hi-Z
GPIO
selected
Trace
selected
Setting
disabled
Setting
disabled
Setting
disabled
Trace
output
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
Internal
input fixed
at "0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
P
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
selected
Hi-Z
GPIO
selected
Trace
selected
Trace
output
Setting
disabled
Setting
disabled
Setting
disabled
External
interrupt
enabled
selected
Maintain
previous
state
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Internal
input fixed
at "0"
GPIO
selected
Q
Resource
other than
above
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
selected
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
R
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at "0"
GPIO
selected
selected
Hi-Z
GPIO
selected
Document Number: 002-05665 Rev. *D
Page 73 of 142
MB9B320TA Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from Deep
standby
Run mode
or SLEEP
mode state
Timer mode,
RTC mode, or
STOP mode state
INITX
input state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 0
-
INITX = 1
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
External
interrupt
enabled
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input
fixed at
"0"
S
Hi-Z /
Resource
other than
above
Internal
input fixed
at "0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
selected
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Hi-Z /
WKUP
input
Maintain
previous
state
WKUP
input
enabled
WKUP
Setting
Setting
Setting
enabled
disabled
disabled
disabled
enabled
Maintain
previous
state
Maintain
previous
state
External
interrupt
enabled
selected
T
GPIO
selected
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Resource
other than
above
Internal
input fixed
at "0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
selected
Hi-Z
GPIO
selected
Hi-Z /
WKUP
input
WKUP
input
enabled
WKUP
enabled
Maintain
previous
state
enabled
Setting
disabled
Setting
disabled
Setting
disabled
External
interrupt
enabled
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
GPIO
selected
Internal
input
fixed at
"0"
U
Hi-Z /
Resource
other than
above
Internal
input fixed
at "0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
selected
GPIO
selected
Document Number: 002-05665 Rev. *D
Page 74 of 142
MB9B320TA Series
Power-on
reset or
low-voltage
detection
state
Device
internal
reset
Deep standby
RTC mode or Deep
standby STOP mode
state
Return
from Deep
standby
Run mode
or SLEEP
mode state
Timer mode,
RTC mode, or
STOP mode state
INITX
input state
state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
-
-
INITX = 0
-
INITX = 1
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input
fixed at
"0"
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
GPIO
selected
Internal
input fixed
at "0"
GPIO
selected
Hi-Z
Hi-Z at
trans-
mission/
Input
Hi-Z at
trans-
mission/
Input
Maintain
previous
state
V
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
enabled/
Internal
input
enabled/
Internal
input
USB I/O pin
fixed at
"0" at
fixed at
"0" at
reception reception
*1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and
Deep standby STOP mode.
*2: Oscillation is stopped at STOP mode and Deep standby STOP mode.
*3: Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode.
*4: Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.
Document Number: 002-05665 Rev. *D
Page 75 of 142
MB9B320TA Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Max
Symbol
VCC
Unit
Remarks
Min
Power supply voltage*1, *2
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
V
Power supply voltage (for USB)*1, * 3
Analog power supply voltage*1, *4
Analog reference voltage*1, *4
USBVCC
AVCC
V
V
V
AVRH
VCC + 0.5
(≤ 6.5V)
VSS - 0.5
VSS - 0.5
V
V
Except for USB pin
USB pin
USBVCC + 0.5
(≤ 6.5 V)
Input voltage*1
VI
VSS - 0.5
VSS - 0.5
VSS + 6.5
V
V
5V tolerant
5V tolerant*8
VSS + 3.63
AVCC + 0.5
(≤ 6.5 V)
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
V
V
VCC + 0.5
(≤ 6.5 V)
VSS - 0.5
-2
Clamp maximum current
ICLAMP
+2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*9
Clamp total maximum current
Σ[ICLAMP
]
+20
10
*9
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
"L" level maximum output current*5
"L" level average output current*6
IOL
-
-
20
39
4
IOLAV
12
16.5
100
50
"L" level total maximum output current
"L" level total average output current*7
∑IOL
-
-
∑IOLAV
- 10
- 20
- 39
- 4
4mA type
12mA type
P80, P81
4mA type
12mA type
P80, P81
"H" level maximum output current*5
"H" level average output current*6
IOH
-
-
IOHAV
- 12
- 18
- 100
- 50
390
+ 150
"H" level total maximum output current
"H" level total average output current*7
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*6: The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
*8: VCC = USBVCC = AVCC = AVRH = VSS = AVSS = AVRL = 0.0 V
Document Number: 002-05665 Rev. *D
Page 76 of 142
MB9B320TA Series
*9 :
• See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
resistor
Digital output
Digital input
+B input (0V to 16V)
N-ch
R
AVCC
Analog input
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
−
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-05665 Rev. *D
Page 77 of 142
MB9B320TA Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Max
5.5
Parameter
Symbol
VCC
Conditions
Unit
Remarks
Min
2.7*4
Power supply voltage
-
-
V
3.6
1
2
3.0
2.7
*
(≤ VCC
)
Power supply voltage (3V power
supply) for USB
USBVCC
V
5.5
*
(≤ VCC
)
Analog power supply voltage
Analog reference voltage
AVCC
AVRH
AVRL
CS
-
-
-
-
2.7
2.7
AVSS
1
5.5
V
AVCC = VCC
AVCC
AVSS
10
V
V
Smoothing capacitor
μF
°C
For built-in Regulator*3
Operating temperature
TA
-
- 40
+ 105
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: See "C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or
built-in Low-speed CR is possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05665 Rev. *D
Page 78 of 142
MB9B320TA Series
12.3 DC Characteristics
12.3.1 Current Rating
Symbol
Value
Typ*1 Max*2
Parameter
(Pin
Conditions
CPU: 60 MHz,
Unit
Remarks
name)
Peripheral: 30 MHz
29
37
mA
*3,*5
PLL
RUN mode
CPU: 60 MHz,
Peripheral clock stops
*3,*5
19
26
mA
CPU/ Peripheral: 4 MHz*4
*
High-speed CR
RUN mode
ICC
3.1
6.4
mA
µA
3
CPU/ Peripheral: 32 kHz
*3,*6
Sub
RUN mode
170
2300
CPU/ Peripheral: 100 kHz
*
Low-speed CR
RUN mode
210
2300
µA
3
Peripheral: 30 MHz
*3,*5
PLL
SLEEP mode
19
2.1
160
190
20
-
26
mA
mA
µA
Peripheral: 4 MHz*4
High-speed CR
SLEEP mode
5.1
2200
2200
75
3
*
ICCS
ICCH
ICCT
ICCR
Power
supply
current
Peripheral: 32 kHz
*3,*6
Sub
SLEEP mode
Peripheral: 100 kHz
Low-speed CR
SLEEP mode
µA
3
*
TA = + 25°C
μA
3
*
STOP mode
TA = + 105°C
1.3
5.5
6.5
95
mA
mA
mA
μA
3
*
TA = + 25°C
*3,*6
2.8
-
Main
TIMER mode
TA = + 105°C
*3,*6
TA = + 25°C
*3,*6
24
-
Sub
TIMER mode
TA = + 105°C
*3,*6
1.7
89
mA
μA
TA = + 25°C
*3,*6
21
-
RTC mode
TA = + 105°C
*3,*6
1.7
mA
*1: TA=+25℃,VCC= 3.3 V
*2: TA=+105℃,VCC=5.5 V
*3: When all ports are fixed.
*4: When setting it to 4 MHz by trimming.
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05665 Rev. *D
Page 79 of 142
MB9B320TA Series
Symbol
(Pin
name)
Value
Max*2
Parameter
Conditions
Unit
Remarks
Typ*1
TA = + 25°C,
When RAM is off
*
1.9
13
μA
3
TA = + 25°C,
When RAM is on(16 KB)*4
*
4.8
5.5
17
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
3
TA = + 25°C,
When RAM is on(32 KB) *4
20
3
*
Deep Standby
STOP mode
ICCHD
TA = + 105°C,
When RAM is off
300
320
330
14
3
*
TA = + 105°C,
When RAM is on(16 KB) *4
-
3
*
TA = + 105°C,
When RAM is on(32 KB) *4
Power
supply
current
3
*
TA = + 25°C,
When RAM is off
*3,*5
2.5
5.4
6.1
TA = + 25°C,
When RAM is on(16 KB) *4
*3,*5
18
TA = + 25°C,
When RAM is on(32 KB) *4
*3,*5
21
Deep Standby
RTC mode
ICCRD
TA = + 105°C,
When RAM is off
*3,*5
305
325
335
TA = + 105°C,
When RAM is on(16 KB) *4
*3,*5
-
TA = + 105°C,
When RAM is on(32 KB) *4
*3,*5
*1: VCC = 3.3 V
*2: VCC = 5.5 V
*3: When all ports are fixed and LVD off.
*4: For more information about RAM retention area, see "Memory Map (2)" in "Memory Map".
*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05665 Rev. *D
Page 80 of 142
MB9B320TA Series
Low-Voltage Detection Current
Symbol
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
(Pin
Conditions
Unit
Remarks
Min
Max
name)
-
-
0.13
0.13
0.3
μA
μA
For occurrence of reset
Low-Voltage
ICCLVD
(VCC)
detection circuit
(LVD) power
supply current
At operation
0.3
For occurrence of interrupt
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
Max
11.8
At ROM0
Write/Erase
-
-
9.9
mA
*1
*1
Flash memory
write/erase
current
ICCFLASH
(VCC)
VCC
At ROM1
Write/Erase
9.5
11.2
mA
*1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power supply
current (ICC).
In addition, When programming or erase in flash memory ROM0 and ROM1 at the same time, Flash Memory Write/Erase
current (ICCFLASH) of both ROM0 and ROM1 are added to the Power supply current (ICC).
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
mA
Remarks
name
Min
Max
0.9
At 1unit
operation
-
-
0.69
0.6
ICCAD
(VCC)
Power supply
current
AVCC
AVRH
At stop
35
μA
mA
μA
At 1unit
operation
AVRH=5.5 V
Reference
power supply
current
-
-
1.1
0.2
1.97
3.4
ICCAVRH
(VCC)
(AVRH)
At stop
Document Number: 002-05665 Rev. *D
Page 81 of 142
MB9B320TA Series
D/A Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
250
Typ
Max
380
At 1unit
operation
AVCC=3.3 V
315
μA
2
IDDA
*
(VCC)
At 1unit
operation
AVCC=5.0 V
Power supply
current*1
AVCC
380
-
475
-
580
30
μA
μA
IDSA
(VCC)
At stop
*1: No-load
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05665 Rev. *D
Page 82 of 142
MB9B320TA Series
12.3.2 Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
CMOS
"H" level
input
voltage
(hysteresis
input)
hysteresis
input pin,
MD0, MD1
-
-
-
-
VCC × 0.8
-
-
-
-
VCC + 0.3
V
V
V
V
VIHS
5V tolerant
input pin
VCC × 0.8
VSS - 0.3
VSS - 0.3
VSS + 5.5
VCC × 0.2
VCC × 0.2
CMOS
"L" level input
voltage
(hysteresis
input)
hysteresis
input pin,
MD0, MD1
VILS
5V tolerant
input pin
VCC ≥ 4.5 V,
IOH = - 4 mA
4mA type
VCC - 0.5
VCC - 0.5
-
VCC
V
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
"H" level
output
VOH
12mA type
P80, P81
4mA type
12mA type
-
-
-
-
VCC
V
V
V
V
V
VCC < 4.5 V,
IOH = - 8 mA
voltage
USBVCC ≥ 4.5 V,
IOH = - 18.0 mA
USBVCC < 4.5 V,
IOH = - 12.0 mA
USBVCC
0.4
-
USBVCC
VCC ≥ 4.5 V,
IOL = 4 mA
VSS
0.4
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
"L" level
output
VOL
VSS
0.4
VCC < 4.5 V,
IOL = 8 mA
voltage
USBVCC ≥ 4.5 V,
IOL = 16.5 mA
P80, P81
-
VSS
- 5
-
-
-
-
0.4
USBVCC < 4.5 V,
IOL = 10.5 mA
-
+ 5
μA
μA
CEC0_0,
CEC0_1,
CEC1_0,
CEC1_1
VCC = USBVCC
AVCC = AVRH =
VSS = AVSS
=
Input leak
current
IIL
+1.8
=
AVRL = 0.0 V
VCC ≥ 4.5 V
VCC < 4.5 V
Pull-up
resistance
value
33
-
50
-
90
RPU
Pull-up pin
kΩ
180
Document Number: 002-05665 Rev. *D
Page 83 of 142
MB9B320TA Series
Value
Typ
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
Other than
VCC,
USBVCC,
VSS,
AVCC,
AVSS,
AVRH,
AVRL
Input
capacitance
CIN
-
-
5
15
pF
Document Number: 002-05665 Rev. *D
Page 84 of 142
MB9B320TA Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
MHz
Remarks
name
Min
Max
48
VCC ≥ 4.5 V
VCC < 4.5 V
-
4
4
4
When crystal oscillator is
connected
20
Input frequency
Input clock cycle
FCH
tCYLH
-
48
MHz
ns
When using external clock
When using external clock
-
20.83
250
X0,
X1
PWH/tCYLH,
PWL/tCYLH
Input clock pulse
width
45
55
%
When using external clock
Input clock rising
time and falling
time
tCF,
tCR
-
-
5
ns
When using external clock
FCM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60
60
32
32
32
-
MHz
MHz
MHz
MHz
MHz
ns
Master clock
FCC
-
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
Internal operating
clock*1 frequency
FCP0
FCP1
FCP2
tCYCC
tCYCP0
tCYCP1
tCYCP2
-
-
-
16.7
31.25
31.25
31.25
-
ns
Internal operating
clock*1 cycle time
-
ns
-
ns
*1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.
X0
Document Number: 002-05665 Rev. *D
Page 85 of 142
MB9B320TA Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal oscillator is
connected*
-
-
32.768
-
kHz
Input frequency
Input clock cycle
1/ tCYLL
-
-
32
10
-
-
100
kHz
When using external clock
When using external clock
X0A,
X1A
tCYLL
-
31.25
μs
PWH/tCYLL,
PWL/tCYLL
Input clock pulse
width
45
-
55
%
When using external clock
*: For more information about crystal oscillator, see "Sub crystal oscillator" in "Handling Devices".
X0A
Document Number: 002-05665 Rev. *D
Page 86 of 142
MB9B320TA Series
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Symbol
Conditions
TA = + 25°C,
Unit
Remarks
Min
3.92
Max
4.08
4
4
4
4
4
4
4
4
-
3.6 V < VCC ≤ 5.5 V
TA = 0°C to + 85°C,
3.6 V < VCC ≤ 5.5 V
3.9
4.1
TA = -40°C to + 105°C,
3.6 V < VCC ≤ 5.5 V
3.88
3.94
3.92
3.9
4.12
4.06
4.08
4.1
When trimming*1
TA = + 25°C,
2.7 V ≤ VCC ≤ 3.6 V
Clock frequency
FCRH
MHz
TA = - 20°C to + 85°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 20°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = -40°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
3.88
2.8
4.12
5.2
TA = - 40°C to + 105°C
-
When not trimming
Frequency stability
time
2
tCRWT
-
30
μs
*
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the
trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
50
Typ
Max
150
Clock frequency
FCRL
-
100
kHz
Document Number: 002-05665 Rev. *D
Page 87 of 142
MB9B320TA Series
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
FPLLI
-
4
-
-
-
-
16
MHz
5
37
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLO
FCLKPLL
75
-
150
60
MHz
After the M frequency
division
USB clock frequency*3
FCLKSPLL
-
-
48
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
*3: For more information about USB clock, see "CHAPTER 2-2: USB Clock Generation" in "FM3 Family PERIPHERAL MANUAL
Communication Macro Part".
Document Number: 002-05665 Rev. *D
Page 88 of 142
MB9B320TA Series
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
FPLLI
-
100
3.8
19
-
-
μs
PLL input clock frequency
4
-
4.2
35
MHz
multipli
er
PLL multiplication rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLO
72
-
-
-
150
60
MHz
MHz
FCLKPLL
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been
trimmed.
Main PLL connection
Main PLL
Main clock (CLKMO)
PLL input
clock
PLL macro
clock
oscillation clock
(CLKPLL)
K
M
Main
PLL
High-speed CR clock (CLKHC)
divider
divider
N
divider
USB PLL connection
PLL input
clock
PLL macro
USB
clock
Main clock (CLKMO)
K
oscillation clock
M
USB PLL
divider
divider
N
divider
Document Number: 002-05665 Rev. *D
Page 89 of 142
MB9B320TA Series
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
500
Max
Reset input time
tINITX
INITX
-
-
ns
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Power supply shut down time
Power ramp rate
tOFF
dV/dt
tPRT
-
1
-
ms
*1
*2
VCC
VCC: 0.2 V to 2.70 V
-
0.9
0.46
1000 mV/ /µs
0.76 ms
Time until releasing power-on reset
*1: Vcc must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF > 1ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset (INTX) at power-up and at any brownout event per 12.4.6.
2.7V
VDH
VCC
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH : detection voltage of Low Voltage detection reset. See “12.8. Low-Voltage Detection Characteristics”
Document Number: 002-05665 Rev. *D
Page 90 of 142
MB9B320TA Series
12.4.8 External Bus Timing
External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Parameter
Symbol
Pin name
Conditions
Min
Max
VCC ≥ 4.5 V
-
-
50
MHz
MHz
Output frequency
tCYCLE
MCLKOUT*
VCC < 4.5 V
32
*: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL
MANUAL".
When external bus clock is not output, this characteristics does not give any effect on external bus operation.
MCLKOUT
External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
VIH
Conditions
Value
0.8 × VCC
Unit
Remarks
V
V
V
V
Signal input characteristics
VIL
0.2 × VCC
0.8 × VCC
0.2 × VCC
-
VOH
VOL
Signal output characteristics
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
Document Number: 002-05665 Rev. *D
Page 91 of 142
MB9B320TA Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Parameter
MOEX
Symbol
tOEW
Pin name
MOEX
Conditions
VCC ≥ 4.5 V
Min
Max
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min pulse width
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
-9
+9
MCSX[7:0],
MAD[24:0]
MCSX ↓ → Address
output delay time
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
-12
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
MOEX,
MAD[24:0]
MOEX ↑ →
Address hold time
0
MCLK×m-9
MCSX ↓ →
MOEX ↓ delay time
MCLK×m-12
MOEX,
MCSX[7:0]
MOEX ↑ →
MCSX ↑ time
0
MCLK×m-9
MCSX ↓ →
MDQM ↓ delay time
MCSX,
MDQM[1:0]
MCLK×m-12
20
38
Data set up →
MOEX ↑ time
MOEX,
MADATA[15:0]
-
MOEX ↑ →
Data hold time
MOEX,
MADATA[15:0]
tDH - OE
0
-
-
MWEX
Min pulse width
tWEW
MWEX
MCLK×n-3
0
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MWEX,
MAD[24:0]
MWEX ↑ → Address
output delay time
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL-DV
MCLK×n-9
MCSX ↓ →
MWEX ↓ delay time
MCLK×n-12
MWEX,
MCSX[7:0]
MWEX ↑ →
MCSX ↑ delay time
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCSX ↓→
MDQM ↓ delay time
MCSX,
MDQM[1:0]
MCSX ↓→
Data output time
MCSX,
MADATA[15:0]
MCLK-12
MCLK+12
MWEX ↑ →
Data hold time
MWEX,
MADATA[15:0]
tWEH - DX
0
MCLK×m+12
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Document Number: 002-05665 Rev. *D
Page 92 of 142
MB9B320TA Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7:0]
tCSL-AV
tOEH-AX
tCSL-AV
Address
Address
MAD[24:0]
tCSL-OEL
tOEW
MOEX
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
tDS-OE
tDH-OE
tWEH-DX
Invalid
RD
WD
MADATA[15:0]
tCSL-DV
Document Number: 002-05665 Rev. *D
Page 93 of 142
MB9B320TA Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Parameter
Symbol
tAV
Pin name
MCLK,
Conditions
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Address delay time
1
1
1
1
1
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAD[24:0]
9
tCSL
tCSH
tREL
tREH
tDS
12
9
MCLK,
MCSX[7:0]
MCSX delay time
MOEX delay time
12
9
12
9
MCLK,
MOEX
12
19
37
Data set up →
MCLK ↑ time
MCLK,
MADATA[15:0]
-
-
MCLK ↑ →
Data hold time
MCLK,
MADATA[15:0]
tDH
0
1
1
1
1
9
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
12
9
MCLK,
MWEX
MWEX delay time
12
9
12
9
MDQM[1:0]
delay time
MCLK,
MDQM[1:0]
12
MCLK+18
MCLK+24
18
MCLK ↑ →
Data output time
MCLK,
MADATA[15:0]
MCLK+1
1
MCLK ↑ →
Data hold time
MCLK,
MADATA[15:0]
24
Note:
−
When the external load capacitance CL = 30 pF.
Document Number: 002-05665 Rev. *D
Page 94 of 142
MB9B320TA Series
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
MAD[24:0]
MOEX
tAV
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
tWEL
MWEX
tDS
tDH
RD
MADATA[15:0]
Invalid
WD
tODS
Document Number: 002-05665 Rev. *D
Page 95 of 142
MB9B320TA Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Parameter
Multiplexed
Symbol
Pin name
Conditions
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
+10
+20
tALE-CHMADV
0
ns
ns
address delay time
MALE,
MADATA[15:0]
MCLK×n+0
MCLK×n+0
MCLK×n+12
MCLK×n+20
Multiplexed
address hold time
tCHMADH
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05665 Rev. *D
Page 96 of 142
MB9B320TA Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
tCHAL
Pin name
Conditions
VCC ≥ 4.5 V
Unit
Remarks
Min
Max
9
ns
ns
ns
ns
1
1
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
12
9
MCLK,
ALE
MALE delay time
tCHAH
12
MCLK ↑ →
Multiplexed
Address delay time
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
tCHMADV
1
1
tOD
ns
ns
MCLK,
MADATA[15:0]
MCLK ↑ →
Multiplexed
Data output time
tCHMADX
tOD
Note:
−
When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05665 Rev. *D
Page 97 of 142
MB9B320TA Series
NAND Flash Memory Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Parameter
MNREX
Symbol
Pin name
MNREX
Conditions
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
tNREW
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min pulse width
20
38
-
-
Data setup →
MNREX↑time
MNREX,
MADATA[15:0]
tDS – NRE
MNREX↑→
Data hold time
MNREX,
MADATA[15:0]
tDH – NRE
0
-
MCLK×m-9
MCLK×m+9
MNALE↑→
MNWEX delay time
MNALE,
MNWEX
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
MCLK×m-12 MCLK×m+12
MCLK×m-9 MCLK×m+9
MCLK×m-12 MCLK×m+12
MCLK×m-9 MCLK×m+9
MNALE↓→
MNWEX delay time
MNALE,
MNWEX
MNCLE↑→
MNWEX delay time
MNCLE,
MNWEX
MCLK×m-12 MCLK×m+12
MCLK×m+9
MNWEX↑→
MNCLE delay time
MNCLE,
MNWEX
0
MCLK×m+12
MNWEX
Min pulse width
MNWEX
MCLK×n-3
-
- 9
+ 9
MNWEX↓→
Data output time
MNWEX,
MADATA[15:0]
tNWEL – DV
tNWEH – DX
-12
+12
MCLK×m+11
MCLK×m+12
MNWEX↑→
Data hold time
MNWEX,
MADATA[15:0]
0
Note:
−
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16).
Document Number: 002-05665 Rev. *D
Page 98 of 142
MB9B320TA Series
NAND Flash Memory Read
MCLK
MNREX
MADATA[15:0]
Read
NAND Flash Memory Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-05665 Rev. *D
Page 99 of 142
MB9B320TA Series
NAND Flash Memory Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-05665 Rev. *D
Page 100 of 142
MB9B320TA Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
MCLK ↑
MRDY input
setup time
Symbol
Pin name Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5 V 19
VCC < 4.5 V 37
MCLK,
MRDY
tRDYI
-
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
·· · ·· ·
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-05665 Rev. *D
Page 101 of 142
MB9B320TA Series
12.4.9 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using
as TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data sheet.
Document Number: 002-05665 Rev. *D
Page 102 of 142
MB9B320TA Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
Baud Rate
-
-
-
-
8
-
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVI
tIVSHI
tSHIXI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Master
mode
SCKx,
SINx
-
-
-
-
SCKx,
SINx
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx
SCKx,
SOTx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
ns
ns
ns
SCKx,
SINx
Slave mode 10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
SCKx
Notes:
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05665 Rev. *D
Page 103 of 142
MB9B320TA Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
SOT
SIN
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05665 Rev. *D
Page 104 of 142
MB9B320TA Series
CSIO (SPI = 0, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
Baud Rate
-
-
-
-
8
-
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVI
- 30
50
0
+ 30
- 20
+ 20
ns
ns
ns
Master mode
SCKx,
SINx
tIVSLI
-
-
30
0
-
-
SCKx,
SINx
tSLIXI
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCKx,
SINx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05665 Rev. *D
Page 105 of 142
MB9B320TA Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
SOT
SIN
VOH
VOL
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05665 Rev. *D
Page 106 of 142
MB9B320TA Series
CSIO (SPI = 1, SCINV = 0)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
Baud Rate
-
-
-
-
8
-
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
ns
ns
ns
SCKx,
SINx
tIVSLI
tSLIXI
tSOVLI
50
-
-
-
30
-
-
-
Master mode
SCKx,
SINx
0
0
SCKx,
SOTx
SCKx
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx
SCKx,
SOTx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
ns
ns
ns
SCKx,
SINx
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
SCKx
Notes:
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05665 Rev. *D
Page 107 of 142
MB9B320TA Series
tSCYC
VOH
VOL
VOL
SCK
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05665 Rev. *D
Page 108 of 142
MB9B320TA Series
CSIO (SPI = 1, SCINV = 1)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
Baud Rate
-
-
-
-
8
-
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
-
-
-
30
-
-
-
ns
ns
ns
Master mode
SCKx,
SINx
0
0
SCKx,
SOTx
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCKx,
SINx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
−
−
The above characteristics apply to CLK synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05665 Rev. *D
Page 109 of 142
MB9B320TA Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
tR
V
SCK
V
V
IH
V
IH
IH
V
V
IL
IL
IL
tF
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXE
tIVSHE
V
IL
V
IL
IH
V
IH
V
Slave mode
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
Max
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
tSLSH
tCYCP + 10
-
ns
ns
ns
ns
tSHSL
tCYCP + 10
-
CL = 30 pF
tF
-
-
5
5
SCK rising time
tR
tF
tR
tSHSL
tSLSH
SCK
VIH
VIH
VIH
IL
IL
IL
V
V
V
Document Number: 002-05665 Rev. *D
Page 110 of 142
MB9B320TA Series
12.4.11 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
ADTG
Conditions
Unit
Remarks
Min
Max
A/D converter trigger input
1
-
2tCYCP
*
-
ns
FRCKx
ICxx
Free-run timer input clock
Input capture
tINH,
tINL
Input pulse width
1
DTTIxX
-
2tCYCP
*
-
-
-
-
ns
ns
ns
ns
Waveform generator
*2
*3
*4
2tCYCP + 100*1
External interrupt,
NMI
INTxx
500
500
WKUPx
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to,
see "Block Diagram" in this data sheet.
*2: When in RUN mode, in SLEEP mode.
*3: When in STOP mode, in TIMER mode.
*4: When in Deep standby RTC mode, in Deep standby STOP mode.
Document Number: 002-05665 Rev. *D
Page 111 of 142
MB9B320TA Series
12.4.12 Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Unit
Parameter
Symbol
Conditions
Min
Max
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
tAHL
tALL
tBHL
tBLL
-
-
-
-
Time from AIN pin "H" level
to BIN rise
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
Time from BIN pin "H" level
to AIN fall
Time from AIN pin "L" level
to BIN fall
Time from BIN pin "L" level
to AIN rise
Time from BIN pin "H" level
to AIN rise
2tCYCP
*
-
ns
Time from AIN pin "H" level
to BIN fall
Time from BIN pin "L" level
to AIN fall
Time from AIN pin "L" level
to BIN rise
ZIN pin "H" width
ZIN pin "L" width
tZHL
tZLL
QCR:CGSC="0"
QCR:CGSC="0"
Time from determined ZIN
level to AIN/BIN rise and
fall
tZABE
QCR:CGSC="1"
QCR:CGSC="1"
Time from AIN/BIN rise and
fall time to determined ZIN
level
tABEZ
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block Diagram"
in this data sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
Document Number: 002-05665 Rev. *D
Page 112 of 142
MB9B320TA Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05665 Rev. *D
Page 113 of 142
MB9B320TA Series
12.4.13 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Standard-mode
Min Max
100
Fast-mode
Min Max
Parameter
Symbol
Conditions
Unit
Remarks
SCL clock frequency
FSCL
0
0
400
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCLclock "L" width
SCLclock "H" width
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
(Repeated) START condition
setup time
tSUSTA
4.7
-
0.6
-
μs
SCL ↑ → SDA ↓
CL = 30 pF,
R = (Vp/IOL)*1
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
tSUDAT
tSUSTO
0
3.45*2
0
0.9*3
μs
ns
μs
Data setup time
250
4.0
-
-
100
0.6
-
-
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
tBUF
tSP
4.7
-
-
1.3
-
-
μs
4
4
Noise filter
-
2 tCYCP
*
2 tCYCP
*
ns
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05665 Rev. *D
Page 114 of 142
MB9B320TA Series
12.4.14 ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Min
Parameter
Symbol
Pin name
Conditions
VCC ≥ 4.5 V
Unit
Remarks
Max
2
10
TRACECLK,
TRACED[3:0]
Data hold
tETMH
ns
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
2
15
40
20
-
-
MHz
MHz
ns
TRACECLK
frequency
1/ tTRACE
-
TRACECLK
25
50
TRACECLK
clock cycle
tTRACE
-
ns
Note:
−
When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05665 Rev. *D
Page 115 of 142
MB9B320TA Series
12.4.15 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Max
Parameter
Symbol
Pin name
TCK,
Conditions
Unit
Remarks
Min
15
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
TMS, TDI setup time tJTAGS
TMS, TDI hold time tJTAGH
-
-
ns
ns
TMS, TDI
TCK,
TMS, TDI
15
-
-
25
45
TCK,
TDO
TDO delay time
tJTAGD
ns
VCC < 4.5 V
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05665 Rev. *D
Page 116 of 142
MB9B320TA Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C)
Value
Typ
Pin
Parameter
Resolution
Symbol
Unit
bit
Remarks
name
Min
Max
-
-
-
-
-
-
-
-
12
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
Conversion time
-
-
± 1.5
± 2.2
± 6
± 4.5
± 2.5
± 15
LSB
LSB
mV
mV
μs
-
-
AVRH = 2.7V to 5.5V
VZT
VFST
-
ANxx
ANxx
-
AVRH ± 5
-
AVRH ± 15
-
1.0*1
Sampling time*2
Ts
-
0.3
-
10
μs
Compare clock cycle*3
Tcck
Tstt
-
-
50
-
-
-
1000
1.0
ns
State transition time to
operation permission
μs
Analog input capacity
Analog input resistor
CAIN
RAIN
-
-
-
-
-
-
9.5
pF
1.62
2.35
4
AVCC ≥ 4.5V
kΩ
AVCC < 4.5V
Interchannel disparity
-
-
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
Analog port input leak current
Analog input voltage
ANxx
ANxx
-
5
AVRL
AVRH
AVCC
AVSS
AVRH 2.7
AVRL AVSS
V
Reference voltage
V
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 300ns, the value of compare time: 700 ns
(AVCC ≥ 4.5 V).
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family PERIPHERAL
MANUAL Analog Macro Part".
The register setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
Document Number: 002-05665 Rev. *D
Page 117 of 142
MB9B320TA Series
Comparator
ANxx
Rext
RAIN
Analog input pin
Analog signal
source
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN
:
Input resistor of A/D = 1.62 kΩ ch.0 to ch.7 at 4.5 V < AVCC < 5.5 V
Input resistor of A/D = 1.58 kΩ ch.8 to ch.15 at 4.5 V < AVCC < 5.5 V
Input resistor of A/D = 1.56 kΩ ch.16 to ch.23 at 4.5 V < AVCC < 5.5 V
Input resistor of A/D = 2.35 kΩ ch.0 to ch.7 at 2.7 V < AVCC < 4.5 V
Input resistor of A/D = 2.3 kΩ ch.8 to ch.15 at 2.7 V < AVCC < 4.5 V
Input resistor of A/D = 2.25 kΩ ch.16 to ch.23 at 2.7 V < AVCC < 4.5 V
Input capacity of A/D = 9.5 pF at 2.7 V < AVCC < 5.5 V
CAIN
:
Rext:
Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck:
Compare clock cycle
Document Number: 002-05665 Rev. *D
Page 118 of 142
MB9B320TA Series
Definition of 12-bit A/D Converter Terms
• Resolution:
• Integral Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
• Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
0x003
0x002
0x001
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVRL
AVRH
AVRL
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST – VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-05665 Rev. *D
Page 119 of 142
MB9B320TA Series
12.6 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C)
Value
Typ
Parameter
Resolution
Symbol Pin name
Unit
Remarks
Min
Max
-
-
-
10
bit
μs
μs
tc20
tc100
INL
0.47
2.37
- 4.0
0.58
2.90
-
0.69
3.43
+ 4.0
Load 20 pF
Conversion time
Load 100 pF
Integral Nonlinearity*1
LSB
Differential
DNL
VOFF
RO
- 0.9
-
+ 0.9
LSB
Nonlinearity*1,*2
DAx
-
-
10.0
+ 5.4
4.50
-
mV
mV
kΩ
Code is 0x000
Code is 0x3FF
D/A operation
D/A stop
Output Voltage offset
- 20.0
3.10
2.0
-
3.80
-
Analog output
impedance
MΩ
Output undefined
period
tR
-
-
70
ns
*1: No-load
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05665 Rev. *D
Page 120 of 142
MB9B320TA Series
12.7 USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 105°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
*1
Min
Max
Input "H" level voltage
VIH
VIL
-
-
-
2.0
USBVCC + 0.3
V
Input "L" level voltage
VSS - 0.3
0.2
0.8
-
V
V
*1
*2
Input
charact-
eristics
Differential input sensitivity VDI
Different common mode
VCM
-
0.8
2.5
3.6
0.3
V
V
V
*2
*3
*3
range
External
pull-down resistor 2.8
= 15 kΩ
Output "H" level voltage
VOH
VOL
External pull-up
0.0
Output "L" level voltage
UDP0,
UDM0
resistor = 1.5 kΩ
Crossover voltage
Rising time
VCRS
tFR
-
1.3
4
2.0
20
20
V
*4
*5
*5
Full-Speed
Full-Speed
ns
ns
Output
charact-
eristics
Falling time
tFF
4
Rising/falling time
matching
tFRFM
Full-Speed
90
111.11
%
*5
Output impedance
Rising time
ZDRV
tLR
Full-Speed
Low-Speed
Low-Speed
28
75
75
44
Ω
*6
*7
*7
300
300
ns
ns
Falling time
tLF
Rising/falling time
matching
tLRFM
Low-Speed
80
125
%
*7
*1: The switching threshold voltage of the Single-End-Receiver of USB I/O buffer is set as within VIL
(Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use the differential-Receiver to receive the USB differential data signal.
The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the
local ground reference level.
The voltage range above is said to be the common mode input voltage range.
Common mode input voltage [V]
Document Number: 002-05665 Rev. *D
Page 121 of 142
MB9B320TA Series
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to ground and 15 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
*5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Falling time
Rising time
Document Number: 002-05665 Rev. *D
Page 122 of 142
MB9B320TA Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28Ω to 44Ω. So, discrete series resistor (Rs)
addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25Ω to 30Ω (recommendation value 27Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistor.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Falling time
Rising time
See "Low-Speed Load (Compliance Load)" for conditions of the external load.
Document Number: 002-05665 Rev. *D
Page 123 of 142
MB9B320TA Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL = 200pF to
600pF
CL = 200pF to
600pF
Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-05665 Rev. *D
Page 124 of 142
MB9B320TA Series
12.8 Low-Voltage Detection Characteristics
12.8.1 Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Value
Unit
Remarks
Parameter
Symbol
Conditions
SVHR*1 = 00000
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
SVHR*1 = 01000
SVHR*1 = 01001
SVHR*1 = 01010
Min
2.25
2.30
2.39
Typ
2.45
Max
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.65
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
2.50
2.60
2.70
2.81
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Same as SVHR = 00000 value
2.48 2.70 2.92
Same as SVHR = 00000 value
2.58 2.80 3.02
Same as SVHR = 00000 value
2.76 3.00 3.24
Same as SVHR = 00000 value
2.94 3.20 3.46
Same as SVHR = 00000 value
3.31 3.60 3.89
Same as SVHR = 00000 value
3.40 3.70 4.00
Same as SVHR = 00000 value
3.68 4.00 4.32
Same as SVHR = 00000 value
3.77 4.10 4.43
Same as SVHR = 00000 value
3.86 4.20 4.54
Same as SVHR = 00000 value
LVD stabilization
wait time
*2
TLVDW
-
-
-
-
-
-
6432 × tCYCP
μs
μs
LVD detection
delay time
TLVDDL
200
*1: The SVHR bit of Low-voltage Detection Voltage Control Register (LVD_CTL) is initialized to “00000” by low-voltage detection
reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05665 Rev. *D
Page 125 of 142
MB9B320TA Series
12.8.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 105°C)
Value
Typ
2.80
Parameter
Symbol
Conditions
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
Unit
Remarks
Min
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
Max
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
LVD stabilization
wait time
*
TLVDW
-
-
-
-
-
-
6432 × tCYCP
μs
μs
LVD detection
delay time
TLVDDL
200
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05665 Rev. *D
Page 126 of 142
MB9B320TA Series
12.9 Flash Memory Write/Erase Characteristics
12.9.1 Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Unit
Remarks
Typ
Max
Large Sector
Small Sector
1.1
0.3
2.7
0.9
Sector erase
time
s
Includes write time prior to internal erase
Half word (16-bit) write time
Chip erase time
20
31
317
79
μs
Not including system-level overhead time
Includes write time prior to internal erase
s
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
12.9.2 Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
Remarks
1,000
20*
10*
10,000
*: At average + 85C
Document Number: 002-05665 Rev. *D
Page 127 of 142
MB9B320TA Series
12.10 Return Time from Low-Power Consumption Mode
12.10.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
SLEEP mode
Symbol
Unit
ns
Remarks
Typ
tCYCC
Max*
High-speed CR TIMER mode,
Main TIMER mode,
43
83
μs
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
310
534
620
724
μs
μs
Ticnt
RTC mode,
STOP mode
278
479
μs
298
288
543
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode,
Deep Standby STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05665 Rev. *D
Page 128 of 142
MB9B320TA Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family
PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the
Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3
Family PERIPHERAL MANUAL".
Document Number: 002-05665 Rev. *D
Page 129 of 142
MB9B320TA Series
12.10.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
SLEEP mode
Symbol
Unit
μs
Remarks
Typ
Max*
149
149
264
264
High-speed CR TIMER mode,
Main TIMER mode,
μs
PLL TIMER mode
Low-speed CR TIMER mode
Sub TIMER mode
318
308
248
298
288
603
583
443
543
523
μs
μs
μs
μs
μs
Trcnt
RTC/STOP mode
When RAM is off
When RAM is on
Deep Standby RTC mode,
Deep Standby STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
Document Number: 002-05665 Rev. *D
Page 130 of 142
MB9B320TA Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
−
−
The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family
PERIPHERAL MANUAL.
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the
Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3
Family PERIPHERAL MANUAL".
The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset
Timing in 4. AC Characteristics in Electrical Characteristics" for the detail on the time during the power-on
reset/low -voltage detection reset.
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or
the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock
stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05665 Rev. *D
Page 131 of 142
MB9B320TA Series
13.Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Main: 1 Mbyte
Work: 64 Kbyte
MB9BF328SAPMC-GK7E2
MB9BF329SAPMC-GK7E2
MB9BF328TAPMC-GK7E2
MB9BF329TAPMC-GK7E2
MB9BF328TABGL-GK7E1
MB9BF329TABGL-GK7E1
160 Kbyte
Plastic・LQFP,
144-pin (0.5mm pitch)
(LQS144)
Main: 1.5 Mbyte
Work: 64 Kbyte
192 Kbyte
160 Kbyte
192 Kbyte
160 Kbyte
192 Kbyte
Main: 1 Mbyte
Work: 64 Kbyte
Plastic・LQFP,
176-pin (0.5mm pitch)
(LQP176)
Tray
Main: 1.5 Mbyte
Work: 64 Kbyte
Main: 1 Mbyte
Work: 64 Kbyte
Plastic・FBGA,
192-pin (0.8mm pitch)
(LBE192)
Main: 1.5 Mbyte
Work: 64 Kbyte
Document Number: 002-05665 Rev. *D
Page 132 of 142
MB9B320TA Series
14.Package Dimensions
Package Type
LQFP 176
Package Code
LQP176
4
D
5
7
D1
132
89
89
132
133
133
88
88
E1
E
5
7
4
3
6
176
45
45
176
1
44
44
1
e
2
A-B
5
7
D
3
0.10
A-B
C
BOTTOM VIEW
0.20
C A-B D
b
0.08
C
D
8
TOP VIEW
2
A
c
9
A
SEATING
PLANE
A1
0.25
A'
b
L1
10
0.08
C
SECTION A-A'
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17
0.09
0.15
0.27
0.20
0.22
c
D
26.00 BSC
24.00 BSC
0.50 BSC
26.00 BSC
24.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0
0.75
0.70
8
L1
0.50
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
002-15150 **
Document Number: 002-05665 Rev. *D
Page 133 of 142
MB9B320TA Series
Package Type
Package Code
LQFP 144
LQS144
4
5
4
5
D
D
7
7
D1
D1
108
73
73
108
109
109
72
72
E1
E
E
E1
5
7
5
7
4
4
3
3
6
144
144
37
37
1
1
36
36
2
A-B
5
D
7
BOTTOM VIEW
e
3
0.10
C
0.20
C
A-B D
b
0.08
C
A-B
D
8
TOP VIEW
2
A
9
c
A
A1
SEATING
PLANE
0.25
L
b
L1
10
A'
SECTION A-A'
0.08
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.09 0.20
0.15
c
D
D1
e
22.00 BSC
20.00 BSC
0.50 BSC
E
22.00 BSC
20.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
002-13015 *A
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
Document Number: 002-05665 Rev. *D
Page 134 of 142
MB9B320TA Series
Package Type
Package Code
BGA 192
LBE192
002-13493 *A
Document Number: 002-05665 Rev. *D
Page 135 of 142
MB9B320TA Series
15.Errata
This chapter describes the errata for MB9B320T series. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
Initial Revision
MB9BF328TPMC-GE2, MB9BF329TPMC-GE2, MB9BF328TBGL-GE1,
MB9BF329TBGL-GE1, MB9BF328SPMC-GE2, MB9BF329SPMC-GE2
MB9BF328TPMC-GK7E2, MB9BF329TPMC-GK7E2, MB9BF328TBGL-GK7E1,
MB9BF329TBGL-GK7E1, MB9BF328SPMC-GK7E2, MB9BF329SPMC-GK7E2
15.2 Qualification Status
Product Status: In Production − Qual.
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Silicon Revision
Fix Status
[1] HDMI-CEC polling message issue
Refer to 15.1
Initial rev.
Fixed in Rev. A
15.4 Errata Detail
15.4.1 HDMI-CEC polling message issue
PROBLEM DEFINITION
Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node.
Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another
node.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This error always happens.
SCOPE OF IMPACT
MCU does not reply properly to another node.
WORKAROUND
The software workaround is applied to Error #1.
1. Store 0x0 to SFREE register.
2. Monitor CEC line with GPIO and wait until 1 lasts for the signal free time.
3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register.
It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F.
If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device
receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases:
Document Number: 002-05665 Rev. *D
Page 136 of 142
MB9B320TA Series
4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-A-2. Return back to step 2 above
If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps.
4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA
4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line
4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-B-4. Return back to step 2 above
For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The
specification says signal free time must be more than and equals to 5-bit.
FIX STATUS
This issue was fixed in Rev. A.
Document Number: 002-05665 Rev. *D
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MB9B320TA Series
16.Major Changes
Spansion Publication Number: DS706-00062
Page
Section
Change Results
Revision 0.1
-
-
-
Initial release
Revision 0.2
-
Company name and layout design change
Revision 1.0
-
-
Preliminary → Full Production
FEATURES
External Bus Interface
FEATURES
Added the descriptions as follows
Maximum area size : Up to 256 Mbytes
2
3
5
8
Corrected conversion time
A/D Converter
FEATURES
Multi-function Timer
Corrected the channel count of "A/D activation compare"
Added the footnote
PRODUCT LINEUP
Function
HANDLING DEVICES
Power supply pins
64
66
67
Added the description
BLOCK DIAGRAM
Corrected the figure
MEMORY MAP
Memory Map(1)
Corrected the Address of “External Device Area”
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
77
79
Added the Item of “Input Voltage”
2. Recommended Operating Conditions
Added the footnote
Corrected the Condition
Corrected the Value
Corrected the Remarks
Added the footnote
3.DC Characteristics
(1) Current Rating
80 - 82
84
89
(2) Pin Characteristics
Added the Item of “Input leak current”
Revised the values of “Time until releasing Power-on reset”
Corrected the figure
Corrected the Glossary
4. AC Characteristics
(6) Power-on Reset Timing
(9) CSIO Timing
Synchronous serial (SPI=1, SCINV=1)
Corrected the figure of “MS bit=1”
108
115
125
External clock (EXT=1):asynchronous only Corrected the figure
Corrected the Pins name
AN00 - AN23 → ANxx
5.12-bit A/D Converter
・Electrical characteristics for the A/D
converter
Corrected the Min Vale of “Conversion time”
Corrected the Min Vale of “Sampling time”
Corrected the Min Value of “Compare clock cycle”
Corrected the “State Transition time to operation permission”
Corrected the footnote
9. Electrical characteristics for the A/D
converter
Revised the values of “TBD”
(1) Write / Erase time
10. Return Time from Low-Power
Consumption Mode
(1) Return Factor: Interrupt/WKUP
Return Count Time
126
128
Revised the values of “TBD”
(2) Return Factor: Reset
Return Count Time
Revised the values of “TBD”
Document Number: 002-05665 Rev. *D
Page 138 of 142
MB9B320TA Series
Page
Section
Change Results
Revision 2.0
-
Changed the series name.
MB9B320T Series -> MB9B320TA Series
-
-
Changed the product name as follows.
MB9BF328SA, MB9BF329SA, MB9BF328TA, MB9BF329TA
-
Features
USB Interface
2
Added the description of PLL for USB
List of Pin Functions
· List of pin functions
42 to 49
56, 57
68
Added LIN to the description of SOTxx
Added about +B input
I/O Circuit Type
Memory Map
· Memory map(2)
Added the summary of Flash memory sector
· Added the Clamp maximum current
· Added about +B input
Electrical Characteristics
1. Absolute Maximum Ratings
77, 78
80, 81
Electrical Characteristics
3. DC Characteristics
(1) Current rating
· Changed the expression of condition
· Added Main TIMER mode current
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main and USB
PLL
· Added the figure of Main PLL connection and USB PLL
connection
88
(4-2) Operating Conditions of Main PLL
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
Electrical Characteristics
4. AC Characteristics
(7) CSIO/UART Timing
101 to
108
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition
voltage
Electrical Characteristics
5. 12bit A/D Converter
115
130
Ordering Information
Change to full part number
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05665 Rev. *D
Page 139 of 142
MB9B320TA Series
Document History
Document Title: MB9B320TA Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05665
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-05665.
No change to document contents or format.
**
-
TOYO
TOYO
01/30/2015
*A
5207566
04/05/2016 Updated to Cypress format.
Updated Cypress Logo
Corrected the package codes the following chapters as the table below.
2. Packages
3. Pin Assignment
13. Ordering Information
14. Package Dimensions
Before
After
FPT-144P-M08
FPT-176P-M07
BGA-192P-M06
LQS144
LQP176
LBE192
Corrected the following statement
USB Function USB Device
in chapter
Features (Page 1)
1. Product Lineup (Page 7)
4. List of Pin Functions (Page 50)
8. Block Diagram (Page 64)
Modified RTC description in chapter Features
Before
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute/Second/A day of the week.) is available.
After
*B
5653479
NOSU
03/10/2017
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute.) is available.
Corrected a word “J-TAG” to “JTAG” in 4. List of Pin Functions (Page 32)
Added a note of “TAP Controller” in 4. List of Pin Functions (Page 52)
Corrected sector size of Memory Map (2) in 10. Memory Map.
ROM1_SA8_15(8KBx8) ROM1_SA8_15(64KBx8)
Replace a word “Ta” to “TA” in the following chapters.
12.2. Recommended Operating Conditions
12.3. DC Characteristics
12.4. AC Characteristics
12.5. 12-bit A/D Converter
12.6. 10-bit D/A Converter
12.7. USB Characteristics
12.8. Low-Voltage Detection Characteristics
12.9. Flash Memory Write/Erase Characteristics
12.10. Return Time from Low-Power Consumption Mode
Updated 12.4.7. Power-on Reset Timing
Added the Baud rate spec in 12.4.10 CSIO Timing (Page 103, 105, 107, 109)
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 117)
Document Number: 002-05665 Rev. *D
Page 140 of 142
MB9B320TA Series
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Corrected the Part numbers
MB9BF328SAPMC-GE1 MB9BF328SAPMC-GK7E2
MB9BF329SAPMC-GE1 MB9BF329SAPMC-GK7E2
MB9BF328TAPMC-GE1 MB9BF328TAPMC-GK7E2
MB9BF329TAPMC-GE1 MB9BF329TAPMC-GK7E2
MB9BF328TABGL-GE1 MB9BF328TABGL-GK7E1
MB9BF329TABGL-GE1 MB9BF329TABGL-GK7E1
In chapter 13. Ordering Information (Page 132)
Updated 14. Package Dimensions
Added 15. Errata
*C
*D
5790535
6013729
YSAT
YSAT
07/03/2017 Adapted new Cypress logo
Updated Arm trademark and the last page
01/12/2018
Updated the figure of LBE192 in 14. Package Dimensions
Document Number: 002-05665 Rev. *D
Page 141 of 142
MB9B320TA Series
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Document Number: 002-05665 Rev. *D
January 12, 2018
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