MT55V1MV18FF-12_技术文档

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

MT55L1MY18F, MT55V1MV18F,

MT55L512Y32F, MT55V512V32F,

MT55L512Y36F, MT55V512V36F

18Mb

ZBT^®SRAM

3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD 2.5V I/O

FEATURES

1

100-Pin TQFP

• High frequency and 100 percent bus utilization

• Fast cycle times: 10ns, 11ns and 12ns

• Single +3.3V ±±5, or 2.±V ±±5 poꢀer supply ꢁV^DD)

• Separate +3.3V or +2.±V isolated output buffer

supply ꢁVDDQ)

• Advanced control logic for minimum control signal

interface

• Individual BYTE WRITE controls may be tied LOW

• Single R/W# ꢁread/ꢀrite) control pin

• CKE# pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data

I/Os, and control signals

165-Ball FBGA

• Internally self-timed, fully coherent WRITE

• Internally self-timed, registered outputs to eliminate

the need to control OE#

• SNOOZE MODE for reduced-poꢀer standby

• Common data inputs and data outputs

• Linear or Interleaved Burst Modes

• Burst feature ꢁoptional)

• Pin and ball/function compatibility ꢀith 2Mb, 4Mb,

and 8Mb ZBT SRAM

NOTE:1. JEDEC-standard MS-026 BHA (LQFP).

OPTIONS

TQFP MARKING

• Timing ꢁAccess/Cycle/MHz)

2.±V VDD, 2.±V I/O

• Operating Temperature Range

Commercial ꢁ0ºC ≤ T_A≤ +70ºC)

None

7.±ns/10ns/100 MHz

9ns/12ns/83 MHz

3.3V V^DD, 3.3V or 2.±V I/O

8.±ns/11ns/90 MHz

9ns/12ns/83 MHz

-10

-12

Part Number Example:

MT55L512Y32FT-12

-11

-12

GENERAL DESCRIPTION

The Micron^®Zero Bus Turnaround^™ꢁZBT^®) SRAM

family employs high-speed, loꢀ-poꢀer CMOS designs

using an advanced CMOS process.

• Configurations

3.3V VDD, 3.3V or 2.±V I/O

1 Meg x 18

MT±±L1MY18F

MT±±L±12Y32F

MT±±L±12Y36F

Micron’s 18Mb ZBT SRAMs integrate a 1 Meg x 18,

±12K x 32, or ±12K x 36 SRAM core ꢀith advanced syn-

chronous peripheral circuitry and a 2-bit burst counter.

These SRAMs are optimized for 100 percent bus utiliza-

tion, eliminating any turnaround cycles for READ to

WRITE, or WRITE to READ, transitions. All synchronous

inputs pass through registers controlled by a positive-

edge-triggered single clock input ꢁCLK). The synchro-

nous inputs include all addresses, all data inputs, chip

enable ꢁCE#), tꢀo additional chip enables for easy depth

expansionꢁCE2, CE2#), cyclestartinputꢁADV/LD#), syn-

chronousclockenableꢁCKE#), byteꢀriteenablesꢁBWa#,

BWb#, BWc#, and BWd#), and read/ꢀrite ꢁR/W#).

±12K x 32

±12K x 36

2.±V V^DD, 2.±V I/O

1 Meg x 18

±12K x 32

MT±±V1MV18F

MT±±V±12V32F

MT±±V±12V36F

±12K x 36

• Packages

100-pin TQFP

16±-ball FBGA

T

F*

* A Part Marking Guide for the FBGA devices can be found on Micron’s

Web site—http://ꢀꢀꢀ.micron.com/support/index.html.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. H, Pub. 9/02

1

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

FUNCTIONAL BLOCK DIAGRAM

1 MEG x 18

18

20

ADDRESS

REGISTER

SA0, SA1, SA

SA1

SA0

SA1'

D1

D0

Q1

Q0

SA0'

MODE

K

BURST

LOGIC

CE

ADV/LD#

K

CLK

CKE#

20

WRITE ADDRESS

REGISTER

O

U

T

P

U

T

D

A

T

S

E

N

S

A

ADV/LD#

BWa#

1 Meg x 9 x 2

B

U

F

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

WRITE

DRIVERS

E

S

T

E

R

I

18

DQs

DQPa

DQPb

18

MEMORY

ARRAY

A

M

P

F

BWb#

R/W#

E

R

S

E

N

G

INPUT

REGISTER

18

E

OE#

CE#

READ LOGIC

CE2

CE2#

FUNCTIONAL BLOCK DIAGRAM

512K x 32/36

17

19

ADDRESS

REGISTER

SA0, SA1, SA

MODE

SA1

SA0

SA1'

SA0'

D1

D0

Q1

Q0

BURST

LOGIC

CE

ADV/LD#

K

CLK

CKE#

K

19

WRITE ADDRESS

REGISTER

19

O

U

T

P

D

A

T

S

E

N

S

U

T

512K x 8 x 4

(x32)

ADV/LD#

BWa#

BWb#

BWc#

A

B

U

F

WRITE

DRIVERS

E

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

S

T

E

R

I

512K x 9 x 4

(x36)

DQs

36

DQPa

DQPb

DQPc

DQPd

A

M

P

F

E

R

S

MEMORY

ARRAY

BWd#

R/W#

S

E

N

G

36

INPUT

E

REGISTER

OE#

CE#

READ LOGIC

CE2

CE2#

NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin/ball descriptions, and timing

diagrams for detailed information.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

NOT RECOMMENDED FOR NEW DESIGNS

GENERAL DESCRIPTION (continued)

AsynchronousinputsincludetheoutputenableꢁOE#,

ꢀhich may be tied LOW for control signal minimization),

clock ꢁCLK) and snooze enable ꢁZZ, ꢀhich may be tied

LOW if unused). There is also a burst mode pin/ball

ꢁMODE)thatselectsbetꢀeeninterleavedandlinearburst

modes. MODE may be tied HIGH, LOW or left uncon-

nected if burst is unused. The floꢀ-through data-out ꢁQ)

is enabled by OE#. WRITE cycles can be from one to four

bytes ꢀide as controlled by the ꢀrite control inputs.

All READ, WRITE, and DESELECT cycles are initiated

by the ADV/LD# input. Subsequent burst addresses can

be internally generated as controlled by the burst ad-

vance pin ꢁADV/LD#). Use of burst mode is optional. It is

alloꢀable to give an address for each individual READ

and WRITE cycle. BURST cycles ꢀrap around after the

fourth access from a base address.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

address. The ꢀrite data associated ꢀith the address is

required one cycle later, or on the rising edge of clock

cycle tꢀo.

Address and ꢀrite control are registered on-chip to

simplify WRITE cycles. This alloꢀs self-timed WRITE

cycles. Individual byte enables alloꢀ individual bytes to

be ꢀritten. During a BYTE WRITE cycle, BWa# controls

DQa pins/balls; BWb# controls DQb pins/balls; BWc#

controls DQc pins/balls; and BWd# controls DQd pins/

balls. Cycle types can only be defined ꢀhen an address is

loaded, i.e., ꢀhen ADV/LD# is LOW. Parity/ECC bits are

only available on the x36 versions.

The device is ideally suited for systems requiring high

bandꢀidth and zero bus turnaround delays.

Please refer to Micron’s Web site ꢁꢀꢀꢀ.micron.com/

sramds) for the latest data sheet.

To alloꢀ for continuous, 100 percent use of the data

bus, the floꢀ-through ZBT SRAM uses a LATE WRITE

cycle. For example, if a WRITE cycle begins in clock cycle

one, the address is present on rising edge one. BYTE

WRITEs need to be asserted on the same cycle as the

DUAL VOLTAGE I/O

The 3.3V VDD device is tested for 3.3V and 2.±V I/O

function. The 2.±V VDD device is tested for only 2.±V

I/O function.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

TQFP PIN ASSIGNMENT TABLE

PIN # x18

x32

NF

DQc

x36

DQPc

DQc

PIN # x18

26

27

x32

x36

PIN # x18

x32

NF

DQa

x36

DQPa

DQa

PIN # x18

76

77

x32

x36

3

1

2

3

NC

V

SS

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

NC

V

SS

VDD

Q

V

DD

Q

DQc

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

NC

DQd

NF

DQd

DQPd

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

NC

SA

DQb

NF

SA

DQb

DQPb

4

5

V

DD

Q

VDDQ

V

SS

V

SS

6

7

NC

DQc

MODE (LBO#)

NC

DQa

SA

8

9

DQb

SA

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

V

SS

SA

V

SS

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

V

DD

Q

SA1

SA0

DNU

V

DD

Q

DQb

DQc

DQa

ZZ

DQc

1

V

SS

V

DD

V

SS

V

DD

V

SS

2

1

V

DD

SS

V

DD

V

SS

VDD

V

DNU

SA

V

SS

CE2#

BWa#

BWb#

BWc# BWc#

BWd# BWd#

CE2

CE#

SA

DQb

DQd

DQa

DQb

V

DD

Q

V

DD

Q

NC

V

SS

V

SS

DQb

NC

DQd

DQa

NC

DQb

SA

NOTE: 1. Pins 14 and 66 do not have to be connected directly to VSS if the input voltage is ≤ VIL.

2. Pin 16 does not have to be connected directly to V^DDif the input voltage is ≥ VIH.

3. NF for x32 version, DQPx for x36 version.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

PIN ASSIGNMENT (TOP VIEW)

100-PIN TQFP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SA

81

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

SA

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

SA

DNU

V

SS

DD

V

DD

SS

V

x18

CE2#

BWa#

BWb#

NC

DNU

SA0

SA1

SA

NC

CE2

CE#

SA

100

MODE

(LBO#)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81 50

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

ADV/LD#

OE# (G#)

CKE#

SA

R/W#

CLK

DNU

V

SS

DD

V

DD

SS

V

x32/x36

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

DNU

SA0

SA1

SA

CE#

SA

100

MODE

(LBO#)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NOTE: 1. NF for x32 version, DQPx for x36 version.

2. Pins 14 and 66 do not have to be connected directly to VSS if the input voltage is ≤ VIL.

3. Pin 16 does not have to be connected directly to V^DDif the input voltage is ≥ VIH.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

NOT RECOMMENDED FOR NEW DESIGNS

TQFP PIN DESCRIPTIONS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

x18

x32/36

SYMBOL TYPE

DESCRIPTION

37

36

37

36

SA0

SA1

SA

Input Synchronous Address Inputs: These inputs are registered

and must meet the setup and hold times around the

rising edge of CLK. SA0 and SA1 are the two least

significant bits (LSB) of the address field and set the

internal burst counter if burst is desired.

32–35, 44–50,

80–84, 99,

100

32–35, 44–50,

81–84, 99,

100

93

94

–

93

94

95

96

BWa# Input Synchronous Byte Write Enables: These active LOW

BWb#

BWc#

BWd#

inputs allow individual bytes to be written when a

WRITE cycle is active and must meet the setup and hold

times around the rising edge of CLK. BYTE WRITEs need

to be asserted on the same cycle as the address. BWa#

controls DQa pins; BWb# controls DQb pins; BWc#

controls DQc pins; BWd# controls DQd pins.

–

89

CLK

Input Clock: This signal registers the address, data, chip

enables, byte write enables, and burst control inputs on

its rising edge. All synchronous inputs must meet setup

and hold times around the clock’s rising edge.

98

92

98

92

CE#

Input Synchronous Chip Enable: This active LOW input is used

to enable the device and is sampled only when a new

external address is loaded (ADV/LD# LOW).

CE2#

Input Synchronous Chip Enable: This active LOW input is used

to enable the device and is sampled only when a new

external address is loaded (ADV/LD# LOW). This input

can be used for memory depth expansion.

97

CE2

Input Synchronous Chip Enable: This active HIGH input is used

to enable the device and is sampled only when a new

external address is loaded (ADV/LD# LOW). This input

can be used for memory depth expansion.

86

85

86

85

OE#

(G#)

Input Output Enable: This active LOW, asynchronous input

enables the data I/O output drivers. G# is the JEDEC-

standard term for OE#.

ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this

input is used to advance the internal burst counter,

controlling burst access after the external address is

loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW

on ADV/LD# clocks a new address at the CLK rising edge.

87

64

87

64

CKE#

Input Synchronous Clock Enable: This active LOW input

permits CLK to propagate throughout the device. When

CKE is HIGH, the device ignores the CLK input and

effectively internally extends the previous CLK cycle. This

input must meet setup and hold times around the rising

edge of CLK.

ZZ

Input Snooze Enable: This active HIGH, asynchronous input

causes the device to enter a low-power standby mode in

which all data in the memory array is retained. When ZZ

is active, all other inputs are ignored. This pin has an

internal pull-down and can be floating.

(continued on next page)

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

NOT RECOMMENDED FOR NEW DESIGNS

TQFP PIN DESCRIPTIONS (continued)

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

x18

x32/36

SYMBOL TYPE

R/W#

DESCRIPTION

88

Input Read/Write: This input determines the cycle type when

ADV/LD# is LOW and is the only means for determining

READs and WRITEs. READ cycles may not be converted

into WRITEs (and vice versa) other than by loading a

new address. A LOW on this pin permits BYTE WRITE

operations and must meet the setup and hold times

around the rising edge of CLK. Full bus-width WRITEs

occur if all byte write enables are LOW.

31

MODE Input Mode: This input selects the burst sequence. A LOW on

(LBO#)

this pin selects linear burst. NC or HIGH on this pin

selects interleaved burst. Do not alter input state while

device is operating. LBO# is the JEDEC-standard term for

MODE.

(a) 58, 59, 62, 63, (a) 52, 53, 56–59,

DQa

DQb

DQc

DQd

Input/ SRAM Data I/Os: Byte “a” is associated with DQa pins;

Output Byte “b” is associated with DQb pins; Byte “c” is

associated with DQc pins; Byte “d” is associated with

DQd pins. Input data must meet setup and hold times

around the rising edge CLK.

68, 69, 72–74

(b) 8, 9, 12, 13,

18, 19, 22–24

62, 63

(b) 68, 69, 72–75,

78, 79

(c) 2, 3, 6–9,

12, 13

(d) 18, 19, 22–25,

28, 29

–

51

80

1

NF/DQPa NF/

NF/DQPb I/O

NF/DQPc

No Function/Data Bits: On the x32 version, these pins are

no function (NF) and can be left floating or connected

to GND to minimize thermal impedance. On the x36

version, these bits are DQs.

30

NF/DQPd

No function balls are internally connected to the die and

have the capacitance of an input pin. It is allowable to

leave these pins unconnected or driven by signals.

15, 16, 41, 65, 91 15, 16, 41, 65, 91

VDD

Supply Power Supply: See DC Electrical Characteristics and

Operating Conditions for range.

4, 11, 20, 27,

54, 61, 70, 77

4, 11, 20, 27,

54, 61, 70, 77

V^DDQ Supply Isolated Output Buffer Supply: See DC Electrical

Characteristics and Operating Conditions for range.

5, 10, 14, 17, 21, 5, 10, 14, 17, 21,

26, 40, 55, 60, 26, 40, 55, 60,

66, 67, 71, 76, 90 66, 67, 71, 76, 90

VSS

Supply Ground: GND.

1–3, 6, 7, 25,

28–30, 51–53, 56,

57, 75, 78, 79,

95, 96

–

NC

–

No Connect: These pins can be left floating or connected

to GND to minimize thermal impedance.

38, 39, 42, 43

DNU

Do Not Use: These signals may either be unconnected or

wired to GND to minimize thermal impedance.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

BALL LAYOUT (TOP VIEW)

165-BALL FBGA

x18

x32/x36

1

2

3

4

5

6

7

8

9

10

11

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

NC

SA

CE# BWb#

NC

CE2# CKE# ADV/LD# SA

SA

NC

SA

CE# BWc# BWb# CE2# CKE# ADV/LD# SA

CE2 BWd# BWa# CLK R/W# OE# (G#) SA

SA

NC

CE2

NC

BWa# CLK R/W# OE# (G#) SA

NC

V

DD

Q

V

SS

VSS

V

SS

VSS

V

SS

V

DD

Q

NC

DQPa

DQa

ZZ

NF/DQPc NC

V

DD

Q

V

SS

V

SS

V

SS

VSS

V

SS

V

DD

Q

NC NF/DQPb

DQb DQb

DQb

V

Q

VDD

NC

DQc

VDD

NC

F

NC

G

H

J

G

H

J

G

H

J

G

H

J

NC

VSS

VDD

NC

VSS

VDD

NC

ZZ

DQb

DQPb

NC

V

DD

Q

V

DD

Q

DQa

NC

DQd DQd

NF/DQPd NC

V

DD

Q

V

DD

Q

DQa

K

L

K

L

K

L

K

L

V

Q

V

Q

NC

V

Q

V

Q

NC

M

N

P

M

N

P

M

N

P

M

N

P

NC

V

SS

NC

TDI

NC

SA1

SA0

VSS

NC

V

SS

NC

TDI

NC

SA1

SA0

VSS

NC NF/DQPa

SA

TDO

TCK

SA

NC

SA

TDO

TCK

SA

NC

SA

R

MODE NC

(LBO#)

TMS

SA

MODE NC

(LBO#)

TMS

TOP VIEW

*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

NOT RECOMMENDED FOR NEW DESIGNS

FBGA BALL DESCRIPTIONS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

6R

6P

6R

6P

SA0

SA1

SA

Input Synchronous Address Inputs: These inputs are registered and

must meet the setup and hold times around the rising edge of

CLK.

2A, 2B, 3P,

3R, 4P, 4R,

8P, 8R, 9A,

9B, 9P, 9R,

2A, 2B, 3P,

3R, 4P, 4R,

8P, 8R, 9A,

9B, 9P, 9R,

10A, 10B, 10P,10A, 10B, 10P,

10R, 11A, 11R

10R, 11R

5B

4A

–

5B

5A

4A

4B

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold

times around the rising edge of CLK. A byte write enable is LOW

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa balls and DQPa; BWb# controls DQb balls

and DQPb. For the x32 and x36 versions, BWa# controls DQa balls

and DQPa; BWb# controls DQb balls and DQPb; BWc# controls

DQc balls and DQPc; BWd# controls DQd balls and DQPd. Parity is

only available on the x18 and x36 versions.

–

7A

7B

7A

7B

CKE#

R/W#

Input Synchronous Clock Enable: This active LOW input permits CLK to

propogate throughout the device. When CKE# is HIGH, the

device ignores the CLK input and effectively internally extends

the previous CLK cycle. This input must meet the setup and hold

times around the rising edge of CLK.

Input Read/Write: This input determines the cycle type when ADV/LD#

is LOW and is the only means for determining READs and

WRITEs. READ cycles may not be converted into WRITEs (and vice

versa) other than by loading a new address. A LOW on this ball

permits BYTE WRITE operations to meet the setup and hold times

around the rising edge of CLK. Full bus-width WRITEs occur if all

byte write enables are LOW.

6B

CLK

Input Clock: This signal registers the address, data, chip enable, byte

write enables, and burst control inputs on its rising edge. All

synchronous inputs must meet setup and hold times around the

clock’s rising edge.

3A

6A

3A

6A

CE#

CE2#

ZZ

Input Synchronous Chip Enable: This active LOW input is used to enable

the device. CE# is sampled only when a new external address is

loaded. (ADV/LD# LOW)

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

11H

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in

the memory array is retained. When ZZ is active, all other inputs

are ignored.

3B

CE2

Input Synchronous Chip Enable: This active HIGH input is used to

enable the device and is sampled only when a new external

address is loaded.

(continued on next page)

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

NOT RECOMMENDED FOR NEW DESIGNS

FBGA BALL DESCRIPTIONS (continued)

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

8B

OE#(G#) Input Output Enable: This active LOW, asynchronous input enables the

data I/O output drivers.

8A

1R

8A

1R

ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input is used

to advance the internal burst counter, controlling burst access after

the external address is loaded. When ADV/LD# is HIGH, R/W# is

ingored. A LOW on ADV/LD# clocks a new address at the CLK rising

edge.

MODE

(LB0#)

Input Mode: This input selects the burst sequence. A LOW on this input

selects “linear burst.” NC or HIGH on this input selects “interleaved

burst.” Do not alter input state while device is operating.

5R

5P

7R

5R

5P

7R

TMS

TDI

TCK

Input IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls

may be left not connected if the JTAG function is not used in the

circuit.

(a) 10J, 10K, (a) 10J, 10K,

10L, 10M, 11D, 10L, 10M, 11J,

11E, 11F, 11G 11K, 11L, 11M

DQa

DQb

DQc

DQd

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with

Output DQa balls; Byte “b” is associated with DQb balls. For the x32 and

x36 versions, Byte “a” is associated with DQa balls; Byte “b” is

associated with DQb balls; Byte “c” is associated with DQc balls;

Byte “d” is associated with DQd balls. Input data must meet setup

and hold times around the rising edge of CLK.

(b) 1J, 1K,

(b) 10D, 10E,

1L, 1M, 2D, 10F, 10G, 11D,

2E, 2F, 2G

11E, 11F, 11G

(c) 1D, 1E,

1F, 1G, 2D,

2E, 2F, 2G

(d) 1J, 1K, 1L,

1M, 2J, 2K,

2L, 2M

11C

1N

–

11N

11C

1C

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

NC/ No Function/Parity Data I/Os: On the x32 version, these are no

I/O

function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”

parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte

“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.

No function balls are internally connected to the die and have

the capacitance of an input pin. It is allowable to leave these

balls unconnected or driven by signals.

–

1N

2H, 4D, 4E, 4F, 2H, 4D, 4E, 4F,

VDD

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

4G, 4H, 4J,

4K, 4L, 4M,

8D, 8E, 8F,

8G, 8H, 8J,

8K, 8L, 8M

4G, 4H, 4J,

4K, 4L, 4M,

8D, 8E, 8F,

8G, 8H, 8J,

8K, 8L, 8M

3C, 3D, 3E,

3F, 3G, 3J,

3K, 3L, 3M,

3N, 9C, 9D,

9E, 9F, 9G,

9J, 9K, 9L,

9M, 9N

3C, 3D, 3E,

3F, 3G, 3J,

3K, 3L, 3M,

3N, 9C, 9D,

9E, 9F, 9G,

9J, 9K, 9L,

9M, 9N

VDDQ

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

Operating Conditions for range.

(continued on next page)

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

NOT RECOMMENDED FOR NEW DESIGNS

FBGA BALL DESCRIPTIONS (continued)

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

x18

x32/x36

SYMBOL TYPE

Supply Ground: GND.

DESCRIPTION

1H, 4C, 4N,

VSS

5C, 5D, 5E, 5F, 5C, 5D, 5E, 5F,

5G, 5H, 5J,

5K, 5L, 5M,

5G, 5H, 5J,

5K, 5L, 5M,

6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,

6G, 6H, 6J,

6K, 6L, 6M,

7C, 7D, 7E,

7F, 7G, 7H,

7J, 7K, 7L,

6G, 6H, 6J,

6K, 6L, 6M,

7C, 7D, 7E,

7F, 7G, 7H,

7J, 7K, 7L,

7M, 7N, 8C, 8N 7M, 7N, 8C, 8N

7P

TDO

NC

Output IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.

1A, 1B, 1C,

1D, 1E, 1F,

1G, 1P, 2C,

2J, 2K, 2L,

2M, 2N, 2P,

2R, 3H, 4B,

5A, 5N, 6N,

9H, 10C,

1A, 1B, 1P,

2C, 2N, 2P,

2R, 3H, 5N,

6N, 9H, 10C,

10H, 10N,

11A, 11B,

11P

–

No Connect: These signals are not internally connected and may

be connected to ground to improve package heat dissipation.

10D, 10E,

10F, 10G,

10H, 10N,

11B, 11J,

11K, 11L,

11M, 11N,

11P

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)

FUNCTION

R/W#

BWa#

BWb#

READ

H

L

X

L

X

H

L

WRITE Byte “a”

WRITE Byte “b”

WRITE All Bytes

WRITE ABORT/NOP

H

L

H

NOTE: Using R/W# and byte write(s), any one or more bytes may be

written.

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)

FUNCTION

R/W#

BWa#

BWb#

BWc# BWd#

READ

H

L

X

L

X

H

L

X

H

L

X

H

L

WRITE Byte “a”

WRITE Byte “b”

WRITE Byte “c”

WRITE Byte “d”

WRITE All Bytes

WRITE ABORT/NOP

H

L

H

L

H

L

H

NOTE: Using R/W# and byte write(s), any one or more bytes may be written.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

STATE DIAGRAM FOR ZBT SRAM

DS

BURST

DS

DESELECT

WRITE

DS

WRITE

READ

BEGIN

READ

BEGIN

WRITE

BURST

READ

BURST

WRITE

BURST

READ

BURST

WRITE

BURST

KEY:

COMMAND OPERATION

DS

DESELECT

READ

WRITE

BURST

New READ

New WRITE

BURST READ,

BURST WRITE, or

CONTINUE DESELECT

NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the

clock (CLK) input and does not change the state of the device.

2. States change on the rising edge of the clock (CLK).

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

TRUTH TABLE

(Notes 5-10)

ADDRESS

USED

ADV/

OPERATION

CE# CE2# CE2 ZZ LD# R/W# BWx OE# CKE# CLK

DQ

NOTES

DESELECT Cycle

CONTINUE DESELECT Cycle

None

H

X

L

X

H

X

L

X

L

X

H

X

L

L→H High-Z

None

L

None

X

H

L

1

READ Cycle

(Begin Burst)

External

L→H

Q

READ Cycle

(Continue Burst)

L

X

L

X

H

X

H

X

H

X

L

H

L

X

H

X

L

X

L

L→H

Q

1, 11

2

NOP/DUMMY READ

(Begin Burst)

H

X

L→H High-Z

DUMMY READ

(Continue Burst)

X

L

X

L

H

L

L→H High-Z 1, 2,

11

WRITE Cycle

(Begin Burst)

External

L→H

D

3

WRITE Cycle

(Continue Burst)

X

L

X

L

H

L

X

L

1, 3,

11

NOP/WRITE ABORT

(Begin Burst)

None

H

X

L

L→H High-Z

2, 3

WRITE ABORT

(Continue Burst)

X

H

X

L

L→H High-Z 1, 2,

3, 11

IGNORE CLOCK EDGE

(Stall)

Current

None

H

X

L→H

–

4

SNOOZE MODE

X

High-Z

NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle

is executed first.

2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.

A WRITE ABORT means a WRITE command is given, but no operation is performed.

3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off

the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an

application’s requirements.

4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it

occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE

CLOCK EDGE cycle.

5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,

BWc#, and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.

6. BWa# enables WRITEs to Byte “a” (DQa pins); BWb# enables WRITEs to Byte “b” (DQb pins); BWc# enables WRITEs to

Byte “c” (DQc pins); BWd# enables WRITEs to Byte “d” (DQd pins).

7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

8. Wait states are inserted by setting CKE# HIGH.

9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle.

11. The address counter is incremented for all CONTINUE BURST cycles.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

NOT RECOMMENDED FOR NEW DESIGNS

3.3V VDD, ABSOLUTE MAXIMUM

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

2.5V VDD, ABSOLUTE MAXIMUM

RATINGS*

Voltage on VDD Supply Relative

RATINGS*

Voltage on VDD Supply

Relative to V^SS........................................ -0.5V to +4.6V

Voltage on V^DDQ Supply

to V^SS........................................................ -0.3V to +3.6V

Voltage on V^DDQ Supply Relative

Relative to V^SS........................................... -0.5V to VDD

VIN (DQs) ........................................... -0.5V to VDDQ + 0.5V

V^IN(Inputs) ........................................... -0.5V to VDD + 0.5V

Storage Temperature (TQFP) ................ -55ºC to +150ºC

Storage Temperature (FBGA) ................ -55ºC to +125ºC

Junction Temperature** ......................................... +150ºC

Short Circuit Output Current ................................ 100mA

to V^SS........................................................ -0.3V to +3.6V

V^IN(DQs) ........................................... -0.3V to VDDQ + 0.3V

V^IN(Inputs)........................................... -0.3V to VDD + 0.3V

Storage Temperature (TQFP) ................ -55ºC to +150ºC

Storage Temperature (FBGA) ................ -55ºC to +125ºC

Junction Temperature** ........................................ +150ºC

Short Circuit Output Current ................................ 100mA

*Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only, and functional operation

of the device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

**Junctiontemperaturedependsuponpackagetype,cycle

time, loading, ambient temperature, and airflow. See

Micron Technical Note TN-05-14 for more information.

3.3V VDD, 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0ºC ≤ Τ_A≤ +70ºC; VDD, VDDQ = +3.3V 0.165V unless otherwise notedꢀ

DESCRIPTION

CONDITIONS

DQ pins/balls

0V ≤ VIN ≤ VDD

SYMBOL

MIN

2.0

MAX

DD + 0.3

0.8

UNITS

V

NOTES

1, 2

3

Input High (Logic 1ꢀ Voltage

Input Low (Logic 0ꢀ Voltage

Input Leakage Current

Output Leakage Current

V

IH

V

IH

2.0

V

IL

-0.3

-1.0

V

IL

I

1.0

µA

Output(sꢀ disabled,

O

1.0

0V ≤ VIN ≤ VDD

Output High Voltage

Output Low Voltage

Supply Voltage

I

OH = -4.0mA

V

OH

OL

DD

2.4

V

1, 4

1

I

OL = 8.0mA

V

0.4

V

3.135

3.465

Isolated Output Buffer Supply

V

Q

V

DD

1, 5

NOTE: 1. All voltages referenced to VSS (GNDꢀ.

2. For 3.3V VDD:

t

Overshoot:

VIH ≤ +4.6V for t ≤ KHKH/2 for I ≤ 20mA

t

Undershoot: VIL ≥ -0.7V for t ≤ KHKH/2 for I ≤ 20mA

Power-up:

VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms

For 2.5V VDD:

Overshoot:

t

VIH ≤ +3.6V for t ≤ KHKH/2 for I ≤ 20mA

t

Undershoot: VIL ≥ -0.5V for t ≤ KHKH/2 for I ≤ 20mA

Power-up:

VIH ≤ +2.65V and VDD ≤ 2.375V for t ≤ 200ms

3. MODE pin has an internal pull-up, and input leakage = 10µA.

4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O

curves are available upon request.

5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

3.3V VDD, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0ºC ≤ T_A≤ +70ºC; VDD = +3.3V 0.165V; VDDQ = +2.5V 0.125V unless otherwise noted)

DESCRIPTION

CONDITIONS

Data bus (DQx)

Inputs

SYMBOL

MIN

1.7

MAX

UNITS

V

NOTES

1, 2

3

Input High (Logic 1) Voltage

V

IH

Q

V

DDQ + 0.3

V

IH

1.7

V

DD + 0.3

0.7

V

Input Low (Logic 0) Voltage

Input Leakage Current

V

IL

-0.3

-1.0

V

0V ≤ VIN ≤ VDD

Output(s) disabled,

0V ≤ VIN ≤ VDDQ (DQx)

IL

I

1.0

µA

Output Leakage Current

IL

O

1.0

Output High Voltage

Output Low Voltage

I

OH = -2.0mA

OH = -1.0mA

V

OH

1.7

2.0

–

V

1

I

OL = 2.0mA

OL = 1.0mA

V

OL

–

0.7

I

–

0.4

Supply Voltage

V

DD

3.135

2.375

3.465

2.625

Isolated Output Buffer Supply

V

DD

Q

2.5V VDD, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0ºC ≤ T_A≤ +70ºC; VDD = +2.5V 0.125V; VDDQ = +2.5V 0.125V unless otherwise noted)

DESCRIPTION

CONDITIONS

Data bus (DQx)

Inputs

SYMBOL

MIN

1.7

MAX

UNITS

V

NOTES

1, 2

3

Input High (Logic 1) Voltage

V

IH

Q

V

DDQ + 0.3

V

IH

1.7

V

DD + 0.3

0.7

V

Input Low (Logic 0) Voltage

Input Leakage Current

V

IL

-0.3

-1.0

V

0V ≤ VIN ≤ VDD

Output(s) disabled,

0V ≤ VIN ≤ VDDQ (DQx)

IL

I

1.0

µA

Output Leakage Current

IL

O

1.0

Output High Voltage

Output Low Voltage

I

OH = -2.0mA

OH = -1.0mA

V

OH

1.7

2.0

–

V

1

I

OL = 2.0mA

OL = 1.0mA

V

OL

–

0.7

I

–

0.4

Supply Voltage

V

DD

2.375

2.625

Isolated Output Buffer Supply

V

DD

Q

NOTE: 1. All voltages referenced to VSS (GND).

2. For 3.3V VDD:

t

Overshoot:

VIH ≤ +4.6V for t ≤ KHKH/2 for I ≤ 20mA

t

Undershoot: VIL ≥ -0.7V for t ≤ KHKH/2 for I ≤ 20mA

Power-up:

VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms

For 2.5V VDD:

Overshoot:

t

VIH ≤ +3.6V for t ≤ KHKH/2 for I ≤ 20mA

t

Undershoot: VIL ≥ -0.5V for t ≤ KHKH/2 for I ≤ 20mA

Power-up:

V^IH≤ +2.65V and VDD ≤ 2.375V for t ≤ 200ms

3. MODE pin has an internal pull-up, and input leakage = 10µA.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16

NOT RECOMMENDED FOR NEW DESIGNS

TQFP CAPACITANCE

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

DESCRIPTION

CONDITIONS

T_A= 25ºC; f = 1 MHz

VDD = 3.3V

SYMBOL

TYP

4.8

3.8

4.7

4.5

MAX

6.0

UNITS

pF

NOTES

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

Clock Capacitance

CI

CO

CA

C^CK

1

4.5

pF

5.5

pF

5.0

pF

FBGA CAPACITANCE

DESCRIPTION

CONDITIONS

SYMBOL TYP

MAX

UNITS NOTES

Address/Control Input Capacitance

Output Capacitance (Q)

Clock Capacitance

CI

2.5

4

3.5

5

pF

1

T_A= 25ºC; f = 1 MHz

CO

CCK

2.5

3.5

TQFP THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

θ

46

ºC/W

1

JA

Thermal Resistance

(Junction to Top of Case)

θ

2.8

ºC/W

1

JC

FBGA THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Junction to Ambient

(Airflow of 1m/s)

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

θ_JA

40

ºC/W

1

Junction to Case (Top)

θ_JC

θ_JB

9

ºC/W

1

Junction to Pins/Balls

(Bottom)

17

NOTE: 1. This parameter is sampled.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

17

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

3.3V VDD, IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (512K x 32/36)

(Note 1, unless otherwise noted) (0ºC ≤ T_A≤ +70ºC)

MAX

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-11

-12

UNITS NOTES

Power Supply

Current: Operating

Device selected; All inputs ≤ VIL or ≥ VIH

;

t

Cycle time ≥ KC (MIN);

I

DD

TBD

480

450

mA

2, 3, 4

V

DD = MAX; Outputs open

Power Supply

Current: Idle

Device selected; VDD = MAX;

CKE# ≥ V^IH

;

I

DD1

TBD

160

150

mA

2, 3, 4

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

t

Cycle time ≥ KC (MIN)

CMOS Standby

TTL Standby

Device deselected; VDD = MAX;

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

All inputs static; CLK frequency = 0

I

SB

2

TBD

30

mA

3, 4

Device deselected; VDD = MAX;

All inputs ≤ V^ILor ≥ VIH

;

I

3

100

All inputs static; CLK frequency = 0

Clock Running

Snooze Mode

Device deselected; VDD = MAX;

ADV/LD# ≥ VIH; All inputs ≤ VSS + 0.2

I

4

TBD

160

10

150

10

mA

3, 4

4

t

or ≥ VDD - 0.2; Cycle time ≥ KC (MIN)

ZZ ≥ VIH

ISB2Z

NOTE: 1. VDDQ = +3.3V or +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ.

2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device

is active (not in deselected mode).

4. Typical values are measured at 3.3V, 25ºC, and 12ns cycle time.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

18

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

2.5V VDD, IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (512K x 32/36)

(Note 1, unless otherwise noted) (0ºC ≤ T_A≤ +70ºC)

MAX

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-10

-12

UNITS NOTES

Power Supply

Current: Operating

Device selected; All inputs ≤ VIL or ≥ VIH

;

t

Cycle time ≥ KC (MIN);

I

DD

TBD

400

345

mA

2, 3, 4

V

DD = MAX; Outputs open

Power Supply

Current: Idle

Device selected; V^DD= MAX;

CKE# ≥ V^IH

;

I

DD

1

TBD

135

115

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

t

Cycle time ≥ KC (MIN)

CMOS Standby

TTL Standby

Device deselected; VDD = MAX;

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

All inputs static; CLK frequency = 0

I

SB

2

TBD

225

80

25

80

mA

3, 4

Device deselected; VDD = MAX;

All inputs ≤ V^ILor ≥ VIH

;

I

3

All inputs static; CLK frequency = 0

Clock Running

Snooze Mode

Device deselected; VDD = MAX;

ADV/LD# ≥ VIH; All inputs ≤ VSS + 0.2

I

4

TBD

135

10

115

10

mA

3, 4

4

t

or ≥ VDD - 0.2; Cycle time ≥ KC (MIN)

ZZ ≥ VIH

ISB2Z

NOTE: 1. VDDQ = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ.

2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device

is active (not in deselected mode).

4. Typical values are measured at 2.5V, 25ºC, and 12ns cycle time.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

19

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

3.3V VDD, IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (1 MEG x 18)

(Note 1, unless otherwise noted) (0ºC ≤ T_A≤ +70ºC)

MAX

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-11

-12

UNITS NOTES

Power Supply

Current: Operating

Device selected; All inputs ≤ VIL or ≥ VIH

;

t

Cycle time ≥ KC (MIN);

I

DD

TBD

360

340

mA

2, 3, 4

V

DD = MAX; Outputs open

Power Supply

Current: Idle

Device selected; V^DD= MAX;

CKE# ≥ V^IH

;

I

DD

1

TBD

120

115

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

t

Cycle time ≥ KC (MIN)

CMOS Standby

TTL Standby

Device deselected; VDD = MAX;

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

All inputs static; CLK frequency = 0

I

SB

2

TBD

25

75

25

75

mA

3, 4

Device deselected; VDD = MAX;

All inputs ≤ V^ILor ≥ VIH

;

I

3

All inputs static; CLK frequency = 0

Clock Running

Snooze Mode

Device deselected; VDD = MAX;

ADV/LD# ≥ VIH; All inputs ≤ VSS + 0.2

I

4

TBD

120

10

115

10

mA

3, 4

4

t

or ≥ VDD - 0.2; Cycle time ≥ KC (MIN)

ZZ ≥ VIH

ISB2Z

NOTE: 1. VDDQ = +3.3V or +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ.

2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device

is active (not in deselected mode).

4. Typical values are measured at 3.3V, 25ºC, and 12ns cycle time.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

20

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

2.5V VDD, IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (1 MEG x 18)

(Note 1, unless otherwise noted) (0ºC ≤ T_A≤ +70ºC)

MAX

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-10

-12

UNITS NOTES

Power Supply

Current: Operating

Device selected; All inputs ≤ VIL

t

or ≥ VIH; Cycle time ≥ KC (MIN);

I

DD

TBD

305

260

mA

2, 3, 4

V

DD = MAX; Outputs open

Power Supply

Current: Idle

Device selected; V^DD= MAX;

CKE# ≥ V^IH

;

I

DD

1

TBD

105

90

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

t

Cycle time ≥ KC (MIN)

CMOS Standby

TTL Standby

Device deselected; VDD = MAX;

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

All inputs static; CLK frequency = 0

I

SB

2

TBD

20

80

20

80

mA

3, 4

Device deselected; VDD = MAX;

All inputs ≤ V^ILor ≥ VIH

;

I

3

All inputs static; CLK frequency = 0

Clock Running

Snooze Mode

Device deselected; VDD = MAX;

ADV/LD# ≥ VIH; All inputs ≤ VSS + 0.2

I

4

TBD

105

10

90

10

mA

3, 4

4

t

or ≥ VDD - 0.2; Cycle time ≥ KC (MIN)

ZZ ≥ VIH

ISB2Z

NOTE: 1. VDDQ = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ.

2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device

is active (not in deselected mode).

4. Typical values are measured at 2.5V, 25ºC, and 12ns cycle time.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

21

NOT RECOMMENDED FOR NEW DESIGNS

AC ELECTRICAL CHARACTERISTICS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

(Notes 1, 2, 3) (0ºC ≤ T_A≤ +70ºC)(Note 4, unless otherwise noted)

5

6

-10

-11

-12

DESCRIPTION

SYMBOL MIN

MAX

MIN

MAX

MIN

MAX UNITS NOTES

Clock

t

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

Output Times

Clock to output valid

Clock to output invalid

Clock to output in Low-Z

Clock to output in High-Z

OE# to output valid

OE# to output in Low-Z

OE# to output in High-Z

Setup Times

KHKH

10

11

12

ns

MHz

ns

f

KF

KHKL

KLKH

100

90

83

t

2.5

3.0

7

t

ns

t

KHQV

KHQX

KHQX1

7.5

8.5

9.0

ns

3.0

8

t

ns 8, 9, 10, 11

ns

ns 8, 9, 10, 11

t

KHQZ

GLQV

GLQX

5.0

t

1

t

0

t

GHQZ

5.0

t

Address

AVKH

2.0

ns

12

t

Clock enable (CKE#)

Control signals

Data-in

EVKH

t

CVKH

t

DVKH

Hold Times

Address

Clock enable (CKE#)

Control signals

Data-in

t

KHAX

KHEX

KHCX

KHDX

0.5

ns

12

t

NOTE: 1. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for

turnaround timing.

2. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (V^DDQ = +3.3V 0.165V) and Figure

3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V) unless otherwise noted.

3. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is

defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.

4. If V^DD= +3.3V, then VDDQ = +3.3V or +2.5V. If VDD = +2.5V, then VDDQ = +2.5V.

Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ.

5. The -10 speed grade is available for 2.5V VDD and I/O only.

6. The -11 speed grade is available for 3.3V V^DDand I/O only.

7. Measured as HIGH above VIH and LOW below VIL.

8. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion of these parameters.

9. This parameter is sampled.

10. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.

11. Transition is measured 200mV from steady state voltage.

12. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when they are being registered into the device. All other synchronous inputs must meet the setup and hold times

with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each

rising edge of CLK when ADV/LD# is LOW to remain enabled.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

22

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

3.3V I/O Output Load Equivalents

3.3V VDD, 3.3V I/O AC TEST CONDITIONS

Input pulse levels ...................................VSS to 3.3V

Input rise and fall times..................................... 1ns

Input timing reference levels .......................... 1.5V

Output reference levels ................................... 1.5V

Output load ............................. See Figures 1 and 2

Figure 1

Q

Z_O= 50Ω

50Ω

V = 1.5V

T

Figure 2

+3.3V

317

3.3V V^DD, 2.5V I/O AC TEST CONDITIONS

Input pulse levels ...................................VSS to 2.5V

Input rise and fall times..................................... 1ns

Input timing reference levels ........................ 1.25V

Output reference levels ................................. 1.25V

Output load ............................. See Figures 3 and 4

Q

5pF

351

2.5V VDD, 2.5V I/O AC TEST CONDITIONS

Input pulse levels ...................................VSS to 2.5V

Input rise and fall times..................................... 1ns

Input timing reference levels ........................ 1.25V

Output reference levels ................................. 1.25V

Output load ............................. See Figures 3 and 4

2.5V I/O Output Load Equivalents

Figure 3

Q

Z_O= 50Ω

50Ω

V_T= 1.25V

LOAD DERATING CURVES

Micron1Megx18, ±12Kx32, and±12K x36ZBT SRAM

timing is dependent upon the capacitive loading on the

outputs.

Consult the factory for copies of I/O current versus

voltage curves.

Figure 4

+2.5V

225Ω

5pF

Q

225Ω

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

23

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

SNOOZE MODE

SNOOZEMODEisaloꢀ-current,“poꢀer-doꢀn”mode

in ꢀhich the device is deselected and current is reduced

to I^SB2Z. The duration of SNOOZE MODE is dictated by

the length of time the ZZ pin is in a HIGH state. After the

device enters SNOOZE MODE, all inputs except ZZ be-

come disabled and all outputs go to High-Z.

theZZpinbecomesalogicHIGH, I^SB2Z isguaranteedafter

the time ZZI is met. Any READ or WRITE operation

t

pending ꢀhen the device enters SNOOZE MODE is not

guaranteedtocompletesuccessfully.Therefore,SNOOZE

MODE must not be initiated until valid pending opera-

tions are completed. Similarly, ꢀhen exiting SNOOZE

t

The ZZ pin is an asynchronous, active HIGH input

that causes the device to enter SNOOZE MODE. When

MODE during RZZ, only a DESELECT or READ cycle

should be given.

SNOOZE MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

CONDITIONS

SYMBOL MIN

MAX

10

^tKHKH

UNITS NOTES

Current during SNOOZE MODE

ZZ active to input ignored

ZZ inactive to input sampled

ZZ active to snooze current

ZZ inactive to exit snooze current

ZZ ≥ VIH

ISB2Z

mA

^tZZ

^tRZZ

^tZZI

0

ns

1

^tRZZI

0

NOTE: 1. This parameter is sampled.

SNOOZE MODE WAVEFORM

CLK

t

ZZ

t

RZZ

ZZ

t

ZZI

I

SUPPLY

I

ISB2Z

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT

or READ Only

Outputs (Q)

High-Z

DON’T CARE

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

24

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

READ/WRITE TIMING

1

2

3

4

5

6

7

8

9

10

t

KHKH

t

CLK

t

EVKH KHEX

KLKH

KHKL

CKE#

t

CVKH KHCX

CE#

ADV/LD#

R/W#

BWx#

A1

A2

A4

A3

A5

A6

A7

ADDRESS

DQ

t

KHQV

t

AVKH KHAX

t

KHQZ

KHQX

GLQV

KHQX1

D(A1)

t

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

D(A7)

t

GHQZ

t

DVKH KHDX

t

KHQX

t

GLQX

OE#

COMMAND

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

READ/WRITE TIMING PARAMETERS

-10*

-11**

-12

-10*

-11**

-12

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX UNITS

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX UNITS

t

KHKH

10

11

12

ns

GHQZ

5.0

ns

f

t

KF

100

90

83

MHz

ns

AVKH

2.0

0.5

2.2

0.5

2.5

0.5

t

KHKL

2.5

3.0

EVKH

t

KLKH

ns

CVKH

t

KHQV

7.5

8.5

9.0

ns

DVKH

t

KHQX

3.0

ns

KHAX

t

KHQX1

ns

KHEX

t

KHQZ

5.0

ns

KHCX

t

GLQV

ns

KHDX

t

GLQX

0

ns

*The -10 speed grade available for 2.5V VDD and I/O only.

**The -11 speed grade available for 3.3V VDD and I/O only.

NOTE: 1. For this waveform, ZZ is tied LOW.

2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.

3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

25

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

NOP, STALL, AND DESELECT CYCLES

1

2

3

4

5

6

7

8

9

10

CLK

CKE#

CE#

ADV/LD#

R/W#

BWx#

A1

A2

A3

A4

A5

ADDRESS

t

KHQZ

D(A1)

Q(A2)

Q(A3)

D(A4)

Q(A5)

KHQX

DQ

t

COMMAND

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

NOP, STALL, AND DESELECT TIMING PARAMETERS

-10*

-11**

-12

SYMBOL

MIN

3.0

MAX

MIN

3.0

MAX

MIN

MAX UNITS

t

KHQX

3.0

ns

t

KHQZ

5.0

ns

*The -10 speed grade available for 2.5V VDD and I/O only.

**The -11 speed grade available for 3.3V VDD and I/O only.

NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not

performed during this cycle.

2. For this waveform, ZZ and OE# are tied LOW.

3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

26

NOT RECOMMENDED FOR NEW DESIGNS

IEEE 1149.1 SERIAL BOUNDARY SCAN

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

TEST ACCESS PORT (TAP)

TEST CLOCK (TCK)

The test clock is used only ꢀith the TAP controller. All

inputs are captured on the rising edge of TCK. All outputs

are driven from the falling edge of TCK.

(JTAG)

The 18Mb SRAM incorporates a serial boundary scan

test access port ꢁTAP). This port operates in accordance

ꢀith IEEE Standard 1149.1-1990 but does not have the set

of functions required for full 1149.1 compliance. These

functions from the IEEE specification are excluded be-

cause their inclusion places an added delay in the critical

speed path of the SRAM. Note that the TAP controller

functions in a manner that does not conflict ꢀith the

operation of other devices using 1149.1 fully compliant

TAPs. The TAP operates using JEDEC-standard 2.±V I/O

logic levels.

TEST MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It is

alloꢀable to leave this pin/ball unconnected if the TAP is

not used. The pin/ball is pulled up internally, resulting in

a logic HIGH level.

TEST DATA-IN (TDI)

The SRAM contains a TAP controller, instruction reg-

ister, boundary scan register, bypass register, and ID

register.

The TDI pin/ball is used to serially input information

into the registers and can be connected to the input of

any of the registers. The register betꢀeen TDI and TDO is

chosen by the instruction that is loaded into the TAP

instruction register. For information on loading the in-

struction register, see Figure 5. TDI is internally pulled up

and can be unconnected if the TAP is unused in an appli-

cation. TDI is connected to the most significant bit ꢁMSB)

of any register. ꢁSee Figure 6.)

DISABLING THE JTAG FEATURE

These pins/balls can be left floating ꢁunconnected), if

theJTAGfunctionisnottobeimplemented.Uponpoꢀer-

up, the device ꢀill come up in a reset state ꢀhich ꢀill not

interfere ꢀith the operation of the device.

Figure 5

Figure 6

TAP Controller State Diagram

TAP Controller Block Diagram

TEST-LOGIC

1

0

RESET

0

Bypass Register

1

2

1 0

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

Selection

Circuitry

Selection

Circuitry

Instruction Register

31 30 29

Identification Register

0

TDI

TDO

.

. 2 1 0

1

CAPTURE-DR

CAPTURE-IR

0

x

.

. 2 1 0

SHIFT-DR

0

SHIFT-IR

0

Boundary Scan Register*

1

EXIT1-DR

EXIT1-IR

0

TCK

TMS

PAUSE-DR

1

0

PAUSE-IR

1

0

TAP CONTROLLER

0

EXIT2-DR

1

EXIT2-IR

1

*x = 52 for the x18 configuration, x = 67 for the x32 configuration,

x = 71 for the x36 configuration.

UPDATE-DR

UPDATE-IR

1

0

1

0

NOTE: The 0/1 next to each state represents the value of

TMS at the rising edge of TCK.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

27

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

TEST DATA-OUT (TDO)

The boundary scan register is loaded ꢀith the con-

tentsoftheRAMI/OringꢀhentheTAPcontrollerisinthe

Capture-DR state and is then placed betꢀeen the TDI

and TDO pins ꢀhen the controller is moved to the Shift-

DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE

Z instructions can be used to capture the contents of the

I/O ring.

The TDO output pin/ball is used to serially clock data-

out from the registers. The output is active depending

upon the current state of the TAP state machine. ꢁSee

Figure 5.) The output changes on the falling edge of TCK.

TDO is connected to the least significant bit ꢁLSB) of any

register. ꢁSee Figure 6.)

The Boundary Scan Order tables shoꢀ the order in

ꢀhich the bits are connected. Each bit corresponds to

one of the pins on the SRAM package. The MSB of the

register is connected to TDI, and the LSB is connected to

TDO.

PERFORMING A TAP RESET

A RESET is performed by forcing TMS HIGH ꢁV^DD) for

five rising edges of TCK. This RESET does not affect the

operation of the SRAM and may be performed ꢀhile the

SRAM is operating.

At poꢀer-up, the TAP is reset internally to ensure that

TDO comes up in a High-Z state.

IDENTIFICATION (ID) REGISTER

The ID register is loaded ꢀith a vendor-specific, 32-

bit code during the Capture-DR state ꢀhen the IDCODE

command is loaded in the instruction register. The

IDCODE is hardꢀired into the SRAM and can be shifted

out ꢀhen the TAP controller is in the Shift-DR state. The

ID register has a vendor code and other information

describedintheIdentificationRegisterDefinitionstable.

TAP REGISTERS

Registers are connected betꢀeen the TDI and TDO

pins/balls and alloꢀ data to be scanned into and out of

the SRAM test circuitry. Only one register can be selected

at a time through the instruction register. Data is serially

loaded into the TDI pin on the rising edge of TCK. Data is

output on the TDO pin on the falling edge of TCK.

TAP INSTRUCTION SET

OVERVIEW

INSTRUCTION REGISTER

Eightdifferentinstructionsarepossibleꢀiththethree-

bit instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are

listed as RESERVED and should not be used. The other

five instructions are described in detail beloꢀ.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of the

mandatory1149.1instructionsarenotfullyimplemented.

The TAP controller cannot be used to load address, data

or control signals into the SRAM and cannot preload the

I/O buffers. The SRAM does not implement the 1149.1

commands EXTEST or INTEST or the PRELOAD portion

of SAMPLE/PRELOAD; rather, it performs a capture of

the I/O ring ꢀhen these instructions are executed.

InstructionsareloadedintotheTAPcontrollerduring

the Shift-IR state ꢀhen the instruction register is placed

betꢀeenTDIandTDO. Duringthisstate, instructionsare

shifted through the instruction register through the TDI

and TDO pins/balls. To execute the instruction once it is

shifted in, the TAP controller needs to be moved into the

Update-IR state.

Three-bit instructions can be serially loaded into the

instruction register. This register is loaded ꢀhen it is

placed betꢀeen the TDI and TDO pins/balls as shoꢀn in

Figure5.Uponpoꢀer-up,theinstructionregisterisloaded

ꢀith the IDCODE instruction. It is also loaded ꢀith the

IDCODE instruction if the controller is placed in a reset

state as described in the previous section.

WhentheTAPcontrollerisintheCapture-IRstate, the

tꢀo least significant bits are loaded ꢀith a binary “01”

patterntoalloꢀforfaultisolationoftheboard-levelserial

test data path.

BYPASS REGISTER

To save time ꢀhen serially shifting data through reg-

isters, it is sometimes advantageous to skip certain chips.

The bypass register is a single-bit register that can be

placed betꢀeen the TDI and TDO pins/balls. This alloꢀs

data to be shifted through the SRAM ꢀith minimal delay.

The bypass register is set LOW ꢁVSS) ꢀhen the BYPASS

instruction is executed.

BOUNDARY SCAN REGISTER

EXTEST

The boundary scan register is connected to all the

input and bidirectional pins/balls on the SRAM. The x36

configuration has a 71-bit-long register, the x32 configu-

ration has a 67-bit-long register, and the x18 configura-

tion has a ±2-bit-long register.

EXTEST is a mandatory 1149.1 instruction ꢀhich is to

be executed ꢀhenever the instruction register is loaded

ꢀith all 0s. EXTEST is not implemented in this SRAM TAP

controller, and therefore this device is not compliant to

1149.1.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

28

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the

instruction register, the SRAM responds as if a SAMPLE/

PRELOAD instruction has been loaded. There is one dif-

ference betꢀeen the tꢀo instructions. Unlike the

SAMPLE/PRELOADinstruction,EXTESTplacestheSRAM

outputs in a High-Z state.

faster. Because there is a large difference in the clock

frequencies, it is possible that during the Capture-DR

state, an input or output ꢀill undergo a transition. The

TAP may then try to capture a signal ꢀhile in transition

ꢁmetastable state). This ꢀill not harm the device, but

there is no guarantee as to the value that ꢀill be captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register ꢀill

capture the correct value of a signal, the SRAM signal

must be stabilized long enough to meet the TAP

controller’s capture setup plus hold time ꢁ^tCS plus ^tCH).

The SRAM clock input might not be captured correctly if

there is no ꢀay in a design to stop ꢁor sloꢀ) the clock

during a SAMPLE/PRELOAD instruction. If this is an

issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It

also places the instruction register betꢀeen the TDI and

TDO pins/balls and alloꢀs the IDCODE to be shifted out

of the device ꢀhen the TAP controller enters the Shift-DR

state. The IDCODE instruction is loaded into the instruc-

tion register upon poꢀer-up or ꢀhenever the TAP con-

troller is given a test logic reset state.

Once the data is captured, it is possible to shift out the

data by putting the TAP into the Shift-DR state. This

places the boundary scan register betꢀeen the TDI and

TDO pins.

Note that since the PRELOAD part of the command is

not implemented, putting the TAP to the Update-DR

state ꢀhile performing a SAMPLE/PRELOAD instruction

ꢀill have the same effect as the Pause-DR command.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan

register to be connected betꢀeen the TDI and TDO pins/

balls ꢀhen the TAP controller is in a Shift-DR state. It also

places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not

implemented, so the device TAP controller is not fully

1149.1-compliant.

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in

the Capture-DR state, a snapshot of data on the inputs

and bidirectional pins/balls is captured in the boundary

scan register.

BYPASS

When the BYPASS instruction is loaded in the instruc-

tion register and the TAP is placed in a Shift-DR state, the

bypass register is placed betꢀeen TDI and TDO. The

advantage of the BYPASS instruction is that it shortens

the boundary scan path ꢀhen multiple devices are con-

nected together on a board.

The user must be aꢀare that the TAP controller clock

can only operate at a frequency up to 10 MHz, ꢀhile the

SRAM clock operates more than an order of magnitude

RESERVED

These instruction are not implemented but are re-

served for future use. Do not use these instructions.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

29

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

TAP TIMING

1

2

3

4

5

6

Test Clock

(TCK)

t

THTH

THTL

TLTH

t

MVTH

DVTH

THMX

Test Mode Select

(TMS)

t

THDX

Test Data-In

(TDI)

t

TLOV

t

TLOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

TAP AC ELECTRICAL CHARACTERISTICS

(Notes 1, 2) (0ºC ≤ T_A≤ +70ºC; +2.4V ≤ VDD ≤ +2.6V)

DESCRIPTION

Clock

SYMBOL

MIN

MAX

UNITS

t

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

Output Times

TCK LOW to TDO unknown

TCK LOW to TDO valid

TDI valid to TCK HIGH

TCK HIGH to TDI invalid

Setup Times

THTH

TF

THTL

TLTH

100

ns

MHz

ns

f

10

t

40

t

ns

t

TLOX

TLOV

0

ns

t

20

t

DVTH

THDX

10

t

TMS setup

Capture setup

MVTH

CS

10

ns

t

Hold Times

TMS hold

t

THMX

CH

10

ns

t

Capture hold

t

NOTE: 1. CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the load in Figure 7.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

30

NOT RECOMMENDED FOR NEW DESIGNS

TAP AC TEST CONDITIONS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

Figure 7

TAP AC Output Load Equivalent

Input pulse levels ...................................... VSS to 2.5V

Input rise and fall times ....................................... 1ns

Input timing reference levels ...........................1.25V

Output reference levels ....................................1.25V

Test load termination supply voltage ..............1.25V

1.25V

50Ω

TDO

Z_O= 50Ω

20pF

3.3V VDD, TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0ºC ≤ T_A≤ +70ºC; +3.135V ≤ VDD ≤ +3.465V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

2.0

MAX

VDD + 0.3

0.8

UNITS

V

NOTES

1, 2

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

VIH

VIL

ILI

-0.3

-5.0

V

1, 2

0V ≤ VIN ≤ VDD

Output(s) disabled,

0V ≤ VIN ≤ VDDQ (DQx)

IOLC = 100µA

5.0

µA

ILO

5.0

Output Low Voltage

Output High Voltage

VOL1

VOL2

VOH1

VOH2

0.7

0.8

V

1

IOLT = 2mA

IOHC = 100µA

2.9

2.0

I^OHT= 2mA

2.5V VDD, TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0ºC ≤ T_A≤ +70ºC; +2.4V ≤ VDD ≤ +2.6V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

1.7

MAX

VDD + 0.3

0.7

UNITS

V

NOTES

1, 2

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

VIH

VIL

ILI

-0.3

-5.0

V

1, 2

0V ≤ VIN ≤ VDD

Output(s) disabled,

0V ≤ VIN ≤ VDDQ (DQx)

IOLC = 100µA

5.0

µA

ILO

5.0

Output Low Voltage

Output High Voltage

VOL1

VOL2

VOH1

VOH2

0.2

0.7

V

1

IOLT = 2mA

IOHC = 100µA

2.1

1.7

IOHT = 2mA

NOTE: 1. All voltages referenced to VSS (GND).

t

2. Overshoot:

VIH (AC) ≤ VDD + 1.5V for t ≤ KHKH/2

t

Undershoot: VIL (AC) ≥ -0.5V for t ≤ KHKH/2

Power-up:

During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD#, R/W#, etc.) may not have

V^IH≤ +2.6V and VDD ≤ 2.4V and VDDQ ≤ 1.4V for t ≤ 200ms

t

f

pulse widths less than KHKL (MIN) or operate at frequencies exceeding KF (MAX).

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

31

NOT RECOMMENDED FOR NEW DESIGNS

IDENTIFICATION REGISTER DEFINITIONS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

INSTRUCTION FIELD 512K x 18

DESCRIPTION

REVISION NUMBER

(31:28)

xxxx

Reserved for version number.

Defines depth of 512K or 1Mb words.

Defines width of 18, 32, or 36 bits.

Reserved for future use.

DEVICE DEPTH

(27:23)

00111

00011

xxxxxx

DEVICE WIDTH

(22:18)

MICRON DEVICE ID

(17:12)

MICRON JEDEC ID

CODE (11:1)

00000101100 Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

ID Register Presence

Indicator (0)

1

SCAN REGISTER SIZES

REGISTER NAME

Instruction

Bypass

BIT SIZE

3

1

ID

32

Boundary Scan

x18: 52 x32: 67 x36: 71

INSTRUCTION CODES

INSTRUCTION

CODE

DESCRIPTION

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI

and TDO. This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1-compliant.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect

SRAM operations.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

165-BALL FBGA BOUNDARY SCAN ORDER (x18)

FBGA BIT#

SIGNAL NAME

SA

BALL ID

8P

FBGA BIT#

27

SIGNAL NAME

CLK

BALL ID

6B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

SA

9R

9P

10R

10P

11R

8R

10M

10L

10K

10J

11H

11G

11F

11E

11D

11C

11A

10B

10A

9A

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

CE2#

BWa#

BWb#

CE2

CE#

SA

6A

5B

4A

3B

3A

2A

2B

2D

2E

SA

DQa

ZZ

DQa

DQPa

SA

DQb

VSS

2F

2G

1H

1J

1K

1L

1M

1N

1R

DQb

DQPb

MODE (LBO#)

SA

3P

3R

SA

9B

8A

8B

7A

SA

SA1

SA0

4P

4R

6P

6R

ADV/LD#

OE# (G#)

CKE#

R/W#

7B

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

33

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

165-BALL FBGA BOUNDARY SCAN ORDER (x32)

FBGA BIT#

SIGNAL NAME

SA

BALL ID

8P

FBGA BIT#

34

SIGNAL NAME

CE2#

BALL ID

6A

5B

5A

4A

4B

3B

3A

2A

2B

1D

1E

1

2

3

4

5

6

7

8

SA

9R

9P

10R

10P

11R

8R

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

BWa#

BWb#

BWc#

BWd#

CE2

CE#

SA

DQc

VSS

SA

DQa

ZZ

DQb

SA

11M

11L

11K

11J

10M

10L

10K

10J

11H

11G

11F

11E

11D

10G

10F

10E

10D

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

1F

1G

2D

2E

2F

2G

1H

1J

1K

1L

DQd

MODE (LBO#)

SA

1M

2J

2K

2L

2M

1R

3P

3R

4P

SA

9B

8A

8B

7A

7B

6B

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

SA

SA1

4R

6P

6R

SA0

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

34

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

165-BALL FBGA BOUNDARY SCAN ORDER (x36)

FBGA BIT#

SIGNAL NAME

SA

BALL ID

8P

FBGA BIT#

36

SIGNAL NAME

CE2#

BALL ID

6A

5B

5A

4A

4B

3B

3A

2A

2B

1C

1D

1E

1

2

3

4

5

6

7

8

SA

9R

9P

10R

10P

11R

8R

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

BWa#

BWb#

BWc#

BWd#

CE2

CE#

SA

NF/DQPc

DQc

SA

NF/DQPa

DQa

ZZ

DQb

NF/DQPb

SA

11N

11M

11L

11K

11J

10M

10L

10K

10J

11H

11G

11F

11E

11D

10G

10F

10E

10D

11C

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

1F

1G

2D

2E

2F

2G

1H

1J

1K

1L

1M

2J

2K

2L

2M

1N

1R

3P

3R

4P

4R

6P

6R

VSS

DQd

NF/DQPd

MODE (LBO#)

SA

9B

8A

8B

7A

7B

6B

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

SA

SA1

SA0

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

35

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

100-PIN PLASTIC TQFP

(JEDEC LQFP)

+0.10

-0.20

22.10

20.10 0.10

0.65 TYP

0.32

+0.06

-0.10

0.625

(TYP)

SEE DETAIL A

14.00 0.10

16.00 0.20

PIN #1 ID

+0.03

0.15

1.40 0.05

-0.02

GAGE PLANE

0.60 0.15

1.60 MAX

0.10

+0.10

-0.05

0.10

1.00 TYP

0.10

DETAIL A

MAX

MIN

NOTE: 1. All dimensions in millimeters

or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

36

NOT RECOMMENDED FOR NEW DESIGNS

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

165-BALL FBGA

0.85 0.075

0.12

C

SEATING PLANE

C

BALL A11

165X Ø 0.45

10.00

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION. THE

PRE-REFLOW DIAMETER IS Ø 0.40

BALL A1

PIN A1 ID

1.20 MAX

1.00

TYP

PIN A1 ID

7.50 0.05

14.00

15.00 0.10

7.00 0.05

1.00

TYP

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 0.05

5.00 0.05

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb

SOLDER BALL PAD: Ø .33mm

13.00 0.10

MAX

MIN

NOTE: 1. All dimensions in millimeters

or typical where noted.

DATA SHEET DESIGNATION

No Marking

This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications

are subject to change, as further product development and data characterization sometimes

occur.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M and Micron logos are trademarks and/or servicemarks of Micron Technology, Inc.

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc.,

and the architecture is supported by Micron Technology, Inc., and Motorola Inc.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

37

NOT RECOMMENDED FOR NEW DESIGNS

REVISION HISTORY

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

Rev. H, Pub. 9/02 ................................................................................................................................................................ Sept/02

• Updated operating temperature range: From +10ºC ≤ T_J≤ +110ºC to 0ºC ≤ T_A≤ +70ºC

Rev. G, Pub. 6/02 ................................................................................................................................................................ June/02

• Added “NOT RECOMMENDED FOR NEW DESIGNS” to header

Rev. F, Pub. 3/02 .................................................................................................................................................................. Mar/02

• Removed 119-Pin PBGA and references

• Removed ADVANCE designation

• Updated operating temperature range:

From 0ºC ≤ T_A≤ +70ºC to +10ºC ≤ T_J≤ +110ºC

• Removed -8.8 speed grade from 2.± V^DDand I/O

• Removed -10 speed grade from 3.3 VDD and I/O

Rev. E, Pub. 1/02, ADVANCE .............................................................................................................................................. Jan/02

• Changed MAX temperature from +70ºC to +110ºC

• Updated 100-pin TQFP capacitance values:

CI from TYP 3pF, MAX 4pF to TYP 4.8pF, MAX 6.0pF

C^Ofrom TYP 4pF, MAX ±pF to TYP 3.8pF, MAX 4.±pF

CA from TYP 3pF, MAX 3.±pF to TYP 4.7pF, MAX ±.±pF

C^CKfrom TYP 3pF, MAX 3.±pF to TYP 4.±pF, MAX ±.0pF

Rev. D, Pub. 9/01, ADVANCE............................................................................................................................................ Sept/01

• Removed -11 speed grade from 3.3 VDD and I/O

Rev. C, Pub. 9/01, ADVANCE ............................................................................................................................................ Sept/01

• Removed Industrial Temperature references

• Changed IDD tables by splitting x18 and x32/36 configuration

• Changed NC references to NF

• Removed note “Not Recommended for Neꢀ Design” from 119-pin FBGA

• Changed boundary scan order, 16±-ball FBGA, x18 and x32/36

8P ꢁSA) moved to bit #7 from bit #1

• Increased I^DDtable values

Rev. 3/01, ADVANCE ................................................................................................................................................ March/19/01

• Added Industrial Temperature note and references

• Changed 16Mb to 18Mb references

• Added -8.8 speed grades

Rev. 1/01, ADVANCE ....................................................................................................................................................... Jan/9/01

• Added 16±-ball JTAG Boundary Scan

• Added 119-pin PBGA package and references

Rev. 8/00, ADVANCE .................................................................................................................................................... Aug/22/00

• Removed FBGA Part Marking Guide

Rev. 7/00, ADVANCE ...................................................................................................................................................... Aug/8/00

• Changed FBGA capacitance values

• CI; TYP 2.± pF from 4 pF; MAX 3.± pF from ± pF

• C^O; TYP 4 pF from 6 pF; MAX ± pF from 7 pF

• CCK; TYP 2.± pF from ± pF; MAX 3.± pF from 6 pF

Rev. 7/00, ADVANCE ..................................................................................................................................................... Jun/28/00

• Added 16±-PIN FBGA Package

• Added FBGA Part Marking References

• Removed 119-Pin PBGA and references

Rev. 4/00, ADVANCE ..................................................................................................................................................... Apr/13/00

• Added note: ZZ has internal pull-doꢀn

Rev. 3/00, ADVANCE ....................................................................................................................................................... Apr/6/00

• Updated Boundary Scan Order

Rev. 1/00, ADVANCE ..................................................................................................................................................... Jan/18/00

• Added BGA JTAG functionality

• Added 119-pin PBGA package

• Added ADVANCE status

Original document, Rev. 11/99, DRAFT ..................................................................................................................... Nov/11/99

18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM

MT55L1MY18F_H.p65 – Rev. G, Pub. 6/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

38


型号：	MT55V1MV18FF-12
厂家：	CYPRESS
描述：	ZBT SRAM, 1MX18, 9ns, CMOS, PBGA165, FBGA-165 静态存储器
文件：	总38页 (文件大小：515K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT55V1MV18FF-12 [CYPRESS]

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