MT58V512V36PT-10_技术文档

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

MT58L1MY18P, MT58V1MV18P,

MT58L512Y32P, MT58V512V32P,

18Mb SYNCBURST^™

SRAM

MT58L512Y36P, MT58V512V36P

3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O

Features

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

•

Fast clock and OE# access times

Single 3.3V ±± percent or 2.±V ±± percent power

supply

•

Separate 3.3V ±± percent or 2.±V ±± percent isolated

output buffer supply (VDDQ)

•

SNOOZE MODE for reduced-power standby

Single-cycle deselect (Pentium^®BSRAM-

compatible)

•

Common data inputs and data outputs

Individual byte write control and global write

Three chip enables for simple depth expansion and

address pipelining

•

Clock-controlled and registered addresses, data

I/Os, and control signals

•

Internally self-timed WRITE cycle

Burst control (interleaved or linear burst)

Low capacitive bus loading

Figure 2: 165-Ball FBGA

JEDEC-Standard MS-216 (Var. CAB-1)

TQFP

Options

Marking

•

Timing (Access/Cycle/MHz)

3.1ns/±ns/200 MHz

3.±ns/6ns/166 MHz

4.2ns/7.±ns/133 MHz

±ns/10ns/100 MHz

Configurations

3.3V VDD, 3.3V or 2.±V I/O

1 Meg x 18

-±

-6

-7.±

-10

•

MT±8L1MY18P

MT±8L±12Y32P

MT±8L±12Y36P

±12K x 32

±12K x 36

Part Number Example:

2.±V VDD, 2.±V I/O

1 Meg x 18

±12K x 32

±12K x 36

Packages

MT58L512Y36PT-10

MT±8V1MV18P

MT±8V±12V32P

MT±8V±12V36P

General Description

The Micron^®SyncBurst™ SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

•

100-pin TQFP

T

16±-ball, 13mm x 1±mm FBGA

Operating Temperature Range

Commercial (0ºC ? T_A? +70ºC)

F¹

Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x

18, ±12K x 32, or ±12K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single-clock

input (CLK). The synchronous inputs include all

addresses, all data inputs, active LOW chip enable

(CE#), two additional chip enables for easy depth

expansion (CE2, CE2#), burst control inputs (ADSC#,

None

IT²

Industrial (-40ºC ? T_A? +8±ºC)

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

2. Contact factory for availability of Industrial Temperature

devices.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

1

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

ADSP#, ADV#), byte write enables (BWx#), and global

write (GW#).

DQPb; BWc# controls DQc pins/balls and DQPc; BWd#

controls DQd pins/balls and DQPd. GW# LOW causes

all bytes to be written. Parity bits are only available on

the x18 and x36 versions.

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is

also a burst mode input (MODE) that selects between

interleaved and linear burst modes. The data out (Q) is

enabled by OE#. WRITE cycles can be from one to two

bytes wide (x18) or from one to four bytes wide (x32/

x36), as controlled by the write control inputs.

This device incorporates a single-cycle deselect fea-

ture during READ cycles. If the device is immediately

deselected after a READ cycle, the output bus goes to a

t

High-Z state KQHZ nanoseconds after the rising edge

of clock.

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) inputs. Subsequent burst addresses can be

internally generated as controlled by the burst

advance input (ADV#).

The device is ideally suited for Pentium and Pow-

erPC pipelined systems and systems that benefit from

a very wide, high-speed data bus. The device is also

ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide

applications.

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins/balls and DQPa; BWb# con-

trols DQb pins/balls and DQPb. During WRITE cycles

on the x32 and x36 devices, BWa# controls DQa pins/

balls and DQPa; BWb# controls DQb pins/balls and

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

DUAL VOLTAGE I/O

The 3.3V VDD device is tested for 3.3V and 2.±V I/O

function. The 2.±V VDD device is tested for only 2.±V

I/O function.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 3: Functional Block Diagram

1 Meg x 18

20

18

20

2

ADDRESS

REGISTER

SA0, SA1, SAs

MODE

SA0-SA1

Q1

SA1'

ADV#

CLK

BINARY

COUNTER AND

LOGIC

SA0'

CLR

Q0

ADSC#

ADSP#

BYTE “b”

WRITE DRIVER

BYTE “b”

WRITE REGISTER

9

OUTPUT

BUFFERS

BWb#

DQs

DQPa

DQPb

1 Meg x 9 x 2

MEMORY

ARRAY

OUTPUT

REGISTERS

SENSE

AMPS

18

BYTE “a”

WRITE DRIVER

E

BYTE “a”

WRITE REGISTER

BWa#

BWE#

INPUT

REGISTERS

GW#

18

ENABLE

REGISTER

CE#

CE2

PIPELINED

ENABLE

CE2#

OE#

2

Figure 4: Functional Block Diagram

512K x 32/36

19

17

19

ADDRESS

REGISTER

SA0, SA1, SAs

MODE

SA0-SA1

SA1'

SA0'

Q1

BINARY

COUNTER

ADV#

CLK

CLR

Q0

ADSC#

ADSP#

BYTE “d”

WRITE DRIVER

BYTE “d”

WRITE REGISTER

9

BWd#

BWc#

512K x 8 x 4

(x32)

BYTE “c”

WRITE DRIVER

BYTE “c”

WRITE REGISTER

OUTPUT

BUFFERS

OUTPUT

REGISTERS

512K x 9 x 4

(x36)

SENSE

AMPS

DQs

36

DQPa

DQPb

DQPc

DQPd

E

BYTE “b”

WRITE DRIVER

MEMORY

ARRAY

BYTE “b”

WRITE REGISTER

9

BWb#

BYTE “a”

WRITE DRIVER

BYTE “a”

WRITE REGISTER

BWa#

BWE#

INPUT

REGISTERS

36

GW#

CE#

CE2

ENABLE

REGISTER

PIPELINED

ENABLE

CE2#

OE#

4

NOTE:

Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball descriptions, and tim-

ing diagrams for detailed information.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 5: Pin layout (Top View)

100-Pin TQFP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SA

81

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

SA

ADV#

ADSP#

ADSC#

OE# (G#)

BWE#

GW#

CLK

SA

V^SS

VDD

V^DD

VSS

DNU

SA0

SA1

SA

x18

2

CE2#

BWa#

BWb#

NC

CE2

SA

CE#

SA

MODE

(LBO#)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81

SA

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

V^DD

VSS

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

ADV#

ADSP#

ADSC#

OE# (G#)

BWE#

GW#

CLK

V^SS

VDD

x32/x36

2

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

DNU

SA0

SA1

SA

CE#

SA

MODE

(LBO#)

1 2 3 4 5 6 7 8 9 10 11 12 1314151617181920 21 22 2324 252627 28 29 30

NOTE:

1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.

2. Pins 39 and 38 are reserved for address expansion, 36Mb and 72Mb, respectively.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 1:

TQFP Pin Descriptions

SYMBOL

TYPE

DESCRIPTION

ADSC#

Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,

causing a new external address to be registered. A READ or WRITE is performed using the new

address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is

HIGH.

ADSP#

ADV#

Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,

causing a new external address to be registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.

ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.

Input Synchronous Address Advance: This active LOW input is used to advance the internal burst

counter, controlling burst access after the external address is loaded. A HIGH on this pin

effectively causes wait states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an

ADSP# cycle is initiated.

BWa#

BWb#

BWc#

BWd#

Input

Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a

WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK.

BWs need to be asserted on the same cycle as the address. To enable the BW’s functionality, the

byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa pins; BWb# controls

DQb pins; BWc# controls DQc pins; and BWd# controls DQa pins.

BWE#

CE#

Input

Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the

setup and hold times around the rising edge of CLK.

Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the

internal use of ADSP#. CE# is sampled only when a new external address is loaded.

CE2#

CE2

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only

when a new external address is loaded.

Input

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only

when a new external address is loaded.

CLK

Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst control

inputs on its rising edge. All synchronous inputs must meet setup and hold times around the

clock’s rising edge.

GW#

Input

Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent

of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of

CLK.

MODE (LBO#)

OE# (G#)

Input

Mode: This input selects the burst sequence. A LOW on this pin selects “linear burst.” NC or HIGH

on this pin selects “interleaved burst.” Do not alter input state while device is operating. LBO# is

the JEDEC-standard term for MODE.

Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is

the JEDEC-standard term for OE#.

SA0

SA1

SA

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK.

ZZ

Input

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power

standby mode in which all data in the memory array is retained. When ZZ is active, all other

inputs are ignored. This pin has an internal pull-down and can be left unconnected.

DQa

DQb

DQc

DQd

Input/

Output

SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa pins; byte “b” is associated

with DQb pins. For the x32 and x36 versions, byte “a” is associated with DQa pins; byte “b” is

associated with DQb pins; byte “c” is associated with DQc pins; byte “d” is associated with DQd

pins. Input data must meet setup and hold times around the rising edge of CLK.

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

NF

I/O

No Function/Parity Data I/Os: On the x32 version, these pins are No Function (NF). On the x18

version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity is

DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 1:

TQFP Pin Descriptions (continued)

SYMBOL

TYPE

DESCRIPTION

VDD

Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range.

VDDQ

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for

range.

VSS

Supply

–

Ground: GND.

DNU

Do Not Use: These pins are internally connected to the die. They may be left floating or

connected to ground to improve package heat dissipation.

NC

NF

–

No Connect: These pins are not internally connected to the die. They may be left floating, driven

by signals, or connected to ground to improve package heat dissipation.

No Function: These pins are internally connected to the die and have the capacitance of an input

pin. They may be left floating, driven by signals, or connected to ground to improve package

heat dissipation.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 6: Ball Layout (Top View)

165-Ball FBGA

x18

x32/x36

1

2

3

4

5

6

7

8

9

10

11

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

NC

SA

NC

CE# BWb#

NC

CE2# BWE# ADSC# ADV#

SA

NC

SA

NC

CE# BWc# BWb# CE2# BWE# ADSC# ADV#

SA

NC

CE2

NC

VSS

BWa# CLK

GW# OE# (G#) ADSP# SA

CE2 BWd# BWa# CLK

GW# OE# (G#) ADSP# SA

1

NC

VDDQ

VSS

NC

VSS

SA

VSS

TD0

TCK

VSS

VDD

VSS

VDDQ

NC

DQPa

DQa

ZZ

NF/DQPc

DQc

VDD

VDDQ

VSS

VDD

VSS

NC

VSS

SA

VSS

TD0

TCK

VSS

VDD

VSS

VDDQ

NC NF/DQPb

NC

DQb VDDQ

VDD

VSS

DQc VDDQ

VDDQ DQb DQb

NC

F

NC

G

H

J

G

H

J

G

H

J

G

H

J

NC

VDD

DQb

DQPb

NC

VSS

NC

VSS

NC

ZZ

VDDQ

SA

VDDQ DQa

NC

DQd DQd VDDQ

VDDQ DQa

DQa

K

L

K

L

K

L

K

L

NC

M

N

P

M

N

P

M

N

P

M

N

P

NC

DQd DQd VDDQ

1

VDDQ

SA

NC

SA

NC

1

NF/DQPd

NC

VDDQ

SA

NC NF/DQPa

2

NC

SA

TDI

TMS

SA1

SA0

SA

2

NC

SA

TDI

TMS

SA1

SA0

SA

R

2

MODE NC

(LBO#)

SA

2

MODE NC

(LBO#)

SA

TOP VIEW

NOTE:

1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.

2. Balls 2R and 2P are reserved for address expansionely, 36Mb and 72Mb, respectively.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 2:

FBGA Ball Descriptions

SYMBOL

TYPE

DESCRIPTION

ADSC#

Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,

causing a new extrnal address to be registered. A READ or WRITE is performed using the new

address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is

HIGH.

ADSP#

ADV#

Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,

causing a new external address to be registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.

ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.

Input Synchcronous Address Advance: This active LOW input is used to advance the internal burst

counter, controlling busrt access after the external address is loaded. A HIGH on ADV#

effectively causes wait states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an

ADSP# cycle is initiated.

BWa#

BWb#

BWc#

BWd#

Input

Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a

WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK.

BWs need to be asserted on the same cycle as the address. To enable the BW’s functionality, the

byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa balls; BWb# controls

DQb balls; BWc# controls DQc balls; and BWd# controls DQa balls.

BWE#

CE#

Input

Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the

setup and hold times around the rising edge of CLK.

Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the

internal use of ADSP#. CE# is sampled only when a new external address is loaded.

CE2#

CE2

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only

when a new external address is loaded.

Input

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled

only when a new external address is loaded.

CLK

Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst control

inputs on its rising edge. All synchronous inputs must meet setup and hold times around the

clock’s rising edge.

GW#

Input

Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent

of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of

CLK.

MODE (LBO#)

OE#(G#)

Input

Mode: This input selects the burst sequence. A LOW on this ball selects “linear burst.” NC or

HIGH on this ball selects “interleaved burst.” Do not alter input state while device is operating.

LBO# is the JEDEC-standard term for MODE.

Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is

the JEDEC-standard term for OE#.

SA0

SA1

SA

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK.

TMS

TDI

Input

IEEE 1149.1 test inputs: JEDEC-standard 3.3V or 2.5V I/O levels. These balls may be left as No

Connects if the JTAG function is not used in the circuit.

TCK

ZZ

Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power

standby mode in which all data in the memory array is retained. When ZZ is active, all other

inputs are ignored. This ball has an internal pull-down and can be left unconnected.

DQa

DQb

DQc

DQd

Input/

SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa pins; byte “b” is associated

Output with DQb balls. For the x32 and x36 versions, byte “a” is associated with DQa balls; byte “b” is

associated with DQb balls; byte “c” is associated with DQc balls; byte “d” is associated with DQd

balls. Input data must meet setup and hold times around the rising edge of CLK.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 2:

FBGA Ball Descriptions (continued)

SYMBOL

TYPE

DESCRIPTION

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

NF

I/O

No Function/Parity Data I/Os: On the x32 version, these pins are No Function (NF). On the x18

version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity is

DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.

TDO

VDD

Output

Supply

IEEE 1149.1 test outputs: JEDEC-standard 3.3V or 2.5V I/O levels.

Power Supply: See DC Electrical Characteristics and Operating Conditions for range.

VDDQ

Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for

range.

VSS

NC

Supply Ground: GND.

–

No Connect: These balls are not internally connected to the die. They may be left floating,

driven by signals, or connected to ground to improve package heat dissipation.

NF

–

No Function: These balls are internally connected to the die and have the capacitance of an

input pin. They may be left floating, driven by signals, or connected to ground to improve

package heat dissipation.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 3:

Interleaved Burst Address Table (Mode = NC or HIGH)

FIRST ADDRESS

(EXTERNAL)

SECOND ADDRESS

(INTERNAL)

THIRD ADDRESS

(INTERNAL)

FOURTH ADDRESS

(INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

Table 4:

Linear Burst Address Table (Mode = LOW)

FIRST ADDRESS

(EXTERNAL)

SECOND ADDRESS

(INTERNAL)

THIRD ADDRESS

FOURTH ADDRESS

(INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

Table 5:

Partial Truth Table For WRITE Commands (x18)

FUNCTION

GW#

BWE#

BWa#

BWb#

READ

H

L

H

L

X

H

L

X

H

L

READ

WRITE Byte “a”

WRITE Byte “b”

WRITE All Bytes

L

H

L

X

NOTE:

Using BWE# and BWa# through BWd#, any one or more bytes may be written.

Table 6:

Partial Truth Table For WRITE Commands (x32/x36)

FUNCTION

GW#

BWE#

BWa#

BWb#

BWc#

BWd#

READ

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

READ

WRITE Byte “a”

WRITE All Bytes

L

X

NOTE:

Using BWE# and BWa# through BWd#, any one or more bytes may be written.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 7:

Notes: 1–8

Truth Table

ADDRESS

USED

OPERATION

CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE# CLK

DQ

None

H

X

H

X

H

X

L

X

L

X

L

X

L–H

X

High-Z

DESELECT Cycle,

Power-Down

L

High-Z

DESELECT Cycle,

Power-Down

DESELECT Cycle,

Power-Down

L

X

L

H

X

DESELECT Cycle,

Power-Down

L

X

L

DESELECT Cycle,

Power-Down

SNOOZE MODE,

Power-Down

X

H

X

External

L

H

X

L

X

L

X

L

X

L

H

X

L

L–H

Q

READ Cycle, Begin Burst

WRITE Cycle, Begin Burst

READ Cycle, Begin Burst

READ Cycle, Continue Burst

WRITE Cycle, Continue Burst

READ Cycle, Suspend Burst

WRITE Cycle, Suspend Burst

High-Z

L

H

X

H

X

H

X

H

X

D

L

H

L

Q

L

H

L

High-Z

X

H

X

H

X

H

X

H

X

H

Q

H

L

High-Z

Q

H

X

L

High-Z

D

L

D

Current

H

L

Q

High-Z

Q

H

L

H

X

High-Z

D

L

D

NOTE:

1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.

2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#) and BWE# are LOW

or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.

3. BWa# enables WRITEs to DQa pins/balls and DQPa. BWb# enables WRITEs to DQb pins/balls and DQPb. BWc# enables

WRITEs to DQc pins/balls and DQPc. BWd# enables WRITEs to DQd pins/balls and DQPd. DQPa and DQPb are only

available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.

4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held

HIGH throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8. ADSP# LOW always initiates an internal READ at the L–H edge of CLK. A WRITE is performed by setting one or more

byte write enable signals and BWE# LOW or GW# LOW for the subsequent L–H edge of CLK. Refer to WRITE timing

diagram for clarification.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Maximum Junction Temperature depends upon

package type, cycle time, loading, ambient tempera-

ture and airflow.

Absolute Maximum Ratings

3.3V VDD

Voltage on VDD Supply

Relative to VSS .......................................-0.±V to +4.6V

Voltage on VDDQ Supply

Relative to VSS .......................................-0.±V to +4.6V

VIN (DQx) ....................................... -0.±V to VDDQ + 0.±V

VIN (inputs) ....................................... -0.±V to VDD + 0.±V

Storage Temperature (TQFP).................-±±ºC to +1±0ºC

Storage Temperature (FBGA).................-±±ºC to +12±ºC

Junction Temperature .......................................... +1±0ºC

Short Circuit Output Current ...............................100mA

2.5V VDD

Voltage on VDD Supply

Relative to VSS .......................................-0.3V to +3.6V

Voltage on VDDQ Supply

Relative to VSS .......................................-0.3V to +3.6V

VIN (DQx) ....................................... -0.3V to VDDQ + 0.3V

VIN (inputs) ....................................... -0.3V to VDD + 0.3V

Storage Temperature (TQFP).................-±±ºC to +1±0ºC

Storage Temperature (FBGA).................-±±ºC to +12±ºC

Junction Temperature .......................................... +1±0ºC

Short Circuit Output Current ...............................100mA

Table 8:

3.3V VDD, 3.3V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 17; 0ºC ? T_A? +70ºC; VDD and VDDQ = 3.3V 0.165V unless otherwise

noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

VIH

VIL

ILI

2.0

-0.3

-1.0

VDD + 0.3

0.8

V

1, 2

4

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

0V ? VIN ? VDD

1.0

µA

Output(s) disabled,

ILO

1.0

Output Leakage Current

0V ? VIN ? VDD

IOH = -4.0mA

IOL = 8.0mA

VOH

VOL

2.4

–

V

1

Output High Voltage

Output Low Voltage

Supply Voltage

0.4

VDD

3.135

3.465

VDD

1

VDDQ

1, 5

Isolated Output Buffer Supply

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 9:

3.3V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 17; 0ºC ? T_A? +70ºC; VDD = 3.3V 0.165V and VDDQ = 2.5V 0.125V unless

otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Data bus (DQx)

Inputs

VIHQ

VIH

VIL

1.7

VDDQ + 0.3

VDD + 0.3

0.7

V

1, 2

4

Input High (Logic 1) Voltage

-0.3

-1.0

V

Input Low (Logic 0) Voltage

Input Leakage Current

0V ? VIN ? VDD

ILI

1.0

µA

Output(s) disabled,

ILO

1.0

Output Leakage Current

0V ? VIN ? VDDQ (DQx)

IOH = -2.0mA

IOH = -1.0mA

IOL = 2.0mA

IOL = 1.0mA

VOH

VOL

1.7

2.0

–

V

1

Output High Voltage

Output Low Voltage

–

0.7

1

VOL

–

0.4

1

VDD

VDDQ

3.135

2.375

3.465

2.625

1

Supply Voltage

1, 5

Isolated Output Buffer Supply

Table 10: 2.5V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 17; 0ºC ? T_A? +70ºC; VDD and VDDQ = 2.5V 0.125V unless otherwise

noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Data bus (DQx)

Inputs

VIHQ

VIH

VIL

1.7

VDDQ + 0.3

VDD + 0.3

0.7

V

1, 3

4

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

-0.3

-1.0

V

0V ? VIN ? VDD

ILI

1.0

µA

Output Leakage Current

Output(s) disabled,

ILO

1.0

0V ? VIN ? VDDQ (DQx)

Output High Voltage

Output Low Voltage

IOH = -2.0mA

IOH = -1.0mA

IOL = 2.0mA

IOL = 1.0mA

VOH

VOL

1.7

2.0

–

V

1

–

0.7

1

VOL

–

0.4

1

VDD

VDDQ

2.375

2.625

1

Supply Voltage

1, 5

Isolated Output Buffer Supply

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 11: TQFP Capacitance

Note 6; notes appear following parameter tables on page 17

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

CI

CO

CA

4.2

3.5

4

5

4

5

pF

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Input Capacitance

Clock Capacitance

T_A= 25ºC; f = 1 MHz;

VDD = 3.3V

CCK

4.2

Table 12: FBGA Capacitance

Note 6; notes appear following parameter tables on page 17

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

CI

CO

CA

4

5

pF

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Input Capacitance

Clock Capacitance

4.5

5

T_A= 25ºC; f = 1 MHz;

VDD = 3.3V

CCK

5.5

Table 13: TQFP Thermal Resistance

Note 6; notes appear following parameter tables on page 17

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

Junction to Ambient

(Airflow of 1m/s, two-layer

board)

ꢀ

28.9

°C/W

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51.

JA

Thermal Resistance

Junction to Case (Top)

ꢀ

4.2

°C/W

JC

Table 14: FBGA Thermal Resistance

Note 6; notes appear following parameter tables on page 17

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

ꢀ

32

°C/W

Junction to Ambient

(Airflow of 1m/s, two-layer

board)

JA

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51.

Junction to Case (Top)

ꢀ

1.7

°C/W

JC

Junction to Board (Bottom)

ꢀ

10.4

JB

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 15: 3.3V VDD IDD Operating Conditions and Maximum Limits

(1 Meg x 18 and 512K x 36)

Notes appear following parameter tables on page 17; 0ºC ? T_A? +70ºC; VDD and VDDQ = 3.3V 0.165V unless otherwise

noted

MAX

DESCRIPTION

CONDITIONS

SYM TYP

-5

-6

-7.5

-10

UNITS NOTES

Power Supply

Current:

Device selected; All inputs ? VIL or

t

O VIH; Cycle time O KC (MIN);

IDD

300

120

420

380

340

300

mA

7, 8, 9

VDD = MAX; Outputs open

Operating

Device selected; VDD = MAX;

ADSC#, ADSP#, GW#, BWx#,

ADV# OꢁVIH; All inputs ? VSS + 0.2

Power Supply

Current: Idle

IDD1

180

30

170

30

160

30

150

30

t

or O VDDQ - 0.2; Cycle time O KC (MIN)

Device deselected; VDD = MAX;

All inputs ? VSS + 0.2

or O VDDQ - 0.2; All inputs static;

CLK frequency = 0

CMOS Standby

Clock Running

Snooze Mode

ISB2

8

mA

8, 9

Device deselected; VDD = MAX; ADSC#,

ADSP#, GW#, BWx#,

ISB4

120

8

180

30

170

30

160

30

150

30

mA

8, 9

9

ADV# OꢁVIH; All inputs ? VSS + 0.2

t

or O VDDQ - 0.2; Cycle time O KC (MIN)

ZZ OꢁVIH

ISB2Z

Table 16: 2.5V VDD, IDD Operating Conditions and Maximum Limits

(1 Meg x 18 and 512K x 36)

Notes appear following parameter tables on page 17; 0ºC ? T_A? +70ºC; VDD and VDDQ = 2.5V 0.125V unless otherwise

noted

MAX

DESCRIPTION

CONDITIONS

SYM TYP

-5

-6

-7.5

-10

UNITS NOTES

Power Supply

Current:

Device selected; All inputs ? VIL or

t

O VIH; Cycle time O KC (MIN);

IDD

230

90

350

300

260

230

mA

7, 8, 10

VDD = MAX; Outputs open

Operating

Device selected; VDD = MAX;

ADSC#, ADSP#, GW#, BWx#,

ADV# OꢁVIH; All inputs ? VSS + 0.2

Power Supply

Current: Idle

IDD1

150

30

130

30

110

30

90

30

t

or O VDDQ - 0.2; Cycle time O KC (MIN)

Device deselected; VDD = MAX;

All inputs ? VSS + 0.2

or O VDDQ - 0.2; All inputs static;

CLK frequency = 0

CMOS Standby

Clock Running

Snooze Mode

ISB2

8

mA

8, 10

Device deselected; VDD = MAX; ADSC#,

ADSP#, GW#, BWx#,

ISB4

90

8

150

30

130

30

110

30

90

30

mA

8, 10

10

ADV# OꢁVIH; All inputs ? VSS + 0.2

t

or O VDDQ - 0.2; Cycle time O KC (MIN)

ZZ OꢁVIH

ISB2Z

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 17: AC Electrical Characteristics and Recommended Operating Conditions

Note 11; notes appear following parameter tables on page 17; 0ºC ? T_A? +70ºC; T_J? 95ºC (commercial); T_J? 110ºC

(industrial); VDD = 3.3V 0.165V unless otherwise noted

-5

-6

-7.5

MAX

-10

MAX UNITS NOTES

DESCRIPTION

SYM

MIN

MAX

MIN

MAX

MIN

Clock

^tKC

^fKF

^tKH

^tKL

5.0

6.0

7.5

10.0

ns

MHz

ns

Clock cycle time

200

166

133

4.0

100

5.0

Clock frequency

Clock HIGH time

Clock LOW time

2.0

2.3

2.5

3.0

12

ns

Output Times

Clock to output valid

^tKQ

3.1

3.5

ns

^tKQX

^tKQLZ

^tKQHZ

^tOEQ

^tOELZ

^tOEHZ

1.0

0

1.5

0

1.5

0

1.5

0

13

Clock to output invalid

Clock to output in Low-Z

Clock to output in High-Z

OE# to output valid

6, 13, 14

15

3.1

3.5

4.2

4.0

5.0

0

6, 13, 14

OE# to output in Low-Z

OE# to output in High-Z

3.0

3.5

4.5

Setup Times

^tAS

^tADSS

Address

1.4

1.5

2.0

ns

16, 17

Address status (ADSC#,

ADSP#)

^tAAS

^tWS

1.4

1.5

2.0

ns

16, 17

Address advance (ADV#)

Write signals

(BWa#-BWd#, BWE#, GW#)

^tDS

^tCES

1.4

1.5

2.0

ns

16, 17

Data-in

Chip enables (CE#, CE2#,

CE2)

Hold Times

^tAH

^tADSH

0.4

0.5

ns

16, 17

Address

Address status (ADSC#,

ADSP#)

^tAAH

^tWH

0.4

0.5

ns

16, 17

Address advance (ADV#)

Write signals

(BWa#-BWd#, BWE#, GW#)

^tDH

^tCEH

Data-in

0.4

0.5

ns

16, 17

Chip enables (CE#, CE2#,

CE2)

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Notes

1. All voltages referenced to VSS (GND).

2. For 3.3V VDD:

Figures 13 and 14 for 2.±V I/O unless otherwise

noted.

12. Measured as HIGH above V^IHand LOW below VIL.

13. This parameter is measured with the output load-

ing shown in Figure 12 for 3.3V I/O and Figure 14

for 2.±V I/O.

14. Refer to Technical Note TN-±8-09, “Synchronous

SRAM Bus Contention Design Considerations,”

for a more thorough discussion of these parame-

ters.

1±. OE# is a “Don’t Care” when a byte write enable is

sampled LOW.

16. A WRITE cycle is defined by at least one byte write

(BWa#–BWd#) being LOW, the byte write enable

(BWE#) active, and ADSC# LOW for the required

setup and hold times. A READ cycle is defined by

the byte write enable (BWE#) being HIGH or

ADSP# LOW for the required setup and hold

times.

17. This is a synchronous device. All addresses must

meet the specified setup and hold times when

either ADSC# or ADSP# is LOW and chip is

enabled. All other synchronous inputs must meet

the setup and hold times with stable logic levels

for all rising edges of CLK when the chip is

enabled. To remain enabled, chip enable must be

valid at each rising edge when either ADSC# or

ADSP# is LOW.

t

Overshoot: VIH ? +4.6V for t ? KC/2 for I ? 20mA

t

Undershoot: VIL O -0.7V for t ? KC/2 for I ? 20mA

Power-up: VIH ? +3.6V and VDD ? 3.13±V for t ?

200ms

3. For 2.±V VDD:

t

Overshoot: VIH ? +3.6V for t ? KC/2 for I ? 20mA

t

Undershoot: VIL O -0.±V for t ? KC/2 for I ? 20mA

Power-up: VIH ? +2.6±V and VDD ? 2.37±V for t ?

200ms

4. The MODE and ZZ pins/balls have an internal

pull-up/pull-down and input leakage = ±10µA.

±. VDDQ should never exceed VDD. VDD and VDDQ

can be connected together.

6. This parameter is sampled.

7. IDD is specified with no output current and

increases with faster cycle times. IDDQ increases

with faster cycle times and greater output loading.

8. “Device deselected” means device is in power-

down mode as defined in the truth table. “Device

selected” means device is active (not in power-

down mode).

9. Typical values are measured at 3.3V, 2±^ºC, and

10ns cycle time.

10. Typical values are measured at 2.±V, 2±^ºC, and

10ns cycle time.

11. Test conditions as specified with the output load-

ing shown in Figures 11 and 12 for 3.3V I/O and

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

17

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 7:

READ Timing

t

KC

CLK

t

KL

KH

t

ADSH

ADSS

ADSP#

ADSC#

t

ADSH

ADSS

t

AH

AS

A1

A2

A3

Burst continued with

ADDRESS

t

WH

WS

new base address

GW#, BWE#,

BWa#-BWd#

Deselect

cycle

t

CEH

(NOTE 4)

CES

CE#

(NOTE 2)

t

AAH

AAS

ADV#

OE#

ADV#

suspends

burst.

t

OEQ

KQ

(NOTE 3)

High-Z

t

OEHZ

t

OELZ

t

KQHZ

KQX

t

KQLZ

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Q(A1)

Q

t

KQ

Burst wraps around

to its initial state

(NOTE 1)

Single READ

BURST READ

DON’T CARE

UNDEFINED

NOTE:

1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#

is HIGH, CE2# is HIGH and CE2 is LOW.

3. Timing diagram is shown assuming that the device was not enabled before entering into this sequence. OE# does not

cause Q to be driven until after the following clock rising edge. (This note applies to whole diagram.)

4. Outputs are disabled within one clock cycle after deselect.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

18

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 8:

WRITE Timing

t

KC

CLK

t

KL

KH

t

ADSH

ADSS

ADSP#

ADSC# extends burst

t

ADSH

ADSS

t

ADSH

ADSS

ADSC#

t

AH

AS

A1

A2

A3

ADDRESS

Byte write signals are

ignored for first cycle when

ADSP# initiates burst

t

WS

t

WH

BWE#,

BWa#-BWd#

t

WH (NOTE 5)

WS

GW#

t

CEH

CES

CE#

(NOTE 2)

t

AAS

t

AAH

ADV#

OE#

ADV# suspends burst

(NOTE 4)

(NOTE 3)

t

DH

DS

D

Q

D(A2)

(NOTE 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

High-Z

t

OEHZ

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE UNDEFINED

NOTE:

1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#

is HIGH, CE2# is HIGH and CE2 is LOW.

3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/out-

put data contention for the time period prior to the byte write enable inputs being sampled.

4. ADV# must be HIGH to permit a WRITE to the loaded address.

5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa#, and BWb# LOW for x18 device; or GW#

HIGH and BWE#, BWa#–BWd# LOW for x32 and x36 devices.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

19

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 9:

READ/WRITE Timing

t

KC

CLK

t

KL

KH

t

ADSH

ADSS

ADSP#

ADSC#

t

AH

AS

A1

A2

A3

A4

A5

A6

ADDRESS

t

WH

WS

BWE#,

BWa#-BWd#

(NOTE 4)

t

CEH

CES

CE#

(NOTE 2)

ADV#

OE#

D

t

DH

t

KQ

DS

t

OELZ

High-Z

D(A3)

D(A5)

D(A6)

t

OEHZ

KQLZ

(NOTE 6)

(NOTE 1)

Q(A4)

Q

Q(A1)

Q(A2)

Q(A4+1)

Q(A4+2)

Q(A4+3)

(NOTE 3)

Back-to-Back READs

(NOTE 5)

Single WRITE

BURST READ

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

NOTE:

1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.

2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#

is HIGH, CE2# is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed.

4. GW# is HIGH.

5. Back-to-back READs may be controlled by either ADSP# or ADSC#.

6. This undefined READ will follow any WRITE cycle which is transitioned to a Read, Deselect, or Snooze.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

20

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

SNOOZE MODE

SNOOZE MODE is a low-current, power-down

mode in which the device is deselected and current is

reduced to ISB2Z. The duration of SNOOZE MODE is

dictated by the length of time ZZ is in a HIGH state.

After the device enters SNOOZE MODE, all inputs

except ZZ become gated inputs and are ignored.

ZZ is an asynchronous, active HIGH input that

causes the device to enter SNOOZE MODE. When ZZ

becomes a logic HIGH, ISB2Z is guaranteed after the

setup time ZZ is met. Any READ or WRITE operation

pending when the device enters SNOOZE MODE is not

guaranteed to complete successfully. Therefore,

SNOOZE MODE must not be initiated until valid pend-

ing operations are completed.

t

Table 18: SNOOZE MODE Electrical Characteristics

DESCRIPTION

CONDITIONS

SYMBOL

ISB2Z

^tZZ

^tRZZ

^tZZI

^tRZZI

MIN

MAX

30

2(^tKC)

UNITS

NOTES

ZZ O VIH

mA

ns

Current during SNOOZE MODE

ZZ active to input ignored

1

2(^tKC)

0

ZZ inactive to input sampled

ZZ active to snooze current

ZZ inactive to exit snooze current

ns

2(^tKC)

NOTE:

1. This parameter is sampled.

Figure 10:

SNOOZE MODE Waveform

CLK

t

ZZ

t

RZZ

ZZ

t

ZZI

I

SUPPLY

I

ISB2Z

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

21

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

3.3V VDD, 3.3V I/O AC Test Conditions

2.5V VDD, 2.5V I/O AC Test Conditions

Input pulse levels ....................VIH = (VDD/2.2) + 1.±V

...................................................VIL = (VDD/2.2) - 1.±V

Input rise and fall times......................................... 1ns

Input timing reference levels ........................ VDD/2.2

Output reference levels................................VDDQ/2.2

Output load ..............................See Figures 11 and 12

Input pulse levels .................... VIH = (VDD/2) + 1.2±V

....................................................VIL = (VDD/2) - 1.2±V

Input rise and fall times......................................... 1ns

Input timing reference levels ........................... VDD/2

Output reference levels.................................. VDDQ/2

Output load...............................See Figures 13 and 14

3.3V VDD, 2.5V I/O AC Test Conditions

Input pulse levels ................VIH = (VDD/2.64) + 1.2±V

...............................................VIL = (VDD/2.64) - 1.2±V

Input rise and fall times......................................... 1ns

Input timing reference levels ...................... VDD/2.64

Output reference levels...................................VDDQ/2

Output load ..............................See Figures 13 and 14

3.3V I/O Output Load Equivalents

2.5V I/O Output Load Equivalents

Figure 11:

Figure 13:

V_T= VDDQ/2.2

V_T= VDDQ/2

50Ω

Q

Z_O= 50Ω

30pF

Z_O= 50Ω

30pF

Figure 12:

Figure 14:

+3.3V

+2.5V

317

5pF

225Ω

5pF

Q

351

225Ω

NOTE:

For Figures 11 and 13, 30pF = distributive test jig capacitance.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

22

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

IEEE 1149.1 Serial Boundary Scan (JTAG)

The SRAM incorporates a serial boundary scan test

access port (TAP). This port operates in accordance

with IEEE Standard 1149.1-1990 but does not have the

set of functions required for full 1149.1 compliance.

These functions from the IEEE specification are

excluded because their inclusion places an added

delay in the critical speed path of the SRAM. Note that

the TAP controller functions in a manner that does not

conflict with the operation of other devices using

1149.1 fully compliant TAPs. The TAP operates using

JEDEC-standard 3.3V or 2.±V I/O logic levels.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller.

All inputs are captured on the rising edge of TCK. All

outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It

is allowable to leave this ball unconnected if the TAP is

not used. The ball is pulled up internally, resulting in a

logic HIGH level.

The SRAM contains a TAP controller, instruction

register, boundary scan register, bypass register, and

ID register.

Test Data-In (TDI)

The TDI ball is used to serially input information

into the registers and can be connected to the input of

any of the registers. The register between TDI and TDO

is chosen by the instruction that is loaded into the TAP

instruction register. For information on loading the

instruction register, see Figure 1±. TDI is internally

pulled up and can be unconnected if the TAP is unused

in an application. TDI is connected to the most signifi-

cant bit (MSB) of any register. (See Figure 16.)

Disabling the JTAG Feature

These balls can be left floating (unconnected), if the

JTAG function is not to be implemented. Upon power-

up, the device will come up in a reset state which will

not interfere with the operation of the device.

Figure 15:

TAP Controller State Diagram

Test Data-Out (TDO)

TEST-LOGIC

1

The TDO output ball is used to serially clock data-

out from the registers. The output is active depending

upon the current state of the TAP state machine. (See

Figure 1±.) The output changes on the falling edge of

TCK. TDO is connected to the least significant bit

(LSB) of any register. (See Figure 16.)

RESET

0

1

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

CAPTURE-IR

0

SHIFT-DR

0

SHIFT-IR

0

Figure 16:

1

TAP Controller Block Diagram

1

EXIT1-DR

EXIT1-IR

0

Bypass Register

PAUSE-DR

1

0

PAUSE-IR

1

0

2

1 0

Selection

Circuitry

Selection

Circuitry

0

Instruction Register

31 30 29

Identification Register

EXIT2-DR

1

EXIT2-IR

1

TDI

TDO

.

. 2 1 0

UPDATE-DR

UPDATE-IR

x

.

. 2 1 0

1

0

1

0

Boundary Scan Register*

NOTE:

TCK

TMS

The 0/1 next to each state represents the value

of TMS at the rising edge of TCK.

TAP CONTROLLER

NOTE:

X = 74 for all configurations.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

23

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to

one of the bumps on the SRAM package. The MSB of

the register is connected to TDI, and the LSB is con-

nected to TDO.

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD)

for five rising edges of TCK. This RESET does not affect

the operation of the SRAM and may be performed

while the SRAM is operating.

At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the IDCO-

DEcommand is loaded in the instruction register. The

IDCODE is hardwired into the SRAM and can be

shifted out when the TAP controller is in the Shift-DR

state. The ID register has a vendor code and other

information described in the Identification Register

Definitions table.

TAP Registers

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the

SRAM test circuitry. Only one register can be selected

at a time through the instruction register. Data is seri-

ally loaded into the TDI ball on the rising edge of TCK.

Data is output on the TDO ball on the falling edge of

TCK.

TAP Instruction Set

Overview

Instruction Register

Three-bit instructions can be serially loaded into

the instruction register. This register is loaded when it

is placed between the TDI and TDO balls as shown in

Figure 16. Upon power-up, the instruction register is

loaded with the IDCODE instruction. It is also loaded

with the IDCODE instruction if the controller is placed

in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state,

the two least significant bits are loaded with a binary

“01” pattern to allow for fault isolation of the board-

level serial test data path.

Eight different instructions are possible with the

threebit instruction register. All combinations are

listed in the Instruction Codes table. Three of these

instructions are listed as RESERVED and should not be

used. The other five instructions are described in detail

below.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of

the mandatory 1149.1 instructions are not fully imple-

mented.

The TAP controller cannot be used to load address,

data or control signals into the SRAM and cannot pre-

load the I/O buffers. The SRAM does not implement

the 1149.1 commands EXTEST or INTEST or the PRE-

LOAD portion of SAMPLE/PRELOAD; rather, it per-

forms a capture of the I/O ring when these instructions

are executed.

Instructions are loaded into the TAP controller dur-

ing the Shift-IR state when the instruction register is

placed between TDI and TDO. During this state,

instructions are shifted through the instruction regis-

ter through the TDI and TDO balls. To execute the

instruction once it is shifted in, the TAP controller

needs to be moved into the Update-IR state.

Bypass Register

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain

chips. The bypass register is a single-bit register that

can be placed between the TDI and TDO balls. This

allows data to be shifted through the SRAM with mini-

mal delay. The bypass register is set LOW (VSS) when

the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. The SRAM

has a 7±-bit-long register.

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in

the Capture-DR state and is then placed between the

TDI and TDO balls when the controller is moved to the

Shift-DR state. The EXTEST, SAMPLE/PRELOAD and

SAMPLE Z instructions can be used to capture the

contents of the I/O ring.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is

to be executed whenever the instruction register is

loaded with all 0s. EXTEST is not implemented in this

SRAM TAP controller, and therefore this device is not

compliant to1149.1. The TAP controller does recognize

an all-0 instruction.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

24

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

When an EXTEST instruction is loaded into the

instruction register, the SRAM responds as if a SAM-

PLE/PRELOAD instruction has been loaded. There is

one difference between the two instructions. Unlike

the SAMPLE/PRELOAD instruction, EXTEST places

the SRAM outputs in a High-Z state.

the clock frequencies, it is possible that during the

Capture-DR state, an input or output will undergo a

transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not

harm the device, but there is no guarantee as to the

value that will be captured. Repeatable results may not

be possible.

To guarantee that the boundary scan register will

capture the correct value of a signal, the SRAM signal

must be stabilized long enough to meet the TAP con-

troller’s capture setup plus hold time (^tCS plus ^tCH).

The SRAM clock input might not be captured cor-

rectly if there is no way in a design to stop (or slow) the

clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals

and simply ignore the value of the CLK captured in the

boundary scan register.

Once the data is captured, it is possible to shift out

the data by putting the TAP into the Shift-DR state.

This places the boundary scan register between the

TDI and TDO balls.

Note that since the PRELOAD part of the command

is not implemented, putting the TAP to the Update-DR

state while performing a SAMPLE/PRELOAD instruc-

tion will have the same effect as the Pause-DR com-

mand.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It

also places the instruction register between the TDI

and TDO balls and allows the IDCODE to be shifted

out of the device when the TAP controller enters the

Shift-DR state.

The IDCODE instruction is loaded into the instruc-

tion register upon power-up or whenever the TAP con-

troller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary

scan register to be connected between the TDI and

TDO balls when the TAP controller is in a Shift-DR

state. It also places all SRAM outputs into a High-Z

state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not

implemented, so the device TAP controller is not fully

1149.1-compliant.

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in

the Capture-DR state, a snapshot of data on the inputs

and bidirectional balls is captured in the boundary

scan register.

The user must be aware that the TAP controller

clock can only operate at a frequency up to 10 MHz,

while the SRAM clock operates more than an order of

magnitude faster. Because there is a large difference in

BYPASS

When the BYPASS instruction is loaded in the

instruction register and the TAP is placed in a Shift-DR

state, the bypass register is placed between the TDI

and TDO balls. The advantage of the BYPASS instruc-

tion is that it shortens the boundary scan path when

multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are

reserved for future use. Do not use these instructions.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

25

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 17:

TAP Timing

1

2

3

4

5

6

Test Clock

(TCK)

t

THTH

THTL

TLTH

t

MVTH

DVTH

THMX

Test Mode Select

(TMS)

t

THDX

Test Data-In

(TDI)

t

TLOV

t

TLOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

Table 19: TAP AC Electrical Characteristics

Notes 1, 2; 0ºC ? T_A? +70ºC; VDD = 3.3V 0.165V or 2.5V 0.125V

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock

^tTHTH

^fTF

^tTHTL

^tTLTH

100

ns

MHz

ns

Clock cycle time

10

Clock frequency

Clock HIGH time

Clock LOW time

40

ns

Output Times

^tTLOX

^tTLOV

^tDVTH

^tTHDX

0

ns

TCK LOW to TDO unknown

TCK LOW to TDO valid

TDI valid to TCK HIGH

TCK HIGH to TDI invalid

20

10

Setup Times

^tMVTH

^tCS

TMS setup

10

ns

Capture setup

Hold Times

^tTHMX

^tCH

10

ns

TMS hold

Capture hold

NOTE:

t

1. CS and ^tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the load in Figures 18 and 19.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

26

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

3.3V TAP AC Test Conditions

2.5V TAP AC Test Conditions

Input pulse levels ........................................... VSS to 3.0V

Input rise and fall times ..............................................1ns

Input timing reference levels.................................... 1.±V

Output reference levels............................................. 1.±V

Test load termination supply voltage ...................... 1.±V

Input pulse levels............................................ VSS to 2.±V

Input rise and fall times ............................................. 1ns

Input timing reference levels.................................. 1.2±V

Output reference levels........................................... 1.2±V

Test load termination supply voltage .................... 1.2±V

Figure 18:

3.3V TAP AC Output Load Equivalent

Figure 19:

2.5V TAP AC Output Load Equivalent

1.25V

1.5V

50Ω

TDO

Z_O= 50Ω

20pF

Table 20: 3.3V VDD, TAP DC Electrical Characteristics and Operating Conditions

0ºC ? T_A? +70ºC; VDD = 3.3V 0.165V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS NOTES

VIH

VIL

ILI

2.0

-0.3

-10

VDD + 0.3

V

1, 2

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

0.8

10

0V ? VIN ? VDD

µA

Output(s) disabled,

ILO

Output Leakage Current

0V ? VIN ? VDD (TDO)

IOLC = 100µA

IOLT = 2mA

VOL1

VOL2

VOH1

VOH2

0.7

0.8

V

1, 2

Output Low Voltage

Output High Voltage

IOHC = -100µA

IOHT = -2mA

2.9

2.0

Table 21: 2.5V VDD, TAP DC Electrical Characteristics and Operating Conditions

0ºC ? T_A? +70ºC; VDD = 2.5V 0.125V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS NOTES

VIH

VIL

ILI

1.7

-0.3

-10

VDD + 0.3

V

1, 2

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

0.7

10

0V ? VIN ? VDD

µA

Output(s) disabled,

ILO

Output Leakage Current

0V ? VIN ? VDD (TDO)

IOLC = 100µA

IOLT = 2mA

VOL1

VOL2

VOH1

VOH2

0.2

0.7

V

1, 2

Output Low Voltage

Output High Voltage

IOHC = -100µA

IOHT = -2mA

2.1

1.7

NOTE:

1. All voltages referenced to VSS (GND).

2. TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and

Operation Conditions tables.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

27

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 22: Identification Register Definitions

BIT

INSTRUCTION FIELD

CONFIGURATION DESCRIPTION

0000

Revision Number

(31:28)

Reserved for version number.

Device Depth

(27:23)

00111

00110

Defines depth of 1Mb.

Defines depth of 512K.

00011

00100

Device Width

(22:18)

Defines width of x18 bits.

Defines width of x32 or x36 bits.

xxxxxx

00000101100

1

Micron Device ID

(17:12)

Reserved for future use.

Micron JEDEC ID Code

(11:1)

Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

ID Register Presence

Indicator (0)

Table 23: Scan Register Sizes

REGISTER NAME

BIT SIZE

Instruction

3

1

Bypass

ID

32

75

Boundary Scan: x18, x32, x36

Table 24: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

001

010

IDCODE

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1-compliant.

101

110

111

RESERVED

BYPASS

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

28

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 25: 165-Ball FBGA Boundary Scan Order (x18)

BIT#

SIGNAL NAME

BALL ID

1R

BIT#

SIGNAL NAME

BALL ID

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1

2

3

4

5

6

7

8

MODE (LB0#)

SA

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

CLK

NC

CE2#

BWa#

NC

BWb#

NC

CE2

CE#

SA

NC

6N

11P

8R

SA

ZZ

NC

DQa

DQPa

NC

SA

8P

9R

9P

10R

10P

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

11C

10F

10E

10D

10G

11A

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

NC

1F

1G

2D

2E

NC

DQb

DQPb

NC

SA

SA1

SA0

2F

2G

1J

1K

1L

1M

1N

2K

2L

2M

2J

3P

3R

4P

ADV#

ADSP#

ADSC#

OE# (G#)

BWE#

GW#

9B

8A

4R

6P

8B

7A

6R

7B

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

29

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 26: 165-Ball FBGA Boundary Scan Order (x32)

BIT#

SIGNAL NAME

BALL ID

1R

BIT#

SIGNAL NAME

BALL ID

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1

2

3

4

5

6

7

8

MODE (LB0#)

SA

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

CLK

NC

6N

11P

8R

SA

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

CE#

SA

8P

9R

9P

10R

10P

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

10G

10F

10E

10D

11C

11A

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

ZZ

NF

SA

NC

NF

DQa

DQb

NF

DQc

DQd

NF

1F

1G

2D

2E

2F

2G

1J

1K

1L

1M

2J

2K

2L

2M

1N

3P

NC

SA

SA1

SA0

3R

4P

ADV#

ADSP#

ADSC#

OE# (G#)

BWE#

GW#

9B

8A

4R

6P

8B

7A

6R

7B

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

30

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 27: 165-Ball FBGA Boundary Scan Order (x36)

BIT#

SIGNAL NAME

BALL ID

1R

BIT#

SIGNAL NAME

BALL ID

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1

2

3

4

5

6

7

8

MODE (LB0#)

SA

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

CLK

NC

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

CE#

SA

NC

DQPc

DQc

DQd

DQPd

SA

6N

11P

8R

SA

8P

9R

9P

10R

10P

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

11C

10F

10E

10D

10G

11A

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

ZZ

DQPa

DQa

DQb

DQPb

NC

1F

1G

2D

2E

2F

2G

1J

1K

1L

1M

1N

2K

2L

2M

2J

SA

3P

3R

4P

ADV#

ADSP#

ADSC#

OE# (G#)

BWE#

GW#

SA

SA1

SA0

9B

8A

4R

6P

8B

7A

6R

7B

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

31

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 20:

100-Pin Plastic TQFP (JEDEC LQFP)

+0.10

-0.20

22.10

20.10 0.10

0.65 TYP

0.32

+0.06

-0.10

0.625

SEE DETAIL A

14.00 0.10

16.00 0.20

PIN #1 ID

+0.03

-0.02

0.15

1.40 0.05

GAGE PLANE

0.60 0.15

1.60 MAX

+0.10

-0.05

0.10

1.00 TYP

0.25

DETAIL A

NOTE:

1. All dimensions in inches (millimeters) ------------- or typical where noted.

MAX

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Figure 21:

165-Ball FBGA

0.85 0.075

0.12

C

SEATING PLANE

C

BALL A11

165X Ø 0.45

10.00

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION. THE

PRE-REFLOW DIAMETER IS Ø 0.40

BALL A1

PIN A1 ID

1.20 MAX

1.00

TYP

PIN A1 ID

7.50 0.05

14.00

15.00 0.10

7.00 0.05

1.00

TYP

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 0.05

5.00 0.05

SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø .33mm

13.00 0.10

NOTE:

MAX

1. All dimensions in inches (millimeters) ------------- or typical where noted.

MIN

Data Sheet Designation

No Marking: This data sheet contains minimum and maximum limits specified over the complete power

supply and temperature range for production devices. Although considered final, these specifications are sub-

ject to change, as further product development and data characterization sometimes occur.

®

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, the Micron logo, and SyncBurst are trademarks and/or service marks of Micron Technology, Inc.

Pentium is a registered trademark of Intel Corporation.

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

33

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED, SCD SYNCBURST SRAM

Document Revision History

•

Rev D; Pub. 2/03..........................................................................................................................................................2/03

Changed designation from Preliminary to Production

•

Rev C; Pub. 12/02 ......................................................................................................................................................12/02

Added T_Jspecifications to the AC Electrical Characteristics table

Corrected Boundary Scan errors

Updated TQFP and FBGA Thermal Resistance values

Corrected grammatical errors

•

Rev. B; Pub. 11/02......................................................................................................................................................11/02

Changed designation from ADVANCE to PRELIMINARY

Corrected grammatical errors

New ADVANCE data sheet for 0.16µm process; Rev. A, Pub. 6/02 ..........................................................................6/02

18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

34


型号：	MT58V512V36PT-10
厂家：	CYPRESS
描述：	Cache SRAM, 512KX36, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100 静态存储器
文件：	总34页 (文件大小：535K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT58V512V36PT-10 [CYPRESS]

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