PALCE16V8L-25 [CYPRESS]
Flash-Erasable Reprogrammable CMOS PAL Device; 闪存擦除可再编程的CMOS PAL器件
| 型号： | PALCE16V8L-25 |
| 厂家： | 
CYPRESS |
| 描述： | Flash-Erasable Reprogrammable CMOS PAL Device |
| 文件： | 总13页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PALCE16V8
Flash-Erasable Reprogrammable
CMOS PAL® Device
• Up to 16 input terms and eight outputs
Features
• 7.5 ns com’l version
5 ns tCO
5 ns tS
• Active pull-up on data input pins
• Low power version (16V8L)
7.5 ns tPD
125-MHz state machine
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 65 mA military (15 and 25 ns)
• 10 ns military/industrial versions
7 ns tCO
10 ns tS
10 ns tPD
62-MHz state machine
• Standard version has low power
— 90 mA max. commercial (10, 15, 25 ns)
— 115 mA max. commercial (7 ns)
— 130 mA max. military/industrial (10, 15, 25 ns)
• High reliability
— Proven Flash technology
— 100% programming and functional testing
• CMOS Flash technology for electrical erasability and
reprogrammability
Functional Description
• PCI-compliant
• User-programmable macrocell
— Output polarity control
The Cypress PALCE16V8 is a CMOS Flash Electrical
Erasable second-generation programmable array logic
device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
— Individually selectable for registered or combina-
torial operation
Logic Block Diagram (PDIP/CDIP)
GND
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
CLK/I
0
10
9
8
7
6
5
4
3
2
1
PROGRAMMABLE
AND ARRAY
(64 x 32)
8
8
8
8
8
8
8
8
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
11
12
I/O
13
I/O
14
I/O
15
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
OE/I
V
CC
9
0
1
2
3
4
5
6
7
PLCC/LCC
Top View
Pin Configurations
DIP
Top View
1
2
3
4
20
19
18
CLK/I
V
I/O
I/O
I/O
5
0
CC
I
1
7
3 2 1 2019
I
2
6
I
18
I/O
6
4
5
6
7
8
17
I
3
3
I
17
I/O
5
6
4
5
16 I/O
I
I
5
4
4
I
I/O
16
15
14
5
4
I/O
15 I/O
3
I
6
3
I/O
14
13
12
11
7
8
9
10
I/O
I
2
I
6
7
7
2
I/O
I
9 10111213
1
I
I/O
8
0
GND
OE/I
9
Cypress Semiconductor Corporation
Document #: 38-03025 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
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PALCE16V8
Selection Guide
tPD ns
tS ns
Com’l/Ind
tCO ns
Com’l/Ind
ICC mA
Generic Part Number
PALCE16V8-5
Com’l/Ind
Mil
Mil
Mil
Com’l
115
115
90
Mil/Ind
5
3
4
PALCE16V8-7
7.5
10
15
25
15
25
7
5
PALCE16V8-10
PALCE16V8-15
PALCE16V8-25
PALCE16V8L-15
PALCE16V8L-25
10
15
25
15
25
10
12
15
12
15
10
12
20
12
20
7
10
10
12
12
20
130
130
130
65
10
12
10
12
90
90
55
55
65
Shaded areas contain preliminary information.
macrocell, the input/output pin associated with an adjacent
pin, or from the macrocell register itself.
Functional Description
The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,
a 300-mil cerdip, a 20-lead square ceramic leadless chip
carrier, and a 20-lead square plastic leaded chip carrier.
Power-Up Reset
All registers in the PALCE16V8 power-up to a logic LOW for
predictable system initialization. For each register, the
associated output pin will be HIGH due to active-LOW outputs.
The device provides up to 16 inputs and 8 outputs. The
PALCE16V8 can be electrically erased and reprogrammed.
The programmable macrocell enables the device to function
as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.
Electronic Signature
An electronic signature word is provided in the PALCE16V8
that consists of 64 bits of programmable memory that can
contain user-defined data.
The PALCE16V8 features 8 product terms per output and 32
input terms into the AND array. The first product term in a
macrocell can be used either as an internal output enable
control or as a data product term.
Security Bit
A security bit is provided that defeats the readback of the
internal programmed pattern when the bit is programmed.
There are a total of 18 architecture bits in the PALCE16V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are
selectable from either the input/output pin associated with the
Low Power
The Cypress PALCE16V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each
product term. The PTD fuses allow each product term to be
individually disabled.
Configuration Table
CG0
CG1
CL0x
Cell Configuration
Devices Emulated
Registered Med PALs
0
0
1
1
1
1
1
0
0
1
0
1
0
1
1
Registered Output
Combinatorial I/O
Combinatorial Output
Input
Registered Med PALs
Small PALs
Small PALs
Combinatorial I/O
16L8 only
Document #: 38-03025 Rev. *A
Page 2 of 13
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PALCE16V8
Macrocell
To
Adjacent
Macrocell
1 1
1 0
0 0
OE
1 1
V
CC
0 X
1 0
0 1
CL0
x
CG
1
1 1
0 X
I/O
x
1 0
D
Q
Q
V
CC
CLK
CL1
1 0
1 1
0 X
x
From
Adjacent
Pin
CG for pin 13 to 18
1
CL0
x
CG for pin 12 and 19
0
Document #: 38-03025 Rev. *A
Page 3 of 13
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PALCE16V8
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 24 mA
DC Programming Voltage............................................. 12.5V
Latch-Up Current....................................................> 200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Range
Commercial
Military[1]
Ambient Temperature
0°C to +75°C
VCC
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
5V ±5%
5V ±10%
5V ±10%
–55°C to +125°C
–40°C to +85°C
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
Industrial
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
Min.
Max. Unit
VOH
Output HIGH Voltage
VCC = Min.,
IN = VIH or VIL
IOH = –3.2 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
2.4
V
V
I
OH = –2 mA
IOL = 24 mA
OL = 12 mA
VOL
Output LOW Voltage
VCC = Min.,
IN = VIH or VIL
0.5
V
V
I
VIH
Input HIGH Level
Input LOW Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Guaranteed Input Logical LOW Voltage for All Inputs[3]
2.0
V
V
[4]
VIL
–0.5
0.8
10
IIH
Input or I/O HIGH Leakage 3.5V < VIN < VCC
Current
µA
[5]
IIL
Input or I/O LOW Leakage
Current
0V < VIN < VIN (Max.)
–100 µA
ISC
ICC
Output Short Circuit Current VCC = Max., VOUT = 0.5V[6, 7]
–30
–150 mA
Operating Power Supply
Current
VCC = Max.,
VIL = 0V, VIH = 3V,
Output Open,
f = 15 MHz
5, 7 ns
Com’l
115
90
mA
mA
mA
mA
mA
mA
10, 15, 25 ns
15L, 25L ns
10, 15, 25 ns
15L, 25L ns
15L, 25L ns
55
(counter)
Mil/Ind
Mil.
130
65
Ind.
65
Capacitance[7]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.
Unit
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
5
5
pF
pF
COUT
Endurance Characteristics[7]
Parameter
Description
Minimum Reprogramming Cycles
Test Conditions
Min.
100
Max.
Unit
N
Normal Programming Conditions
Cycles
Notes:
1. T is the “instant on” case temperature.
A
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. V (Min.) is equal to –3.0V for pulse durations less than 20 ns.
IL
5. The leakage current is due to the internal pull-up resistor on all pins.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
caused by tester ground degradation.
= 0.5V has been chosen to avoid test problems
OUT
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03025 Rev. *A
Page 4 of 13
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PALCE16V8
AC Test Loads and Waveforms
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
GND
< 2 ns
< 2 ns
5V
S1
R1
OUTPUT
TEST POINT
R2
C
L
Commercial
Military
Specification
tPD, tCO
PZX, tEA
S1
CL
R1
200Ω
R2
R1
R2
Measured Output Value
Closed
50 pF
390Ω
390Ω
750Ω
1.5V
1.5V
t
Z · H: Open
Z · L: Closed
tPXZ, tER
H · Z: Open
L · Z: Closed
5 pF
H · Z: VOH – 0.5V
L · Z: VOL + 0.5V
Commercial and Industrial Switching Characteristics [2]
16V8-5
16V8-7
16V8-10
16V8-15
16V8-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
tPD
Input to Output
1
5
3
7.5
3
10
3
15
3
25
ns
Propagation Delay[8, 9]
OE to Output Enable
OE to Output Disable
tPZX
tPXZ
tEA
1
1
1
6
5
6
6
6
9
10
10
10
15
15
15
20
20
25
ns
ns
ns
Input to Output
Enable Delay[7]
tER
Input to Output
1
5
4
9
5
10
7
15
10
25
12
ns
Disable Delay[7, 10]
tCO
tS
Clock to Output Delay[8, 9]
1
3
2
5
2
2
2
ns
ns
Input or Feedback
Set-up Time
7.5
12
15
tH
tP
Input Hold Time
0
7
0
0
0
0
ns
ns
External Clock
Period (tCO + tS)
10
14.5
22
27
Shaded areas contain preliminary information.
Notes:
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in a given access cycle.
10. This parameter is measured as the time after OEpin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH
level has fallen to 0.5 volts below V min. or a previous LOW level has risen to 0.5 volts above V max.
OH
OL
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
internal (1/f
) as measured (see Note 7 above) minus t .
MAX
MAX3 S
Document #: 38-03025 Rev. *A
Page 5 of 13
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PALCE16V8
Commercial and Industrial Switching Characteristics (continued)[2]
16V8-5
16V8-7
16V8-10
16V8-15
16V8-25
Parameter
tWH
Description
Clock Width HIGH[7]
Clock Width LOW[7]
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
ns
3
3
4
4
6
6
8
8
12
12
37
tWL
ns
fMAX1
External Maximum
143
100
69
45.5
MHz
Frequency (1/(tCO + tS))[7, 11]
fMAX2
fMAX3
Data Path Maximum
166
166
125
125
83
74
62.5
50
41.6
40
MHz
MHz
Frequency (1/(tWH + tWL))[7, 12]
Internal Feedback
Maximum Frequency
(1/(tCF + tS))[7, 13]
tCF
tPR
Register Clock to
3
3
6
8
10
ns
Feedback Input[7, 14]
Power-Up Reset Time[7]
1
1
1
1
1
µs
Military Switching Characteristics[7]
16V8-10
16V8-15
16V8-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
3
10
3
15
3
25
ns
Propagation Delay[8, 9]
OE to Output Enable
OE to Output Disable
tPZX
tPXZ
tEA
tER
tCO
tS
10
10
10
10
7
15
15
15
15
10
20
20
25
25
12
ns
ns
Input to Output Enable Delay[7]
Input to Output Disable Delay[7, 10]
Clock to Output Delay[8, 9]
Input or Feedback Set-up Time
Input Hold Time
ns
ns
2
10
.5
17
6
2
12
.5
2
ns
15
.5
ns
tH
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[7]
Clock Width LOW[7]
22
8
27
12
12
37
ns
tWH
tWL
ns
6
8
ns
fMAX1
fMAX2
fMAX3
tCF
External Maximum Frequency
(1/(tCO + tS)[7, 11]
58
45.5
MHz
Data Path Maximum Frequency
(1/(tWH + tWL))[7, 12]
83
62.5
50
41.6
40
MHz
MHz
ns
Internal Feedback Maximum
Frequency (1/(tCF + tS))[7, 13]
62.5
Register Clock to
6
8
10
Feedback Input[7, 14]
tPR
Power-Up Reset Time[7]
1
1
1
µs
Document #: 38-03025 Rev. *A
Page 6 of 13
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PALCE16V8
Switching Waveform
INPUTS, I/O,
REGISTERED
FEEDBACK
tWH
tWL
tS
tH
CP
tCO
tP
]
[10
[10]
[10]
t
t
, t
t
t
, t
PXZ ER
EA PZX
REGISTERED
OUTPUTS
[10]
tPD
, t
, t
PXZ ER
EA PZX
COMBINATORIAL
OUTPUTS
Power-Up Reset Waveform
VCC
90%
10%
POWER
SUPPLY VOLTAGE
tPR
REGISTERED
ACTIVE LOW
OUTPUTS
tS
CLOCK
tWL
t
MAX= 1 µs
PR
Document #: 38-03025 Rev. *A
Page 7 of 13
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PALCE16V8
Functional Logic Diagram for PALCE16V8
PIN NUMBERS
PIN NUMBERS
INPUT LINE
NUMBERS
V
CC
PRODUCTLINE FIRSTCELL NUMBERS
1
20
19
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28
31
00
64
MC7
CL1=2048
CL0=2120
PTD=2128
-2135
32
96
128
160
224
192
2
3
4
5
6
7
8
256
320
384
MC6
CL1=2049
CL0=2121
PTD=2136
-2143
288
352
18
17
16
15
14
13
416
480
448
512
576
640
MC5
CL1=2050
CL0=2122
PTD=2144
-2151
544
608
672
736
704
768
832
896
MC4
CL1=2051
CL0=2123
PTD=2152
-2159
800
864
928
992
960
1024
1088
MC3
CL1=2052
CL0=2124
PTD=2160
-2167
1056
1120
1152
1216
1184
1248
1280
1344
1408
1472
MC2
CL1=2053
CL0=2125
PTD=2168
-2175
1312
1376
1440
1504
1536
1600
1664
1728
MC1
CL1=2054
CL0=2126
PTD=2176
-2183
1568
1632
1696
1760
1792
1856
1920
1984
MC0
CL1=2055
CL0=2127
PTD=2184
-2191
1824
1888
12
11
1952
2016
9
10
0
3
2056
4
7
8
11 12 15 16 19 20 23 24 27 28
31
2104
BYTE6
USER ELECTRONIC SIGNATURE ROW
2064
2072
BYTE2
2080
BYTE3
2088
BYTE4
2096
BYTE5
2112 2119
GLOBALARCH BITS
BYTE0
BYTE1
BYTE7
CG =2192
0
CG =2193
1
MSB LSB
MSB LSB
Document #: 38-03025 Rev. *A
Page 8 of 13
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PALCE16V8
Ordering Information
ICC
tPD
tS
tCO
Package
Operating
Range
(mA) (ns)
(ns)
(ns)
Ordering Code
Name
J61
J61
P5
Package Type
115
115
5
3
5
4
5
PALCE16V8-5JC
PALCE16V8-7JC
PALCE16V8-7PC
PALCE16V8-10JC
PALCE16V8-10PC
PALCE16V8-10JI
PALCE16V8-10PI
PALCE16V8-10DMB
PALCE16V8-10LMB
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead (300-Mil) CerDIP
Commercial
Commercial
7.5
90
130
130
90
10
10
10
15
15
7.5
7.5
10
7
7
7
J61
P5
J61
P5
Industrial
Military
D6
L61
J61
P5
20-Pin Square Leadless Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead(300Mil) Molded DIP
12
10 PALCE16V8-15JC
PALCE16V8-15PC
Commercial
130
12
10 PALCE16V8-15PI
PALCE16V8-15DMB
PALCE16V8-15LMB
12 PALCE16V8-25JC
PALCE16V8-25PC
P5
Industrial
Military
D6
20-Lead (300-Mil) CerDIP
L61
J61
P5
20-Pin Square Leadless Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) CerDIP
90
25
25
15
15
Commercial
130
12 PALCE16V8-25JI
PALCE16V8-25DMB
PALCE16V8-25LMB
J61
D6
Industrial
Military
L61
J61
P5
20-Pin Square Leadless Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead (300-Mil) CerDIP
55
65
55
65
55
65
10
10
15
15
25
25
7.5
10
12
12
15
15
7
PALCE16V8L-10JC
PALCE16V8L-10PC
PALCE16V8L-10JI
PALCE16V8L-10PI
Commercial
Industrial
Commercial
Military
7
J61
P5
10 PALCE16V8L-15JC
PALCE16V8L-15PC
J61
P5
10 PALCE16V8L-15DMB
PALCE16V8L-15LMB
12 PALCE16V8L-25JC
PALCE16V8L-25PC
D6
L61
J61
P5
20-Pin Square Leadless Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead (300-Mil) Molded DIP
20-Lead (300-Mil) CerDIP
Commercial
Military
12 PALCE16V8L-25DMB
PALCE16V8L-25LMB
D6
L61
20-Pin Square Leadless Chip Carrier
Shaded areas contain preliminary information.
Document #: 38-03025 Rev. *A
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PALCE16V8
Switching Characteristics
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
tPD
tCO
tS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
Parameter
Subgroups
VOH
VOL
VIH
VIL
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tH
IIX
IOZ
ICC
Package Diagrams
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835 D-8 Config. A
51-80029-**
Document #: 38-03025 Rev. *A
Page 10 of 13
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PALCE16V8
Package Diagrams (continued)
20-Lead Plastic Leaded Chip Carrier J61
51-85000-*A
20-Square Leadless Chip Carrier L61
51-80049-**
Document #: 38-03025 Rev. *A
Page 11 of 13
USE ULTRA37000™ FOR
ALL NEW DESIGNS
PALCE16V8
Package Diagrams (continued)
20-Lead (300-Mil) Molded DIP P5
51-85011-*A
Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices,
Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-03025 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
PALCE16V8
Document History Page
Document Title: PALCE16V8 Flash Erasable Reprogrammable CMOS PAL® Device
Document Number: 38-03025
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106370
213375
07/11/01
See ECN
SZV
FSG
Change from Spec Number: 38-00364 to 38-03025
*A
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03025 Rev. *A
Page 13 of 13
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