PLDC20RA10-15PC [CYPRESS]
Reprogrammable Asynchronous CMOS Logic Device; 可重新编程的异步CMOS逻辑器件
| 型号： | PLDC20RA10-15PC |
| 厂家： | 
CYPRESS |
| 描述： | Reprogrammable Asynchronous CMOS Logic Device |
| 文件： | 总14页 (文件大小：582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLDC20RA10
Reprogrammable Asynchronous
CMOS Logic Device
1PLDC20RA10
—ICC max = 85 mA (Military)
• High reliability
Features
—Proven EPROM technology
—>2001V input protection
• Advanced-user programmable macrocell
• CMOS EPROM technology for reprogrammability
• Up to 20 input terms
• 10 programmable I/O macrocells
• Output macrocell programmable as combinatorial or
asynchronous D-type registered output
• Product-termcontrolofregisterclock,resetandsetand
output enable
• Register preload and power-up reset
• Four data product terms per output macrocell
• Fast
—100% programming and functional testing
• Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PLDC20RA10 is a high-performance, sec-
ond-generation programmable logic device employing a flexi-
ble macrocell structure that allows any individual output to be
configured independently as a combinatorial output or as a
fully asynchronous D-type registered output.
— Commercial
The Cypress PLDC20RA10 provides lower-power operation
with superior speed performance than functionally equivalent
bipolar devices through the use of high-performance 0.8-mi-
cron CMOS manufacturing technology.
t
PD = 15 ns
tCO = 15 ns
tSU = 7 ns
— Military
The PLDC20RA10 is packaged in a 24 pin 300-mil molded
DIP, a 300-mil windowed cerDIP, and a 28-lead square lead-
less chip carrier, providing up to 20 inputs and 10 outputs.
When the windowed device is exposed to UV light, the 20RA10
is erased and can then be reprogrammed.
tPD = 20 ns
tCO = 20 ns
tSU = 10 ns
• Low power
— ICC max - 80 mA (Commercial)
Logic Block Diagram
V
I
I
I
I
I
I
I
I
I
I
PL
1
SS
9
8
7
6
5
4
3
2
1
0
12
10
11
9
8
7
6
5
4
3
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
17
I/O
13
14
I/O
15
I/O
16
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
OE
V
CC
9
8
7
6
5
4
3
2
1
0
RA10–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03012 Rev. **
Revised March 26, 1997
PLDC20RA10
Selection Guide
tPD ns
tSU ns
tCO ns
tCC ns
Generic Part
Number
20RA10-15
20RA10-20
20RA10-25
20RA10-35
Com‘l
Mil
Com’l
7
Mil
Com’l
15
Mil
Com’l
Mil
15
20
80
80
20
25
35
10
10
15
20
20
20
25
35
85
85
85
Pin Configurations
JEDEC PLCC/HLCC[1]
Top View
LCC
Top View
STD PLCC/HLCC
Top View
4
3 2 1 282726
4
3
2
1
2827 26
25
4
3
2
1
2827 26
25
I
I
I
I
I
I
5
6
7
8
9
10
11
25
24
23
NC
I/O
I/O
I/O
2
3
4
5
5
6
7
8
9
10
11
NC
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
5
6
7
8
9
10
11
I/O
I/O
I/O
NC
I/O
I/O
I/O
I
I
I
2
2
3
4
2
3
4
I
I
24
23
22
21
20
19
3
4
24
23
22
21
20
19
3
4
5
PLDC20RA10 22
PLDC20RA10
NC
21 I/O
20 I/O
19
PLDC20RA10
CG7C324
6
7
NC
I
I
I
I
5
6
5
5
6
7
6
NC
I/O
7
6
NC
12131415161718
NC
I
121314 1516 1718
7
121314 1516 1718
RA10–2
RA10–3
RA10–4
product terms and four uncommitted product terms of each
programmable I/O macrocell that has been configured as an
output.
Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell.
The cell dedicates three product terms for fully asynchronous
control of the register set, reset, and clock functions, as well
as, one term for control of the output enable function.
An I/O cell is programmed as an input by tying the output en-
able pin (pin 13) HIGH or by programming the output enable
product term to provide a LOW, thereby disabling the output
buffer, for all possible input combinations.
The output enable product term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources. If product-term-only control is selected, it is automat-
ically chosen for all outputs since, for this case, the external
output enable pin must be tied LOW. The active polarity of
each output may be programmed independently for each out-
put cell and is subsequently fixed. Figure 2 illustrates the out-
put enable options available.
When utilizing the I/O macrocell as an output, the input path
functions as a feedback path allowing the output signal to be
fed back as an input to the product term array. When the output
cell is configured as a registered output, this feedback path
may be used to feed back the current output state to the device
inputs to provide current state control of the next output state
as required for state machine implementation.
Preload and Power-Up Reset
When an I/O cell is configured as an output, combinatorial-only
capability may be selected by forcing the set and reset product
term outputs to be HIGH under all input conditions. This is
achieved by programming all input term programming cells for
these two product terms. Figure 3 illustrates the available out-
put configuration options.
Functional testability of programmed devices is enhanced by
inclusion of register preload capability, which allows the state
of each register to be set by loading each register from an
external source prior to exercising the device. Testing of com-
plex state machine designs is simplified by the ability to load
an arbitrary state without cycling through long test vector se-
quences to reach the desired state. Recovery from illegal
states can be verified by loading illegal states and observing
recovery. Preload of a particular register is accomplished by
impressing the desired state on the register output pin and
lowering the signal level on the preload control pin (pin1) to a
logic LOW level. If the specified preload set-up, hold and pulse
width minimums have been observed, the desired state is
loaded into the register. To insure predictable system initializa-
tion, all registers are preset to a logic LOW state upon pow-
er-up, thereby setting the active LOW outputs to a logic HIGH.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-de-
fined logic functions.
Programmable I/O
Because any of the ten I/O pins may be selected as an input,
the device input configuration programmed by the user may
vary from a total of nine programmable plus ten dedicated in-
puts (a total of nineteen inputs) and one output down to a
ten-input, ten-output configuration with all ten programmable
I/O cells configured as outputs. Each input pin available in a
given configuration is available as an input to the four control
Note:
1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
principal difference is in the location of the “no connect” (NC) pins
Document #: 38-03012 Rev. **
Page 2 of 14
PLDC20RA10
.
OUTPUT ENABLE
(FROM PIN 13)
PRELOAD
(FROM PIN 1)
S
TO I/O PIN
1
S
R
O
D
Q
P
O
C0
PL
RA10–5
Figure 1. PLDC20RA10 Macrocell
Output Always Enabled
Programmable
RA10–7
RA10–6
Combination of
Programmable and Hardwired
External Pin
OE
RA10–8
RA10–9
Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10
Document #: 38-03012 Rev. **
Page 3 of 14
PLDC20RA10
Registered/ActiveLOW
Combinatorial/Active LOW
S
Q
D
R
RA10–10
RA10–11
Combinatorial/Active HIGH
Registered/ActiveHIGH
S
Q
D
R
RA10–13
RA10–12
Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10
Document #: 38-03012 Rev. **
Page 4 of 14
PLDC20RA10
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
DC Program Voltage .................................................... 13.0V
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
Range
Commercial
Military[2]
Temperature
VCC
0°C to +75°C
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
–55°C to +125°C
DC Input Voltage......................................... –3.0 V to + 7.0 V
]
Output Current into Outputs (LOW) .............................16 mA
Electrical Characteristics Over the Operating Range[3]
Parameter
Description
Test Conditions
IOH = –3.2 mA
IOH = –2 mA
IOL = 8 mA
Min. Max. Unit
VOH
Output HIGH Voltage
VCC = Min.,
VIN =VIH or VIL
Com’l
2.4
V
Mil
VOL
Output LOW Voltage
VCC = Min.,
0.5
V
VIN = VIH or VIL
VIH
VIL
IIX
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[4]
Guaranteed Input Logical LOW Voltage for All Inputs[4]
2.0
V
Input LOW Level
0.8
+10
+40
–90
75
V
Input Leakage Current
Output Leakage Current
Output Short Circuit Current[5]
VSS ≤ VIN ≤ VCC, VCC = Max
–10
–40
–30
µA
µA
mA
mA
mA
mA
mA
IOZ
ISC
ICC1
VCC = Max., VSS ≤ VOUT ≤ VCC
VCC = Max., VOUT = 0.5V[6]
Standby Power Supply Current VCC= Max., VIN = GND Outputs Open
Com’l
Mil
80
ICC2
Power Supply Current at
Frequency[5]
VCC = Max., Outputs Disabled (In High Z
State) Device Operating at fMAX
Com’l
Mil
80
85
Capacitance[5]
Parameter
Description
Test Conditions
VIN = 2.0 V @ f = 1 MHz
VOUT = 2.0 V @ f = 1 MHz
Max.
Unit
CIN
Input Capacitance
Output Capacitance
10
10
pF
pF
COUT
Notes:
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
5. Tested initially and after any design or process changes that may affect these parameters.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5 V has been chosen to
avoid test problems caused by tester ground degradation.
Document #: 38-03012 Rev. **
Page 5 of 14
PLDC20RA10
AC Test Loads and Waveforms (Commercial)
R1 457Ω
(470Ω MIL)
R1 457Ω
(470Ω MIL)
ALL INPUT PULSES
90%
10%
3.0V
GND
90%
10%
5V
5V
OUTPUT
OUTPUT
R2
270Ω
(319Ω Mil)
R2
270Ω
(319Ω Mil)
50 pF
5 pF
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
RA10–15
RA10–17
RA10–14
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT(Commercial)
170Ω
Equivalent to:
THÉVENIN EQUIVALENT(Military)
190Ω
1.86V=V
thc
OUTPUT
2.02V=V
OUTPUT
thc
RA10–16
Parameter Vth
Output Waveform Measurement Level
tPXZ(–)
1.5V
2.6V
VOH
VX
0.5V
0.5V
RA10–18
VX
tPXZ(+)
VOL
RA10–19
RA10–20
0.5V
VOH
tPZX(+)
tPZX(–)
tER(–)
tER(+)
tEA(+)
tEA(–)
Vthc
Vthc
1.5V
2.6V
Vthc
Vthc
VX
VX
VOL
0.5V
RA10–21
RA10–22
VOH
VX
VX
0.5V
0.5V
VOL
RA10–23
RA10–24
RA10–25
0.5V
VOH
VX
VX
(c)
VOL
0.5V
Document #: 38-03012 Rev. **
Page 6 of 14
PLDC20RA10
Switching Characteristics Over the Operating Range[3, 7, 8]
Commercial
Military
–15
–20
–20
–25
–35
Parameter
tPD
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Input or Feedback to
Non-Registered Output
15
20
20
25
35
ns
tEA
tER
Input to Output Enable
15
15
20
20
20
20
30
30
35
35
ns
ns
Input to Output
Disable
tPZX
tPXZ
Pin 13 to Output
Enable
12
12
15
15
15
20
15
15
20
20
20
25
25
25
35
ns
ns
Pin 13 to Output
Disable
tCO
tSU
Clock to Output
ns
ns
Input or Feedback
Set-Up Time
7
10
10
15
20
tH
tP
Hold Time
3
5
3
5
5
ns
ns
Clock Period
(tSU + tCO)
22
30
30
40
55
tWH
tWL
Clock Width HIGH[5]
Clock Width LOW[5]
10
10
13
13
12
12
18
18
25
25
ns
ns
fMAX
Maximum Frequency
(1/tP)[5]
45.5
33.3
33.3
25.0
18.1
MHz
tS
tR
Input of Asynchronous
Set to Registered Output
15
15
20
20
20
20
25
25
40
40
ns
ns
Input of Asynchronous
Reset to Registered
Output
tARW
Asynchronous Reset
Width[5]
15
20
20
25
25
ns
tASW
tAR
Asynchronous S-Width[5]
15
10
20
12
20
12
25
15
25
20
ns
ns
Asynchronous Set/
Reset Recovery Time
tWP
Preload Pulse Width
Preload Set-Up Time
Preload Hold Time
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
ns
ns
ns
tSUP
tHP
Notes:
7. Part (a) of AC Test Loads was used for all parameters except tEA, tER, tPZX and tPXZ, which use part (b).
8. The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled HIGH output or VOL
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
Document #: 38-03012 Rev. **
Page 7 of 14
PLDC20RA10
Switching Waveform
t
H
INPUTS,REGISTERED
FEEDBACK
t
SU
t
P
CP
t
t
WL
WH
ASYNCHRONOUS
RESET
t
AR
ASYNCHRONOUS
SET
t
PD
t
OUTPUTS
(HIGHASSERTED)
CO
t
t
EA
ER
OUTPUT ENABLE
INPUTPIN
RA10–26
Preload Switching Waveform
PIN 13
OUTPUT
ENABLE
t
ER
t
EA
REGISTER
OUTPUTS
t
t
HP
SUP
PIN 1
PRELOAD
CLOCK
t
WP
RA10–27
Asynchronous Reset
ASYNCHRONOUS
RESET
t
ARW
t
R
OUTPUT
RA10–28
Asynchronous Set
ASYNCHRONOUS
SET
t
ASW
t
S
OUTPUT
RA10–29
Document #: 38-03012 Rev. **
Page 8 of 14
PLDC20RA10
Functional Logic Diagram
Document #: 38-03012 Rev. **
Page 9 of 14
PLDC20RA10
Ordering Information
tPD
tSU
tCO
Package
Name
Operating
Range
ICC2
(ns)
(ns)
(ns)
Ordering Code
PLDC20RA10-15JC
PLDC20RA10-15PC
CG7C324-A15JC
Package Type
80
15
7
15
J64
P13
J64
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
Commercial
20
20
25
35
10
10
15
20
20
20
25
35
PLDC20RA10-20PC
CG7C324-A20JC
P13
J64
85
PLDC20RA10-20DMB
PLDC20RA10-20WMB
PLDC20RA10-25DMB
PLDC20RA10-25WMB
PLDC20RA10-35DMB
PLDC20RA10-35WMB
D14
W14
D14
W14
D14
W14
Military
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
24-Lead (300-Mil) Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
1, 2, 3
ICC
DC Characteristics
Parameter
VOH
Subgroups
1, 2, 3
Switching Characteristics
Parameter
Subgroups
9, 10, 11
VOL
VIH
VIL
IIX
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tPD
tPZX
tCO
tSU
tH
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
IOZ
Document #: 38-03012 Rev. **
Page 10 of 14
PLDC20RA10
Package Diagrams
24-Lead (300-Mil) CerDIP D14
28-Lead Plastic Leaded Chip Carrier J64
MIL-STD-1835 D- 9Config.A
28-Square L64 Carrier Chip Leadless
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
MIL-STD-1835 C-4
Document #: 38-03012 Rev. **
Page 11 of 14
PLDC20RA10
Package Diagrams (continued)
28-Pin Windowed Leaded Chip Carrier H64
Document #: 38-03012 Rev. **
Page 12 of 14
PLDC20RA10
Package Diagrams (continued)
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D- 9 Config.A
Document #: 38-03012 Rev. **
Page 13 of 14
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PLDC20RA10
Document Title: PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device
Document Number: 38-03012
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
Change from Spec number: 38-00073 to 38-03012
**
106294
04/24/01
SZV
Document #: 38-03012 Rev. **
Page 14 of 14
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