S29AL004D55BANR10 [CYPRESS]
Flash, 256KX16, 55ns, PBGA48, FBGA-48;
| 型号： | S29AL004D55BANR10 |
| 厂家： | 
CYPRESS |
| 描述： | Flash, 256KX16, 55ns, PBGA48, FBGA-48 |
| 文件： | 总47页 (文件大小：1110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS SPEC IS OBSOLETE
Spec No: 002-01235
Spec Title: S29AL004D, 4-MBIT (512K X 8-BIT/256K X 16-
BIT), 3 V BOOT SECTOR FLASH
Replaced by: NONE
S29AL004D
4-Mbit (512K x 8-Bit/256K x 16-Bit), 3 V
Boot Sector Flash
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Distinctive Characteristics
Architectural A
Performance Characteristics
Single Power
– 2.7 to 3.6 ations for battery-powered
applica
High Performance
– Access times as fast as 55 ns
– Extended temperature range (-40°C to +125°C)
Ultra-low Power Consumption (typical values at 5 MHz)
– 200 nA Automatic Sleep mode current
– 200 nA standby mode current
Manufass Tec
– Compm29L29LV400T/BC
Flexible ure
– One 16 Kwo 8 Kbyteseven 64 Kbyte
sectors (byte mode)
– 9 mA read current
– 20 mA program/erase current
– One 8 Kword, two 4 ord, and sen 32 K
sectors (word mod
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
– Supports full chip eras
Unlock Bypass Program Cond
Package Options
all FBGA
n TSOP
n SO
– Reduces overall programming time wn issuing ple program
command sequences
Top or Bottom Boot Block ConfiguratAvailable
Embedded Algorithms
– Embedded Erase algorithm automatically preprogra
erases the entire chip or any combination of design
– Embedded Program algorithm automatically write
data at specified addresses
tware eatures
Dataolling and Toggle Bits
– vides a software method of detecting program or erase
operation completion
Compatibility with JEDEC Standards
Erase Suspend/Erae
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
– Suspends an ee operto read data from, or program data
to, a sector t is not being ed, then resumes the erase
operation
Sector Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
ardwe Featu
Ry/Busy# Pin (RY/BY#)
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
– Pes a hardware method of tecting pgram or erase cycle
comn
Hardwarset Pin (RESE)
– Hardware method to rt the device to rding arra
Cypress Semiconductor Corporation
Document Number: 002-01235 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 25, 2017
S29AL004D
General Description
The S29AL004D is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-
ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A
standard EPROM programmer can also be used to program and erase the device.
This device is manufaSpansion’s 200 nm process technology, and offers all the features and benefits of the
Am29LV400B and BC, which were manufactured using 320 nm process technology.
The standard times of 70 and 90 ns, allowing high speed microprocessors to operate without wait states. To
eliminate bue has sarate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The devicle 3.0 er supply for both read and write functions. Internally generated and regulated
voltages aprogroperations.
The device mmanwith the JEDEC single-power-supply Flash standard. Commands are written to
the command register using ocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase ancircuitry. es also internally latch addresses and data needed for the programming
and erase operations. of the dice is sir to reading from other Flash or EPROM devices.
Device programming octing the ram coand sequence. This initiates the Embedded Program algorithm—an
internal algorithm that autoly times the pam pue widths and verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times bequiring y two write cprogram data instead of four.
Device erasure occurs by executing erase comand stiates the Embedded Erase algorithm—an internal
algorithm that automatically preprogs the ar(if it ammed) before executing the erase operation. During
erase, the device automatically times tpulse roper cell margin.
The host system can detect whether a program or mplete observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. Aftee cyclcompleted, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory secterased d reprogrammed wt affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detecthat automatically hibits write ations during power
transitions. The hardware sector protection feature disables program and operations in ancombination of the sectors
of memory. This can be achieved in-system or via programming ment.
The Erase Suspend feature enables the user to put erase on hold for any eriod of time read data frorogram data to, any
sector that is not selected for erasure. True background erase can thus chieved.
The hardware RESET# pin terminates any operation in progress and resetinternal state macne to reading y data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thlso reset the vice, enabling e m
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified ount of time, evice enters he
automatic sleep mode. The system can also place the device into the standby mode. Power consumon reatly reduced in
both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to proe the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultasly via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
Document Number: 002-01235 Rev. *B
Page 2 of 46
S29AL004D
Contents
1.
2.
3.
Product Selector Guide............................................... 4
30.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15
x 6.15 mm .....................................................................40
30.3 SO 044—44-Pin Small Outline Package ...................... 41
Block Diagram.............................................................. 4
Connection Diagrams.................................................. 5
31. Revision Summary...................................................... 42
31.1 Revision A0 (November 12, 2004)................................ 42
31.2 Revision A1 (February 18, 2005).................................. 42
31.3 Revision A2 (June 1, 2005)........................................... 42
31.4 Revision A3 (June 21, 2005)......................................... 43
31.5 Revision A4 (May 22, 2006).......................................... 43
31.6 Revision A5 (June 22, 2006)......................................... 43
31.7 Revision A6 (February 27, 2009).................................. 43
3.1 Special Handling Instructions for FBGA Package.......... 6
4.
5.
6.
7.
Pin Configuratio.......................................... 6
Logic Sym....................................... 7
Orderindard Products)................ 7
Devic................................... 9
8.1 Wor.............................. 9
8.2 Reqding A.................. 9
8.3 Writi/Comm.................. 10
8.4 Program d Erase Op..................... 10
8.5 Standby Mode.........................10
8.6 Automatic Sleep .........................0
8.7 RESET#: Hardw...........................1
8.8 Output Disable Mod...........................11
10.1 Autoselect Mode ............................................... 12
11.1 Sector Protection/Unprotection......................... 1
11.2 Temporary Sector Unprotect...........................
11.3 Hardware Data Protection.........................
12. Command Definitions...............................
12.1 Reading Array Data .......................................
12.2 Reset Command..........................................
12.3 Autoselect Command Sequence .................
12.4 Word/Byte Program Command Sequence.....
12.5 Chip Erase Command Sequence ................................ 17
12.6 Sector Erase Command Sequence ............................. 18
12.7 Erase Suspend/Erase Resume Commands ................ 1
14. Write Operation Status .............................................. 20
14.1 DQ7: Data# Polling ...................................................... 20
14.2 RY/BY#: Ready/Busy#................................................. 21
14.3 DQ6: Toggle Bit I ......................................................... 22
14.4 DQ2: Toggle Bit II ........................................................ 22
14.5 Reading Toggle Bits DQ6/DQ2.................................... 22
14.6 DQ5: Exceeded Timing Limits ..................................... 23
14.7 DQ3: Sector Erase Timer............................................. 23
16. Absolute Maximum Ratings...................................... 24
17. Operating Ranges...................................................... 25
18. DC Characteristics..................................................... 25
18.1 Zero Power Flash......................................................... 26
19. Test Conditions.......................................................... 27
21. Key to Switching Waveforms.................................... 28
22. AC Characteristics..................................................... 29
22.1 Read Operations.......................................................... 29
25.1 Erase/Program Operations .......................................... 32
28. Erase And Programming Performance.................... 37
30. Physical Dimensions................................................. 39
30.1 TS 048—48-Pin Standard TSOP................................. 39
Document Number: 002-01235 Rev. *B
Page 3 of 46
S29AL004D
1. Product Selector Guide
Family Part Number
S29AL004D
Speed Options
Full Voltage Range: V = 2.7–3.6 V
55
55
55
25
70
70
70
30
90
90
90
35
CC
Max access time, ns (t
)
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
Note
See AC Characteriscifications.
2. Bl
DQ0–DQ15 (A-1)
V
CC
ector Switches
V
SS
EVoltage
enerator
Input/Output
Buffers
RESET#
State
WE#
Control
BYTE#
Command
Register
PGM V
Gene
Data
Latch
hip Enable
Output Enable
Logic
TB
CE#
OE#
Y-Decoder
STB
V
Detector
CC
Timer
Celtrix
X-Decoder
A0–A17
Document Number: 002-01235 Rev. *B
Page 4 of 46
S29AL004D
3. Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
6
17
18
1
2
DQ12
DQ4
VCC
Standard TSOP
WE
RESE
RY
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A
A7
A6
A5
A4
A3
A2
A1
#
A17
A7
2
3
4
5
6
7
8
9
44 RESET#
3 WE#
A8
41 A9
A6
40 A10
A5
39 A11
A4
38 A12
A3
37 A13
A2
36 A14
A1 10
A0 11
35 A15
SO
34 A
CE# 12
VSS 13
33 TE#
3SS
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
15/A-1
30
29 D
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
3 VCC
Document Number: 002-01235 Rev. *B
Page 5 of 46
S29AL004D
FBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
ESET#
NC
NC
DQ5
DQ12
VCC
DQ4
C3
D3
E3
F3
G3
H3
NC
NC
DQ2
DQ10
DQ11
DQ3
A7
B2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
VSS
3.1
Special Handling trctioackage
Special handling is required for Flash Memory prodes. Flamemory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methodor datntegrity may be compromised if the package body is
exposed to temperatures above 150C for prolon.
4. Pin Configuration
A0–A17
DQ0–DQ14
DQ15/A-1
BYTE#
CE#
18 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode), A-1 (LSB address iyte mode)
Selects 8-bit or 16-bit mode
Chip enable
OE#
Output enable
WE#
Write enable
RESET#
RY/BY#
Hardware reset pin, active low
Ready/Busy# output
3.0 volt-only single power supply
V
CC
(see Product Selector Guide on page 4 for speed options and voltage supply tolerances)
V
Device ground
SS
NC
Pin not connected internally
Document Number: 002-01235 Rev. *B
Page 6 of 46
S29AL004D
5. Logic Symbol
18
A0–A17
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
6. Ordering on (SndarProducts)
This product has been renot recomnded foesigns. For new and current designs, S29AL008J supercedes
S29AL004D. This is the factory-recomnded ation path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Spansion standard products are avale in sevl pacg ranges. The order number (Valid Combination) is
formed by a combination of the elembelo
S29AL004D
55
T
A
I
g Type
1
2
3
= Tray
= Tu
= Tape and Reel
13” Tape and Reel
odel Number
= V = 2.7 - 3.6Vboot sector devic
CC
V = 3.0 - 3tt sector device
CC
0= 2.7 6V, bottot sector device
C
R2 = V = - 3.6V, bottom sector device
CC
Temperaange
I
N
= Indust0°C to +85°C)
= Extended C to +125°C)
Package Material
A
F
= Standard
= Pb-Free
Package Type
T
B
M
= Thin Small Outline Package (TSOP) Stand Pinou
= Fine-pitch Ball-Grid Array Package
= Small Outline Package (SOP) StanPinout
Speed Option
55 = 55 ns Access Speed
70 = 70 ns Access Speed
90 = 90 ns Access Speed
Device Number/Description
S29AL004D
4 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase
Document Number: 002-01235 Rev. *B
Page 7 of 46
S29AL004D
S29AL004D Valid Combinations
Package Type,
Package Description
Speed
Model
Number
Device Number
Material, and
Packing Type
Option
Temperature Range
TAI, TFI
TAN, TFN
01, 02
R1, R2
01, 02
01, 02
R1, R2
01, 02
01, 02
R1, R2
01, 02
55
70
0, 3 (Note 1)
TS048 (Note 3)
VBK048 (Note 4)
SO044 (Note 3)
TSOP
AI, TFI, TAN, TFN
BAI, BFI
Fine-Pitch
BGA
S29AL004D
BAN, BFN
0, 2, 3 (Note 1)
0, 1, 3 (Note 2)
I, BFI, BA, BFN
MA
SOP
Notes
1. Type 0 is standard. Specify oth.
2. Type 1 is standard. Specify uired.
3. TSOP and SOP packagg type deator from ong part number.
4. BGA package marking omitd packing tyesignator ordering part number.
Valid Combinations
Valid Combinations list configurationlanned to supporor this device. Consult your local sales office to confirm
availability of specific valid combinas and to ck on mbinations.
Document Number: 002-01235 Rev. *B
Page 8 of 46
S29AL004D
7. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command
register. The command register itself does not occupy any addressable memory location. The register is composed of latches that
store the commands, along with the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 8 lists the device
bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these
operations in further detai
le 8. S29AL004D Device Bus Operations
DQ8–DQ15
Addresses
(Note 1)
DQ0–
DQ7
Oper
OE#
RESET#
BYTE#
BYTE# = V
IL
= V
IH
Read
L
H
H
A
A
D
D
OUT
IN
IN
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write
D
D
IN
IN
Standby
V
H
X
V
0.3V
CC
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
CC
Output Disable
Reset
L
X
X
ctor Address,
6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
H
L
D
X
X
X
D
IN
Se
Sector Unprotect (Note 2)
L
X
L
D
D
X
D
ID
IN
IN
Temporary Sector Unprotect
X
V
D
High-Z
IN
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
V
= 12.0 0.5 V
ID
X = Don’t Care
A
= Address In
= Data In
IN
D
D
IN
= Data Out
OUT
Notes
1. Addresses are A17:A0 in word mode (BYTE# = V ), A17:A-1 in byte mode (BYTV ).
IH
IL
2. The sector protect and sector unprotect functions may also be implemented via progamminuipment. See or Protection/Unon on page 12.
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate ihe byte or woconfigurationthe E# pin is
set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by Cand OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O piDQ0–DQ7 are and controlled by
CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for thSB (address function.
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the r control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. ThBYTE# pin determines
whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register contents are altered.
Document Number: 002-01235 Rev. *B
Page 9 of 46
S29AL004D
See Reading Array Data on page 15 for more information. Refer to the AC Read Operations on page 29 for timing specifications and
to Figure 23.1 on page 29 for the timing diagram. ICC1 in DC Characteristics on page 25 represents the active current specification
for reading array data.
8.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WEo VIL, and OE# to VIH.
For program opepin determines whether the device accepts program data in bytes or words. Refer to Word/Byte
Configuration formation.
The device ypass e to facilitate faster programming. Once the device enters the Unlock Bypass mode,
only two wed to pword or byte, instead of four. The Word/Byte Program Command Sequence
on page 1ogramhe device using both standard and Unlock Bypass command sequences.
An erase oerase le sectors, or the entire device. Table 9 on page 11 and Table 10 on page 11
indicate the address space ccupies. A sector address consists of the address bits required to uniquely select a
sector. The Command Dge 15 has aerasing a sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes tt commanequenche device enters the autoselect mode. The system can then read
autoselect codes from the il regiser (whisepate from the memory array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to AutoseleMode on e 12 and ACommand Sequence on page 16 for more information.
I
CC2 in DC Characteristics on page epresente actiation for the write mode. The AC Characteristics
on page 29 contains timing specificatables d time operations.
8.4
Program and Erase Oper
During an erase or program operation, the system tatus he operation by reading the status bits on DQ7–DQ0.
Standard read cycle timings and ICC read specificaefer to rite Operation Staton page 20 for more information, and
to AC Characteristics on page 29 for timing diagrams.
8.5
Standby Mode
When the system is not reading or writing to the device, it can plae devicn the dby mode. In mode, current
consumption is greatly reduced, and the outputs are placed in the high impance statedependent of E# input.
The device enters the CMOS standby mode when the CE# and RESET# are both held at VCC 0V. (Nothat this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but nthin VCC 0.3 V, thevice is in the andby mode,
but the standby current is greater. The device requires standard access time (or read accewhen the devieither of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active currenntil the operatis completed
In the DC Characteristics on page 25 table, ICC3 and ICC4 represents the standby current specification
8.6
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically ens this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, d OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. ICC4 in DC Characteristics on page 25 represents the automatic sleep mode current specification.
Document Number: 002-01235 Rev. *B
Page 10 of 46
S29AL004D
8.7
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for
at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data
integrity.
Current is reduced for tn of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby
current (ICC4). If REVIL but not within VSS±0.3 V, the standby current is greater.
The RESET# psystem reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to rere from he Flash memory.
If RESET# prograse operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is
complete, me of tg Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether tn is coT# is asserted when a program or erase operation is not executing (RY/BY# pin is
1), the reseis come of tREADY (not during Embedded Algorithms). The system can read data tRH after
the RESET# pin returns to
Refer to the tables in Aon pag9 for RET# parameters and to Figure 24.1 on page 30 for the timing diagram.
8.8
Output Dise Mode
When the OE# input is at VIH, output om the deis disabut pins are placed in the high impedance state.
Table 9. AL004D op Bdresses
AddreRange (in hexadecimal)
Sector
A17
A16
A15
A14
A13
A12
x8) Adds Range
00h–0FFFFh
0000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FF
50000hF
600–6FFFFh
0h–7FFFFh
7–79FFFh
7A00FFFh
7C000h–FFFh
(x16) Address Range
00000h–07FFFh
8000h–0FFFFh
0h–17FFFh
18FFFFh
20000h7FFFh
28000h–2FF
30000h–37FFF
38000h–38FF
3C000h–3Fh
3D000DFFFh
3Eh–3FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
64/32
64/32
64/
64/32
64/32
32/16
8/4
1
1
0
1
8/4
1
1
X
16/8
Note
The address range is A17:A-1 in byte mode and A17:A0 in word mode. See Word/Byte Configuration on page 9.
Table 10. S29AL004D Bottom Boot Block Sector Addresses
Address Range (in hexaal)
Sector Size
(Kbytes/
Kwords)
Sector
A17
A16
A15
A14
A13
A12
(x8)
(x1
Address Range
Address R
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
X
0
16/8
8/4
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
0
1
1
8/4
1
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
X
X
X
X
Document Number: 002-01235 Rev. *B
Page 11 of 46
S29AL004D
Table 10. S29AL004D Bottom Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector Size
(Kbytes/
Kwords)
Sector
A17
A16
A15
A14
A13
A12
(x8)
(x16)
Address Range
Address Range
SA8
SA9
1
1
1
0
1
1
1
0
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
SA10
Note
The address range nd A17:A0 in word mode. See Word/Byte Configuration on page 9.
10.1 ode
The autoses madevice identification, and sector protection verification, through identifier codes
output on is modnded for programming equipment to automatically match a device to be
programmed wits corresping algorithm. However, the autoselect codes can also be accessed in-system
through the command reg
When using programhe autoect mode quires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1,
and A0 must be as sho. In addiwhen vying sector protection, the sector address must appear on the
appropriate highest order bits (see Taon pae 11 and Table 10 on page 11). Table 11 on page 12 shows the
remaining address bits that are don’t e. Whenecessary biet as required, the programming equipment may then read
the corresponding identifier code on Q7–DQ0.
To access the autoselect codes in-sm, the ht sysutoselect command via the command register, as shown
in Table 12.2 on page 19. This methot requd Definitions on page 15 for details on using the
autoselect mode.
Table 11. S29AL004D AutVoltaMethod)
A1
to
A10
8
DQ
DQ7
to
DQ0
A17
to
A12
to
A7
o
A5
A3
to
A2
Description
Mode CE#
OE# WE#
A6
L
A1
L
A0
L
Manufacturer ID: Spansion
L
L
L
L
H
H
X
X
V
V
X
X
L
X
01h
B
ID
ID
Device ID:
S29AL004D
(Top Boot Block)
Word
Byte
22h
X
X
X
X
L
L
L
L
L
L
H
H
X
B9
BA
Device ID:
S29AL004D
(Bottom Boot
Block)
Word
22h
X
X
X
V
V
X
X
L
L
X
X
L
L
H
L
ID
ID
Byte
L
L
H
X
Ah
01h
(protected)
X
Sector Protection
Verification
L
L
H
SA
H
00h
(unprot
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
SA = Sector Address
X = Don’t care.
11.1 Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previously protected sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory
prior to shipping the device through Spansion’s ExpressFlash™ Service. Contact an Spansion representative for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 12 for details.
Document Number: 002-01235 Rev. *B
Page 12 of 46
S29AL004D
Sector Protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment.
Figure 11.2 on page 14 shows the algorithms and Figure 26.2 on page 36 shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector
unprotect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is
compatible with programnes written for earlier 3.0 volt-only Spansion flash devices.
11.2 Teor Unprotect
This feature protectif previously protected sectors to change data in-system. The Sector Unprotect mode is
activated b# pin ting this mode, formerly protected sectors can be programmed or erased by selecting
the sector VID is the RESET# pin, all the previously protected sectors are protected again.
Figure 11.1 lgorith1 on page 35 shows the timing diagrams, for this feature.
Figure 11Temary Sector Unprotect Operation
START
1)
or
ration
RESE= VIH
Temporactor
Unprotect Complete
(Note 2)
Notes
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Document Number: 002-01235 Rev. *B
Page 13 of 46
S29AL004D
Figure 11.2 In-System Sector Protect/Sector Unprotect Algorithms
START
START
Protect all sectors:
PLSCNT = 1
PLSCNT = 1
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
RESET# = VID
RESET# = VID
Wait 1 μs
1 μs
unprotect address
No
First Write
Cycle = 60h?
rite
= 60h?
Temporary Sector
Unprotect Mode
Tempora
Unpro
Yes
Y
Set u
No
All sectors
protected?
Yes
tor
1,
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
Wait 150
A6 = 1, A1 = 1,
A0 = 0
Verify S
Protect: Wrh
to sector ad
with A6 = 0,
Re
PLS
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h o sector
awith
= = 1,
A0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
ector address
h A6 = 1,
= 1, A0 = 0
Data = 01h?
Yes
No
Yes
up
next sector
addre
Yes
No
PLSCN
= 1000?
Protect another
sector?
Data = 0?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
verified?
Device failed
Write reset
command
Remove VID
from RESET#
Sector Unprotect
Algorithm
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Document Number: 002-01235 Rev. *B
Page 14 of 46
S29AL004D
11.3 Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to Table 12.2 on page 19 for command definitions). In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC
power-up and power-down transitions, or from system noise.
11.3.1
Low te Inhibit
When VCC is less vice does not accept any write cycles. This protects data during VCC power-up and power-down.
The command nal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored
until VCC is ge system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is grea
11.3.2
Pulse tection
Noise pulses of less than 5 #, CE# or WE# do not initiate a write cycle.
11.3.3
Log
Write cycles are inhibited any one o# = VIE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical on
11.3.4
Power-Up WriInhibit
If WE# = CE# = VIL and OE# = VIH durer up, ccept commands on the rising edge of WE#. The internal
state machine is automatically reset to reading arra
12. Command Definitions
Writing specific address and data commands or sequences into the ommand register intvice operations. Figure 12.2
on page 19 defines the valid register command sequences. Writincorrect addresnd datlues or writing them in the
improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, wher happelatll data is latchn the rising edge of WE#
or CE#, whichever happens first. Refer to the appropriate timing dims in C Charastics on page
12.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No mands are ruired to retriedahe device
is also ready to read array data after completing an Embedded Program or Embedded Erase gorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspmode. The sm can read array data
using the standard read timings, except that if it reads at an address within erase-suspended sectors, thdevutputs status data.
After completing a programming operation in the Erase Suspend mode, the system may once again ad array with the same
exception. See Erase Suspend/Erase Resume Commands on page 18 for more information on tmode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 gogh, or while in the autoselect
mode. See Reset Command on page 15.
See also Requirements for Reading Array Data on page 9 for more information. The Read Operations on page 29 provides the read
parameters, and Figure 23.1 on page 29 shows the timing diagram.
12.2 Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
Document Number: 002-01235 Rev. *B
Page 15 of 46
S29AL004D
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins.
This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command maen between the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset cowritten to return to reading array data (also applies to autoselect during Erase Suspend).
If DQ5 goes hior erase operation, writing the reset command returns the device to reading array data (also
applies durin
12.3 Comquence
The autosed sequost system to access the manufacturer and devices codes, and determine whether
or not a sector is protected. ge 19 shows the address and data requirements. This method is an alternative to that
shown in Table 11 on paintended fPprogrammers and requires VID on address bit A9.
The autoselect commnitiated writing tunlock cycles, followed by the autoselect command. The device then
enters the autoselect msystem mead at aaddress any number of times, without initiating another command
sequence.
A read cycle at address XX00h retries the mancturer codcle at address XX01h in word mode (or 02h in byte mode)
returns the device code. A read cycontaining ector the address 02h in word mode (or 04h in byte mode)
returns 01h if that sector is protected00h if iunpble 9 on page 11 and Table 10 on page 11 for valid
sector addresses.
The system must write the reset command to exit tnd retto reading array data.
12.4 Word/Byte Program Comquene
The system may program the device by word or byte, depending ohe state of the BY# programming is a four-bus-cycle
operation. The program command sequence is initiated by writitwo unlock write cys, followy the program set-up
command. The program address and data are written next, win turn initiate thmbedded Prram algorithm. The system is
not required to provide further controls or timings. The device aatically proeernally generatprogram pulses and
verifies the programmed cell margin. Table 12.2 on page 19 showaddrand dequirements fe byte program
command sequence.
When the Embedded Program algorithm is complete, the device then retto reading array data anaddress are no longer
latched. The system can determine the status of the program operation by uDQ7, DQ6, or RY/#. See Write ration Status
on page 20 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Ne that a harde reset idiately
terminates the programming operation. The program command sequence should be reinied once the de has reset to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programed from a ack to a 1.
Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algoritho indicate the operation was
successful. However, a succeeding read shows that the data is still 0. Only erase operations can ert a 0 to a 1.
12.4.1
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the
unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. Table 12.2 on page 19 shows the requirements for the command sequence.
Document Number: 002-01235 Rev. *B
Page 16 of 46
S29AL004D
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h (F0h). Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 12.1 illustrates the algorithm for the program operation. See Table 25 on page 30 for parameters, and Figure 25.3
on page 32 for timing diagrams.
Figure 12.1 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embeed
Prram
algorithm
in progres
y Data?
No
Ye
Increme
LaAddress?
Yes
Programmin
Comple
Note
See Table 13 on page 19 for program command sequence.
12.5 Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by ting two unlocycles, followby a
set-up command. Two additional unlock write cycles are then followed by the chip erase mmand, whicrn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. ThmbeErase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrl erase. Tystem is not
required to provide any controls or timings during these operations. Table 12.2 on page 19 showe address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a harre reset during the chip
erase operation immediately terminates the operation. The Chip Erase command sequence should be renitiated once the device
has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status
on page 20 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Figure 12.2 on page 19 illustrates the algorithm for the erase operation. See Table 25 on page 30 for parameters and Figure 25.4
on page 33 for timing diagrams.
Document Number: 002-01235 Rev. *B
Page 17 of 46
S29AL004D
12.6 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector
erase command. Table 12.2 on page 19 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically
programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings duriperations.
After the commanten, a sector erase time-out of 50 µs begins. During the time-out period, additional sector
addresses and nds may be written. Loading the sector erase buffer may be done in any sequence, and the
number of see sector to all sectors. The time between these additional cycles must be less than 50 µs,
otherwise tommanht not be accepted, and erasure may begin. It is recommended that processor
interrupts is timall commands are accepted. The interrupts can be re-enabled after the last Sector
Erase comthe tiditional sector erase commands can be assumed to be less than 50 µs, the system
need not mAny coan Sector Erase or Erase Suspend during the time-out period resets the
device to reaarray daust rewrite the command sequence and any additional sector addresses and
commands.
The system can moniine if thector eratimer has timed out. (See DQ3: Sector Erase Timer on page 23). The
time-out begins from thf the finaE# pulse the command sequence.
Once the sector erase operahas bun, one Erase Suspend command is valid. All other commands are ignored. Note that
a hardware reset during the sector ese operaimmediatees the operation. The Sector Erase command sequence
should be reinitiated once the devicas returneo readiensure data integrity.
When the Embedded Erase algorithcomple, the ding array data and addresses are no longer latched.
The system can determine the status of rase o, DQ6, Q2, or RY/BY#. Refer to Write Operation Status
on page 20 for information on these status bits.
Figure 12.2 on page 19 illustrates the algorithm fon. Reto Table 25 on page 30 for parameters, and to
Figure 25.4 on page 33 for timing diagrams.
12.7 Erase Suspend/Erase Resume Comands
The Erase Suspend command allows the system to interrupt tor erase operand then read data from, or program data to,
any sector not selected for erasure. This command is valid only g the secerperation, inclg the 50 µs time-out
period during the sector erase command sequence. The Erase Susnd coand is ied if written dthe chip erase
operation or Embedded Program algorithm. Writing the Erase Suspend cmand during he Sector Erasout immediately
terminates the time-out period and suspends the erase operation. Addreare don’t-cares when wrg the se Suspend
command.
When the Erase Suspend command is written during a sector erase operation, device requis a maximum 20 suspend
the erase operation. However, when the Erase Suspend command is written during the secterase time-ouhe devic
immediately terminates the time-out period and suspends the erase operation.
After the erase operation is suspended, the system can read array data from or program data to any seor nected for erasure.
(The device erase suspends all sectors selected for erasure.) Normal read and write timings and comand defins apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. Thstem can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write OperaStatus on page 20 for
information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data whin non-suspended
sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See Write Operation Status on page 20 for more information.
The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows
reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 16 for more information.
Document Number: 002-01235 Rev. *B
Page 18 of 46
S29AL004D
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the
sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after
the device has resumed erasing.
Figure 12.2 Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
DFFh?
Y
Era
Notes
1. See Sector Erase Command Sequence on page 18 for erase
2. See DQ3: Sector Erase Timer on page 23 for more informati
Table 13ommaDefinitions
Bus Cycles (Notes
Command
First
Second
Third
ourth
Fifth
Addr Data
Sixth
Addr Data
Sequence
(Note 1)
Addr
Data
RD
F0
Addr
D
Addr
Data
ddr
Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
555
AAA
555
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90
90
X00
01
AAA
555
X01
X02
X01
X0
22B9
Device ID,
Top Boot Block
AAA
555
AAA
555
2BA
BA
Device ID,
Bottom Boot Block
AAA
AAA
XX00
XX01
00
Word
Byte
555
2AA
555
555
(SA)X02
(SA)X04
PA
Sector Protect Verify
(Note 9)
4
AA
55
55
90
AAA
AAA
01
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
PA
555
AAA
555
Program
4
3
AA
AA
A0
20
PD
Unlock Bypass
55
AAA
XXX
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
(F0h)
XXX
XXX
Document Number: 002-01235 Rev. *B
Page 19 of 46
S29AL004D
Table 13. S29AL004D Command Definitions
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
10
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
AAA
Sector Erase
SA
30
AAA
XXX
XXX
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
B0
30
Legend
X = Don’t care
RA = Address oread
RD = Data reead oped
PA = Addresbe proesses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to tion PAe rising edge of WE# or CE# pulse, whichever happens first.
SA = Addresverified or erased. Address bits A17–A12 uniquely select any sector.
Notes
1. See Table 8 on page 9 for desons.
2. All values are in hexadecim
3. Except when reading arall bus cyare write otions.
4. Data bits DQ15–DQ8 are dck and comd cycles.
5. Address bits A17–A11 are don’r unlocand comd cyclesunless PA or SA required.
6. No unlock or command cycles required wheading arra.
7. The Reset command is required to return tading array dwhen devct mode, or if DQ5 goes high (while the device is
providing status data).
8. The fourth cycle of the autoselect command nce ead c
9. The data is 00h for an unprotected sector and 0r a protectmmand quence on page 16 for more
information.
10.The Unlock Bypass command is required prior to the Unlock d.
11. The Unlock Bypass Reset command is required to return to n the de is in the unlock bypass mode.
12.The system may read and program in non-erasing sectors, oect modhen in the Erase Suspemode. The Erase
Suspend command is valid only during a sector erase operation
13. The Erase Resume command is valid only during the Erase Suspend mode.
14. Write Operation Status
The device provides several bits to determine the status of a write oeratioDQ2, DQ3Q5, DQ6, DQ7RY/BY#. Table 15
on page 24 and the following subsections describe the functions of thess. DQ7, RY/BY#, and DQ6 ch a method for
determining whether a program or erase operation is complete or in progrThese three bits are dussed first.
14.1 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algoriths in progress mpleted, or whether
the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the ogor erase command
sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the daprogrammed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithcomplete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status inftion on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the vice returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if
the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum
output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
Document Number: 002-01235 Rev. *B
Page 20 of 46
S29AL004D
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following
read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low.
Figure 25.6 on page 34 illustrates this.
Table 15 on page 24 shutputs for Data# Polling on DQ7. Figure 14.1 on page 21 shows the Data# Polling algorithm.
Figure 14.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 ata?
Yes
DQ7 = Data
No
SS
FAIL
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sectlected for erasururing che, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
14.2 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since R# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.
Table 15 on page 24 shows the outputs for RY/BY#. Figure 23.1 on page 29, Figure 24.1 on page 30, Figure 25.3 on page 32, and
Figure 25.4 on page 33 shows RY/BY# for read, reset, program, and erase operations, respectively.
Document Number: 002-01235 Rev. *B
Page 21 of 46
S29AL004D
14.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.
After an erase commis written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to renot all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and igectors that are protected.
The system 2 togetto determine whether a sector is actively erasing or is erase-suspended. When the
device is as, the d Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend gglinge system must also use DQ2 to determine which sectors are erasing or erase-
suspendehe sys7 (see DQ7: Data# Polling on page 20).
If a program ass falls wiector, DQ6 toggles for approximately 1 µs after the program command sequence is
written, then returns to re.
DQ6 also toggles duriend-proam modnd stops toggling once the Embedded Program algorithm is complete.
Table 15 on page 24 shouts for ToBit I on Q6. Figure 14.2 on page 23 shows the toggle bit algorithm. Figure 25.7
on page 34 shows the toggltiming agramgure 25.8 on page 34 shows the differences between DQ2 and DQ6 in graphical
form. See also DQ2: Toggle Bit II on ge 22.
14.4 DQ2: Toggle Bit I
The Toggle Bit II on DQ2, when used with DQ6, indcular stor is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that seed. Tle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
DQ2 toggles when the system reads at addresses sectorat are selected for asure. (The system may use either
OE# or CE# to control the read cycles.) But DQ2 cannot distinguish hether the sector icerasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is actively erag, or is in Erase Spend, annot distinguish which sectors
are selected for erasure. Thus, both status bits are required foctor and mode inmation. RefeTable 15 on page 24 to
compare outputs for DQ2 and DQ6.
Figure 14.2 on page 23 shows the toggle bit algorithm in flowchart , and e sectio2: Toggle Bit page 22 explains the
algorithm. See also the DQ6: Toggle Bit I on page 22 subsection. Figure 7 on page 34 shows the toggming diagram.
Figure 25.8 on page 34 shows the differences between DQ2 and DQ6 in phical form.
14.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 14.2 on page 23 for the following discussion. Whenever the system initially egins reading gle bit statumust
read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typlly, the systenote and store the
value of the toggle bit after the first read. After the second read, the system would compare the new vue of tggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The stem can rarray data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still togglingsystem also should note
whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 23). If it is, the system sd then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the
operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 14.2 on page 23)
Document Number: 002-01235 Rev. *B
Page 22 of 46
S29AL004D
14.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a 1.
Under both these conystem must issue the reset command to return the device to reading array data.
14.7 Dase Timer
After writinmand ce, the system may read DQ3 to determine whether or not an erase operation has
begun. (Tr does the chip erase command.) If additional sectors are selected for erasure, the entire
time-out aeach aerase command. When the time-out is complete, DQ3 switches from 0 to 1. The
system ma3 if the antee that the time between additional sector erase commands is always less than
50 µs. See also the Sector Sequence on page 18.
igure 14Toggle Bit Algorithm
START
(Note 1
No
Toggle
= To
Ye
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes 1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Program/Erase
Complete, Write
Reset Command
Operation Complete
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
Document Number: 002-01235 Rev. *B
Page 23 of 46
S29AL004D
After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle
has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the
device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the
status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. Table 15 shows the outputs for DQ3.
Table 15. Write Operation Status
7
)
DQ5
(Note 1)
DQ2
(Note 2)
DQ6
DQ3
RY/BY#
gorithm
Algorith
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
0
N/A
Toggle
1
Erase
Suspend
Mode
Reading withi
Suspended S
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Pr
DQ7
Toggl
Notes
1. DQ5 switches to 1 when an Embedded Prom or EmbedErase operd the maximum timing limits. See DQ5: Exceeded Timing Limits
on page 23 for more information.
2. DQ7 and DQ2 require a valid address wheing statuformate subsection for further details.
16. Absolute Maximum Rating
Storage Temperature Plastic Packages–65°C to
Ambient Temperature with Power Applied–65°C to +
Voltage with Respect to Ground VCC (Note 1)–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2)–0.5 V to +12.5 V
All other pins (Note 1)
–0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3)200 mA
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pinundershoot V to –2.0 r periods of up to ns. See
SS
Figure 17.1 on page 25. Maximum DC voltage on input or I/O pins is V +0.5 V. During voltage tions, input or I/O pmay overshoot to 0 V for periods
CC
up to 20 ns. See Figure 17.2 on page 25.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESEmay undershoot to –2.0 V fods of up
to 20 ns. See Figure 17.1 on page 25. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 0 V for periods up 0 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greathan one second.
4. Stresses above those listed under Absolute Maximum Ratings on page 24 may cause permanent damage to the device. This stress rnly; functional
operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet ot implied. Exre of the device to
absolute maximum rating conditions for extended periods may affect device reliability.
Document Number: 002-01235 Rev. *B
Page 24 of 46
S29AL004D
17. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA)
-40°C to +85°C
Extended (N) Devices
Ambient Temperature (T)
-40°C to +125°C
7 V to +3.6 V
V
Supply Vo
CC
VCC for full vol
Operating rits betwn which the functionality of the device is guaranteed.
1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
2.0 V
Figure 17.2 vershWaveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
18. DC Characteristics
Parameter
Description
Test Conditions
Min
Typ
ax
1.0
35
Unit
µ
V
V
= V to V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
SS
,
OUT
CC
I
1
µA
LO
= V
CC
CC max
10 MHz
5 MHz
1 MHz
10 MHz
5 MHz
1 MHz
18
9
35
16
4
CE# = V OE#
IL,
Byte Mode
V
=
IH,
2
V
Active Read Current
CC
I
I
mA
mA
CC1
(Notes 1, 2)
15
9
30
16
4
CE# = V OE#
IL,
Word Mode
V
V
=
=
IH,
IH
2
V
Active Write Current
CC
CE# = V OE#
20
35
CC2
IL,
(Notes 2, 3, 6)
I
I
V
Standby Current (Notes 2, 4)
CE#, RESET# = V 0.3 V
0.2
0.2
5
5
µA
µA
CC3
CC
CC
CC
V
Reset Current (Notes 2, 4)
RESET# = V 0.3 V
CC4
SS
Document Number: 002-01235 Rev. *B
Page 25 of 46
S29AL004D
Parameter
Description
Test Conditions
Min
Typ
Max
5
Unit
Automatic Sleep Mode
(Notes 2, 4, 5)
V
V
= V 0.3 V;
CC
= V 0.3 V
IH
IL
I
0.2
µA
CC5
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
0.7 x V
V
+ 0.3
CC
IH
CC
Voltage for Autoselect and
Temporary Secttect
V
V
= 3.3 V
11.5
2.4
12.5
0.45
V
ID
CC
V
Output L
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
V
V
= –2.0 mA, V = V
CC
OH1
OH2
LKO
CC min
CC min
O
= –100 µA, V = V
V
–0.4
CC
CC
e
2.3
2.5
V
Notes
1. The I less thOE# at V . Typical V is 3.0 V.
CC
IH
CC
2. Maximum are test
3.
I
active whiledded Erasm is in progress.
CC
4. At extended temperature rancurrent is 5mum current is 10µA.
5. Automatic sleep mode enode when dresses rn stable for t
6. Not 100% tested.
+ 30 ns.
ACC
18.1 Zero Power Flash
Figure 18.1 Currt vs. e and Automatic Sleep Currents)
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
4000
Time in ns
Note
Addresses are switching at 1 MHz.
Document Number: 002-01235 Rev. *B
Page 26 of 46
S29AL004D
Figure 18.2 Typical ICC1 vs. Frequency
10
8
3.6 V
2.7 V
2
0
1
2
4
5
in MHz
Note
T = 25 C
19. Test Conditions
Figure 19est Setup
3.3 V
2.7 k
Device
Under
Test
C
6.2 k
L
Note
Nodes are IN3064 or equivalent.
Document Number: 002-01235 Rev. *B
Page 27 of 46
S29AL004D
Table 20. Test Specifications
Test Condition
55
70
1 TTL gate
90
Unit
Output Load
Output Load Capacitance, C
(including jig capacitance)
L
30
30
100
pF
ns
Input Rise and Fall Times
Input Pulse Levels
5
0.0 or V
CC
Input timing mea
Output timing ls
0.5V
0.5V
V
CC
CC
21. Kechinrms
Waveform
nputs
Outputs
Steady
Changing from H to L
H
Don’t Change
Does Not Ap
Changing, State Unknown
nter Lis High Impedance State (High Z)
Figure 21.1 Input Wavems and Measuremt Levels
Meaent Lev
V
CC
0.5V
Input
Output
0.5V
C
CC
0.0 V
Document Number: 002-01235 Rev. *B
Page 28 of 46
S29AL004D
22. AC Characteristics
22.1 Read Operations
Parameter
Table 23. Read Operations
Speed Options
Description
JEDEC
Std
Test Setup
55
70
90
Unit
t
t
te 1)
Min
55
70
90
AVAV
RC
CE# = V
OE# = V
IL
IL
t
elay
Max
55
70
90
AVQV
t
Output
OE# = V
Max
Max
Max
Max
Min
Min
Min
55
25
70
30
16
16
20
0
90
35
ELQV
GLQV
EHQZ
IL
t
t
t
le to O
nable to 1)
Output EnaNote 1)
LatencWrite Opens
DF
ns
t
GHQZ
t
SR/W
Read
Out
t
OEH
Hold Ti
Toggle ata# Pollin
10
Output Hold Time From Aesses, Cr OE#,
Whichever Occurs First ote 1)
t
t
Min
0
AXQX
OH
Notes
1. Not 100% tested.
2. See Figure 19.1 on page 27 and Table 20 on test sp
Figations mings
t
Addres Stable
Addresses
CE#
t
t
DF
OE
OE#
t
SR/W
t
OEH
WE#
t
CE
t
O
HIGH Z
HZ
Output Val
Outputs
RESET#
RY/BY#
0 V
Document Number: 002-01235 Rev. *B
Page 29 of 46
S29AL004D
Table 24. Hardware Reset (RESET#)
Parameter
JEDEC Std
Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
t
20
µs
READY
READY
Max
Min
RESET# Pin Low (NOT During Embedded
Algoror Write (See Note)
t
500
ns
t
500
50
20
0
ns
ns
µs
ns
RP
t
efore Read (See Note)
dby Mod
Time
R
t
Note
Not 100% te
F4.1 RESET# Timings
RY
CE#, OE#
RESET#
tRP
tRead
Reset Timings NOT duriEmbedded Algorithm
Reset Timings dEmbedded Algorith
tReady
RY/BY#
tRB
CE#, OE#
RESET#
t
RH
tRP
Table 25. Word/Byte Configuration (BYTE#)
Parameter
Speed Options
Description
JEDEC
Std
55
70
90
nit
t
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
5
ELFL/ ELFH
t
16
70
ns
FLQZ
t
55
90
FHQV
Document Number: 002-01235 Rev. *B
Page 30 of 46
S29AL004D
Figure 25.1 BYTE# Timings for Read Operations
CE#
OE#
TE#
tELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
te
Q0–D
mode
Address
Input
DQ15
Output
tFLQZ
tELFH
BYT
BYTE#
Switching
from byte to
word mode
ata Out
(DQ07)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
ddress
Input
D
p
tFHQV
Figure 25.2 BYTE# Timings forite Operations
CE#
The falling edge of the last WEgnal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note
Refer to Erase/Program Operations on page 32 for t and t specifications.
AS
AH
Document Number: 002-01235 Rev. *B
Page 31 of 46
S29AL004D
25.1 Erase/Program Operations
Parameter
Speed Options
Description
JEDEC
Std
55
70
70
0
90
Unit
t
t
Write Cycle Time (Note 1)
Address Setup Time
Adme
55
90
AVAV
WC
t
t
AVWL
WLAX
AS
AH
DS
t
t
45
35
0
t
t
t
35
45
DVWH
WHDX
t
tup Time
0
Min
ns
y Time Bte
WE# L
t
0
GHWL
t
up Tim
0
0
ELWL
WHEH
WLWH
WHWL
WP
t
t
# Hold T
t
Write P
35
30
20
5
t
t
Wri
Land Writerations
WPH
t
Min
ns
µs
SR/W
yte
t
t
t
t
PrograperatioNote 2)
Sector Erase Opera(Note 2)
WHWH1
WHWH2
WHWH1
Word
7
0.7
50
0
sec
µs
WHWH2
t
V
Setup Time (N)
CC
VCS
t
Recovery Time from
RB
ns
t
Program/Erase Valid to RY/BY# Delay
90
BUSY
Notes
1. Not 100% tested.
2. See the Sector Erase Command Sequence on page 18 secttion.
Figure 25.3 PrograOperation Timings
Program Command Sequencst two cycles)
ad Status Datast two cycles)
tAS
PA
tWC
Addresses
555h
tAH
CE#
OE#
tCH
tWHWH
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Document Number: 002-01235 Rev. *B
Page 32 of 46
S29AL004D
Figure 25.4 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
VA
VA
tAS
SA
tWC
Addresses
2AAh
555h for chip erase
tAH
tCH
WP
tWPH
tWHWH2
tDH
In
D
Complete
55
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address fWrite Option Status on page 20).
2. Illustration shows device in word mode.
Figure 25.5 Back to Back ead/Write Cycle Ting
t
t
WC
RC
Addresses
PA
PA
PA
t
t
ACC
t
AH
CP
t
CE
CE#
OE#
t
t
OE
t
GHWL
t
SR/W
t
WP
t
t
WE#
Data
DF
t
WDH
DS
t
OH
t
DH
V
In
Valid
Out
Valid In
Valid Out
Document Number: 002-01235 Rev. *B
Page 33 of 46
S29AL004D
Figure 25.6 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tOE
O
tDF
tOH
High Z
High Z
Valid Data
ement
Complement
True
DQ0–DQ6
Status ta
True
Valid Data
Status Data
tB
RY/BY#
Note
VA = Valid address. Illustration shows first staycle after coand seqcycle, and array data read cycle
Figur7 ToggEmbedded Algorithms)
tRC
Addresses
VA
tACC
tCE
VA
VA
VA
CE#
tCH
tOE
OE#
tOEH
tDF
tOH
WE#
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Sta
Valita
(second read)
(stops gling)
tBUSY
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status rea, and array data
read cycle.
Figure 25.8 DQ2 vs. DQ6
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Document Number: 002-01235 Rev. *B
Page 34 of 46
S29AL004D
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Suspend
Program
Complete
Read
DQ6
DQ2
Taemporary Sector Unprotect
Param
All Speed Options
JEDEC
Unit
ns
t
V
Rise te)
ID
Min
Min
500
4
VIDR
t
RESemporary Sor Unpr
µs
RSP
Note
Not 100% tested.
gure 26.1 mporary tect Timing Diagram
12
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
m or Eraommand Sequence
CE#
WE#
tRSP
RY/BY#
Document Number: 002-01235 Rev. *B
Page 35 of 46
S29AL004D
Figure 26.2 Sector Protect/Unprotect Timing Diagram
V
V
ID
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
ect/Unprotect
Verify
40h
Data
Sector Protect: 150 µs
Sector Unprotect: 15 ms
CE#
WE#
OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For or unprotect= 1, A1
Table 27. Alte# ConOperation
Parameter
JEDEC Std
Speed Options
Descri
Write Cycle Time (Note 1)
55
70
70
0
90
Unit
t
t
55
90
AVAV
AVEL
ELAX
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
AS
AH
DS
DH
t
t
35
t
t
t
35
45
DVEH
EHDX
t
Data Hold Time
t
Output Enable Setup Time
OES
n
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
0
GHEL
GHEL
t
WE# Setup Time
0
0
WLEL
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
30
20
5
ELEH
CP
t
t
CE# Pulse Width High
Latency Between Read and Write Operations
EHEL
CPH
t
Min
Typ
s
µs
SR/W
Byte
Programming Operation
(Note 2)
t
t
t
t
WHWH1
WHWH1
Word
7
Sector Erase Operation (Note 2)
0.7
sec
WHWH2
WHWH2
Note
1. Not 100% tested.
2. See Erase And Programming Performance on page 37 for more information.
Document Number: 002-01235 Rev. *B
Page 36 of 46
S29AL004D
Figure 27.1 Alternate CE# Controlled Write Operation Timings
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
t
tAS
tAH
tG
tWHWH1 or 2
CE#
Data
CPH
DS
tBU
tDH
DQ7#
DOUT
tRH
for program
for erase
D for progr
0 for se
10 for
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data writtethe device, D
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
= datithe device.
OUT
28. Erase And Programming Performce
Parameter
Sector Erase Time
Typ (Note 1)
Max (Note 2)
nit
Comments
0.7
11
7
10
Excludes 00h programg
prior to erasure
Chip Erase Time
Byte Programming Time
Word Programming Time
210
210
12.5
8.5
µs
µs
s
7
Excludes em level
overheNote 5)
Byte Mode
Word Mode
4.2
2.9
Chip Programming Time
(Note 3)
s
Notes
1. Typical program and erase times assume the following conditions: 25C, V = 3.0 V, 100,000 cycles, checkerboard datern.
CC
2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes proaster than the maximum program
times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 on page 19 for further information
on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector
Document Number: 002-01235 Rev. *B
Page 37 of 46
S29AL004D
Table 29. TSOP, SO, And BGA Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
= 0
Package
TSOP, SO
BGA
Typ
6
Max
7.5
5.0
12
Unit
C
Input Capacitance
V
IN
IN
4.2
8.5
5.4
7.5
3.9
TSOP, SO
BGA
C
Output Capacitance
V
= 0
pF
OUT
OUT
6.5
9
TSOP, SO
BGA
C
Capacitance
V
= 0
IN2
IN
4.7
Notes
1. Sampled, n
2. Test condz.
Document Number: 002-01235 Rev. *B
Page 38 of 46
S29AL004D
30. Physical Dimensions
30.1 TS 048—48-Pin Standard TSOP
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
0.10
5
A2
1
N
REVERSE PIN OUT (TOP VIEW)
3
L B
B
1
N
E
N
2
+1
e
9
A1
N
N
2
+1
2
0.2
2X (N
C
SEATING
PLANE
A
SEE DET
0.08MM (0.0031")
M
C
6
A - B S
b
7
WITH PLATING
c1
)
b1
BASE METAL
SECTION B-B
R
(c)
e/2
GAUGE PLANE
0.250098") C
θ°
PARALLEL TO
SEATING PLANE
C
L
= A OR
DETAIL A
DETL B
NOTES:
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Jedec
MO-142 (D) DD
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLAN
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
c1
c
D
D1
E
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
e
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
0.70
8˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3355 \ 16-038.10c
Note
For reference only. BSC is an ANSI standard for Basic Space Centering.
Document Number: 002-01235 Rev. *B
Page 39 of 46
S29AL004D
30.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm
0.10 (4X)
D1
A
D
6
5
4
3
2
1
7
e
SE
E1
E
H
G
F
E
D
C
B
A
INDEX M
6
B
A1 CORNER
COER
7
fb
SD
f 0.08
f 0.15
M
M
C
EW
C A
B
BOTTOM VIEW
0.10 C
A
SEAG PLANE
SIIEW
A1
OTES:
PACKAGE
JEDEC
VBK 048
N/A
1. DNSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2L DIMENSIONS ARE IN MLIMETERS.
8.15 mm x 6.15 mm NOM
PACKAGE
BALL POSITION DESIGNER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
MAX
1.00 OVERALL THICKNESS
--- BALL HEIGHT
NOTE
4.
e
REPRESENTS TOLDER RID PITCH.
A
A1
A2
D
---
---
5. SYMBOL "MD" IE BALL ROW MSIZE IN THE
"D" DIRECTI
0.18
0.62
SYMBOL "BALL COLUMN MATRZE IN THE
"E" DIRON.
---
0.76 BODY THICKNESS
BODY SIZE
8.15 BSC.
6.15 BSC.
5.60 BSC.
4.00 BSC.
8
N IS TOTAL NUF SOLDER BALLS.
E
BODY SIZE
6
7
NSION "b" IS MEARED AT THE MAXIM
ETER IN A PLANE PARALLEL TO DATU
D1
E1
BALL FOOTPRINT
BALL FOOTPRINT
SE ARE MEASURED WITH RESPTO DATUM
A AND DEFINE THE POSITION HE CENTER
SOLDL IN THE OUTER ROW.
MD
ME
N
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
6
WHEN TS AN ODD NUMBF SOLDER BALLS I
THE OUTEROW PARALLEL TE D OR E DIMENSI
RESPECTIVELY, SD OR SE = 00.
48
fb
0.35
---
0.43 BALL DIAMETER
WHEN THERE IS AN EVEUMBER OF SOLDER S IN
THE OUTER ROW, SD E = e/2
e
0.80 BSC.
0.40 BSC.
---
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CEOF DEPOD
BALLS.
10 A1 CORNER TO BE IDENTIFIED BMFER, LASER OR INK
MARK, METALLIZED MARK INDENOR OTHER MEANS.
3338 \ 16-038.25b
Document Number: 002-01235 Rev. *B
Page 40 of 46
S29AL004D
30.3 SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
Document Number: 002-01235 Rev. *B
Page 41 of 46
S29AL004D
31. Revision Summary
Spansion Publication Number: S29AL004D_00
31.1 Revision A0 (November 12, 2004)
Initial release
31.2 Revbruary 18, 2005)
Added Co
Ordering
Change pm S to
Valid Combination Tab
Package Type, Materialre Rangom Snd SFI to MAL and MFI.
Changed Package DeSOP to SP
Erase and Programming Performnce Te
Changed chip erase time in table.
31.3 Revision A2 (Jun05)
Global
Updated status from Advance Information to Prel
Distinctive Characteristics
Updated High Performance access time to 55 ns.
Product Selector Guide
Added 55 ns speed column.
Ordering Information
Added tube packing type.
Added Extended Temperature range.
Added 55 ns speed option.
Valid Combinations Table
Added two designators to packing types.
Added speed option along with speed option package type nomenclature.
Added Note for this table.
Operating Range
Added extended temperature range information.
Moved Figures 7 and 8 under Operating Range area.
Erase and Programming Performance
Changed Byte Programing Time values for Typical and Maximum.
Document Number: 002-01235 Rev. *B
Page 42 of 46
S29AL004D
31.4 Revision A3 (June 21, 2005)
Global
Update from Preliminary status to full Data Sheet.
Ordering Information
Added two Model Numbers.
Valid Combinat
Updated table bers and Package Types.
31.5 (May 06)
AC Char
Added tSR/W pmeter to regram operations tables. Added back-to-back read/write cycle timing diagram.
Changed maximum value LQZ
.
31.6 Revision ne 22, 206)
Connection Diagrams
Changed inputs on pins 1 and 2 of package.
Read Operations Timings figure
Connected end of tRC period to start of tOH period.
Erase/Program Operations table
Changed tBUSY to a maximum specification.
31.7 Revision A6 (February 27, 2009)
Global
Added obsolescence information to Cover Sheet, Distinctive Chararisticsnd Ordenformation ses of data sheet.
Document Number: 002-01235 Rev. *B
Page 43 of 46
S29AL004D
Document History Page
Document Title:S29AL004D, 4-Mbit (512K x 8-Bit/256K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01235
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
11/12/2004 Initial release
02/18/2005
Added Cover Page
Ordering Information
Change package type from S to M.
Valid Combination Table
Package Type, Material, and Temperature Range from SAL and SFI to
MAL and MFI.
Changed Package Description from SSOP to SOP
rand Programming Performance Table
Chanchip erase time in table.
06/01/2
Globa
Updaed status from Advance Information to Preliminary data sheet.
Distinctive ristics
Updatnce access time to 55 ns.
Prode
lumn.
n
g typ
d Temrature range.
s speeption.
**
-
BWHA
Valid Combinans Table
Added two dignators to packinpes.
Added spoption along witeed option pkage type nomenclature.
Added Notthis table.
Operating Ra
Added extended temature range iformation.
Moved Figures 7 annder Operating Range a.
Erase and Programmierformance
Changed Byte Programine values for Tical and Maxi
06/21/2005
05/22/2006
Global
Update from Preliminary status to full ata Sheet.
Ordering Information
Added two Model Numbers.
Valid Combinations Table
Updated table with new Model Numbers and kage Types.
AC Characteristics
Added tSR/W parameter to read and erase/program perations tables.
Added back-to-back read/write cycle
timing diagram. Changed maximum value for tDF and tFLQZ.
Document Number: 002-01235 Rev. *B
Page 44 of 46
S29AL004D
Document History Page (Continued)
Document Title:S29AL004D, 4-Mbit (512K x 8-Bit/256K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01235
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
06/22/2006
Connection Diagrams
Changed inputs on pins 1 and 2 of SO package.
Read Operations Timings figure
Connected end of tRC period to start of tOH period.
Erase/Program Operations table
Changed tBUSY to a maximum specification.
**
9
Global
Added obsolescence information to Cover Sheet, Distinctive
Characteristics, and Ordering Information
s of data sheet.
*A
*B
5043522
5602312
2/09/201Updao Cypress template
01/25/2Obsoldocument.
Comting Sunset Review.
Document Number: 002-01235 Rev. *B
Page 45 of 46
S29AL004D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
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psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
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Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
© Cypress Semiconductor Corporation, 2004-2017. The information contained herein is subject to change without notice. Cypress Smiconductor Corporaasso responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress productnot warror intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, ss does not aits products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The sion of Cypress procts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license , use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product ed only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code excas specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-01235 Rev. *B
Revised January 25, 2017
Page 46 of 46
Cypress®, Spansion®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress
Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.
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