S29AL008D90BFN022 [CYPRESS]
Flash, 512KX16, 90ns, PBGA48, 8.15 X 6.15 MM, LEAD FREE, FBGA-48;
| 型号： | S29AL008D90BFN022 |
| 厂家： | 
CYPRESS |
| 描述： | Flash, 512KX16, 90ns, PBGA48, 8.15 X 6.15 MM, LEAD FREE, FBGA-48 内存集成电路 |
| 文件： | 总49页 (文件大小：1817K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29AL008D
8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V
Boot Sector Flash
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL008D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantage
Performance Characteristics
Single Power Supply Operation
– 2.7 to 3.6 volt read and write operations for battery-powered
applications
High Performance
– Access times as fast as 55 ns
– Extended temperature range (-40°C to +125°C)
Ultra-low Power Consumption (typical values at 5 MHz)
– 200 nA Automatic Sleep mode current
– 200 nA standby mode curren
Manufactured on 200 nm Process Technology
– Compatible with 0.32 µm and 230 nm Am29LV800 devices
Flexible Sector Architecture
– One 16-Kbyte, two 8-Kbyte, one 32-Kbyte, and fifteen 64-Kbyte
sectors (byte mode)
– 7 mA read current
– 15 mA program/erase current
– One 8 Kword, two 4 Kword, one 16-Kword, and fifteen 32-Kword
sectors (word mode)
Cycling Endurance000,000 cycles per sector typical
Data Retention: 20 years typical
– Reliable operation for the life of the system
– Supports full chip erase
– Sector Protection features:
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
Package Option
48-ball FBGA
48in TSOP
44-pin SO
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Unlock Bypass Program Command
Software Features
Data# Polling and Toggle Bits
– Reduces overall programming time when issuing multiple program
command sequences
– Provides a software method of detecting program or erase
operation completion
Top or Bottom Boot Block Configurations Available
Embedded Algorithms
Erase Suspend/Erase Resume
– Embedded Erase algorithm automatically preprograms and
erases the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically wris and verifies
data at specified addresses
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Compatibility with JEDEC Standards
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
Cypress Semiconductor Corporation
Document Number: 002-01233 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 09, 2015
S29AL008D
General Description
The S29AL008D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in
48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data
(x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply
to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.
This device is manufactured using Spansion’s 200 nm process technology, and offers all the features and benefits of the
Am29LV800B, which was manufactured using 0.32 µm process technology.
The standard device offers access times of 55, 60, 70, and 90 ns, allowing high speed microprocessors to operate without wait
states. To eliminate bus contention the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#)
controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flasor EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and veifies proper cell margin.
The host system can detect whether a program or erase operatiois complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a program erase cycle is completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any
sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the
automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Document Number: 002-01233 Rev. *A
Page 2 of 49
S29AL008D
Contents
1.
2.
3.
Product Selector Guide............................................... 4
16.1 TS 048—48-Pin Standard TSOP.................................. 41
16.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 x 6.15 mm .............................................................42
16.3 SO 044—44-Pin Small Outline Package ...................... 43
Block Diagram.............................................................. 4
Connection Diagrams.................................................. 5
3.1 Special Handling Instructions for FBGA Package.......... 6
17. Revision History.......................................................... 44
17.1 Revision A (September 8, 2004)................................... 44
17.2 Revision A 1 (February 18, 2005)................................. 44
17.3 Revision A2 (June 1, 2005)........................................... 44
17.4 Revision A3 (June 16, 2005)......................................... 45
17.5 Revision A4 (February 16, 2006).................................. 45
17.6 Revision A5 (May 22, 2006).......................................... 45
17.7 Revision A6 (September 6, 2006)................................. 45
17.8 Revision A7 (October 31, 2006).................................... 45
17.9 Revision A8 (August 29, 2007)..................................... 45
17.10Revision A9 (September 19, 2007) .............................. 45
17.11Revision A10 (November 27, 2007) ............................. 46
17.12Revision A11 (bruary 27, 2009)................................ 46
4.
5.
6.
Pin Configuration......................................................... 6
Logic Symbol ............................................................... 7
Ordering Information................................................... 7
6.1 Standard Products ......................................................... 7
7. Device Bus Operations................................................ 8
7.1 Word/Byte Configuration................................................ 9
7.2 Requirements for Reading Array Data........................... 9
7.3 Writing Commands/Command Sequences.................... 9
7.4 Program and Erase Operation Status............................ 9
7.5 Standby Mode................................................................ 9
7.6 Automatic Sleep Mode................................................. 10
7.7 RESET#: Hardware Reset Pin..................................... 10
7.8 Output Disable Mode ................................................... 10
7.9 Autoselect Mode .......................................................... 12
7.10 Sector Protection/Unprotection.................................... 12
7.11 Temporary Sector Unprotect........................................ 13
7.12 Hardware Data Protection............................................ 15
8.
Command Definitions................................................ 15
8.1 Reading Array Data ..................................................... 15
8.2 Reset Command.......................................................... 16
8.3 Autoselect Command Sequence ................................ 16
8.4 Word/Byte Program Command Sequence................... 16
8.5 Unlock Bypass Command Sequence .......................... 16
8.6 Chip Erase Command Sequence ................................ 18
8.7 Sector Erase Command Sequence .......................... 18
8.8 Erase Suspend/Erase Resume Commands ................ 19
9.
Write Operation Status ........................................... 21
9.1 DQ7: Data# Polling ...................................................... 21
9.2 RY/BY#: Ready/Busy#............................................. 22
9.3 DQ6: Toggle Bit I ......................................................... 22
9.4 DQ2: Toggle Bit II ........................................................ 23
9.5 Reading Toggle Bits DQ6/DQ2.................................... 23
9.6 DQ5: Exceeded Timing Limits ..................................... 23
9.7 DQ3: Sector Erase Timer............................................. 24
10. Absolute Maximum Ratings...................................... 25
11. Operating Ranges...................................................... 26
12. DC Characteristics..................................................... 27
12.1 Zero Power Flash......................................................... 28
13. Test Conditions.......................................................... 29
14. Key to Switching Waveforms.................................... 29
15. AC Characteristics..................................................... 30
15.1 Erase/Program Operations .......................................... 33
15.2 Erase and Programming Performance ........................ 39
16. Physical Dimensions................................................. 41
Document Number: 002-01233 Rev. *A
Page 3 of 49
S29AL008D
1. Product Selector Guide
Family Part Number
S29AL008D
Full Voltage Range: V = 2.7 – 3.6 V
60
70
90
CC
Speed Options
Regulated Voltage Range: V = 3.0 – 3.6V
55
55
55
25
CC
Max access time, ns (t
)
60
60
25
70
70
30
90
90
35
ACC
Max CE# access time, ns (t
Max OE# access time, ns (t
)
CE
)
OE
Note
See AC Characteristics on page 30 for full specifications.
2. Block Diagram
DQ0–DQ15 (A-1)
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
WE#
Control
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
CC
Timer
Cell Matrix
X-Decoder
A0–A18
Document Number: 002-01233 Rev. *A
Page 4 of 49
S29AL008D
3. Connection Diagrams
Figure 3.1 Standard TSOP
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
7
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
V
SS
CE#
A0
Fiure 3.2 SO Pinout
RY/BY#
A18
A17
1
2
3
4
5
6
7
8
9
44 RESET#
43 WE#
42 A8
41 A9
A6
A5
A4
A3
A2
A1 10
A0 11
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
CE# 12
V
13
32 V
31 DQ15/A-1
30 DQ7
SS
SS
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 V
CC
Document Number: 002-01233 Rev. *A
Page 5 of 49
S29AL008D
Figure 3.3 Fine-pitch BGA Pinout (Top View, Balls Facing Down)
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
V
SS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
NC
D4
NC
E4
F4
G4
H4
WE#
RESET#
DQ5
DQ12
V
DQ4
CC
A3
B3
NC
C3
D3
NC
E3
F3
G3
H3
RY/BY#
A18
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
V
SS
3.1
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is
exposed to temperatures above 150°C for prologed periods of time.
4. Pin Configuration
I/O Name
A0–A18
DQ0–DQ14
DQ15/A-1
BYTE#
CE#
Description
19 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
Chip enable
OE#
Output enable
WE#
Write enable
RESET#
RY/BY#
Hardware reset pin, active low
Ready/Busy# output
3.0 volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage supply
tolerances)
V
CC
V
Device ground
SS
NC
Pin not connected internally
Document Number: 002-01233 Rev. *A
Page 6 of 49
S29AL008D
5. Logic Symbol
19
A0–A18
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
6. Ordering Information
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL008D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
6.1
Standard Products
Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
S29AL008D
55
T
A
I
RI
0
Packing Type
0
1
2
3
= Tray
= Tube
= 7” Tape and Reel
= 13” Tape and Reel
Model Number
01 = x8/x16, V = 2.7 - 3.6V, top boot sector device
CC
R1 = x8/x16, V = 3.0 - 3.6V. top boot sector device
CC
02 = x8/x16, V = 2.7 - 3.6V, bottom boot sector device
CC
R2 = x8/x16, V = 3.0 - 3.6V. bottom boot sector device
CC
Temperature Range
I
= Industrial (-40°C to +85°C)
= Extended (-40°C to +125°C)
N
Package Material Set
A
F
= Standard
= Pb-Free
Package Type
T
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Small Outline Package (SOP) Standard Pinout
B
M
Speed Option
55 = 55 ns Access Speed
60 = 60 ns Access Speed
70 = 70 ns Access Speed
90 = 90 ns Access Speed
Device Number/Description
S29AL008D
8 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase
Document Number: 002-01233 Rev. *A
Page 7 of 49
S29AL008D
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
S29AL008D Valid Combinations
Package Type,
Speed
Option
Material, and
Temperature Range
Model
Number
Device Number
Packing Type
Package Description
55
60, 70, 90
55
TAI, TFI
TAI, TFI, TAN, TFN
BAI, BFI
R1, R2
01, 02
R1, R2
01, 02
R1, R2
01, 02
0, 3 (Note 1)
TS048 (Note 3)
VBK048 (Note 4)
SO044 (Note 3)
TSOP
Fine-Pitch
BGA
S29AL008D
0, 2, 3 (Note 1)
0, 1, 3 (Note 2)
60, 70, 90
55
BAI, BFI, BAN, BFN
MAI, MFI
SOP
60, 70, 90
MAI, MFI, MAN, MFN
Notes
1. Type 0 is standard. Specify other options as required.
2. Type 1 is standard. Specify other options as required.
3. TSOP and SOP package markings omit packing type designator from ordering part number.
4. BGA package marking omits leading S29 and packing type designator from ordering part number.
7. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command
register. The command register itself does not occupy any addressable memory location. The register is composed of latches that
store the commands, along with the address and data information needeto execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus
operations, the inputs and control levels they require, and the resultg output. The following subsections describe each of these
operations in further detail.
S29AL008D Device Bus Operations
DQ8–DQ15
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
BYTE#
= V
Operation
CE#
L
OE# WE# RESET#
= V
IH
IL
Read
Write
L
H
L
H
H
A
A
D
D
OUT
IN
IN
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
L
H
D
D
IN
IN
V
0.3 V
V
0.3 V
CC
CC
Standby
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
V
D
X
X
X
ID
IN
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
V
V
D
D
X
ID
ID
IN
IN
Temporary Sector Unprotect
X
X
A
D
High-Z
IN
IN
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
V
= 12.0 0.5 V
ID
X = Don’t Care
A
= Address In
= Data In
IN
D
D
IN
= Data Out
OUT
Notes
1. Addresses are A18:A0 in word mode (BYTE# = V ), A18:A-1 in byte mode (BYTE# = V ).
IH
IL
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/Unprotection on page 12.
Document Number: 002-01233 Rev. *A
Page 8 of 49
S29AL008D
7.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is
set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by
CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
7.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inpus produce valid data on the
device data outputs. The device remains enabled for read access until the command register contents are altered.
See Reading Array Data on page 15 for more information. Refer to Table , Read Operations n page 30 for timing specifications and
to Figure 15.1 on page 30 for the timing diagram. ICC1 in DC Characteristics on page 27 presents the active current specification
for reading array data.
7.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the deve accepts program data in bytes or words. Refer to Word/Byte
Configuration on page 9 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,
only two write cycles are required to program a word or bte, instead of four. The Word/Byte Program Command Sequence
on page 16 contains details on programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 10 and Table on page 11 indicate
the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The
Command Definitions on page 15 contains details on erasing a sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to the Auoselect Mode on page 12 and Autoselect Command Sequence on page 16 for more information.
ICC2 in DC Characteristics on page 27 represents the active current specification for the write mode. The AC Characteristics
on page 30 contains timing specification tables and timing diagrams for write operations.
7.4
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0.
Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 21 for more information, and
to AC Characteristics on page 30 for timing diagrams.
7.5
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device is in the standby mode,
Document Number: 002-01233 Rev. *A
Page 9 of 49
S29AL008D
but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
In DC Characteristics on page 27, ICC3 and ICC4 represents the standby current specification.
7.6
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. ICC5 in DC Characteristics on page 27 represents the automatic sleep mode current specification.
7.7
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for
at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept anher command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held t VSS±0.3 V, the device draws CMOS standby
current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RYY# pin remains a 0 (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is assertewhen a program or erase operation is not executing (RY/BY# pin is
1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Refer to AC Characteristics on page 30 for RESET# parameters and to Figure 15.2 on page 31 for the timing diagram.
7.8
Output Disable Mode
When the OE# input is at VIH, output frm the device is disabled. The output pins are placed in the high impedance state.
S29AL008D Top Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector Size
(Kbytes/
Kwords)
(x8)
(x16)
Address Range
Sector
SA0
A18
0
A17
0
A16
0
A15
0
A14
X
A13
X
A12
X
Address Range
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
SA1
0
0
0
1
X
X
X
SA2
0
0
1
0
X
X
X
SA3
0
0
1
1
X
X
X
SA4
0
1
0
0
X
X
X
SA5
0
1
0
1
X
X
X
SA6
0
1
1
0
X
X
X
SA7
0
1
1
1
X
X
X
SA8
1
0
0
0
X
X
X
SA9
1
0
0
1
X
X
X
SA10
SA11
SA12
1
0
1
0
X
X
X
1
0
1
1
X
X
X
1
1
0
0
X
X
X
Document Number: 002-01233 Rev. *A
Page 10 of 49
S29AL008D
S29AL008D Top Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x8)
(x16)
Sector
SA13
SA14
SA15
SA16
SA17
SA18
A18
1
A17
1
A16
0
A15
1
A14
X
A13
X
A12
X
Kwords)
Address Range
Address Range
64/32
64/32
32/16
8/4
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–F7FFFh
F8000h–F9FFFh
FA000h–FBFFFh
FC000h–FFFFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7BFFFh
7C000h–7CFFFh
7D000h–7DFFFh
7E000h–7FFFFh
1
1
1
0
X
X
X
1
1
1
1
0
X
X
1
1
1
1
1
0
0
1
1
1
1
1
0
1
8/4
1
1
1
1
1
1
X
16/8
Note
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration on page 9.
S29AL008D Bottom Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x8)
(x16)
Sector
SA0
A18
0
A17
0
A16
0
A15
0
A14
0
A13
0
A12
X
0
Kwords)
Address Range
Address Range
16/8
8/4
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–FFFFFh
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
SA1
0
0
0
0
0
1
SA2
0
0
0
0
0
1
1
8/4
SA3
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
4/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
0
0
1
0
SA6
0
0
1
1
SA7
0
1
0
0
SA8
0
1
0
1
SA9
0
1
1
0
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration on page 9.
Document Number: 002-01233 Rev. *A
Page 11 of 49
S29AL008D
7.9
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes
output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1,
and A0 must be as shown in Table . In addition, when verifying sector protection, the sector address must appear on the appropriate
highest order address bits (see Table on page 10 and Table on page 11). Table shows the remaining address bits that are don’t
care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on
DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown
in Table on page 20. This method does not require VID. See Command Definitions on page 15 for details on using the autoselect
mode.
S29AL008D Autoselect Codes (High Voltage Method)
A11
to
DQ8
to
DQ7
to
A18
to
A8
to
A5
to
A3
Description
Mode
CE#
L
OE#
WE#
H
A12
A10
A9
A7
A6
A4
A
A1
A0
DQ15
DQ0
Manufacturer ID: Spansion
L
L
X
X
X
V
X
L
X
L
L
L
X
01h
ID
Device ID:
S29AL008D
(Top Boot Block)
Word
Byte
L
H
22h
DAh
X
V
X
L
L
X
L
L
L
H
H
ID
L
L
L
L
L
L
H
H
H
X
22h
X
DAh
5Bh
Device ID:
S29AL008D
(Bottom Boot Block)
Word
Byte
X
X
X
V
V
X
X
X
X
L
L
ID
ID
5Bh
X
01h (protected)
Sector Protection Verification
L
L
H
SA
L
H
L
00h
(unprotected)
X
Legend
L = Logic Low = V
IL
H = Logic High = V
IH
SA = Sector Address
X = Don’t care.
7.10 Sector ProtectionUnprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection
feature re-enables both program ad erase operations in previously protected sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory
prior to shipping the device through Spansion’s ExpressFlash™ Service. Contact an Spansion representative for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 12 for details.
Sector Protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment.
Figure 7.2 on page 14 shows the algorithms and Figure 15.12 on page 37 shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector
unprotect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is
compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Publication number 20536 contains
further details; contact an Spansion representative to request a copy.
Document Number: 002-01233 Rev. *A
Page 12 of 49
S29AL008D
7.11 Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is
activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting
the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again.
Figure 7.1 shows the algorithm, and Figure 15.11 on page 37 shows the timing diagrams, for this feature.
Figure 7.1 Temporary Sector Unprotect Operation
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Document Number: 002-01233 Rev. *A
Page 13 of 49
S29AL008D
Figure 7.2 In-System Sector Protect/Sector Unprotect Algorithms
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 ms
Wait 1 ms
unprotect address
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sector
protected
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Sup first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Document Number: 002-01233 Rev. *A
Page 14 of 49
S29AL008D
7.12 Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to Table on page 20 for command definitions). In addition, the following hardware data protection measures prevent
accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
7.12.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is greater than VLKO
.
7.12.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
7.12.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
7.12.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to reading array data on power-up.
8. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table on page 20
defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper
sequence resets the device to reading array data.
All addresses are latched on the falling edge of E# or CE#, whichever happens later. All data is latched on the rising edge of WE#
or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics on page 30.
8.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device
is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.
After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 19 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect
mode. See Reset Command on page 16.
See also Requirements for Reading Array Data on page 9 for more information. Table , Read Operations on page 30 provides the
read parameters, and Figure 15.1 on page 30 shows the timing diagram.
Document Number: 002-01233 Rev. *A
Page 15 of 49
S29AL008D
8.2
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins.
This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also
applies during Erase Suspend).
8.3
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer d devices codes, and determine whether
or not a sector is protected. Table on page 20 shows the address and data requirementsThis method is an alternative to that
shown in Table on page 12, which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then
enters the autoselect mode, and the system may read at any address any number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode)
returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode)
returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table on page 10 and Table on page 11 for valid sector
addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
8.4
Word/Byte Program Command Sequence
The system may program the device by word oyte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is
not required to provide further controls or timings. The device automatically provides internally generated program pulses and
verifies the programmed cell margin. Table on page 20 shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer
latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status
on page 21 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. The program command sequence should be reinitiated once the device resets to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1.
Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
8.5
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the
Document Number: 002-01233 Rev. *A
Page 16 of 49
S29AL008D
unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. Table shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Table 8.1 illustrates the algorithm for the program operation. See Erase/Program Operations on page 33 for parameters, and
Figure 15.5 on page 33 for timing diagrams.
Figure 8.1 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note
See Table on page 20 for program command sequence.
Document Number: 002-01233 Rev. *A
Page 17 of 49
S29AL008D
8.6
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations. Table on page 20 shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip
erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device
returns to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status
on page 21 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Figure 8.2 on page 19 illustrates the algorithm for the erase operation. See Erase/Program Operaons on page 33 for parameters,
and Figure 15.6 on page 34 for timing diagrams.
8.7
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector
erase command. Table on page 20 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically
programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector
addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs,
otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system
need not monitor DQ3. Any command other tn Sector Erase or Erase Suspend during the time-out period resets the
device to reading array data. The system must rewrite the command sequence and any additional sector addresses and
commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer on page 24.) The
time-out begins from the rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. Note that a
hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence
should be reinitiated once the device returns to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status
on page 21 for information on these status bits.
Figure 8.2 on page 19 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 33 for
parameters, and to Figure 15.6 on page 34 for timing diagrams.
Document Number: 002-01233 Rev. *A
Page 18 of 49
S29AL008D
8.8
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,
any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend
the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure.
(The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 21 for
information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within non-suspended
sectors. The system can determine the status of the program operation using the DQ7 Q6 status bits, just as in the standard
program operation. See Write Operation Status on page 21 for more information.
The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows
reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 16 for more information.
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the
sector erase operation. Further writes of the Resume command are nored. Another Erase Suspend command can be written after
the device resumes erasing.
Figure 8.2 Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes
1. See Table on page 20 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 24 for more information.
Document Number: 002-01233 Rev. *A
Page 19 of 49
S29AL008D
S29AL008D Command Definitions
Bus Cycles (Notes 2-5)
Third Fourth
Addr
Command
First
Addr
Second
Fifth
Addr
Sixth
Sequence
(Note 1)
Data
RD
F0
Addr
Data
Data
Addr
Data
Data
Addr
Data
Read (Note 6)
Reset (Note 7)
1
RA
XXX
555
AAA
555
AAA
555
AAA
1
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
555
AAA
555
Manufacturer ID
4
AA
AA
AA
55
55
55
90
90
90
X00
01
X01
X02
X01
X02
22DA
DA
Device ID,
Top Boot Block
4
4
AAA
555
225B
5B
Device ID,
Bottom Boot Block
AAA
XX0
XX01
00
(SA)
X02
Word
Byte
555
2AA
555
555
Sector Protect Verify
(Note 9)
4
AA
55
55
90
(S
X
AAA
AAA
01
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
PA
555
AAA
555
Program
4
3
AA
AA
A0
20
PA
PD
Unlock Bypass
55
AAA
XXX
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
(F0)
XXX
XXX
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
Sector Erase
SA
AAA
XXX
XXX
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
Legend
X = Don’t care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation, and
PA = Address of the memory location to be pogrammed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.
Notes
1. See Table on page 8 for a description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence on page 16 for more information.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.
13. The Erase Resume command is valid only during the Erase Suspend mode.
Document Number: 002-01233 Rev. *A
Page 20 of 49
S29AL008D
9. Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table
on page 25 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
9.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether
the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if
the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This inalogous to the complement/true datum
output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectothat are protected.
When the system detects DQ7 changes from the complement to trudata, it can read valid data at DQ7–DQ0 on the following read
cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figure 15.8,
Data# Polling Timings (During Embedded Algorithms) on pag35, illustrates this.
Table on page 25 shows the outputs for Data# Polling on DQ7. Figure 9.1 on page 22 shows the Data# Polling algorithm.
Document Number: 002-01233 Rev. *A
Page 21 of 49
S29AL008D
Figure 9.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 beuse DQ7 may change simultaneously with DQ5.
9.2
RY/BY#: ReadyBusy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC
.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.
Table on page 25 shows the outputs for RY/BY#. Figure 15.1 on page 30, Figure 15.2 on page 31, Figure 15.5 on page 33 and
Figure 15.6 on page 34 shows RY/BY# for read, reset, program, and erase operations, respectively.
9.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse
in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.
Document Number: 002-01233 Rev. *A
Page 22 of 49
S29AL008D
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 21).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is
written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
Table on page 25 shows the outputs for Toggle Bit I on DQ6. Figure 9.2 on page 24 shows the toggle bit algorithm. Figure 15.9
on page 36 shows the toggle bit timing diagrams. Figure 15.10 on page 36 shows the differences between DQ2 and DQ6 in
graphical form. See also DQ2: Toggle Bit II on page 23.
9.4
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is vely erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The system may use either
OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table on page 25 to compare
outputs for DQ2 and DQ6.
Figure 9.2 on page 24 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 23 explains the algorithm.
See also DQ6: Toggle Bit I on page 22. Figure 15.9 on page 36 hows the toggle bit timing diagram. Figure 15.10 on page 36 shows
the differences between DQ2 and DQ6 in graphical form.
9.5
Reading Toggle Bits DQ6/DQ2
Refer to Figure 9.2 on page 24 for the following iscussion. Whenever the system initially begins reading toggle bit status, it must
read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the
value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7–
DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 23). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device successfully completed the program or erase operation. If it is still toggling, the device did not completed the
operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 9.2 on page 24).
9.6
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation exceeds
the timing limits, DQ5 produces a 1.
Document Number: 002-01233 Rev. *A
Page 23 of 49
S29AL008D
Under both these conditions, the system must issue the reset command to return the device to reading array data.
9.7
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation started.
(The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands is always less than 50 µs. See also Sector Erase Command Sequence on page 18.
Figure 9.2 Toggle Bit Algorithm
START
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
o
Toggle Bit
= Toggle?
Ye
No
DQ5 = 1?
Yes
(Notes
1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle
started; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device
accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command
might not be accepted. Table shows the outputs for DQ3.
Document Number: 002-01233 Rev. *A
Page 24 of 49
S29AL008D
Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing Limits on page 23 for
more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
10. Absolute Maximum Ratings
Parameter
Rating
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
–65C to +150C
–65C to +125C
–0.5 V to +4.0 V
–0.5 V to +12.5 V
Voltage with Respect to Ground V (Note 1)
CC
A9, OE#, and RESET# (Note 2)
All other pins (Note 1)
–0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3)
200 mA
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot V to –2.0 V for periods of up to 20 ns. See
SS
Figure 11.1 on page 26. Maximum DC voltage on input or I/O pins is V +0.5 V. During voltage transitions, input or I/O pins may overshoot to V +2.0 V for periods
C
CC
up to 20 ns. See Figure 11.2 on page 26.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot V to –2.0 V for periods of up
SS
to 20 ns. See Figure 11.1 on page 26. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those ndicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affdevice reliability.
Document Number: 002-01233 Rev. *A
Page 25 of 49
S29AL008D
11. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA)
-40°C to +85°C
Extended (N) Devices
Ambient Temperature (TA)
-40°C to +125°C
V
Supply Voltages
CC
VCC for regulated voltage range+3.0 V to +3.6 V
VCC for full voltage range +2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed
Figure 11.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 11.2 Maximum ositive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
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S29AL008D
12. DC Characteristics
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
Unit
V
V
,
CC
IN
SS
I
Input Load Current
1.0
µA
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
V
= V
; A9 = 12.5 V
35
1.0
30
16
4
µA
µA
LIT
CC
CC max
I
= V to V , V = V
SS CC CC CC max
LO
OUT
10 MHz
15
9
CE# = V OE#
IL,
Byte Mode
V
=
IH,
5 MHz
1 MHz
10 MHz
5 MHz
1 MHz
2
V
Active Read Current
CC
I
mA
mA
CC1
CC2
(Notes 1, 2)
15
9
30
16
4
CE# = V OE#
IL,
Word Mode
V
V
=
=
IH,
IH
2
V
Active Write Current
CC
I
CE# = V OE#
20
35
IL,
(Notes 2, 3, 6)
I
I
V
V
Standby Current (Notes 2, 4)
CE#, RESET# = V 0.3 V
0.2
0.
5
5
µA
µA
CC3
CC
CC
CC
Reset Current (Notes 2, 4)
RESET# = V 0.3 V
CC4
SS
Automatic Sleep Mode
(Notes 2, 4, 5)
V
V
= V 0.3 V;
IH
IL
CC
I
0.2
5
µA
CC5
= V 0.3 V
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
0.7 x V
V
+ 0.3
CC
IH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
V
V
= –2.0 mA, V = V
CC CC mi
2.4
OH1
OH2
LKO
Output High Voltage
= –100 µA, V = V
V
–0.4
CC
CC n
CC
Low V Lock-Out Voltage
2.3
2.5
V
CC
Notes
1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.
CC
IH
CC
2. Maximum I specifications are tested with V = V .
CCmax
CC
CC
3.
I
active while Embedded Erase or Embedded Program in progress.
CC
4. At extended temperature range (>+85°C), typical current is 5µA and maximum current is 10µA.
5. Automatic sleep mode enables the low power modwhen addresses remain stable for t
6. Not 100% tested.
+ 30 ns.
ACC
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S29AL008D
12.1 Zero Power Flash
Figure 12.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note
Addresses are switching at 1 MHz
Figure 12.2 Typical ICC1 vs. Frequency
10
8
3.6 V
6
2.7 V
4
2
0
1
2
3
4
5
Frequency in MHz
Note
T = 25 C
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S29AL008D
13. Test Conditions
Figure 13.1 Test Setup
3.3 V
2.7 k
Device
Under
Test
C
6.2 k
L
Note
Nodes are IN3064 or equivalent.
Test Specifications
Test Condition
55
60
70
90
Unit
Output Load
1 TTL gate
30
Output Load Capacitance, C
(including jig capacitance)
L
30
30
100
pF
ns
Input Rise and Fall Times
Input Pulse Levels
5
0.0 or V
CC
Input timing measurement reference levels
Output timing measurement reference levels
0.5 V
V
CC
CC
0.5 V
14. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
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Page 29 of 49
S29AL008D
Figure 14.1 Input Waveforms and Measurement Levels
V
CC
0.5 V
0.5 V
CC
Input
Measurement Level
Output
CC
0.0 V
15. AC Characteristics
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
55
60
70
90
Unit
t
t
Read Cycle Time (Note 1)
Min
55
60
70
90
90
AVAV
RC
CE# = V
OE# = V
IL
IL
t
t
Address to Output Delay
Max
55
60
70
AVQV
ACC
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
55
25
60
70
30
90
35
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Latency Between Read and Write Operations
16
16
20
0
DF
DF
ns
t
t
t
SR/W
Read
Min
Output Enable
Hold Time (Note 1)
t
OEH
Toggle and
Data# Polling
Min
Min
10
0
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
t
t
OH
AXQX
Notes
1. Not 100% tested.
2. See Figure 13.1 on page 29 and DC Characteristics on page 27 for test specifictions.
Figure 15.1 Read Operations Timings
t
RC
Addresses Stable
Addresses
CE#
t
ACC
t
DF
t
OE
OE#
t
SW
t
OEH
WE#
t
CE
t
OH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
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Page 30 of 49
S29AL008D
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
t
t
20
µs
READY
Max
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
500
READY
ns
t
RESET# Pulse Width
500
50
20
0
RP
t
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
Min
t
µs
ns
RPD
t
RB
Note
Not 100% tested.
Figure 15.2 RESET# Timings
RY/BY#
CE#, OE#
RESET#
t
RH
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
RESET#
t
RP
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S29AL008D
Word/Byte Configuration (BYTE#)
Parameter
Speed Options
JEDEC
Std
Description
55
60
70
90
Unit
t
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
5
ELFL/ ELFH
t
16
ns
FLQZ
t
55
60
70
90
FHQV
Figure 15.3 BYTE# Timings for Read Operations
CE#
OE#
BYTE#
tELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
Switching
from word
to byte
DQ0–DQ14
DQ15/A-1
mode
Address
Input
DQ15
Outpu
tFLQ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
Address
Input
DQ15
Output
tFHQV
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S29AL008D
Figure 15.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note
Refer to Erase/Program Operations on page 33 for t and t specifications.
AS
AH
15.1 Erase/Program Operations
Parameter
Speed Opti
JEDEC
Std
Description
Write Cycle Time (Note 1)
55
60
70
90
Unit
t
t
55
60
70
90
AVAV
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
0
AVWL
WLAX
AS
AH
DS
DH
t
t
45
t
t
t
35
35
35
45
DVWH
WHDX
t
Data Hold Time
0
0
t
Output Enable Setup Time
OES
ns
Min
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
0
GHWL
GHWL
t
t
CE# Setup Time
0
0
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
CE# Hold Time
t
t
Write Pulse Width
35
30
20
7
t
t
Write Pulse Width High
Latency Between Read and Write Operations
WPH
t
ns
µs
SR/W
Byte
Word
t
t
t
t
Programming Operation Note 2)
WHWH1
WHWH1
Typ
7
Sector Erase Operion (Note 2)
0.7
50
0
sec
µs
WHWH2
WHWH2
t
V
Setup Time (Note 1)
CC
Min
Min
Max
VCS
t
Recovery Time from RY/BY#
RB
ns
t
Program/Erase Valid to RY/BY# Delay
90
BUSY
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 39 for more information.
Figure 15.5 Program Operation Timings
Notes
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode
Document Number: 002-01233 Rev. *A
Page 33 of 49
S29AL008D
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
t
t
AS
PA
WC
Addresses
555h
PA
PA
t
AH
CE#
OE#
t
CH
t
WHWH1
t
WP
WE#
t
WPH
t
CS
t
DS
A0h
t
D
PD
Status
D
Data
OUT
t
t
BUSY
RB
RY/BY#
V
CC
t
VCS
Figure 15.6 Chip/Sector Ease Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
t
t
AS
SA
WC
Addresses
CE#
2AAh
VA
VA
555h for chip erase
t
AH
t
C
OE#
t
WP
WE#
t
t
WPH
WHWH2
t
CS
t
DS
t
DH
In
Data
Complete
30h
55h
Progress
10 for Chip Erase
t
t
RB
BUSY
RY/BY#
t
VCS
V
CC
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 21).
2. Illustration shows device in word mode.
Document Number: 002-01233 Rev. *A
Page 34 of 49
S29AL008D
Figure 15.7 Back to Back Read/Write Cycle Timing
t
t
WC
RC
Addresses
CE#
PA
RA
PA
PA
t
t
ACC
t
AH
t
CPH
CE
t
CP
t
OE
t
OE#
WE#
t
SR/W
GHWL
t
WP
t
t
DF
t
WDH
DS
t
OH
t
DH
Data
Valid In
Valid Out
Valid In
Valid Out
Figure 15.8 Data# Polling Timings (During Embedded Algorithms)
t
RC
Addresses
CE#
VA
VA
VA
t
ACC
t
CE
t
CH
t
OE
OE#
WE#
t
t
OEH
DF
t
OH
High Z
High Z
DQ7
Valid Data
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Status Data
t
BUS
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Document Number: 002-01233 Rev. *A
Page 35 of 49
S29AL008D
Figure 15.9 Toggle Bit Timings (During Embedded Algorithms)
t
RC
Addresses
CE#
VA
VA
VA
VA
t
ACC
t
CE
t
CH
t
OE
OE#
WE#
t
t
OEH
DF
t
OH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
t
BUS
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last sts read cycle, and array data read cycle.
Figure 15.10 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
spend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
t
V
Rise and Fall Time (See Note)
ID
Min
Min
500
ns
VIDR
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note
Not 100% tested.
Document Number: 002-01233 Rev. *A
Page 36 of 49
S29AL008D
Figure 15.11 Temporary Sector Unprotect Timing Diagram
12 V
RESET#
0 or 3 V
0 or 3 V
t
t
VIDR
VIDR
Program or Erase Command Sequence
CE#
WE#
t
RSP
RY/BY#
Figure 15.12 Sector Protect/Unprotect Timing Diagram
V
V
ID
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Sector Protect/Unprote
Verify
40h
Data
60h
60h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Document Number: 002-01233 Rev. *A
Page 37 of 49
S29AL008D
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
Write Cycle Time (Note 1)
55
60
70
90
Unit
t
t
55
60
70
90
AVAV
AVEL
ELAX
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
0
AS
AH
DS
DH
t
t
45
t
t
35
35
35
45
DVEH
EHDX
t
t
Data Hold Time
0
0
t
Output Enable Setup Time
OES
Min
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
0
GHEL
GHEL
t
WE# Setup Time
0
0
WLEL
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
30
20
7
ELEH
EHEL
CP
t
t
CE# Pulse Width High
Latency Between Read and Write Operations
CPH
t
ns
µs
SR/W
Byte
Word
Programming Operation
(Note 2)
t
t
t
t
WHWH1
WHWH1
WHWH2
Typ
7
Sector Erase Operation (Note 2)
0.7
sec
WHWH2
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 39 for more information.
Document Number: 002-01233 Rev. *A
Page 38 of 49
S29AL008D
Figure 15.13 Alternate CE# Controlled Write Operation Timings
555 for program PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
t
t
WC
AS
t
AH
t
WH
WE#
OE#
t
GHEL
t
WHWH1 or 2
t
t
CP
CE#
t
WS
CPH
DS
t
BUSY
t
t
DH
DOUT
DQ7#
Data
t
RH
A0 for program PD for program
55 for erase
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
2. Figure indicates the last two bus cycles of command seqce.
3. Word mode address used as an example.
= data written to the device.
OUT
15.2 Erase and Programming Performance
Parameter
Sector Erase Time
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
0.7
14
7
10
Excludes 00h programming
prior to erasure
Chip Erase Time
s
Byte Programming Time
Word Programming Time
210
210
25
µs
µs
s
7
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
8.4
5.8
Chip Programming Time
(Note 3)
17
s
Notes
1. Typical program and erase times assume the following conditions: 25C, 3.0 V V , 1,000,000 cycles. Additionally, programming typicals assume checkerboard
CC
pattern.
2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 20 for further information on
command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
Document Number: 002-01233 Rev. *A
Page 39 of 49
S29AL008D
Latchup Characteristics
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
SS
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Note
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
TSOP, SO, and BGA Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
= 0
Package
Typ
6
Max
7.5
5.0
12
Unit
TSOP, SO
BGA
C
Input Capacitance
Output Capacitance
Control Pin Capacitance
V
IN
IN
4.2
8.5
5.4
3.9
TSOP, SO
BGA
C
V
= 0
OUT
pF
OUT
6.5
9
TSOP, SO
BGA
C
V
= 0
IN2
IN
4.7
Notes
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
Document Number: 002-01233 Rev. *A
Page 40 of 49
S29AL008D
16. Physical Dimensions
16.1 TS 048—48-Pin Standard TSOP
NOTES:
PACKAGE
TS/TSR 48
JEDEC
MO-142 (B) DD
1. ONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1982)
SYMBOL
MIN
---
NOM
---
MAX
1.20
0.15
1.05
0.23
0.27
0.16
0.21
20.20
18.50
12.10
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
0.05
0.95
0.17
0.17
0.10
0.10
19.80
18.30
11.90
---
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
1.00
0.20
0.22
---
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTUSION IS 0.15mm (.0059") PER SIDE.
c1
c
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR
PROTUSION SHALL BE 0.08mm (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT
LEAD TO BE 0.07mm (0.0028").
---
D
20.00
18.40
12.00
0.50 BASIC
0.60
---
D1
E
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm (.0039") AND 0.25mm (0.0098") FROM THE LEAD TIP.
e
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM
THE SEATING PLANE.
L
0.50
0˚
0.70
8
Θ
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
R
0.08
---
0.20
N
48
3641 \ 16-038.10 \ 7.10.7
Note
For reference only. BSC is an ANSI standard for Basic Space Centering.
Document Number: 002-01233 Rev. *A
Page 41 of 49
S29AL008D
16.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm
0.10 (4X)
D1
A
D
6
5
4
3
2
1
7
e
SE
E1
E
H
G
F
E
D
C
B
A
INDEX MARK
10
6
B
A1 CORNER
PIN A1
CORNER
7
fb
SD
f 0.08 M C
f 0.15 M C A B
TOP VIEW
BOTTVIEW
0.10 C
0.08 C
A2
A
SEATING PLANE
SIDE VIEW
C
A1
NOTES:
PACKAGE
JEDEC
VBK 048
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
6.15 mm x 8.15 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
---
NOM
MAX
1.00 OVERALL THICKNESS
--- BALL HEIGHT
NOTE
4.
e
REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
---
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.18
0.62
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
0.76 BODY CKNESS
BODY SIZE
8.15 BSC.
6.15 BSC.
5.60 BSC.
4.00 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
ODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
MD
ME
N
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
6
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
48
fb
0.35
---
0.43 BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
---
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25b
Document Number: 002-01233 Rev. *A
Page 42 of 49
S29AL008D
16.3 SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
Document Number: 002-01233 Rev. *A
Page 43 of 49
S29AL008D
17. Revision History
Spansion Publication Number: S29AL008D_00
17.1 Revision A (September 8, 2004)
Initial release
17.2 Revision A 1 (February 18, 2005)
Global
Updated Trademark
Ordering Information
Added Package type designator
Valid Combinations
Changed Package Type, Material, and Temperature Range designator
Under Package Descriptions, change SSOP to SOP
17.3 Revision A2 (June 1, 2005)
Global
Updated status from Advance Information to Preliminary data sheet
Distinctive Characteristics
Updated manufactured process technology. Updated high performance access time. Added extended temperature range. Added
cycling endurance information.
Production Selector Guide
Added 55 ns speed option and column.
Ordering Information
Added tube and tray packing types. Added extended temperature range Added model numbers.
Valid Combinations Table
Added speed option. Added packing types. Added model number. Added note for this table.
Operating Range
Added extended temperature range information.
Test Conditions
Added 55ns speed option.
AC Characteristics
Read Operation Table: Added 55ns speed option.
Word/Byte Configuration Table: Added 55 ns speed option.
Erase/Program Operation Table: Added 55ns speed option.
Alternate CE# Controlled Erase/Program Operation Table: Added 55 ns speed option.
Erase and Programming Performance: Changed Byte Programing Time values for Typical and Maximum.
Document Number: 002-01233 Rev. *A
Page 44 of 49
S29AL008D
17.4 Revision A3 (June 16, 2005)
Changed from Preliminary to full Data Sheet. Updated Valid Combinations table.
17.5 Revision A4 (February 16, 2006)
Corrected minor typo on page 1. Added cover page.
17.6 Revision A5 (May 22, 2006)
AC Characteristics
Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram.
Changed maximum value for tDF and tFLQZ
.
17.7 Revision A6 (September 6, 2006)
Global
Added 60 ns speed option.
17.8 Revision A7 (October 31, 2006)
Automatic Sleep Mode
Changed ICC4 to ICC5 in description.
AC Characteristics, Erase / Program Operations
Changed tBUSY to a maximum value.
17.9 Revision A8 (August 29, 2007)
TS048 Physical dimensions
Changed Revision from AA to E: changed degrees (max) from 5 to 8
17.10 Revision A9 (September 19, 2007)
Product Selector Guide
Changed TOE for 55ns access speed
Autoselect Codes Table
Changed part references to AL008D
Added A3 to A2 column
Command Definitions Table
Added F0 as an alternative 2nd cycle command for Unlock Bypass Reset
Test Specifications Table
Added CL = 30 pF under 60 ns access speed
Changed Input Pulse Levels, Input and Output timing measurement reference levels
Erase/Program Operations Table
Changed value of Programming Operation for Byte mode
Document Number: 002-01233 Rev. *A
Page 45 of 49
S29AL008D
Alternate CE# Controlled Erase/Program Operations Table
Changed values of Program Operation for both Byte & Word modes
Changed value of Sector Erase Operation
17.11 Revision A10 (November 27, 2007)
Figure: Input Waveforms and Measurement Levels
Updated figure
17.12 Revision A11 (February 27, 2009)
Global
Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information sections of data sheet.
Document History Page
Document Title:S29AL008D 8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01233
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
**
-
BWHA
09/08/2004 Initial release
02/18/2005
Global:
Updated Tradeark
Ordering Information
Added Package type designator
Valid Combinations
Changed Package Type, Material, and Temperature Range designator
Under Package Descriptions, change SSOP to SOP
Document Number: 002-01233 Rev. *A
Page 46 of 49
S29AL008D
Document History Page (Continued)
Document Title:S29AL008D 8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01233
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
06/01/2005
Global
Updated status from Advance Information to Preliminary data sheet.
Distinctive Characteristics
Updated manufactured process technology. Updated high performance
access time. Added extended
temperature range. Added cycling endurance information.
Production Selector Guide
Added 55 ns speed option and column.
Ordering Information
Added tube and tray packing types. Added extended temperature range
Added model numbers.
Valid Combinations Table
Added speed option. Added packing types. Added model number. Added
note for this table.
**
-
BWHA
Operating Range
Added extended temperature range information.
Test Conditions
Added 55ns speed option.AC Characteristics
Read Operation Table: Added 55ns speed option.
Word/Byte Cnfiguration Table: Added 55 ns speed option.
Erase/Progam Operation Table: Added 55ns speed option.
Alternate CE# Controlled Erase/Program Operation Table: Added 55 ns
speed option.
Erase and Programming Performance: Changed Byte Programing Time val-
ues for Typical and Maximum.
06/16/20Changed from Preliminary to full Data Sheet. Updated Valid Combinations
table.
2/16/2006 Corrected minor typo on page 1. Added cover page.
05/22/2006
AC Characteristics
Added tSR/W parameter to read and erase/program operations tables.
Added back-to-back read/write cycle
timing diagram. Changed maximum value for tDF and tFLQZ.
09/06/2006
10/31/2006
Global
Added 60 ns speed option.
**
-
BWHA
Automatic Sleep Mode
Changed ICC4 to ICC5 in description.
AC Characteristics, Erase / Program Operations
Changed tBUSY to a maximum value.
08/29/2007
TS048 Physical dimensions
Changed Revision from AA to E: changed degrees (max) from 5 to 8
Document Number: 002-01233 Rev. *A
Page 47 of 49
S29AL008D
Document History Page (Continued)
Document Title:S29AL008D 8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01233
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
BWHA
BWHA
Date
09/19/2007
Product Selector Guide
Changed TOE for 55ns access speed
Autoselect Codes Table
Changed part references to AL008D
Added A3 to A2 column
Command Definitions Table
Added F0 as an alternative 2nd cycle command for Unlock Bypass Reset
Test Specifications Table
Added CL = 30 pF under 60 ns access speed
Changed Input Pulse Levels, Input and Output timing measurement
reference levels
Erase/Program Operations Table
Changed value of Programming Operation for Byte mode
Alternate CE# Controlled Erase/Program Operations Table
**
-
Changed values of Program Operation for both Byte & Word modes
Changed value of Sector Erase Operation
11/27/2007
02/27/2009
Figure: Input Waveforms and Measurement Levels
Updated figure
Global
Added obsolescence information to Cover Sheet, Distinctive
Characteristics, and Ordering Information
sections of data sheet.
*A
5043511
12/09/2015 Updated to cypress template.
Document Number: 002-01233 Rev. *A
Page 48 of 49
S29AL008D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-01233 Rev. *A
Revised December 09, 2015
Page 49 of 49
Cypress®, Spansion®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress
Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.
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