S29GL01GP11FAIV23 [CYPRESS]
Flash, 64MX16, 110ns, PBGA64,;
| 型号： | S29GL01GP11FAIV23 |
| 厂家： | 
CYPRESS |
| 描述： | Flash, 64MX16, 110ns, PBGA64, |
| 文件： | 总76页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29GLxxxP MirrorBitTM Flash Fam ily
S29GL01GP, S29GL512P, S29GL256P
1 Gigabit, 512 Megabit, and 256 Megabit,
3.0 Volt-only Page Mode Flash Mem ory featuring
90 nm MirrorBit process technology
ADVANCE
INFORMATIO N
Datasheet
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
Single power supply operation
High performance
— 3 volt read, erase, and program operations
— 100 ns access time (S29GL256P, S29GL512P,
S29GL01GP)
— 8-word/16-byte page read buffer
— 25 ns page read times
Enhanced VersatileI/O™ control
— All input levels (address, control, and DQ input levels)
and outputs are determined by voltage on V input.
IO
— 32-word/64-byte write buffer reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V,
5 MHz)
— 25 mA typical active read current;
— 50 mA typical erase/program current
— 1 µA typical standby mode current
V
range is 1.65 to V
IO
CC
Manufactured on 90 nm MirrorBit process
technology
SecSi™ (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
Package options
— 56-pin TSOP
— 64-ball Fortified BGA
— Can be programmed and locked at the factory or by
the customer
Flexible sector architecture
— S29GL01GP: One thousand twenty-four 64 Kword
(128 Kbyte) sectors
Software & Hardware Features
Software features
— Program Suspend and Resume: read other sectors
before programming operation is completed
— Erase Suspend and Resume: read/program other
sectors before an erase operation is completed
— Data# polling and toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
— S29GL512P: Five hundred twelve 64 Kword
(128 Kbyte) sectors
— S29GL256P: Two hundred fifty-six 64 Kword
(128 Kbyte) sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
100,000 erase cycles per sector typical
20-year data retention typical
Hardware features
— Advanced Sector Protection
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
Publication Num ber S29GLxxxP_00 Revision A Am endm ent 0 Issue Date October 29, 2004
This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC
reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e I n f o r m a t i o n
General Description
The S29GL01G/512/256P family of devices are 3.0V single power flash memory
manufactured using 90 nm MirrorBit technology. The S29GL01GP is a 1 Gb, or-
ganized as 67,108,864 words or 134,217,728 bytes. The S29GL512P is a 512
Mbit, organized as 33,554,432 words or 67,108,864 bytes. The S29GL256P is a
256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The devices have
a 16-bit wide data bus that can also function as an 8-bit wide data bus by using
the BYTE# input. The device can be programmed either in the host system or in
standard EPROM programmers.
Access times as fast as 100 ns (S29GL01GP, S29GL512P, S29GL256P) are avail-
able. Note that each access time has a specific operating voltage range (VCC) and
an I/O voltage range (VIO), as specified in “Product Selector Guide” on page 6
and the “Ordering Information” on page 12. The devices are offered in a 56-pin
TSOP or 64-ball Fortified BGA package. Each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a VCC input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times through increased cur-
rent. This feature is intended to facilitate factory throughput during system
production, but can also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the device using
standard microprocessor write timing. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
The Enhanced VersatileI/O™ (VIO) control allows the host system to set the volt-
age levels that the device generates and tolerates on all input levels (address, chip
control, and DQ input levels) to the same voltage level that is asserted on the VIO pin.
This allows the device to operate in a 1.8 V or 3 V system environment as required.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. Persistent Sector
Protection provides in-system, command-enabled protection of any combina-
tion of sectors using a single power supply at VCC. Password Sector Protection
prevents unauthorized write and erase operations in any combination of sectors
through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin can be
tied to the system reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The SecSi™ (Secured Silicon) Sector provides a 128-word/256-byte area for
code or data that can be permanently protected. Once this sector is protected,
no further changes within the sector can occur.
The Write Protect (WP#/ACC) feature protects the first or last sector by as-
serting a logic low on the WP# pin.
MirrorBit flash technology combines years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via hot-hole
assisted erase. The data is programmed using hot electron injection.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
3
A d v a n c e I n f o r m a t i o n
Table of Contents
Table 8. Device Geometry Definition .....................................29
Table 9. Primary Vendor-Specific Extended Query ..................30
Com m and Definitions . . . . . . . . . . . . . . . . . . . . . . 30
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
S29GL01GP ..............................................................................................................6
S29GL512P ...............................................................................................................6
S29GL256P ..............................................................................................................6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagram s . . . . . . . . . . . . . . . . . . . . . . .8
Special Package Handling Instructions ............................................................9
Logic Sym bols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
S29GL01GP ........................................................................................................ 11
S29GL512P .......................................................................................................... 11
S29GL256P ......................................................................................................... 11
O rdering Inform ation . . . . . . . . . . . . . . . . . . . . . . . 12
Device Bus O perations . . . . . . . . . . . . . . . . . . . . . . 13
Table 1. Device Bus Operations ........................................... 13
Word/Byte Configuration .................................................................................13
VersatileIOTM (VIO) Control ............................................................................. 14
Requirements for Reading Array Data ......................................................... 14
Page Mode Read .............................................................................................. 14
Writing Commands/Command Sequences ................................................. 14
Write Buffer ......................................................................................................15
Accelerated Program Operation ................................................................15
Autoselect Functions ......................................................................................15
Standby Mode ........................................................................................................15
Automatic Sleep Mode ...................................................................................... 16
RESET#: Hardware Reset Pin ......................................................................... 16
Output Disable Mode ........................................................................................ 16
Table 2. Sector Address Table, S29GL01GP, S29GL512P,
S29GL256P ...................................................................... 17
Autoselect Mode .................................................................................................17
Table 3. Autoselect Codes, (High Voltage Method) ................. 18
Sector Protection ................................................................................................ 18
Persistent Sector Protection ....................................................................... 18
Password Sector Protection ........................................................................ 18
WP# Hardware Protection ......................................................................... 18
Selecting a Sector Protection Mode ......................................................... 19
Advanced Sector Protection ........................................................................... 19
Lock Register ........................................................................................................ 19
Table 4. Lock Register ........................................................ 20
Persistent Sector Protection .......................................................................... 20
Dynamic Protection Bit (DYB) .................................................................. 20
Persistent Protection Bit (PPB) .................................................................. 21
Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 22
Table 5. Sector Protection Schemes ..................................... 22
Persistent Protection Mode Lock Bit ...........................................................23
Password Sector Protection ............................................................................23
Password and Password Protection Mode Lock Bit ................................23
64-bit Password .................................................................................................. 24
Persistent Protection Bit Lock (PPB Lock Bit) .......................................... 24
SecSi (Secured Silicon) Sector Flash Memory Region ..............................25
Write Protect (WP#) ....................................................................................... 26
Hardware Data Protection ............................................................................. 26
Low VCC Write Inhibit ................................................................................27
Write Pulse “Glitch” Protection ................................................................27
Logical Inhibit ...................................................................................................27
Power-Up Write Inhibit ................................................................................27
Reading Array Data ............................................................................................ 31
Reset Command .................................................................................................. 31
Autoselect Command Sequence ................................................................... 32
Enter SecSi Sector/Exit SecSi Sector Command Sequence ................... 32
Word Program Command Sequence .......................................................... 32
Unlock Bypass Command Sequence .........................................................33
Write Buffer Programming ......................................................................... 34
Accelerated Program .....................................................................................35
Figure 1. Write Buffer Programming Operation....................... 36
Figure 2. Program Operation ............................................... 37
Program Suspend/Program Resume Command Sequence .....................37
Figure 3. Program Suspend/Program Resume........................ 38
Chip Erase Command Sequence ................................................................... 38
Sector Erase Command Sequence ................................................................ 39
Figure 4. Erase Operation ................................................... 40
Erase Suspend/Erase Resume Commands ..................................................40
Lock Register Command Set Definitions .....................................................41
Password Protection Command Set Definitions .......................................41
Non-Volatile Sector Protection Command Set Definitions .................. 43
Global Volatile Sector Protection Freeze Command Set ......................44
Volatile Sector Protection Command Set ..................................................44
SecSi Sector Entry Command ......................................................................... 45
SecSi Sector Exit Command ........................................................................... 45
Command Definitions ........................................................................................46
Table 10. S29GL01GP, S29GL512P, S29GL256P Command Defini-
tions, x16 .........................................................................46
Table 11. S29GL01GP, S29GL512P, S29GL256P Command Defini-
tions, x8 ...........................................................................49
Write Operation Status ................................................................................... 52
DQ7: Data# Polling ........................................................................................... 52
Figure 5. Data# Polling Algorithm ........................................ 53
RY/BY#: Ready/Busy# ........................................................................................53
DQ6: Toggle Bit I ............................................................................................... 54
Figure 6. Toggle Bit Algorithm ............................................. 55
DQ2: Toggle Bit II .............................................................................................. 55
Reading Toggle Bits DQ6/DQ2 ..................................................................... 56
DQ5: Exceeded Timing Limits ........................................................................ 56
DQ3: Sector Erase Timer ................................................................................ 57
DQ1: Write-to-Buffer Abort ........................................................................... 57
Table 12. Write Operation Status .........................................58
Figure 7. Maximum Negative Overshoot Waveform................. 59
Figure 8. Maximum Positive
Overshoot Waveform.......................................................... 59
O perating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 9. Test Setup........................................................... 61
Table 13. Test Specifications ...............................................61
Key to Switching W aveform s . . . . . . . . . . . . . . . . 61
Figure 10. Input Waveforms and
Measurement Levels........................................................... 61
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62
Read-Only Operations-S29GL01GP, S29GL512P, S29GL256P ..............62
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 11. Read Operation Timings....................................... 63
Figure 12. Page Read Timings.............................................. 63
Hardware Reset (RESET#) ..............................................................................64
Com m on Flash Mem ory Interface (CFI) . . . . . . 27
Table 6. CFI Query Identification String ................................ 28
Table 7. System Interface String ......................................... 28
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Figure 13. Reset Timings..................................................... 64
Erase and Program Operations-S29GL01GP, S29GL512P, S29GL256P 65
Figure 14. Program Operation Timings .................................. 66
Figure 15. Accelerated Program Timing Diagram .................... 66
Figure 16. Chip/Sector Erase Operation Timings..................... 67
Figure 17. Data# Polling Timings (During Embedded Algorithms) .
68
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 69
Figure 19. DQ2 vs. DQ6. ..................................................... 69
Alternate CE# Controlled Erase and Program Operations-S29GL01GP,
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.............................................................. 71
Erase And Program m ing Perform ance . . . . . . . . 72
TSO P Pin and BGA Package Capacitance . . . . . 72
Physical Dim ensions . . . . . . . . . . . . . . . . . . . . . . . 73
TS056—56-Pin Standard Thin Small Outline Package (TSOP) ..............73
LAA064—64-Ball Fortified Ball Grid Array (FBGA) ............................... 74
Revision Sum m ary . . . . . . . . . . . . . . . . . . . . . . . . . 75
S29GL512P, S29GL256N ................................................................................... 70
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
5
A d v a n c e I n f o r m a t i o n
Product Selector Guide
S29GL01GP
Part Number
S29GL01GP
V
V
= 2.7–3.6 V
10
11
IO
Speed
VCC = 2.7–3.6 V
Option
= 1.65–1.95 V
11
110
110
30
IO
Max. Access Time (ns)
100
100
25
110
110
25
Max. CE# Access Time (ns)
Max. Page access time (ns)
Max. OE# Access Time (ns)
25
25
30
S29GL512P
Part Number
S29GL512P
11
V
= 2.7–3.6 V
10
IO
Speed
Option
VCC = 2.7–3.6 V
V
= 1.65–1.95 V
11
110
110
30
IO
Max. Access Time (ns)
100
100
25
110
110
25
Max. CE# Access Time (ns)
Max. Page access time (ns)
Max. OE# Access Time (ns)
25
25
30
S29GL256P
Part Number
S29GL256P
11
V
= 2.7–3.6 V
10
IO
Speed
Option
VCC = 2.7–3.6 V
V
= 1.65–1.95 V
11
110
110
30
IO
Max. Access Time (ns)
Max. CE# Access Time (ns)
100
100
25
110
110
25
Max. Page access time (tPACC
)
Max. OE# Access Time (ns)
25
25
30
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
V
V
CC
Sector Switches
SS
V
IO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A
**–A0
Max
** A
GL01GP=A25, A
GL512P = A24, A
GL256P = A23
Max
Max
Max
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
7
A d v a n c e I n f o r m a t i o n
Connection Diagram s
56-Pin Standard TSOP
NC for S29GL256P,
NC for S29G512P
and S29G256P
A23
A22
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
56 A24
55 A25
54 A16
53 BYTE#
52 VSS
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A21 15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
A6 21
A5 22
A4 23
A3 24
A2 25
32 CE#
31 A0
A1 26
NC 27
30 NC
NC 28
29 VIO
8
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Connection Diagram s
64-ball Fortified BGA
Top View, Balls Facing Down
A8
NC
B8
C8
D8
E8
F8
G8
H8
NC
A22
A23
VIO
VSS
A241
A252
A7
B7
C7
D7
E7
F7
G7
H7
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
NC
B1
NC
C1
NC
D1
NC
E1
F1
G1
NC
H1
NC
NC
VIO
Notes:
1. Ball F8 is NC on S29GL256P
2. Ball G8 is NC on S29GL256P and S29GL512P
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA). The package and/or data integrity can be compromised if the pack-
age body is exposed to temperatures above 150°C for prolonged periods of time.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
9
A d v a n c e I n f o r m a t i o n
PIN DESCRIPTIO N
A25-A0
A24–A0
A23–A0
DQ14–DQ0
DQ15/A-1
=
=
=
=
=
26 Address inputs (1 Gb)
25 Address inputs (512 Mb)
24 Address inputs (256 Mb)
15 Data inputs/outputs
DQ15 (Data input/output, word mode),
A-1 (LSB Address input, byte mode)
Chip Enable input
Output Enable input
Write Enable input
Hardware Write Protect input;
Acceleration input
CE#
OE#
WE#
WP#/ACC
=
=
=
=
RESET#
BYTE#
RY/BY#
VCC
=
=
=
=
Hardware Reset Pin input
Selects 8-bit or 16-bit mode
Ready/Busy output
3.0 volt-only single power supply
(see “Product Selector Guide” for speed options and
voltage supply tolerances)
Output Buffer power
VIO
VSS
NC
=
=
=
Device Ground
Pin Not Connected Internally
10
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
LOGIC SYMBOLS
S29GL01GP
26
A25–A0
16 or 8
DQ15–DQ0
CE#
(A-1)
OE#
WE#
WP#/ACC
RESET#
VIO
RY/BY#
BYTE#
S29GL512P
25
A24–A0
16 or 8
DQ15–DQ0
CE#
(A-1)
OE#
WE#
WP#/ACC
RESET#
VIO
RY/BY#
BYTE#
S29GL256P
24
A23–A0
16 or 8
DQ15–DQ0
CE#
(A-1)
OE#
WE#
WP#/ACC
RESET#
VIO
RY/BY#
BYTE#
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
11
A d v a n c e I n f o r m a t i o n
O rdering Inform ation
The ordering part number is formed by a valid combination of the following:
S29GL01GP
S29GL512P
S29GL256P
10
F
A
I
01
0
PACKING TYPE
0
2
3
=
=
=
Tray (standard; see note 1)
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER (V range, protection when WP# =V )
IO
IL
01 = V
02 = V
V1 = V
= V
= V
= 2.7 to 3.6 V, highest address sector protected
= 2.7 to 3.6 V, lowest address sector protected
IO
IO
IO
CC
CC
= 1.65 to 1.95 V, V = 2.7 to 3.6 V, highest address sector
CC
protected
V2 = V
= 1.65 to 1.95 V, V = 2.7 to 3.6 V, lowest address sector
IO
CC
protected
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85 C)
°
PACKAGE MATERIALS SET
A
F
=
=
Standard
Pb-free
PACKAGE TYPE
T
F
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fortified Ball Grid Array, 1.0 mm pitch package
SPEED OPTION
10
11
=
=
100 ns
110 ns
DEVICE NUMBER/DESCRIPTION
S29GL01GP, S29GL512P, S29GL256P
3.0 Volt-only, 1024, 512, 256 Megabit (32 M x 16-Bit/64 M x 8-Bit) Page-Mode Flash Memory
Manufactured on 90 nm MirrorBitTM process technology
S29GLxxxP Valid Combinations
Package &
1 Gb, 512 Mb, 256 Mb
Speed (ns)
Temperature
Model Number
Pack Type
Package Description
S29GL01GP,
S29GL512P,
S29GL256P
10, 11
01, 02
TS056 (TSOP, Note 2)
LAA064 (Fortified BGA, Note 3)
TAI, TFI
FAI, FFI
0,2, 3 (Note 1)
11
V1, V2
Notes:
1. Type 0 is standard. Specify other options as required; TSOPs can be packed in Types 0 and 3; BGA can be packed in Types
0, 2, 3.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from ordering part number.
4. Contact local sales representative for availability.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
12
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Device Bus O perations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus O perations
DQ8–DQ15
WP#/ Addresses DQ0–
BYTE#
= VIH
BYTE#
= VIL
Operation
CE#
OE# WE#
RESET#
ACC
(Note 1)
DQ7
Read
L
L
L
L
H
L
H
H
H
X
Note 2
VHH
H
AIN
AIN
AIN
X
DOUT
DOUT
DQ8–DQ14
Write (Program/Erase)
Accelerated Program
Standby
H
H
X
H
X
(Note 3) (Note 3) = High-Z,
DQ15 = A-1
L
(Note 3) (Note 3)
VCC
±
0.3 V
X
H
X
VCC
±
0.3 V
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
X
X
L
X
X
Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5 V, V = 11.5–12.5V, X = Don’t Care, SA = Sector
IL
IH
ID
HH
Address, A = Address In, D = Data In, D = Data Out
IN
IN
OUT
Notes:
1. Addresses are AMax:A0 in word mode; A
:A-1 in byte mode. Sector addresses are A
:A16 in both modes.
Max
Max
2. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector is protected
or unprotected as determined by the method described in “Write Protect (WP#).” All sectors are unprotected
when shipped from the factory (The SecSi Sector can be factory protected depending on version ordered.)
3. D or D
as required by command sequence, data polling, or sector protect algorithm (see Figure 2 Figure 3, and
OUT
IN
Figure 4).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic “1,” the device is in word con-
figuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic “0” the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data
I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
13
A d v a n c e I n f o r m a t i o n
VersatileIOTM (V ) Control
IO
The VersatileIOTM (VIO) control allows the host system to set the voltage levels
that the device generates and tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See Ordering Information for VIO options on this
device.
For example, a VI/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels,
driving and receiving signals to and from other 1.8 or 3 V devices on the same
data bus.
Requirem ents for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the “Read-Only Opera-
tions-S29GL01GP, S29GL512P, S29GL256P table for timing specifications and to
Figure 11 for the timing diagram. Refer to the DC Characteristics table for the ac-
tive current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 8 words/16 bytes.
The appropriate page is selected by the higher address bits A(max)–A3. Address
bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is de-asserted and reasserted
for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
W riting Com m ands/Com m and Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four.“Word Program
Command Sequence” on page 32 has details on programming data to the device
using both standard and Unlock Bypass command sequences.
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 2, Table 3, and Table 4 indicate the address space that each sector
occupies.
Refer to the DC Characteristics table for the active current specification for the
write mode. “AC Characteristics” starting on page 64 contains timing specification
tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 32 words/
64 bytes in one programming operation. This results in faster effective program-
ming time than the standard programming algorithms.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the afore-
mentioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Removing VHH from the WP#/
ACC pin returns the device to normal operation.
Note: The WP#/ACC pin must not be at VHH for operations other than accelerated
programming, or device damage can result. WP# has an internal pullup; when
unconnected, WP# is at VIH
.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to “ Autoselect Mode” on page 17 and “Au-
toselect Command Sequence” on page 32 for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in
the standby mode. In this mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device
is in the standby mode, but the standby current is greater. The device requires
standard access time (tCE) for read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
Refer to “DC Characteristics” on page 60 for the standby current specification.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
15
A d v a n c e I n f o r m a t i o n
Autom atic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device
automatically enables this mode when addresses remain stable for tACC + 30 ns.
The automatic sleep mode is independent of the CE#, WE#, and OE# control sig-
nals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the
system. Refer to “DC Characteristics” on page 60 for the automatic sleep mode cur-
rent specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin can be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 13
for the timing diagram.
O utput Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
are placed in the high impedance state.
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Table 2. Sector Address Table, S29GL01GP, S29GL512P, S29GL256P
S29GL01GP Sector and Memory Address Map
Uniform
Sector Size
Sector
Count
Sector
Range
Address Range
(16-bit)
Notes
SA00
:
0000000h - 000FFFFh
Sector Starting Address
128 MB
1024
:
SA1023
3FF0000H - 3FFFFFFh
Sector Ending Address
S29GL512P Sector and Memory Address Map
Uniform
Sector Size
Sector
Count
Sector
Range
Address Range
(16-bit)
Notes
SA00
:
0000000h - 000FFFFh
Sector Starting Address
64 MB
512
:
SA511
1FF0000H - 1FFFFFFh
Sector Ending Address
S29GL256P Sector and Memory Address Map
Uniform
Sector Size
Sector
Count
Sector
Range
Address Range
(16-bit)
Notes
SA00
:
0000000h - 000FFFFh
Sector Starting Address
32 MB
256
:
SA255
0FF0000H - 0FFFFFFh
Sector Ending Address
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
group protection verification, through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a
device to be programmed with its corresponding programming algorithm. How-
ever, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID on ad-
dress pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 3.
In addition, when verifying sector protection, the sector address must appear on
the appropriate highest order address bits (see Table 2). Table 3 shows the re-
maining address bits that are don’t care. When all necessary bits have been set
as required, the programming equipment can then read the corresponding iden-
tifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table 10 and Table 11. This
method does not require VID. Refer to the “Autoselect Command Sequence” on
page 32 for more information.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
17
A d v a n c e I n f o r m a t i o n
Ta ble 3. Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
A22 A14
to to
A8
to
A5
to
A3
to
A2
WE
#
BYTE#= BYTE#
Description
CE# OE#
A15 A10 A9 A7 A6 A4
A1
A0
VIH
= VIL
DQ7 to DQ0
Manufacturer ID:
L
L
H
X
X
X
X
VID
X
X
L
X
X
L
L
L
00
X
01h
Spansion Product
Cycle 1
Cycle 2
Cycle 3
Cycle 1
Cycle 2
Cycle 3
Cycle 1
Cycle 2
Cycle 3
L
H
H
L
L
H
H
L
H
L
22
22
22
22
22
22
22
22
22
X
X
X
X
X
X
X
X
X
7Eh
28h
01h
7Eh
23h
01h
7Eh
22h
01h
L
L
H
VID
L
H
H
L
L
L
L
L
H
H
X
X
X
X
VID
X
X
L
L
X
X
H
H
L
H
H
L
H
H
L
VID
H
H
H
H
H
Sector Group
Protection Verification
01h (protected),
00h (unprotected)
L
L
L
L
H
H
SA
X
X
X
VID
X
X
L
L
X
X
L
H
L
X
X
SecSi Sector Indicator
Bit (DQ7), WP#
protects highest
address sector
99h (factory locked),
19h (not factory locked)
VID
L
H
H
X
X
SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
89h (factory locked),
09h (not factory locked)
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
address sector
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection
The device features several levels of sector protection, which can disable both the
program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled pro-
tection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted.
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost
sectors.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The cus-
tomer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method is used. If the customer decides to continue using
the Persistent Sector Protection method, they must set the Persistent Sector
Protection Mode Locking Bit. This permanently sets the part to operate only
using Persistent Sector Protection. If the customer decides to use the password
method, they must set the Password Mode Locking Bit. This permanently sets
the part to operate only using password sector protection.
It is important to remember that setting either the Persistent Sector Protec-
tion Mode Locking Bit or the Password Mode Locking Bit permanently
selects the protection mode. It is not possible to switch between the two methods
once a locking bit has been set. It is important that one mode is explicitly
selected when the device is first programmed, rather than relying on the
default mode alone. This is so that it is not possible for a system program or
virus to later set the Password Mode Locking Bit, which would cause an unex-
pected shift from the default Persistent Sector Protection Mode into the Password
Protection Mode.
The device is shipped with all sectors unprotected. The factory offers the option
of programming and protecting sectors at the factory prior to shipping the device
through the ExpressFlash™ Service. Contact your sales representative for details.
It is possible to determine whether a sector is protected or unprotected.
See “Autoselect Command Sequence” on page 32 for details.
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can
disable both the program and erase operations in certain sectors.
Persistent Sector Protection is a method that replaces the old 12V controlled
protection method.
Password Sector Protection is a highly sophisticated protection method that
requires a password before changes to certain sectors are permitted.
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0
bits of the Lock Register are programmable by the user. Users are not allowed to
program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user
tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device
aborts the Lock Register back to the default 11 state. The programming time of
the Lock Register is same as the typical word programming time without utilizing
the Write Buffer of the device. During a Lock Register programming sequence ex-
ecution, the DQ6 Toggle Bit I toggles until the programming of the Lock Register
has completed to indicate programming status. All Lock Register bits are readable
to allow users to verify Lock Register statuses.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
19
A d v a n c e I n f o r m a t i o n
The Customer SecSi Sector Protection Bit is DQ0, Persistent Protection Mode Lock
Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are accessible by all
users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and must be
1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the Lock Reg-
ister. The user is not required to program DQ2, DQ1 and DQ0 bits of the Lock
Register at the same time. This allows users to lock the SecSi Sector and then set
the device either permanently into Password Protection Mode or Persistent Pro-
tection Mode and then lock the SEcSi Sector at separate instances and time
frames.
SecSi Sector Protection allows the user to lock the SecSi Sector area
Persistent Protection Mode Lock Bit allows the user to set the device
permanently to operate in the Persistent Protection Mode
Password Protection Mode Lock Bit allows the user to set the device
permanently to operate in the Password Protection Mode
Table 4. Lock Register
DQ15-3
DQ2
DQ1
DQ0
Password Protection Persistent Protection
SecSi Sector
Protection Bit
Don’t Care
Mode Lock Bit Mode Lock Bit
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protec-
tion method while at the same time enhancing flexibility by providing three
different sector protection states:
Dynamically Locked-The sector is protected and can be changed by a
simple command
Persistently Locked-A sector is protected and cannot be changed
Unlocked-The sector is unprotected and can be changed by a simple
command
In order to achieve these states, three types of “bits” are going to be used:
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYB bits are in the “unprotected state.” Each DYB is in-
dividually modifiable through the DYB Set Command and DYB Clear Command.
When the parts are first shipped, all of the Persistent Protect Bits (PPB) are
cleared into the unprotected state. The DYB bits and PPB Lock bit are defaulted
to power up in the cleared state or unprotected state - meaning the all PPB bits
are changeable.
The Protection State for each sector is determined by the logical OR of the PPB
and the DYB related to that sector. For the sectors that have the PPB bits cleared,
the DYB bits control whether or not the sector is protected or unprotected. By is-
suing the DYB Set and DYB Clear command sequences, the DYB bits are
protected or unprotected, thus placing each sector in the protected or unpro-
tected state. These are the so-called Dynamic Locked or Unlocked states. They
are called dynamic states because it is very easy to switch back and forth be-
tween the protected and un-protected conditions. This allows software to easily
protect sectors against inadvertent changes yet does not prevent the easy re-
moval of protection when changes are needed.
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
The DYB bits can be set or cleared as often as needed. The PPB bits allow for a
more static, and difficult to change, level of protection. The PPB bits retain their
state across power cycles because they are Non-Volatile. Individual PPB bits are
set with a program command but must all be cleared as a group through an erase
command.
The PPB Lock Bit adds an additional level of protection. Once all PPB bits are pro-
grammed to the desired settings, the PPB Lock Bit can be set to the “freeze state.”
Setting the PPB Lock Bit to the “freeze state” disables all program and erase com-
mands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the PPB bits
into their current state. The only way to clear the PPB Lock Bit to the “unfreeze
state” is to go through a power cycle, or hardware reset. The Software Reset
command does not clear the PPB Lock Bit to the “unfreeze state.” System boot
code can determine if any changes to the PPB bits are needed (for example: to
allow new system code to be downloaded). If no changes are needed then the
boot code can set the PPB Lock Bit to disable any further changes to the PPB bits
during system operation.
The WP# write protect pin adds a final level of hardware protection. When this
pin is low it is not possible to change the contents of the WP# protected sectors.
These sectors generally hold system boot code. So, the WP# pin can prevent any
changes to the boot code that could override the choices made while setting up
sector protection during system initialization.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprotected.
If there is a need to protect some of them, a simple DYB Set command sequence
is all that is necessary. The DYB Set and DYB Clear commands for the dynamic
sectors switch the DYB bits to signify protected and unprotected, respectively. If
there is a need to change the status of the persistently locked sectors, a few more
steps are required. First, the PPB Lock Bit must be disabled to the “unfreeze
state” by either putting the device through a power-cycle, or hardware reset. The
PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock
Bit once again to the “freeze state” locks the PPB bits, and the device operates
normally again.
Note: To achieve the best protection, it is recommended to execute the PPB Lock
Bit Set command early in the boot code, and protect the boot code by holding
WP# = VIL.
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB
is programmed to the protected state through the “PPB Program” command, that
sector is protected from program or erase operations are read-only. If a PPB re-
quires erasure, all of the sector PPB bits must first be erased in parallel through
the “All PPB Erase” command. The “All PPB Erase” command preprograms all PPB
bits prior to PPB erasing. All PPB bits erase in parallel, unlike programming where
individual PPB bits are programmable. The PPB bits have the same endurance as
the flash memory.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
21
A d v a n c e I n f o r m a t i o n
Programming the PPB bit requires the typical word programming time without uti-
lizing the Write Buffer. During a PPB bit programming and A11 PPB bit erasing
sequence execution, the DQ6 Toggle Bit I toggles until the programming of the
PPB bit or erasing of all PPB bits has completed to indicate programming and
erasing status. Erasing all of the PPB bits at once requires typical sector erase
time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit outputs
a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all
PPB bits has completed, the DQ3 Sector Erase Timer bit outputs a 0 to indicate
that all PPB bits have been erased. Reading the PPB Status bit requires the initial
access time of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. When set to the “freeze state,” the PPB bits cannot be
changed. When cleared to the “unfreeze state,” the PPB bits are changeable.
There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the “un-
freeze state” after power-up or hardware reset. There is no command sequence
to unlock or “unfreeze” the PPB Lock Bit.
Configuring the PPB Lock Bit to the freeze state requires approximately 100 ns.
Reading the PPB Lock Status bit requires the initial access time of the device.
Table 5. Sector Protection Schem es
Protection States
Sector State
DYB Bit
PPB Bit
PPB Lock Bit
Unfreeze
Freeze
Unprotect Unprotect
Unprotect Unprotect
Unprotected – PPB and DYB are changeable
Unprotected – PPB not changeable, DYB is changeable
Protected – PPB and DYB are changeable
Unprotect
Unprotect
Protect
Protect
Protect
Unfreeze
Freeze
Protected – PPB not changeable, DYB is changeable
Protected – PPB and DYB are changeable
Unprotect
Unprotect
Protect
Unfreeze
Freeze
Protect
Protected – PPB not changeable, DYB is changeable
Protected – PPB and DYB are changeable
Protect
Unfreeze
Freeze
Protect
Protect
Protected – PPB not changeable, DYB is changeable
Table 5 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock
Bit relating to the status of the sector. In summary, if the PPB bit is set, and the
PPB Lock Bit is set, the sector is protected and the protection cannot be removed
until the next power cycle or hardware reset clears the PPB Lock Bit to “unfreeze
state.” If the PPB bit is cleared, the sector can be dynamically locked or unlocked.
The DYB bit then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected sec-
tor enables status polling for approximately 1 µs before the device returns to read
mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling for approximately 50 µs
after which the device returns to read mode without having erased the protected
sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sec-
tor can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock
Status Read commands to the device.
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S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
The Autoselect Sector Protection Verification outputs the OR function of the DYB
bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit
is a 1, the sector is either protected by DYB or PPB or both. When the OR function
of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB
and PPB.
Persistent Protection Mode Lock Bit
Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit
exists to guarantee that the device remain in software sector protection. Once
programmed, the Persistent Protection Mode Lock Bit prevents programming of
the Password Protection Mode Lock Bit. This guarantees that a hacker could not
place the device in Password Protection Mode. The Password Protection Mode
Lock Bit resides in the “Lock Register State.”
Password Sector Protection
The Password Sector Protection method allows an even higher level of security than
the Persistent Sector Protection method. There are two main differences between
the Persistent Sector Protection and the Password Sector Protection methods:
When the device is first powered on, or comes out of a reset cycle, the PPB
Lock Bit is set to the locked state, or the freeze state, rather than cleared to
the unlocked state, or the unfreeze state.
The only means to clear and unfreeze the PPB Lock Bit is by writing a unique
64-bit Password to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
he password is stored in a one-time programmable (OTP) region outside of the
flash memory. Once the Password Protection Mode Lock Bit is set, the password
is permanently set with no means to read, program, or erase it. The password is
used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must
be written to the flash, along with a password. The flash device internally com-
pares the given password with the pre-programmed password. If they match, the
PPB Lock Bit is cleared to the “unfreezed state,” and the PPB bits can be altered.
If they do not match, the flash device does nothing. There is a built-in 2 µs delay
for each “password check” after the valid 64-bit password has been entered for
the PPB Lock Bit to be cleared to the “unfreezed state.” This delay is intended to
thwart any efforts to run a program that tries all possible combinations in order
to crack the password.
Password and Password Protection Mode Lock Bit
n order to select the Password Sector Protection method, the customer must first
program the password. The factory recommends that the password be somehow
correlated to the unique Electronic Serial Number (ESN) of the particular flash de-
vice. Each ESN is different for every flash device; therefore each password should
be different for every flash device. While programming in the password region,
the customer may perform Password Read operations. Once the desired pass-
word is programmed in, the customer must then set the Password Protection
Mode Lock Bit. This operation achieves two objectives:
October 29, 2004 S29GLxxxP_00A0
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A d v a n c e I n f o r m a t i o n
1. It permanently sets the device to operate using the Password Protection
Mode. It is not possible to reverse this function.
2. It also disables all further commands to the password region. All program,
and read operations are ignored.
Both of these objectives are important, and if not carefully considered, can lead
to unrecoverable errors. The user must be sure that the Password Sector Protec-
tion method is desired when programming the Password Protection Mode Lock
Bit. More importantly, the user must be sure that the password is correct when
the Password Protection Mode Lock Bit is programmed. Due to the fact that read
operations are disabled, there is no means to read what the password is after-
wards. If the password is lost after programming the Password Protection Mode
Lock Bit, there is no way to clear and unfreeze the PPB Lock Bit. The Pass-word
Protection Mode Lock Bit, once programmed, prevents reading the 64-bit pass-
word on the DQ bus and further password programming. The Password Protection
Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is pro-
grammed, the Persistent Protection Mode Lock Bit is disabled from programming,
guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through
the use of the Password Program and Password Read commands. The password
function works in conjunction with the Password Protection Mode Lock Bit, which
when programmed, prevents the Password Read command from reading the con-
tents of the password on the pins of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the
Password Protection Mode Lock Bit after power-up reset. If the Password Protec-
tion Mode Lock Bit is also programmed after programming the Password, the
Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit
after a hardware reset (RESET# asserted) or a power-up reset. Successful exe-
cution of the Password Unlock command clears and unfreezes the PPB Lock Bit,
allowing for sector PPB bits to be modified. Without issuing the Password Unlock
command, while asserting RESET#, taking the device through a power-on reset,
or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the “freeze
state.”
If the Password Protection Mode Lock Bit is not programmed, the device defaults
to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit
is cleared to the “unfreeze state” after power-up or hardware reset. The PPB Lock
Bit is set to the “freeze state” by issuing the PPB Lock Bit Set command. Once set
to the “freeze state” the only means for clearing the PPB Lock Bit to the “unfreeze
state” is by issuing a hardware or power-up reset. The Password Unlock com-
mand is ignored in Persistent Protection Mode.
Reading the PPB Lock Bit requires a 200 ns access time.
24
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
SecSi (Secured Silicon) Sector Flash Mem ory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that
enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator
Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from
the factory. This bit is permanently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This ensures the security of the
ESN once the product is shipped to the field. The factory offers the device with
the SecSi Sector either customer lockable (standard shipping option) or factory
locked (contact an AMD sales representative for ordering information). The cus-
tomer-lockable version is shipped with the SecSi Sector unprotected, allowing
customers to program the sector after receiving the device. The customer-lock-
able version also has the SecSi Sector Indicator Bit permanently set to a “0.” The
factory-locked version is always protected when shipped from the factory, and
has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.”
Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
Note: The ACC function and unlock bypass modes are not available when the
SecSi Sector is enabled.
The SecSi sector address space in this device is allocated as follows:
SecSi Sector
ExpressFlash
Address Range
Customer Lockable
ESN Factory Locked
ESN
Factory Locked
000000h–000007h
000008h–00007Fh
ESN or determined by customer
Determined by customer
Determined by customer
Unavailable
The system accesses the SecSi Sector through a command sequence. See “Write
Protect (WP#).” After the system has written the Enter SecSi Sector command
sequence, it can read the SecSi Sector by using the addresses normally occupied
by the first sector (SA0). This mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until power is removed from the de-
vice. On power-up, or following a hardware reset, the device reverts to sending
commands to sector SA0.
Customer Lockable: SecSi Sector NOT Programmed or Protected
At the Factory
Unless otherwise specified, the device is shipped such that the customer can pro-
gram and protect the 256-byte SecSi sector.
The system can program the SecSi Sector using the write-buffer, accelerated,
and/or unlock bypass methods, in addition to the standard programming com-
mand sequence. See “Command Definitions” on page 30.
Programming and protecting the SecSi Sector must be used with caution be-
cause, once protected, there is no procedure available for unprotecting the SecSi
Sector area and none of the bits in the SecSi Sector memory space can be mod-
ified in any way.
October 29, 2004 S29GLxxxP_00A0
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A d v a n c e I n f o r m a t i o n
The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and
then follow the in-system sector protect algorithm, except that RESET# can
be at either VIH or VID. This allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note: This method is only applicable to the SecSi Sector.
To verify the protect/unprotect status of the SecSi Sector, follow the
algorithm.
Once the SecSi Sector is programmed, locked and verified, the system must write
the Exit SecSi Sector Region command sequence to return to reading and writing
within the remainder of the array.
Factory Locked: SecSi Sector Programmed and Protected At the Factory
In devices with an ESN, the SecSi Sector is protected when the device is shipped
from the factory. The SecSi Sector cannot be modified in any way. An ESN Factory
Locked device has an 16-byte random ESN at addresses 000000h–000007h.
Please contact your sales representative for details on ordering ESN Factory
Locked devices.
Customers can opt to have their code programmed by the factory through the
ExpressFlash service (Express Flash Factory Locked). The devices are then
shipped from the factory with the SecSi Sector permanently locked. Contact your
sales representative for details on using the ExpressFlash service.
W rite Protect (W P#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using VID. Write Protect is one of two functions provided
by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected using the method described in “Ad-
vanced Sector Protection” on page 19.
Note: If WP#/ACC is at VIL when the device is in the standby mode, the maxi-
mum input load current is increased. See the table in “DC Characteristics” on
page 60.
If the system asserts VIH on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or un-
protected using the method described in “Sector Protection” on page 18
Note that WP# has an internal pullup; when unconnected, WP# is at VIH
.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 10 and
Table 11 for command definitions). In addition, the following hardware data pro-
tection measures prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
26
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This pro-
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or
WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while
OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Com m on Flash Mem ory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and backward
compatible for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Table 6, Table 7,
Table 8, and Table 9. To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 6, Table 7, Table 8, and Table 9. The sys-
tem must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alter-
natively, contact your sales representative for copies of these documents.
October 29, 2004 S29GLxxxP_00A0
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A d v a n c e I n f o r m a t i o n
Ta ble 6. CFI Q uery Identification String
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Ta ble 7. System Interface String
Addresses
(x16)
Addresses
(x8)
Data
0027h
0036h
0000h
0000h
0007h
0007h
000Ah
0000h
0003h
0005h
0004h
0000h
Description
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 mV
VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 mV
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N
µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
28
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Table 8. Device Geom etry Definition
Addresses
(x16)
Addresses
(x8)
Data
Description
001Bh
001Ah
0019h
Device Size = 2N byte
27h
4Eh
1B = 1 Gb, 1A= 512 Mb, 19 = 256 Mb
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0006h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Ch
58h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FFh, 002h, 0000h, 0002h =1 Gb
00FFh, 0001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
0000h
000xh
31h
32h
33h
34h
60h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
October 29, 2004 S29GLxxxP_00A0
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A d v a n c e I n f o r m a t i o n
Table 9 . Prim ary Vendor-Specific Extended Q uery
Addresses
(x16)
Addresses
(x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0014h
Process Technology (Bits 7-2) 0101b = 90 nm MirrorBit
Erase Suspend
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0000h
0008h
0000h
0000h
0002h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
0008h = Advanced Sector Protection
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
WP# Protection
4Fh
50h
9Eh
A0h
00xxh
0001h
04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors
top WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
Com m and Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 10 and Table 11 define the valid regis-
ter command sequences. Writing incorrect address and data values or writing
them in the improper sequence can place the device in an unknown state. A reset
command is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to “AC Characteristics” on page 62 for timing diagrams.
30
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
erase-suspend-read mode, after which the system can read data from any non-
erase-suspended sector. After completing a programming operation in the Erase
Suspend mode, the system can once again read array data with the same excep-
tion. See “Erase Suspend/Erase Resume Commands” on page 40 for more
information.
The system must issue the reset command to return the device to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode. See the next section, “Reset
Command,” for more information.
See “Requirements for Reading Array Data” on page 14 for more information. The
Read-Only Operations–“AC Characteristics” on page 62 provides the read param-
eters, and Figure 11 shows the timing diagram.
Reset Com m and
Writing the reset command resets the device to the read or erase-suspend-read
mode. Address bits are “don’t cares” for this command.
The reset command can be written between the sequence cycles in an erase com-
mand sequence before erasing begins. This resets the device to the read mode.
Once erasure begins, however, the device ignores reset commands until the op-
eration is complete.
The reset command can be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to the
read mode. If the program command sequence is written while the device is in
the Erase Suspend mode, writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command can be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If the device entered the autoselect mode
while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to the read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the sys-
tem must write the Write-to-Buffer-Abort Reset command sequence to reset the
device for the next operation.
October 29, 2004 S29GLxxxP_00A0
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A d v a n c e I n f o r m a t i o n
Autoselect Com m and Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
Table 10 and Table 11 show the address and data requirements. This method is
an alternative to that shown in Table 3, which is intended for PROM programmers
and requires VID on address pin A9. The autoselect command sequence can be
written to an address that is either in the read or erase-suspend-read mode. The
autoselect command cannot be written while the device is actively programming
or erasing.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system can read at any address any
number of times without initiating another autoselect command sequence:
A read cycle at address XX00h returns the manufacturer code.
Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code.
A read cycle to an address containing a sector address (SA), and the address
02h on A7–A0 in word mode returns 01h if the sector is protected, or 00h if
it is unprotected.
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the device was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector Com m and Sequence
The SecSi Sector region provides a secured data area containing an 8-word/
16-byte random Electronic Serial Number (ESN). The system can access the
SecSi Sector region by issuing the three-cycle Enter SecSi Sector command se-
quence. The device continues to access the SecSi Sector region until the system
issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector
command sequence returns the device to normal operation. Table 10 and
Table 11 show the address and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash Memory Region” on page 25 for
further information.
Note: The ACC function and unlock bypass modes are not available when the
SecSi Sector is enabled.
Word Program Com m and Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 10 shows the address and
data requirements for the word program command sequence.
When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to “Write Oper-
ation Status” on page 52 for information on these status bits.
32
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Any commands written to the device during the Embedded Program Algorithm
are ignored.
Note: The SecSi Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.
Note: A hardware reset immediately terminates the program operation.
The program command sequence should be reinitiated once the device has re-
turned to the read mode, to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without in-
tervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of in-
dividual words. Use of Write Buffer Programming is strongly recommended for
general programming use when more than a few words are to be programmed.
The effective word programming time using Write Buffer Programming is much
shorter than the single word programming time. Any word cannot be pro-
grammed from “0” back to a “1.” Attempting to do so can cause the device
to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation
was successful. However, a succeeding read shows that the data is still “0.” Only
erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. Table 10 and Table 11 show the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (See Table 10
and Table 11).
October 29, 2004 S29GLxxxP_00A0
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A d v a n c e I n f o r m a t i o n
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the
Sector Address in which programming occurs. The fourth cycle writes the sector
address and the number of word locations, minus one, to be programmed. For
example, if the system programs six unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses
are loaded with data and therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot exceed the size of the
write buffer or the operation aborts.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits AMAX–A5. All subsequent address/
data pairs must fall within the selected-write-buffer-page. The system then
writes the remaining address/data pairs into the write buffer. Write buffer loca-
tions can be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded
into the write buffer. (This means Write Buffer Programming cannot be performed
across multiple write-buffer pages. This also means that Write Buffer Program-
ming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation
aborts.)
Note that if a Write Buffer address location is loaded multiple times, the address/
data pair counter are decremented for every data load operation. The host sys-
tem must therefore account for loading a write-buffer location more than once.
The counter decrements for each data load operation, not for each unique write-
buffer-address location. Note also that if an address location is loaded more than
once into the buffer, the final data loaded for that address are programmed.
Once the specified number of write buffer locations have been loaded, the system
must then write the Program Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write Buffer Programming oper-
ation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5,
and DQ1 should be monitored to determine the device status during Write Buffer
Programming.
The write-buffer programming operation can be suspended using the standard
program suspend/resume commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of
Locations to Program step.
Write to an address in a sector different than the one specified during the
Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one
selected by the Starting Address during the write buffer data loading stage of
the operation.
Write data other than the Confirm Command after the specified number of
data load cycles.
34
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address
location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset com-
mand sequence must be written to reset the device for the next operation. Note
that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required
when using Write-Buffer-Programming features in Unlock Bypass mode.
Write buffer programming is allowed in any sequence.
Note: The SecSi sector, autoselect, and CFI functions are unavailable when a
program operation is in progress.
This flash device is capable of handling multiple write buffer programming oper-
ations on the same write buffer address range without intervening erases. For
applications requiring incremental bit programming, a modified programming
method is required, please contact your local Spansion representative. Any bit
in a write buffer address range cannot be programmed from “0” back to
a “1.” Attempting to do so can cause the device to set DQ5 = 1, or cause the
DQ7 and DQ6 status bits to indicate the operation was successful. However, a
succeeding read shows that the data is still “0.” Only erase operations can convert
a “0” to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system can then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation
Note: The WP#/ACC pin must not be at VHH for operations other than acceler-
ated programming, or device damage can result. WP# has an internal pullup;
when unconnected, WP# is at VIH.
Figure 2 illustrates the algorithm for the program operation. Refer to Erase and
Program Operations–“AC Characteristics” or parameters, and Figure 14 for timing
diagrams.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
35
A d v a n c e I n f o r m a t i o n
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Yes
Buffer Operation?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
(Note 1)
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any
address in the selected sector is acceptable.
However, when loading Write-Buffer
address locations with data, all addresses
must fall within the selected Write-Buffer
Page.
Read DQ15 - DQ0 at
Last Loaded Address
2. DQ7 can change simultaneously with DQ5.
Therefore, DQ7 should be verified.
Yes
DQ7 = Data?
No
3. If this flowchart location was reached
because DQ5= “1,” then the device FAILED.
If this flowchart location was reached
because DQ1= “1,” then the Write to Buffer
operation was ABORTED. In either case, the
proper reset command must be written
before the device can begin another
operation. If DQ1=1, write the Write-
Buffer-Programming-Abort-Reset
No
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
Read DQ15 - DQ0 with
address = Last Loaded
Address
command. if DQ5=1, write the Reset
command.
4. See Table 10 and Table 11 for command
sequences required for write buffer
programming.
Yes
(Note 2)
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
PASS
Figure 1. W rite Buffer Program m ing O peration
36
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Start
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
Algorithm
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 10 and Table 11 for program command sequence.
Figure 2. Program O peration
Program Suspend/Program Resum e Com m and Sequence
The Program Suspend command allows the system to interrupt a programming
operation or a Write to Buffer programming operation so that data can be read
from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the program operation within
15 µs maximum (5µs typical) and updates the status bits. Addresses are not re-
quired when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array
data from any non-suspended sector. The Program Suspend command can also
be issued during a programming operation while an erase is suspended. In this
case, data can be read from any addresses not in Erase Suspend or Program Sus-
pend. If a read is needed from the SecSi Sector area (One-time Program area),
then user must use the proper command sequences to enter and exit this region.
Note: The SecSi Sector, autoselect, and CFI functions are unavailable when pro-
gram operation is in progress.
The system can also write the autoselect command sequence when the device is
in the Program Suspend mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode, the device reverts to the
Program Suspend mode, and is ready for another valid operation. See “Autoselect
Command Sequence” on page 32 for more information.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
37
A d v a n c e I n f o r m a t i o n
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write
Operation Status” on page 52 for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resume programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 3. Program Suspend/Program Resum e
Chip Erase Com m and Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not re-
quire the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to provide any con-
trols or timings during these operations. Table 10 and Table 11 show the address
and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to “Write Operation Sta-
tus” on page 52 for information on these status bits.
38
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Any commands written during the chip erase operation are ignored, including
erase suspend commands. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase command sequence
should be reinitiated once the device has returned to reading array data, to en-
sure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Note: The SecSi Sector, autoselect, and CFI functions are unavailable when an
erase operation in is progress.
See the table, “Erase and Program Operations-S29GL01GP, S29GL512P,
S29GL256P” on page 65, and Figure 16 for timing diagrams.
Sector Erase Com m and Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 10 and Table 11 show
the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands can be written. Loading the sector erase buffer can be done in any
sequence, and the number of sectors can be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
can begin. Any sector erase address and command following the exceeded time-
out can or cannot be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode.
Note: The SecSi Sector, autoselect, and CFI functions are unavailable when an
erase operation in is progress.
The system must rewrite the command sequence and any additional addresses
and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See “DQ3: Sector Erase Timer” on page 57). The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to “Write Operation Status” on page 52 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
39
A d v a n c e I n f o r m a t i o n
Figure 4 illustrates the algorithm for the erase operation. See the table, “Erase
and Program Operations-S29GL01GP, S29GL512P, S29GL256P” on page 65 in
“AC Characteristics” for parameters, and Figure 16 for timing diagrams.
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1.See Table 10 and Table 11 for program command sequence.
2.See “DQ3: Sector Erase Timer” on page 57 for information on the sector erase timer.
Figure 4. Erase Operation
Erase Suspend/Erase Resum e Com m ands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, includ-
ing the 50 µs time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend command is written during the sec-
tor erase time-out, the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to “Write Operation Status” on page 52 for information on these status bits.
40
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
After an erase-suspended program operation is complete, the device returns to
the erase-suspend-read mode. The system can determine the status of the pro-
gram operation using the DQ7 or DQ6 status bits, just as in the standard word
program operation. Refer to “Write Operation Status” on page 52 for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. Refer to “ Autoselect Mode” on page 17 and “Autoselect
Command Sequence” on page 32 for details.
To resume the sector erase operation, the system must write the Erase Resume
command. The address of the erase-suspended sector is required when writing
this command. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has resumed erasing. It is
important to allow an interval of at least 5 ms between Erase Resume and Erase
Suspend.
Lock Register Com m and Set Definitions
The Lock Register Command Set permits the user to one-time program the SecSi
Sector Protection Bit, Persistent Protection Mode Lock Bit, and Password Protec-
tion Mode Lock Bit. The Lock Register bits are all readable after an initial access
delay.
The Lock Register Command Set Entry command sequence must be issued
prior to any of the following commands listed, to enable proper command
execution.
Note that issuing the Lock Register Command Set Entry command disables
reads and writes for the flash memory.
Lock Register Program Command
Lock Register Read Command
The Lock Register Command Set Exit command must be issued after the ex-
ecution of the commands to reset the device to read mode. Otherwise the device
hangs. If this happens, the flash device must be reset. Please refer to RESET#
for more information. It is important to note that the device is in either Persistent
Protection mode or Password Protection mode depending on the mode selected
prior to the device hang.
For either the SecSi Sector to be locked, or the device to be permanently set to
the Persistent Protection Mode or the Password Protection Mode, the associated
Lock Register bits must be programmed.
Note: The Persistent Protection Mode Lock Bit and Password Protection Mode
Lock Bit can never be programmed together at the same time. If so, the Lock
Register Program operation aborts.
The Lock Register Command Set Exit command must be initiated to re-enable
reads and writes to the main memory.
Password Protection Com m and Set Definitions
The Password Protection Command Set permits the user to program the 64-bit
password, verify the programming of the 64-bit password, and then later unlock
the device by issuing the valid 64-bit password.
The Password Protection Command Set Entry command sequence must be
issued prior to any of the commands listed following to enable proper command
execution.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
41
A d v a n c e I n f o r m a t i o n
Note: Issuing the Password Protection Command Set Entry command dis-
abled reads and writes the main memory.
Password Program Command
Password Read Command
Password Unlock Command
The Password Program command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. There is no special addressing order required for programming the pass-
word. The password is programmed in 8-bit or 16-bit portions. Each
portion requires a Password Program Command.
Once the Password is written and verified, the Password Protection Mode Lock Bit
in the “Lock Register” must be programmed in order to prevent verification. The
Password Program command is only capable of programming “0”s. Programming
a “1” after a cell is programmed as a “0” results in a time-out by the Embedded
Program AlgorithmTM with the cell remaining as a “0.” The password is all Fs when
shipped from the factory. All 64-bit password combinations are valid as a
password.
The Password Read command is used to verify the Password. The Password is
verifiable only when the Password Protection Mode Lock Bit in the “Lock Register”
is not programmed. If the Password Protection Mode Lock Bit in the
“Lock Register” is programmed and the user attempts to read the Password, the
device always drives all Fs onto the DQ databus.
The lower two address bits (A1–A0) for word mode and (A1–A-1) for by byte
mode are valid during the Password Read, Password Program, and Password
Unlock commands. Writing a “1” to any other address bits (AMAX-A2)
aborts the Password Read and Password Program commands.
The Password Unlock command is used to clear the PPB Lock Bit to the “unfreeze
state” so that the PPB bits can be modified. The exact password must be entered
in order for the unlocking function to occur. This 64-bit Password Unlock com-
mand sequence takes at least 2 µs to process each time to prevent a
hacker from running through the all 64-bit combinations in an attempt
to correctly match the password. If another password unlock is issued
before the 64-bit password check execution window is completed, the
command is ignored. If the wrong address or data is given during pass-
word unlock command cycle, the device can enter the write-to-buffer
abort state. In order to exit the write-to-abort state, the write-to-buffer-
abort-reset command must be given. Otherwise the device hangs.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit to the
“unfreeze state.” The password is 64 bits long. A1 and A0 are used for matching
in word mode and A1, A0, A-1 in byte mode. Writing the Password Unlock com-
mand does not need to be address order specific. An example sequence is
starting with the lower address A1-A0=00, followed by A1-A0=01, A1-A0=10,
and A1-A0=11 if the device is configured to operate in word mode.
42
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Approximately 2 µs is required for unlocking the device after the valid
64-bit password is given to the device. It is the responsibility of the
microprocessor to keep track of the entering the portions of the 64-bit
password with the Password Unlock command, the order, and when to
read the PPB Lock bit to confirm successful password unlock. To re-lock
the device into the Password Protection Mode, the PPB Lock Bit Set command can
be re-issued.
The Password Protection Command Set Exit command must be issued after
the execution of the commands listed previously to reset the device to read
mode. Otherwise the device hangs.
Note: Issuing the Password Protection Command Set Exit command
re-enables reads and writes for the main memory.
Non-Volatile Sector Protection Com m and Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the
Persistent Protection Bits (PPB bits), erase all of the Persistent Protection Bits
(PPB bits), and read the logic state of the Persistent Protection Bits (PPB bits).
The Non-Volatile Sector Protection Command Set Entry command se-
quence must be issued prior to any of the commands listed following to enable
proper command execution.
Note: Issuing the Non-Volatile Sector Protection Command Set Entry com-
mand disables reads and writes for the main memory.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB bit. Each PPB
bit is individually programmed (but is bulk erased with the other PPB bits). The
specific sector address (A25-A16 for S29GL01GP, A24-A16 for S29GL512P,
A23-A16 for S29GL256P) is written at the same time as the program command.
If the PPB Lock Bit is set to the “freeze state,” the PPB Program command does
not execute and the command times-out without programming the PPB bit.
All PPB Erase Command
The All PPB Erase command is used to erase all PPB bits in bulk. There is no
means for individually erasing a specific PPB bit. Unlike the PPB program, no spe-
cific sector address is required. However, when the All PPB Erase command is
issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set to
“freeze state,” the ALL PPB Erase command does not execute and the command
times-out without erasing the PPB bits.
The device preprograms all PPB bits prior to erasing when issuing the All PPB
Erase command. Also note that the total number of PPB program/erase cycles has
the same endurance as the flash memory array.
PPB Status Read Command
The programming state of the PPB for a given sector can be verified by writing a
PPB Status Read Command to the device. This requires an initial access time
latency.
The Non-Volatile Sector Protection Command Set Exit command must be
issued after the execution of the commands listed previously to reset the device
to read mode.
Note: Issuing the Non-Volatile Sector Protection Command Set Exit com-
mand re-enables reads and writes for the main memory.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
43
A d v a n c e I n f o r m a t i o n
Global Volatile Sector Protection Freeze Com m and Set
The Global Volatile Sector Protection Freeze Command Set permits the user to set
the PPB Lock Bit and reading the logic state of the PPB Lock Bit.
The Global Volatile Sector Protection Freeze Command Set Entry com-
mand sequence must be issued prior to any of the commands listed following to
enable proper command execution.
Reads and writes from the main memory are not allowed.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock Bit to the “freeze state”
if it is cleared either at reset or if the Password Unlock command was successfully
executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set
to the “freeze state,” it cannot be cleared unless the device is taken through a
power-on clear (for Persistent Protection Mode) or the Password Unlock command
is executed (for Password Protection Mode). If the Password Protection Mode Lock
Bit is programmed, the PPB Lock Bit status is reflected as set to the “freeze state,”
even after a power-on reset cycle.
PPB Lock Bit Status Read Command
The programming state of the PPB Lock Bit can be verified by executing a PPB
Lock Bit Status Read command to the device.
The Global Volatile Sector Protection Freeze Command Set Exit command
must be issued after the execution of the commands listed previously to reset the
device to read mode.
Volatile Sector Protection Com m and Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic
Protection Bit (DYB) to the “protected state,” clear the Dynamic Protection Bit
(DYB) to the “unprotected state,” and read the logic state of the Dynamic Protec-
tion Bit (DYB).
The Volatile Sector Protection Command Set Entry command sequence
must be issued prior to any of the commands listed following to enable proper
command execution.
Note: Issuing the Volatile Sector Protection Command Set Entry command
disables reads and writes from the main memory.
DYB Set Command
DYB Clear Command
The DYB Set and DYB Clear commands are used to protect or unprotect a DYB for
a given sector. The high order address bits are issued at the same time as the
code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the
data write cycle. The DYB bits are modifiable at any time, regardless of the state
of the PPB bit or PPB Lock Bit. The DYB bits are cleared to the “unprotected state”
at power-up or hardware reset.
DYB Status Read Command
The programming state of the DYB bit for a given sector can be verified by writing
a DYB Status Read command to the device. This requires an initial access delay.
The Volatile Sector Protection Command Set Exit command must be issued
after the execution of the commands listed previously to reset the device to read
mode.
44
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Note: Issuing the Volatile Sector Protection Command Set Exit command
re-enables reads and writes to the main memory.
SecSi Sector Entry Com m and
The SecSi Sector Entry command allows the following commands to be executed
Read from SecSi Sector
Program to SecSi Sector
Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command
has to be issued to exit SecSi Sector Mode.
SecSi Sector Exit Com m and
The SecSi Sector Exit command can be issued to exit the SecSi Sector Mode.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
45
A d v a n c e I n f o r m a t i o n
Com m and Definitions
Table 10. S29GL01GP, S29GL512P, S29GL256P Com m and Definitions, x16
Bus Cycles (Notes 2–5)
Command (Notes)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (6)
1
1
4
RA
RD
F0
Reset (7)
XXX
555
Manufacturer ID
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
Note
17
Note
17
Device ID
4
4
4
555
555
555
AA
AA
AA
227E
X0E
X0F
XX00
XX01
(SA)
X02
Sector Protect Verify
Secure Device Verify (9)
2AA
2AA
55
55
555
555
90
90
Note
10
X03
CFI Query (11)
1
4
3
1
3
3
2
2
2
2
6
6
1
1
55
98
AA
AA
29
AA
AA
A0
80
80
90
AA
AA
B0
30
Program
555
555
SA
2AA
2AA
55
55
555
SA
A0
25
PA
SA
PD
Write to Buffer
WC
PA
PD
WBL
PD
Program Buffer to Flash (confirm)
Write-to-Buffer-Abort Reset (16)
Unlock Bypass
555
555
XXX
XXX
XXX
XXX
555
555
XXX
XXX
2AA
2AA
PA
55
55
PD
30
10
00
55
55
555
555
F0
20
Unlock Bypass Program (12)
Unlock Bypass Sector Erase (12)
Unlock Bypass Chip Erase (12)
Unlock Bypass Reset (13)
Chip Erase
SA
XXX
XXX
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend/Program Suspend (14)
Erase Resume/Program Resume (15)
Sector Command Definitions
SecSi Sector Entry
3
555
AA
2AA
55
555
88
90
SecSi Sector Exit (18)
4
555
AA
2AA
55
555
XX
00
Lock Register Command Set Definitions
Lock Register Command Set Entry
Lock Register Bits Program (22)
Lock Register Bits Read (22)
3
2
1
2
555
XXX
00
AA
A0
2AA
XXX
55
555
40
Data
Data
90
Lock Register Command Set Exit (18, 23)
XXX
XXX
00
46
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Table 10. S29GL01GP, S29GL512P, S29GL256P Com m and Definitions, x16 (Continued)
Bus Cycles (Notes 2–5)
Command (Notes)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Password Protection Command Set Definitions
Password Protection Command Set Entry
3
555
AA
2AA
55
555
60
PWA
x
PWD
x
Password Program (20)
Password Read (19)
2
XXX
A0
PWD
0
PWD
1
PWD
2
PWD
3
4
7
2
XXX
01
00
02
00
03
01
PWD
0
PWD
1
PWD
2
PWD
3
00
00
25
29
90
03
02
03
Password Unlock (19)
Password Protection Command Set Exit (18,
23)
XXX
XXX
00
Non-Volatile Sector Protection Command Set Definitions
Nonvolatile Sector Protection Command Set
Entry
3
555
AA
2AA
55
555
C0
PPB Program (24, 25)
All PPB Erase
2
2
XXX
XXX
A0
80
SA
00
00
30
RD
(0)
PPB Status Read (25)
1
2
SA
Non-Volatile Sector Protection Command Set
Exit (18)
XXX
90
XXX
00
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Non-Volatile Sector Protection Freeze
Command Set Entry
3
2
1
555
XXX
XXX
AA
A0
2AA
XXX
55
00
555
50
PPB Lock Bit Set (25)
RD
(0)
PPB Lock Status Read (25)
Global Non-Volatile Sector Protection Freeze
Command Set Exit (18)
2
XXX
90
XXX
00
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection Command Set Entry
DYB Set (24, 25)
3
2
2
555
XXX
XXX
AA
A0
A0
2AA
SA
55
00
01
555
E0
DYB Clear (25)
SA
RD
(0)
DYB Status Read (25)
1
2
SA
Volatile Sector Protection Command Set Exit
(18)
XXX
90
XXX
00
Legend:
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
47
A d v a n c e I n f o r m a t i o n
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
PWD = Password
PWDx = Password word0, word1, word2, and word3.
DATA = Lock Register Contents: PD(0) = SecSi Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) =
Password Protection Mode Lock Bit.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.
5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.
10. The data value for DQ7 is “1” for a serialized and protected OTP region and “0” for an unserialized and unprotected
SecSi™Sector region. See “SecSi (Secured Silicon) Sector Flash Memory Region” on page 25” for more information. For
S29GLxxxPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked. For S29GLxxxPL: XX09h/09h = Not Factory
Locked. XX89h/88h = Factory Locked.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command.
13. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
14. The system can read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
15. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
16. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the
full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.
17. S29GL01GPH/L = 2228h/28h, 2201h/01h; S29GL512PH/L = 2223h/23h, 2201h/01h; S29GL256PH/L = 2222h/22h, 2201h/
01h.
18. The Exit command returns the device to reading the array.
19. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
20. For PWDx, only one portion of the password can be programmed per each “A0” command.
21. The All PPB Erase command embeds programming of all PPB bits before erasure.
22. All Lock Register bits are one-time programmable. Note that the program state = “0” and the erase state = “1.” Also note
that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the
same time or the Lock Register Bits Program operation aborts and returns the device to read mode. Lock Register bits that
are reserved for future use default to “1's.” The Lock Register is shipped out as “FFFF's” before Lock Register Bit program
execution.
23. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise
the device hangs.
24. If ACC = VHH, sector protection matches when ACC = VIH
25. Protected State = “00h,” Unprotected State = “01h.”
48
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Ta ble 11. S29GL01GP, S29GL512P, S29GL256P Com m and Definitions, x8
Bus Cycles (Notes 2–5)
Command (Notes)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (6)
1
1
4
RA
RD
F0
Reset (7)
XXX
AAA
Manufacturer ID
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
Note
17
Note
17
Device ID
4
4
4
AAA
AAA
AAA
AA
AA
AA
XX7E
X1C
X1E
00
01
(SA)
X04
Sector Protect Verify
Secure Device Verify (9)
555
555
55
55
AAA
AAA
90
90
Note
10
X06
SA
CFI Query (11)
1
3
1
3
6
6
1
1
AA
98
AA
29
AA
AA
AA
B0
30
Write to Buffer
AAA
SA
555
55
SA
25
WC
PA
PD
WBL
PD
Program Buffer to Flash (confirm)
Write-to-Buffer-Abort Reset (16)
Chip Erase
AAA
AAA
AAA
XXX
XXX
PA
55
55
55
555
AAA
AAA
F0
80
80
555
555
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Erase Suspend/Program Suspend (14)
Erase Resume/Program Resume (15)
SecSi Sector Command Definitions
SecSi Sector Entry
3
AAA
AA
555
55
AAA
88
SecSi Sector Exit (18)
4
AAA
AA
555
55
AAA
90
XX
00
Lock Register Command Set Definitions
Lock Register Command Set Entry
Lock Register Bits Program (22)
Lock Register Bits Read (22)
3
2
1
2
AAA
XXX
00
AA
A0
555
XXX
55
AAA
40
Data
Data
90
Lock Register Command Set Exit (18, 23)
XXX
XXX
00
Password Protection Command Set Definitions
Password Protection Command Set Entry
3
AAA
AA
555
55
AAA
60
PWA PWD
Password Program (20)
2
XXX
A0
x
x
PWD
0
PWD
1
00
06
01
PWD
2
PWD
3
PWD
4
PWD
5
Password Read (19)
Password Unlock (19)
8
02
03
04
05
03
PWD
6
PWD
7
07
00
PWD
0
PWD
1
PWD
2
PWD
3
00
25
03
00
06
01
07
02
00
11
2
PWD
4
PWD
5
PWD
6
PWD
7
04
05
29
Password Protection Command Set Exit
(18, 23)
XXX
90
XXX
00
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
49
A d v a n c e I n f o r m a t i o n
Table 11. S29GL01GP, S29GL512P, S29GL256P Com m and Definitions, x8 (Continued)
Bus Cycles (Notes 2–5)
Command (Notes)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Non-Volatile Sector Protection Command Set Definitions
Nonvolatile Sector Protection Command
Set Entry
3
AAA
AA
55
55
AAA
C0
PPB Program (24, 25)
All PPB Erase
2
2
XXX
XXX
A0
80
SA
00
00
30
RD
(0)
PPB Status Read (25)
1
2
SA
Non-Volatile Sector Protection Command
Set Exit (18)
XXX
90
XXX
00
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Non-Volatile Sector Protection
Freeze Command Set Entry
3
2
1
AAA
XXX
XXX
AA
A0
555
XXX
55
00
AAA
50
PPB Lock Bit Set (25)
RD
(0)
PPB Lock Status Read (25)
Global Non-Volatile Sector Protection
Freeze Command Set Exit (18)
2
XXX
90
XXX
00
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection Command Set
Entry
3
AAA
AA
555
55
AAA
E0
DYB Set (24, 25)
DYB Clear (25)
2
2
XXX
XXX
A0
A0
SA
SA
00
01
RD
(0)
DYB Status Read (25)
1
2
SA
Volatile Sector Protection Command Set
Exit (18)
XXX
90
XXX
00
Legend:
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
PWD = Password
PWDx = Password word0, word1, word2, word3. word 4, word 5, word 6, and word 7.
DATA = Lock Register Contents: PD(0) = SecSi Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) =
Password Protection Mode Lock Bit.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
50
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.
5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.
10. The data value for DQ7 is “1” for a serialized and protected OTP region and “0” for an unserialized and unprotected
SecSi™ Sector region. See “SecSi (Secured Silicon) Sector Flash Memory Region” on page 25” for more information. For
S29GLxxxPH.: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked. For S29GLxxxPL: XX09h/09h = Not Factory
Locked. XX89h/89h = Factory Locked.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The system can read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
13. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
14. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the
full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.
15. S29GL01GPH/L = 2228h/28h, 2201h/01h; S29GL512PH/L = 2223h/23h, 2201h/01h; S29GL256PH/L = 2222h/22h, 2201h/01h.
16. The Exit command returns the device to reading the array.
17. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
18. For PWDx, only one portion of the password can be programmed per each “A0” command.
19. The All PPB Erase command embeds programming of all PPB bits before erasure.
20. All Lock Register bits are one-time programmable. Note that the program state = “0” and the erase state = “1.” Also note
that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the
same time or the Lock Register Bits Program operation aborts and returns the device to read mode. Lock Register bits that
are reserved for future use defaults to “1's.” The Lock Register is shipped out as “FFFF's” before Lock Register Bit program
execution.
21. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise
the device hangs.
22. If ACC = VHH, sector protection matches when ACC = VIH
Protected State = “00h,” Unprotected State = “01h.”
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
51
A d v a n c e I n f o r m a t i o n
W rite O peration Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
Note that all Write Operation Status DQ bits are valid only after 4 µs delay.
DQ 7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device is
in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status might not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
can change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-
serted low. That is, the device can change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
can read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 can be
still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.
Table 12 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data#
Polling algorithm. Figure 17 in “AC Characteristics” shows the Data# Polling tim-
ing diagram.
52
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
START
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1
Yes
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 can change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or in the erase-suspend-read
mode. Table 12 shows the outputs for RY/BY#.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
53
A d v a n c e I n f o r m a t i o n
DQ 6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I can be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system can use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see “DQ7: Data# Polling” on page 52).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit
algorithm. Figure 18 in “AC Characteristics” shows the toggle bit timing diagrams.
Figure 19 shows the differences between DQ2 and DQ6 in graphical form. See
“SecSi (Secured Silicon) Sector Flash Memory Region” on page 25.
54
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
START
Read DQ7–DQ0
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note:
The system should recheck the toggle bit even if DQ5 =
“1” because the toggle bit can stop toggling as DQ5
changes to “1.” See “DQ6: Toggle Bit I” on page 54 and
“DQ2: Toggle Bit II” for more information.
Figure 6. Toggle Bit Algorithm
DQ 2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system can use either OE# or CE# to control the
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
55
A d v a n c e I n f o r m a t i o n
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 12 to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart form, and “DQ2: Toggle Bit
II” explains the algorithm. See “RY/BY#: Ready/Busy#” on page 53. Figure 18
shows the toggle bit timing diagram. Figure 19 shows the differences between
DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ 6/DQ 2
Refer to Figure 6 and Figure 19 for the following discussion. Whenever the sys-
tem initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device has completed the program or erase op-
eration. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see “DQ5: Exceeded Timing Limits”). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit can have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling,
the device did not completed the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system can continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it can choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 6).
DQ 5: Exceeded Tim ing Lim its
DQ5 indicates whether the program, erase, or write-to-buffer time has ex-
ceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device can output a “1” on DQ5 if the system tries to program a “1” to a lo-
cation that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
56
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
DQ 3: Sector Erase Tim er
After writing a sector erase command sequence, the system can read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not monitor DQ3. See “Sector
Erase Command Sequence” on page 39.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device accepts additional
sector erase commands. To ensure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second status check, the last com-
mand might not have been accepted.
Table 12 shows the status of DQ3 relative to the other status bits.
DQ 1: W rite-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these
conditions DQ1 produces a “1.” The system must issue the Write-to-Buffer-Abort-
Reset command sequence to return the device to reading array data. See “Write
Buffer” on page 15 for more details.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
57
A d v a n c e I n f o r m a t i o n
Table 12. W rite O peration Status
DQ7
(Note 2)
DQ5
(Note 1) DQ3
DQ2
(Note 2)
RY/
BY#
Status
DQ6
DQ1
0
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Suspend
Read
Sector
Non-Program
Suspended Sector
Erase-Suspended
Sector
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Suspend
Read
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to “1” when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. See “DQ5: Exceeded Timing Limits” on page 56 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. See “DQ7: Data# Polling” on page 52
and “DQ2: Toggle Bit II” on page 55 for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to “1” when the device has aborted the write-to-buffer operation.
58
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
ABSOLUTE MAXIMUM RATINGS
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and ACC (Note 2) . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . .–0.5 V to Vcc + 0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os can overshoot V to –2.0 V for periods of up to 20 ns. See Figure 7.
SS
Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions,
CC
input or I/O pins can overshoot to V + 2.0 V for periods up to 20 ns. See
CC
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and ACC is –0.5 V. During voltage
transitions, A9, OE#, and ACC can overshoot V to –2.0 V for periods of up to
SS
20 ns. See Figure 7. Maximum DC input voltage on pin A9, OE#, and ACC is +12.5
V which can overshoot to +14.0V for periods up to 20 ns.
3. No more than one output can be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” can cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods can affect device
reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
–0.5 V
–2.0 V
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 7. Maxim um Negative
O vershoot W aveform
Figure 8. Maxim um Positive
O vershoot W aveform
O perating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC
. . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V or +3.0 V to +3.6 V
VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65V to 1.95V or VCC
Notes:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
2. See “Product Selector Guide” on page 6
3. See “Ordering Information” on page 12 for valid V /V range combinations. The I/Os do not operate at 3 V when
CC IO
V
=1.8 V.
IO
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
59
A d v a n c e I n f o r m a t i o n
DC Characteristics
CMO S Com patible-S29GL01GP, S29GL512P, S29GL256P
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
Unit
WP/ACC: ±2.0 µA
Others: ±1.0
VIN = VSS to VCC
VCC = VCC max
ILI
Input Load Current (1)
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 12.5 V
35
µA
µA
VOUT = VSS to VCC , VCC = VCC max
±1.0
CE# = VIL, OE# = VIL, VCC = VCCmax
6
20
50
f = 1 MHz
CE# = VIL, OE# = VIL, VCC = VCCmax
f = 5 MHz
ICC1
VCC Active Read Current (1)
30
µA
CE# = VIL, OE# = VIL, VCC = VCCmax
60
0.2
25
90
10
30
f = 10 MHz
IIO2
VIO Non-Active Output
CE# = VIL, OE# = VIH
mA
mA
CE# = VIL, OE# = VIH, VCC = VCCmax
f = 5 MHz, Byte Mode
,
ICC1
VCC Active Read Current (1)
CE# = VIL, OE# = VIH, VCC = VCCmax
,
25
1
30
10
f = 5 MHz, Word Mode
CE# = VIL, OE# = VIH, VCC = VCCmax
f = 10 MHz
ICC2
VCC Intra-Page Read Current (1)
mA
CE# = VIL, OE# = VIH, VCC = VCCmax
f = 33 MHz
,
5
20
80
ICC3
VCC Active Erase/Program Current (2, 3) CE# = VIL, OE# = VIH, VCC = VCCmax
50
mA
µA
CE#, RESET# = VSS ± 0.3 V, OE# = VIH,
VCC = VCCmax
VIL = VSS + 0.3 V/-0.1V,
ICC4
VCC Standby Current
VCC Reset Current
1
1
5
5
VCC = VCCmax;
VIL = VSS + 0.3 V/-0.1V,
RESET# = VSS ± 0.3 V
ICC5
µA
VCC = VCCmax
VIH = VCC ± 0.3 V,
VIL = VSS + 0.3 V/-0.1V,
WP#/ACC = VIH
ICC6
Automatic Sleep Mode (4)
1
5
µA
WP#/ACC pin 10
20
80
CE# = VIL, OE# = VIH, VCC = VCCmax,
WP#/ACC = VIH
IACC
ACC Accelerated Program Current
mA
VCC pin
–0.1
50
Input Low Voltage (5)
Input High Voltage (5)
0.3 x VIO
V
V
VIL
0.7 x VIO
VIO + 0.3
12.5
VIH
Voltage for ACC Erase/
Program Acceleration
VHH
VCC = 2.7 –3.6 V
VCC = 2.7 –3.6 V
11.5
11.5
V
V
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VOL
12.5
Output Low Voltage (5)
Output High Voltage (5)
Low VCC Lock-Out Voltage (3)
IOL = 100 µA
IOH = -100 µA
0.15 x VIO
V
V
V
0.85 x VIO
2.3
VOH
VLKO
2.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH
.
2. ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
3. Not 100% tested.
4. Automatic sleep mode enables the lower power mode when addresses remain stable tor tACC + 30 ns.
5. VIO = 1.65–1.95 V or 2.7–3.6 V
6. VCC = 3 V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at 3V.
60
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Test Conditions
Note: Diodes are IN3064 or equivalent
3.3 V
Table 13. Test Specifications
Test Condition
All Speeds
1 TTL gate
Unit
2.7 kΩ
Output Load
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0–VIO
Input timing measurement
reference levels (See Note)
0.5VIO
V
V
Output timing measurement
reference levels
0.5 VIO
Note: Diodes are IN3064 or equivalent.
Figure 9. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO
.
Key to Switching W aveform s
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
VIO
0.5 VIO
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO
.
Figure 10. Input W aveform s and
Measurem ent Levels
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
61
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read-Only O perations-S29GL01GP, S29GL512P, S29GL256P
Parameter
Speed Options
JEDEC Std. Description
Test Setup
VIO = VCC = 3 V
100 110 110 Unit
100 110
100 110
100 110
ns
tAVAV
tAVQV
tELQV
tRC Read Cycle Time
Min
Max
Max
VIO = 1.8 V, VCC = 3 V
VIO = VCC = 3 V
110
ns
tACC Address to Output Delay (Note 2)
tCE Chip Enable to Output Delay (Note 3)
V
IO = 1.8 V, VCC = 3 V
VIO = VCC = 3 V
IO = 1.8 V, VCC = 3 V
110 ns
ns
V
110 ns
tPACC Page Access Time
Max
Max
Max
Max
25
25
25
35
20
20
30
35
ns
ns
ns
ns
tGLQV
tEHQZ
tGHQZ
tOE Output Enable to Output Delay
tDF Chip Enable to Output High Z (Note 1)
tDF Output Enable to Output High Z (Note 1)
Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
Min
0
0
ns
ns
ns
ns
Read
Output Enable Hold
Time (Note 1)
tOEH
Toggle and
Data# Polling
10
35
tCEH Chip Enable Hold Time Read
Notes:
1. Not 100% tested.
2. CE#, OE# = VIL
3. OE# = VIL
4. See Figure 9 and Table 13 for test specifications.
5. Unless otherwise indicated, AC specifications for 100 and 110 ns speed options are tested with VIO = VCC = 3 V. AC
specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
62
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
tRC
Addresses Stable
tACC
Addresses
CE#
tCEH
tRH
tRH
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 11. Read O peration Tim ings
Same Page
Amax:A2
A2:A0*
Ad
Aa
Ab
Ac
tPACC
tPACC
tPACC
tACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
* Figure 12 shows word mode. Addresses are A2:A1 for byte mode.
Figure 12. Page Read Tim ings
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
63
A d v a n c e I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Speed (Note 2)
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode
tReady
Max
Max
30
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode
tReady
10
µs
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
30
200
20
0
µs
ns
µs
ns
Reset High Time Before Read
RESET# Low to Standby Mode
RY/BY# Recovery Time
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 13. Reset Tim ings
64
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase and Program O perations-S29GL01GP, S29GL512P, S29GL256P
Speed
Options
Parameter
JEDEC Std. Description
Unit
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
100 110 Unit
tAVAV
tAVWL
tWC
tAS
Write Cycle Time (Note 1)
Address Setup Time
100 110 ns
0
15
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tASO Address Setup Time to OE# low during toggle bit polling
tAH Address Hold Time
tAHT Address Hold Time From CE# or OE# high during toggle bit polling
tWLAX
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Data Hold Time
45
0
tCEPH CE# High during toggle bit polling
20
20
0
tOEPH Output Enable High during toggle bit polling
tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low)
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
tWP
CE# Setup Time
CE# Hold Time
Write Pulse Width
0
0
35
30
240
tWPH Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program Operation
(Notes 2, 4)
Per Word
Per Word
Typ
Typ
15
µs
µs
tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program
Operation (Notes 2, 4)
13.5
Program Operation (Note 2)
Accelerated Programming Operation (Note 2)
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
tVHH VHH Rise and Fall Time (Note 1)
tVCS VCC Setup Time (Note 1)
Word
Word
Typ
Typ
Typ
Min
Min
Min
60
54
µs
µs
0.5
250
50
sec
ns
µs
ns
tBUSY Erase/Program Valid to RY/BY# Delay
90
Notes:
1. Not 100% tested.
2. See the table, “Erase and Program Operations-S29GL01GP, S29GL512P, S29GL256P” on page 65 for more
information.
3. For 1–32 words/1–64 bytes programmed.
4. Effective write buffer specification is based upon a 32-word/64-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 100 ns, and 110 ns speed options are tested with
V
= V
= 3 V. AC specifications for 110 ns speed options are tested with V = 1.8 V and V
= 3.0 V.
CC
IO
CC
IO
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
65
A d v a n c e I n f o r m a t i o n
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 14. Program O peration Tim ings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Notes:
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See Figure 9 and Table 13 for test specifications.
Figure 15. Accelerated Program Tim ing Diagram
66
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status.”
2. These waveforms are for the word mode
Figure 16. Chip/Sector Erase Operation Tim ings
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
67
A d v a n c e I n f o r m a t i o n
AC Characteristics
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ6–DQ0
Status Data
True
Valid Data
tBUSY
RY/BY#
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle.
2. tOE for data polling is 45 ns when VIO = 1.65 to 2.7 V and is 35 ns when VIO = 2.7 to 3.6 V
Figure 17. Data# Polling Tim ings (During Em bedded Algorithm s)
68
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ2 and DQ6
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence,
last status read cycle, and array data read cycle
Figure 18. Toggle Bit Tim ings (During Em bedded Algorithm s)
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erasing
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Suspend
Program
Complete
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system can use OE#
or CE# to toggle DQ2 and DQ6.
Figure 19. DQ 2 vs. DQ 6.
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
69
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program Operations-S29GL01GP, S29GL512P, S29GL256N
Parameter
Speed Options
JEDEC
tAVAV
tAVWL
Std.
tWC
Description
100
110
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
100
110
tAS
0
tASO
tAH
tAHT
tDS
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
0
tELAX
Address Hold Time From CE# or OE# high during toggle bit polling Min
tDVEH
tEHDX
Data Setup Time
Min
Min
Min
Min
45
0
tDH
Data Hold Time
tCEPH
tOEPH
CE# High during toggle bit polling
OE# High during toggle bit polling
20
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
CE# Pulse Width
CE# Pulse Width High
35
30
240
tCPH
tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program Operation
(Notes 2, 4)
Per Word
Per Word
Typ
Typ
15
µs
µs
Effective Accelerated Write Buffer Program
Operation (Notes 2, 4)
13.5
Program Operation (Note 2)
Accelerated Programming Operation (Note 2)
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Word
Word
Typ
Typ
Typ
60
54
µs
µs
0.5
sec
Notes:
1. Not 100% tested.
2. See the “AC Characteristics” section for more information.
3. For 1–32 words/1–64 bytes programmed.
4. Effective write buffer specification is based upon a 32-word/64-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 100 ns and 100 ns speed options are tested with VIO = VCC = 3 V.
AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
70
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure 20 indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. Waveforms are for the word mode.
is the data written to the device.
OUT
Figure 20. Alternate CE# Controlled W rite (Erase/Program )
O peration Tim ings
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
71
A d v a n c e I n f o r m a t i o n
Erase And Program m ing Perform ance
Typ
Max
Parameter
(Note 1)
(Note 2)
Unit
Comments
Sector Erase Time
0.5
3.5
512
sec
S29GL256P
S29GL512P
S29GL01GP
128
Excludes 00h programming
prior to erasure (Note 5)
Chip Erase Time
256
1024
2048
sec
512
Total Write Buffer Time
(Note 3)
240
µs
µs
Total Accelerated Effective
Write Buffer Programming
Time (Note 3)
200
Excludes system level
overhead (Note 6)
S29GL256P
S29GL512P
S29GL01GP
246
492
984
Chip Program Time
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 10,000 cycles, checkerboard
CC
pattern.
2. Under worst case conditions of 90°C, V = 3.0 V, 100,000 cycles.
CC
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See refer to Table 10 and Table 11 for command definitions for further information on command
definitions.
TSO P Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
TSOP
TSOP
TSOP
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
72
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Physical Dim ensions
TS056—56-Pin Standard Thin Sm all O utline Package (TSO P)
NOTES:
PACKAGE
TS 56
JEDEC
MO-142 (B) EC
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
SYMBOL
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.23
0.27
0.16
0.21
2
3
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.05
0.95
0.17
0.17
0.10
0.10
---
1.00
0.20
0.22
---
4
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
c1
c
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
---
D
19.80
18.30
20.00
18.40
20.20
18.50
D1
6
7
8
THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
E
e
13.90
14.00
14.10
0.50 BASIC
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
L
0.50
0˚
0.60
-
0.70
8˚
O
R
N
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
---
56
0.20
3160\38.10A
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
73
A d v a n c e I n f o r m a t i o n
Physical Dim ensions
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
74
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
A d v a n c e I n f o r m a t i o n
Revision Sum m ary
Revision A0 (O ctober 29, 2004)
Initial Release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product
names used in this publication are for identification purposes only and may be trademarks of their respective companies
October 29, 2004 S29GLxxxP_00A0
S29GLxxxP MirrorBitTM Flash Family
75
A d v a n c e I n f o r m a t i o n
76
S29GLxxxP MirrorBitTM Flash Family
S29GLxxxP_00A0 October 29, 2004
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