S71GL064NA0BHWOF0 [CYPRESS]
Memory IC,;S71GL-N Based MCPs
Stacked Multi-Chip Product (MCP)
Flash Memory and RAM
64/32 Megabit (4/2 M x 16-bit) CMOS 3.0 Volt-Only
Page Mode Flash Memory and
32/16/8/4 Megabit (2M/1M/512k/256k x 16-bit) Pseudo Static RAM
S71GL-N Based MCPs Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71GL-N_00
Revision 06
Issue Date January 13, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S71GL-N Based MCPs
S71GL-N_00_06 January 13, 2010
S71GL-N Based MCPs
Stacked Multi-Chip Product (MCP)
Flash Memory and RAM
64/32 Megabit (4/2 M x 16-bit) CMOS 3.0 Volt-Only
Page Mode Flash Memory and
32/16/8/4 Megabit (2M/1M/512k/256k x 16-bit) Pseudo Static RAM
Data Sheet (Advance Information)
Distinctive Characteristics
Packages
MCP Features
Power supply voltage of 2.7 to 3.1 volt
– 7 x 9 x 1.2 mm 56 ball FBGA
Operating Temperature
High performance
– –25°C to +85°C
– 90 ns access time (90 ns Flash, 70 ns pSRAM/SRAM)
– 25 ns page read times
General Description
The S71GL-N product series consists of S29GL-N Flash memory with pSRAM combinations defined as:
Flash Memory Density
32 Mb
64 Mb
4 Mb
8 Mb
S71GL032N40
S71GL032N80
S71GL032NA0
pSRAM Density
16 Mb
32 Mb
S71GL064NA0
S71GL064NB0
For detailed specifications, please refer to the individual data sheets.
Document
S29GL-N
Publication Identification Number (PID)
S29GL-N_00
pSRAM_33
4 Mb pSRAM Type 9
8 Mb pSRAM Type 9
16 Mb pSRAM Type 9/10
32 Mb pSRAM Type 8
32 Mb pSRAM Type 9
pSRAM_34
pSRAM_40
pSRAM_31
SPH032D970R1R
Publication Number S71GL-N_00
Revision 06
Issue Date January 13, 2010
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
1. Product Selector Guide
Flash Access time
(p)SRAM
density
(p)SRAM Access time
(ns)
Device-Model# (Note)
(p)SRAM type Package
(ns)
S71GL032N40-0K
S71GL032N40-0P
S71GL032N80-0K
S71GL032N80-0P
S71GL032NA0-0B
S71GL032NA0-0F
S71GL032NA0-0K
S71GL032NA0-0P
S71GL064NA0-0B
S71GL064NA0-0F
S71GL064NB0-0K
S71GL064NB0-0P
S71GL064NB0-0U
S71GL064NB0-0Z
4 Mb
8 Mb
pSRAM 9
TLC056
pSRAM 10
pSRAM 10
90
16 Mb
70
pSRAM 9
pSRAM 10
pSRAM 10
pSRAM 9
pSRAM 8
TSC056
32 Mb
Note
Please see the valid combinations table for the model# description.
4
S71GL-N Based MCPs
S71GL-N_00_06 January 13, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
2. MCP Block Diagram
VCC
f
VCC
CE1#f
WP#/ACC
RESET#
Flash-only Address
Flash
Shared Address
OE#
WE#
RY/BY#
DQ15 to DQ0
VCCS
VCC
pSRAM
IO15-IO0
CE1#s
UB#
CE#
UB#
LB#
LB#
CE2s
January 13, 2010 S71GL-N_00_06
S71GL-N Based MCPs
5
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
3. Connection Diagram
56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend
A2
A7
A3
LB#
B3
A4
WP/ACC
B4
A5
WE#
B5
A6
A8
A7
A11
B7
B1
B2
B6
B8
A15
C8
Shared
(Note 1)
A3
C1
A6
UB#
C3
RST#f
C4
CE2s
C5
A19
C6
A12
C7
C2
A2
A5
A18
D3
RY/BY#
A20
A9
A13
D7
A21
D8
Flash only
RAM only
D1
D2
D6
A1
A4
A17
E3
A10
E6
A14
E7
RFU
E8
E1
E2
A0
VSS
F2
DQ1
F3
DQ6
F6
RFU
F7
A16
F8
F1
F4
DQ3
G4
F5
DQ4
G5
Reserved for
Future Use
CE1#f
G1
OE#
G2
DQ0
H2
DQ9
G3
DQ13
G6
DQ15
G7
RFU
G8
CE1#s
DQ10
H3
VCCf
H4
VCCs
H5
DQ12
H6
DQ7
H7
VSS
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
Note
May be shared depending on density.
MCP
Flash-only Addresses
Shared Addresses
A19-A0
S71GL032NA0
S71GL032N80
S71GL032N40
S71GL064NB0
S71GL064NA0
A20
A20-A19
A20-A18
A21
A18-A0
A17-A0
A20-A0
A21-A20
A19-A0
3.1
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
6
S71GL-N Based MCPs
S71GL-N_00_06 January 13, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
4. Pin Description
Pin
A21–A0
DQ15–DQ0
CE1#f
Description
22 Address Inputs (Common and Flash only) (A20-A0 for the S71GL032N)
16 Data Inputs/Outputs (Common)
Chip Enable (Flash)
CE1#s
CE2s
Chip Enable 1 (pSRAM/SRAM)
Chip Enable 2 (pSRAM/SRAM)
OE#
Output Enable (Common)
WE#
Write Enable (Common)
RY/BY#
UB#
Ready/Busy Output (Flash 1)
Upper Byte Control (pSRAM/SRAM)
Lower Byte Control (pSRAM/SRAM)
Hardware Reset Pin, Active Low (Flash)
Hardware Write Protect/Acceleration Pin (Flash)
LB#
RESET#
WP#/ACC
Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage
supply tolerances)
VCC
f
VCCS
VSS
pSRAM/SRAM Power Supply
Device Ground (Common)
Not Connected. No device internal signal is connected to the package connector nor is there any
future plan to use the connector for a signal. The connection may safely be used for routing space for
a signal on a Printed Circuit Board (PCB).
NC
January 13, 2010 S71GL-N_00_06
S71GL-N Based MCPs
7
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
5. Ordering Information
The order number is formed by a valid combinations of the following:
S71GL
064
N
A0
BF
W
0
Z
0
PACKING TYPE
0
2
3
= Tray
= 7” Tape and Reel
= 13” Tape and Reel
MODEL NUMBER
See the Valid Combinations table.
PACKAGE MODIFIER
0
= 7 x 9 mm, 1.2 mm height, 56 balls
TEMPERATURE RANGE
= Wireless (-25°C to +85°C)
W
PACKAGE TYPE
BF = Fine-pitch BGA Lead (Pb)-free package
BH = Fine-pitch BGA Lead (PB)-free, Low-Halogen package
pSRAM / SRAM DENSITY
B0 = 32 Mb pSRAM
A0 = 16 Mb pSRAM
40 = 4 Mb pSRAM
80 = 8 Mb pSRAM
PROCESS TECHNOLOGY
N
= 110 nm, MirrorBit® Technology
FLASH DENSITY
064 = 64Mb
032 = 32Mb
PRODUCT FAMILY
S71GL Multi-chip Product (MCP)
3.0-volt Page Mode Flash Memory and RAM
Table 5.1 Valid Combinations
S71GL064N Valid Combinations
(p)SRAM Type/
Access Time
(ns)
Speed Options (ns)/Boot
Sector Option
Package
Marking
Base Ordering
Part Number
Package &
PackageModifier/Model
Number
Packing Type
Temperature
0K
0P
0K
0P
0B
0F
0K
0P
0B
0F
0K
0P
0U
0Z
90 / Bottom Boot Sector
90 / Top Boot Sector
90 / Bottom Boot Sector
90 / Top Boot Sector
90 / Bottom Boot Sector
90 / Top Boot Sector
90 / Bottom Boot Sector
90 / Top Boot Sector
90 / Bottom Boot Sector
90 / Top Boot Sector
90 / Bottom Boot Sector
90 / Top Boot Sector
90 / Bottom Boot Sector
90 / Top Boot Sector
S71GL032N40
S71GL032N80
S71GL032NA0
S71GL032NA0
S71GL064NA0
pSRAM 9 / 70
pSRAM 9 / 70
pSRAM 10 / 70
pSRAM 9 / 70
pSRAM 10 / 70
pSRAM 9 / 70
pSRAM 8 / 70
BFW, BHW
TLC056
BHW
BHW
BHW
0, 2, 3 (1)
S71GL064NB0
S71GL064NB0
S71GL064NB0
S71GL064NB0
TSC056
BFW, BHW
Note
1. Type 0 is standard. Specify other options as required.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
8
S71GL-N Based MCPs
S71GL-N_00_06 January 13, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6. Physical Dimensions
6.1
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package
A
D1
D
eD
0.15
(2X)
C
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
H
G
F
E
D
C
B
A
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
56X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
TLC 056
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.20
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
5.60 BSC.
5.60 BSC.
8
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3348 \ 16-038.22a
January 13, 2010 S71GL-N_00_06
S71GL-N Based MCPs
9
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
6.2
TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package
D1
A
D
eD
0.15
(2X)
C
8
7
6
5
4
3
2
1
SE
7
E
B
E1
eE
H
G
F
E
D
C
B
A
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
56X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TSC 056
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
9.00 mm x 7.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
1.20
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
9.00 BSC.
7.00 BSC.
5.60 BSC.
5.60 BSC.
8
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A1,A8,D4,D5,E4,E5,H1,H8
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3427 \ 16-038.22
10
S71GL-N Based MCPs
S71GL-N_00_06 January 13, 2010
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
7. Revision History
Section
Description
Revision 01 (May 14, 2007)
Initial release.
Revision 02 (June 19, 2007)
Global
Editorial changes to valid combinations table
Added Low-Halogen option to package type.
Added pSRAM Type 8, 90 nm
Revision 03 (March 25, 2008)
Ordering Information
Revision 04 (October 31, 2008)
General Description
Added pSRAM Type 8, 90 nm
Product Selector Guide
Changed S71GL064Nxx-xx package to TSC056
Ordering Information
Physical Dimensions
Revision 05 (January 20, 2009)
Global
Changed S71GL064Nxx-xx package to TSC056
Added TSC056
Added OPNs S71GL032NA0BHW0B/0F and S71GL064NA0BHW0B/0F
Added pSRAM Type 10
General Description
Revision 06 (January 13, 2010)
General Description
Updated Table with current pSRAM offerrings
Removed pSRAM Type 7 MCPs
Global
Added 32 Mb and 64 Mb pSRAM Type 9 MCPs
January 13, 2010 S71GL-N_00_06
S71GL-N Based MCPs
11
D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2007-2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
12
S71GL-N Based MCPs
S71GL-N_00_06 January 13, 2010
相关型号:
S71GL064NB0BFW0U2
Memory Circuit, 4MX16, CMOS, PBGA56, 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56
CYPRESS
©2020 ICPDF网 联系我们和版权申明