S99-50214 [CYPRESS]
Flash, 32MX16, 80ns, DIE-62;
| 型号： | S99-50214 |
| 厂家： | 
CYPRESS |
| 描述： | Flash, 32MX16, 80ns, DIE-62 内存集成电路 |
| 文件： | 总59页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions
at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly
interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion,
Inc." products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future
revisions will occur when appropriate, and changes will be noted in a document history page.
Continuity of Ordering Part Numbers
Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed
in this document.
For More Information
Please contact your local sales office for additional information about Cypress products and solutions.
PRELIMINARY
S99-50214
512 Mbit (32M x 16 bit) 1.8 V
MirrorBit® Flash
Features
Single 1.8 V read/program/erase
Hardware (WP#) protection of top and bottom sectors
Dual boot sector configuration (top and bottom)
Handshaking by monitoring RDY
Wafer Form
90 nm MirrorBit® Technology
Simultaneous Read/Write operation with zero latency
Random page read access mode of 8 words with 20 ns intra page
access time
Low VCC write inhibit
32 Word / 64 Byte Write Buffer
Write operation status bits indicate program and erase operation
Sixteen-bank architecture consisting of
completion
32/16/8 Mwords for 512/256/128P, respectively
Suspend and Resume commands for Program and Erase
Four 16 Kword sectors at both top and bottom of memory array
510/254/126 64 Kword sectors (WS512/256/128P)
operations
Unlock Bypass program command to reduce programming time
Asynchronous program operation
Secured Silicon Sector region consisting of 128 words each for
factory and 128 words for customer
Support for Common Flash Interface (CFI)
Command set compatible with JEDEC (42.4) standard
Please note that wafer form flash does not guarantee conformance to the AC/DC, cycling and data retention specifications
mentioned in the standard data sheet.
Spansion has not qualified these products for shipping in this post wafer sort condition so therefore makes no reliability
guarantees.
General Description
The Spansion S99-50214 are Mirrorbit flash products fabricated on 90 nm process technology. These flash devices are capable of
performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins.
These products can operate up to 104 MHz and use a single VCC of 1.8 V that makes them ideal for today’s demanding wireless
applications requiring higher density, better performance and lowered power consumption.
Performance Characteristics
Read Access Times (typical values)
Current Consumption (typical values)
Simultaneous Operation 104 MHz
Max OE# Access Time, ns (t
)
7.6
80
40 mA
20 mA
20 µA
OE
Max. Asynch. Access Time, ns (t
)
Program
ACC
Standby Mode
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V ) Per Word
40 µs
9.4 µs
6 µs
CC
Effective Write Buffer Programming (V
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
) Per Word
ACC
350 ms
600 ms
Cypress Semiconductor Corporation
Document Number: 002-01310 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 16, 2015
PRELIMINARY
S99-50214
Table of Contents
Features................................................................................. 2
General Description ............................................................. 2
Performance Characteristics............................................... 2
14.6 Switching Waveforms ................................................... 40
14.7 Power-up/Initialization................................................... 41
14.8 CLK Characterization.................................................... 41
14.9 AC Characteristics........................................................ 42
14.10Erase and Programming Performance......................... 51
1.
2.
3.
4.
5.
6.
7.
8.
Ordering Information................................................... 4
DC Operating Conditions............................................ 4
Input/Output Descriptions & Logic Symbol .............. 4
Block Diagrams............................................................ 5
Product Selector Guide............................................... 5
Die Pad Locations........................................................ 6
Physical Specifications............................................... 7
Special Handling Instructions .................................... 8
15. Appendix A – Software Interface Reference ............ 51
16. Appendix B – Errata.................................................... 56
16.1 Erase Suspend ............................................................. 56
16.2 PPB - Persistent Protection Bits ................................... 56
16.3 Asynchronous Read Access Time................................ 56
16.4 Synchronous Burst Read Operation............................. 56
16.5 Autoselect..................................................................... 56
16.6 Initial Memory Array State............................................. 56
16.7 Accelerated Mode......................................................... 56
16.8 Factory Secured Silicon Sector..................................... 56
16.9 AC / DC parameters...................................................... 56
16.10Boot Sector Configurations........................................... 56
8.1 Processing ..................................................................... 8
8.2 Storage .......................................................................... 8
9.
Product Overview ........................................................ 8
17. Appendix C – Additional Resources......................... 57
18. Revision History.......................................................... 58
9.1 Memory Map.................................................................. 8
10. Device Operations ....................................................... 9
10.1 Device Operation Table ................................................. 9
10.2 Asynchronous Read..................................................... 10
10.3 Page Mode Read......................................................... 10
10.4 Autoselect .................................................................... 11
10.5 Program/Erase Operations .......................................... 13
10.6 Simultaneous Read/Program or Erase ........................ 28
10.7 Writing Commands/Command Sequences.................. 28
10.8 Handshaking................................................................ 28
10.9 Hardware Reset........................................................... 28
10.10Software Reset............................................................ 29
11. Advanced Sector Protection/Unprotection ............. 30
11.1 Lock Register............................................................... 30
11.2 Dynamic Protection Bits............................................... 31
11.3 Password Protection Method....................................... 32
11.4 Hardware Data Protection Methods............................. 33
12. Power Conservation Modes...................................... 34
12.1 Standby Mode.............................................................. 34
12.2 Automatic Sleep Mode................................................. 35
12.3 Hardware RESET# Input Operation............................. 35
12.4 Output Disable (OE#)................................................... 35
13. Secured Silicon Sector Flash Memory Region ....... 35
13.1 Factory Secured Silicon Sector.................................... 36
13.2 Customer Secured Silicon Sector................................ 36
13.3 Secured Silicon Sector Entry/Exit
Command Sequences ................................................. 36
14. Electrical Specifications............................................ 38
14.1 Absolute Maximum Ratings ......................................... 38
14.2 Operating Ranges........................................................ 38
14.3 DC Characteristics....................................................... 38
14.4 Test Conditions............................................................ 39
14.5 Key to Switching Waveforms ....................................... 40
Document Number: 002-01310 Rev. *A
Page 3 of 59
PRELIMINARY
S99-50214
1. Ordering Information
Device Number/Description
S99-50214 (S29WS512P in 200 mm wafer)
S99-50214-01 (S29WS512P in 300 mm wafer)
512 Megabit (8M x 16-Bit) CMOS Flash Memory
1.8 Volt-only Program and Erase
Temperature Range: -25°C to +85°C
Shipped in wafer jar
2. DC Operating Conditions
VCC (Supply Voltage)
1.8V Typical
Wireless Operating Temperature
–25°C to +85°C
3. Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
–A0
Type
Input
Description
A
Address lines (Amax = 24)
MAX
DQ15–DQ0
CE#
I/O
Data input/output.
Input
Chip Enable. Asynchronous relative to CLK.
OE#
Input
Output Enable. Asynchronous relative to CLK.
WE#
Input
Write Enable.
V
Supply
Supply
Supply
No Connect
Output
Device Power Supply
CC
V
Device Input/Output Power Supply (Must be ramped simultaneously with V
)
CC
CCQ
V
Ground.
SS
NC
Not connected internally.
RDY
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter. Should be at V or V while in asynchronous mode.
CLK
Input
IL
IH
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode, causes
starting address to be latched at the next active clock edge.
AVD#
Input
When high, device ignores address inputs.
RESET#
WP#
Input
Input
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At V , disables program and erase functions in the four outermost sectors. Should be at
IL
V
for all other conditions.
IH
Acceleration Input. At V , accelerates programming; automatically places device in unlock bypass
HH
ACC
RFU
Input
mode. At V , disables all program and erase functions. Should be at V for all other conditions.
IL
IH
Reserved
Reserved for future use (see MCP look-ahead pinout for use with MCP).
Document Number: 002-01310 Rev. *A
Page 4 of 59
PRELIMINARY
S99-50214
4. Block Diagrams
V
CC
V
SS
Bank Address
DQ15–DQ0
V
CCQ
Bank 0
AMAX–A0
X-Decoder
OE#
Bank Address
DQ15–DQ0
Bank 1
WP#
ACC
X-Decoder
AMAX–A0
STATE
CONTROL
&
COMMAND
REGISTER
RESET#
WE#
DQ15–DQ0
Status
CEx#
AVD#
RDY
Control
AMAX–A0
DQ15–DQ0
AMAX–A0
X-Decoder
DQ15–DQ0
Bank (n-1)
Bank Address
X-Decoder
Bank (n)
Bank Address
DQ15–DQ0
Notes:
1. AMAX-A0 = A24-A0
2. n = 15
5. Product Selector Guide
Part Number:
S99-50214 (200 mm wafer) / S99-50214-01 (300 mm wafer)
Voltage:
V
CC = 1.8V Typical
Document Number: 002-01310 Rev. *A
Page 5 of 59
PRELIMINARY
S99-50214
6. Die Pad Locations
32
1
y
x
(0,0)
33
62
Table 6.1 Die Pad (Sheet 1 of 2)
Pad #
1
Pad Name
VSS
A16
X[Mils]
2951.73
2652.985
2529.985
2406.985
2283.985
2012.85
1889.85
1766.85
1643.85
1520.85
1227.635
1104.635
981.635
858.635
735.635
602.8
Y[Mils]
X[µm]
Y[µm]
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
116.21
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
2
104.448
99.606
94.763
89.921
79.246
74.404
69.561
64.719
59.876
48.332
43.49
3
A22
4
A21
5
A15
6
A14
7
A13
8
A12
9
A11
10
11
12
13
14
15
16
17
18
19
20
A10
A9
A8
A19
38.647
33.805
28.962
23.732
17.589
5.998
WP#
ADV#
VCC
VSS
CE#
RESET#
ACC
446.76
152.35
-789.785
-930.805
-31.094
-36.646
Document Number: 002-01310 Rev. *A
Page 6 of 59
PRELIMINARY
S99-50214
Table 6.1 Die Pad (Sheet 2 of 2)
Pad #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Pad Name
WE#
A23
X[Mils]
-1211.075
-1357.285
-1628.885
-1751.885
-1874.885
-1997.885
-2120.885
-2407.68
-2530.68
-2653.68
-2776.68
-2912.04
-2748.47
-2538.355
-2328.24
-2179.015
-2029.78
-1851.26
-1573.95
-1377.485
-1228.25
-1079.025
-929.79
Y[Mils]
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
3561.465
-3517
X[µm]
-47.68
Y[µm]
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
140.215
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-138.465
-53.436
-64.129
-68.972
-73.814
-78.657
-83.499
-94.791
-99.633
-104.476
-109.318
-114.647
-108.207
-99.935
-91.663
-85.788
-79.913
-72.884
-61.967
-54.232
-48.356
-42.481
-36.606
-23.185
-18.343
-13.5
A20
A18
A17
A7
A6
A5
A4
A3
A24
VCC
RDY
DQ0
DQ8
DQ1
DQ9
VSS
VCC
DQ2
DQ10
DQ3
DQ11
VSS
VSS
CLK
VSS
VCC
DQ4
DQ12
DQ5
DQ13
VCC
VSS
DQ6
DQ14
DQ7
DQ15
A0
-3517
-3517
-3517
-3517
-3517
-3517
-3517
-3517
-3517
-3517
-588.91
-3517
-465.91
-3517
-342.91
-3517
109
-3517
4.291
231.24
-3517
9.104
408.5
-3517
16.083
21.958
27.833
33.708
40.773
45.56
557.735
706.96
-3517
-3517
856.195
1035.635
1157.235
1506.97
1656.205
1866.32
2076.435
2418.385
2541.385
2664.385
2944.72
-3517
-3517
-3517
-3517
59.33
-3517
65.205
73.477
81.749
95.212
100.055
104.897
115.934
-3517
-3517
-3517
A1
-3517
A2
-3517
OE#
-3517
7. Physical Specifications
Description
Die Dimensions
Die Thickness
Specification
6.430 mm x 7.470 mm (including scribe)
725 µm
200 mm
Wafer Size
Document Number: 002-01310 Rev. *A
Page 7 of 59
PRELIMINARY
S99-50214
Description
Specification
76 µm x 76 µm
62
Bond Pad Size
Pads Per Die
8. Special Handling Instructions
8.1
Processing
Do not expose wafers to ultraviolet light or process them at temperatures greater than 250°C. Failure to adhere to these handling
instructions results in irreparable damage to the devices. For best yield, Spansion® recommends assembly in a Class 10K clean
room with 30% to 60% relative humidity.
8.2
Storage
Store at a maximum temperature of 30°C in a nitrogen-purged cabinet or vacuum-sealed bag. Observe all standard ESD handling
procedures.
9. Product Overview
The S99-50214 family consists of 512 Mbit, 1.8 volts-only, simultaneous read/write Flash device optimized for today’s wireless
designs that demand a large storage array, rich functionality, and low power consumption.
These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend
functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One
Time Programmable.
9.1
Memory Map
The S99-50214 Mbit devices consist of 16 banks organized as shown in Table 9.1.
Table 9.1 S99-50214 Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank
Address Range
000000h–003FFFh
004000h–007FFFh
008000h–00BFFFh
00C000h–00FFFFh
010000h–01FFFFh
Notes
32
32
SA000
SA001
SA002
SA003
SA004
Sector Starting Address –
Sector Ending Address
4
32
4 MB
32
0
128
Sector Starting Address –
Sector Ending Address
(See Note)
31
128
SA034
1F0000h–1FFFFFh
Document Number: 002-01310 Rev. *A
Page 8 of 59
PRELIMINARY
S99-50214
Table 9.1 S99-50214 Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Bank
1
Address Range
Notes
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
32
32
32
32
32
32
32
32
32
32
32
32
32
32
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SA035–SA066
SA067–SA098
SA099–SA130
SA131–SA162
SA163–SA194
SA195–SA226
SA227–SA258
SA259–SA290
SA291–SA322
SA323–SA354
SA355–SA386
SA387–SA418
SA419–SA450
SA451–SA482
SA483
200000h–3FFFFFh
2
3
4
5
6
First Sector, Starting Address –
Last Sector, Ending Address
(See Note)
7
E00000h–FFFFFFh
1000000-11FFFFF
8
9
10
11
12
13
14
1C00000h-1DFFFFFh
1E00000h-1E0FFFFh
Sector Starting Address –
Sector Ending Address
(See Note)
31
128
SA513
SA514
SA515
SA516
SA517
1FE0000h-1FEFFFFh
1FF0000h-1FF3FFFh
1FF4000h-1FF7FFFh
1FF8000h-1FFBFFFh
1FFC000h-1FFFFFFh
4 MB
15
Sector Starting Address –
Sector Ending Address
4
32
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA005–SA033) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
pattern xx00000h–xxFFFFh.
10. Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash
devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command
registers (see Table 15.1 on page 51 and Table 15.2 on page 54). The command register itself does not occupy any addressable
memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs
dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the
device in an unknown state, in which case the system must write the reset command to return the device to the reading array data
mode.
10.1 Device Operation Table
The device must be setup appropriately for each operation. Table 10.1 describes the required state of each control pin for any
particular operation.
Document Number: 002-01310 Rev. *A
Page 9 of 59
PRELIMINARY
S99-50214
Table 10.1 Device Operations
Operation
CE#
OE#
WE#
CLK
AVD#
Amax–A0
DQ15–0
RDY
RESET#
Asynchronous Read
- Addresses Latched
Output
Valid
L
L
H
X
Addr In
H
H
Asynchronous Read
AVD# Steady State
Output
Valid
L
L
H
X
L
Addr In
H
H
Input
Valid
Asynchronous Write
L
H
X
H
X
X
X
X
X
L
X
X
Addr In
H
H
H
Standby (CE#)
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Hardware Reset
Legend:
L = Logic 0, H = Logic 1, X = can be either V or V .,
= rising edge,
= high to low,
= toggle.
IL
IH
Note:
Address is latched on the rising edge of clock.
10.2 Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at
a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its
outputs to arrive asynchronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware reset. To read data from the memory
array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The
rising edge of AVD# latches the address, preventing changes to the address lines from effecting the address being accessed. Data
is output on DQ15-DQ0 pins after the access time (tACC) has elapsed from the falling edge of AVD#, or the last time the address
lines changed while AVD# was low.
10.3 Page Mode Read
The device is capable of fast page mode read. This mode provides fast (tPACC) random read access speed for locations within a
page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an
asynchronous operation with the microprocessor supplying the specific word location. It does not matter if AVD# stays low or
toggles. However, the address input must be always valid and stable if AVD# is low during the page read.
The random or initial page access is tACC or tCE (depending on how the device was accessed) and subsequent page read accesses
(as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted
(=VIH), the reassertion of CE# for subsequent access has access time of tCE. Here again, CE# selects the device and OE# is the
output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained
by keeping Amax–A3 constant and changing A2–A0 to select the specific word within that page.
Table 10.2 Page Select
Word
A2
0
A1
0
A0
0
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Document Number: 002-01310 Rev. *A
Page 10 of 59
PRELIMINARY
S99-50214
10.4 Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended
for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes
can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order
address bits (see Table 10.3 on page 11). The remaining address bits are don't care. The most significant four bits of the address
during the third write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed
normally for data read without exiting the Autoselect mode.
To access the Autoselect codes, the host system must issue the Autoselect command.
The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-
read mode.
The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not
support simultaneous operations or burst mode.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was
previously in Erase Suspend).
See Table 15.1 on page 51 for command sequence details.
Table 10.3 Autoselect Addresses
Description
Address
Read Data
Manufacturer ID
Word 00
(BA) + 00h
0001h
Device ID,
Word 01
(BA) + 01h
(SA) + 02h
(BA) + 03h
(BA) + 0Eh
(BA) + 0Fh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
Sector Lock/Unlock
Word 02
Indicator Bits
Word 03
Device ID,
Word 0E
Device ID,
Word 0F
Software Functions and Sample Code
Table 10.4 Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Write
Byte Address
BA+AAAh
BA+555h
Word Address
BA+555h
Data
Unlock Cycle 1
Unlock Cycle 2
Autoselect Command
0x00AAh
0x0055h
0x0090h
Write
BA+2AAh
Write
BA+AAAh
BA+555h
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Table 10.5 Autoselect Exit
Cycle
Operation
Byte Address
xxxxh
Word Address
Data
Unlock Cycle 1
Write
xxxxh
0x00F0h
Notes:
1. Any offset within the device works.
2. BA = Bank Address. The bank address is required.
3. base = base address.
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low
Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software
development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef volatile unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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10.5 Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following
sections.
During asynchronous write operations, addresses are latched on the rising edge of AVD# or falling edge of WE# while data is
latched on the 1st rising edge of WE#, or CE# whichever comes first.
Note the following:
When the Embedded Program/Erase algorithm is complete, the device returns to the read mode.
The system can determine the status of the Program/Erase operation. Refer to Write Operation Status on page 24 for
further information.
While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt will be ignored as only an erase
operation can covert a 0 to a 1. For example:
Old Data = 0011
New Data = 0101
Result = 0001
Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except the Program/
Erase Suspend commands.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a Program/Erase operation is in progress.
A hardware reset and/or power removal immediately terminates the Program/Erase operation and the Program/Erase
command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries only for single word programming operation. See
Write Buffer Programming on page 15 when using the write buffer.
10.5.1
Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to
program an individual Flash address. While the single word programming method is supported by all Spansion devices, in general it
is not recommended for devices that support Write Buffer Programming. See Table 15.1 on page 51 for the required bus cycles and
Figure 10.1 for the flowchart.
When the Embedded Program algorithm is complete, the device returns to the read mode and addresses are no longer latched. The
system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for
information on these status bits.
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Figure 10.1 Single Word Program
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= completed
Error condition
No
(Exceeded Timing Limits)
Operation successfully completed
Operation failed
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Software Functions and Sample Code
Table 10.6 Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Program
Write
Write
Write
Write
Base + 555h
Base + 2AAh
Base + 555h
Word Address
0055h
00A0h
Data Word
Note:
Base = Base Address.
The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*/
*/
*/
*/
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
10.5.2
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster
effective word programming time than the standard word programming algorithms. The Write Buffer Programming command
sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming will occur. At this point, the system writes the number of word
locations minus 1 that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the device
how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm
command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (NOTE: the size
of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to
program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.)
The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer. It is to be noted that
Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of
the selected write-buffer addresses, the operation aborts after the Write to Buffer command is executed. Also, the starting address
must be the least significant address. All subsequent addresses and write buffer data must be in sequential order.
The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed,
and selects the write-buffer-page address. All subsequent address/data pairs must be in sequential order.
After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write
buffer locations must be loaded in sequential order starting with the lowest address in the page. Note that if the number of address/
data pairs do no match the word count, the program buffer to flash command is ignored.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data
load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command will be programmed into
the device. It is the software’s responsibility to comprehend ramifications of loading a write-buffer location more than once. The
counter decrements for each data load operation, NOT for each unique write-buffer-address location.
Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash
command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The
device will then go busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the
write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue
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the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5,
DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming.
The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon
successful completion of the Write Buffer Programming operation, the device will return to READ mode.
The Write Buffer Programming Sequence is ABORTED in the following ways:
Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is not valid in this
condition).
Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write
buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
Software Functions and Sample Code
Table 10.7 Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Word Address
Base + 555h
Base + 2AAh
Data
00AAh
1
2
3
4
Unlock
Write
0055h
Write Buffer Load Command
Write Word Count
Write
Program Address
Program Address
0025h
Write
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Last
Load Buffer Word N
Write Buffer to Flash
Write
Write
Program Address, Word N
Sector Address
Word N
0029h
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be
from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */
/* NOTES: Write buffer programming limited to 16 words. */
/* All addresses to be written to the flash in */
/* one operation must be within the same write buffer. */
/* A write buffer begins at addresses evenly divisible */
/* by 0x20.
UINT16 i; */
UINT16 *src = source_of_data; /* address of source data */
UINT16 *dst = destination_of_data; /* flash destination address */
UINT16 wc = words_to_program -1; /* word count (minus 1) */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */
*( (UINT16 *)dst ) = wc; /* write word count (minus 1) */
for (i=0;i<=wc;i++)
{
*dst++ = *src++; /* ALL dst MUST BE in same Write Buffer */
}
*( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */
/* poll for completion */
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
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*( (UINT16 *)base_addr + 0x555 ) = 0x00F0; /* write buffer abort reset */
Figure 10.2 Write Buffer Programming Operation
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Program Address Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
29h
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Done?
No
Error?
Yes
No
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
10.5.3
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer
programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the programming operation within tPSL (program suspend latency). Bank address
needs to be provided when writing the Program Suspend Command. The status bits are undefined during the tPSL period. To verify
that the device is in the suspended state, either:
wait until after tPSL to check the status bits
perform a read and check that the status bits return array data
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check whether any Autoselect commands are accepted.
After the programming operation has been suspended, the system can read array data from any non-suspended sector. The
Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector
area, then user must use the proper command sequences to enter and exit this region.
The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows
reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the
Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect
on page 11 for more information.
After the Program Resume command is written, the device reverts to programming. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status
on page 24 for more information.
Note: While a program operation can be suspended and resumed multiple times, a minimum delay of tPRS (Program Resume to
Suspend) is required from resume to the next suspend.
The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and
continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend
command can be written after the device has resumed programming.
Software Functions and Sample Code
Table 10.8 Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 10.9 Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Byte Address
Bank Address
Word Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
/* write resume command
*/
10.5.4
Sector Erase
The sector erase function erases one or more sectors in the memory array (see Table 15.1 on page 51 and Figure 10.3
on page 20). The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful sector erase, all
locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional
sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and
the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any
sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than
Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to
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determine if the sector erase timer has timed out (see DQ3: Sector Erase Timeout State Indicator on page 27). The time-out begins
from the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note
that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can
determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status
on page 24 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Figure 10.3 on page 20 illustrates the algorithm for the erase operation. Refer to Program/Erase Operations on page 13 for
parameters and timing diagrams.
Software Functions and Sample Code
Table 10.10 Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Sector Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Sector Address
Data
00AAh
0055h
0080h
00AAh
0055h
0030h
1
2
3
4
5
6
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Sector Erase Command
Write
Unlimited additional sectors may be selected for erase; command(s) must be written within t
.
SEA
The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
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Figure 10.3 Sector Erase Operation
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
Yes
Last Sector
Selected?
No
• No limit on number of sectors
Poll DQ3.
DQ3 = 1?
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Perform Write Operation
Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
Notes:
1. See Table 15.1 on page 51 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timeout.
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10.5.5
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 15.1 on page 51. These commands invoke the Embedded Erase
algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all
locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations.
Table 15.1 shows the address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The
system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to Write Operation Status on page 24 for
information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the
erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array
data, to ensure data integrity.
Software Functions and Sample Code
Table 10.11 Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Base + 555h
Data
00AAh
0055h
0080h
00AAh
0055h
0010h
1
2
3
4
5
6
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Chip Erase Command
Write
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*/
*/
*/
/* write chip erase command
*/
10.5.6
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,
any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the
sector erase operation, after the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the tSEA time-out period has expired and during the sector erase operation, the
device requires a minimum of tESL (erase suspend latency) to suspend the erase operation. The status bits are undefined during the
tESL period. To verify that the device is in the suspended state, either:
wait until after tESL to check the status bits
perform a read and check that the status bits return array data
check whether any Autoselect commands are accepted
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or
program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any
address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2
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together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 10.19 on page 28 for information on these
status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation.
Note: While an erase operation can be suspended and resumed multiple times, a minimum delay of tERS (Erase Resume to
Suspend) is required from resume to the next suspend.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to Write Buffer Programming
on page 15 and Autoselect on page 11 for details.
To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-
suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase
Suspend command can be written after the chip has resumed erasing.
Software Functions and Sample Code
Table 10.12 Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
00B0h
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 10.13 Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Byte Address
Bank Address
Word Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
10.5.7
Unlock Bypass
The unlock bypass feature allows the system to primarily program faster than using the standard program command sequence, and
it is not intended for use during erase. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence
contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is
programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. The erase command sequences are four cycles in length instead of
six cycles. Table 15.1 on page 51 shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program, and Unlock Bypass Reset commands are valid. To exit the
unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode.
The device offers accelerated program operations through the ACC input. When the system asserts VHH on this input, the device
automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the ACC input to accelerate the operation.
Refer to Erase/Program Timing on page 46 for parameters, and Figure 14.13 on page 47 for timing diagrams.
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Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Spansion Low
Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software
development guidelines.
Table 10.14 Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
00AAh
0055h
0020h
1
2
3
Unlock
Write
Entry Command
Write
/* Example: Unlock Bypass Entry Command
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
*/
*/
*/
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
Table 10.15 Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Write
Byte Address
Base + xxxh
Word Address
Base +xxxh
Data
1
2
Program Setup Command
Program Command
00A0h
Write
Program Address
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
/* write data to be programmed
*/
*/
*( (UINT16 *)pa )
= data;
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again.
*/
Table 10.16 Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Reset Cycle 1
Reset Cycle 2
Operation
Write
Byte Address
Base + xxxh
Base + xxxh
Word Address
Base +xxxh
Data
0090h
0000h
1
2
Write
Base +xxxh
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
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10.5.8
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following subsections describe the
function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or
completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command
sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer when write buffer
programming is used. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page
returns false status information. Similarly, attempting to program 1 over a 0 does not return valid Date# information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. The system must provide the program address to read valid status
information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then
that bank returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if
the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of
the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an
address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ1 while
Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Even if
the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ1 may be still invalid.
Valid data on DQ7-DQ1 appears on successive read cycles.
See the following for more information: Table 10.19 on page 28, shows the outputs for Data# Polling on DQ7. Figure 10.4
on page 25, shows the Data# Polling algorithm; and Figure 14.16 on page 49, shows the Data# Polling timing diagram.
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Figure 10.4 Write Operation Status Flowchart
START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3=
valid data?
NO
NO
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
DEVICE
ERROR
TIMEOUT
NO
(Note 4)
NO
YES
Read3
DQ1=1?
(Note 2)
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Read3
DQ1=1
YES
Write Buffer
AND DQ7 ≠
Valid Data?
Operation
Failed
NO
Device BUSY,
Re-Poll
Notes:
1. DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2. DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3. May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation.
4. Write buffer error if DQ1 of last read =1.
5. Invalid state, use RESET command to exit operation.
6. Valid data is the data that is intended to be programmed or all 1's for an erase operation.
7. Data polling algorithm valid for all operations except advanced sector protection.
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DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the
operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all
sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is
written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete.
See the following for additional information: Figure 10.4 on page 25, Figure 14.17 on page 49, and Table 10.18 on page 26 and
Table 10.19 on page 28.
Toggle Bit I on DQ6 requires Read address to be relatched by toggling AVD# for each reading cycle.
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for
erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 10.18 to compare outputs for DQ2 and DQ6. See the
following for additional information: Figure 10.4 on page 25, DQ6: Toggle Bit I on page 26, and Figures 14.16–14.18.
Read address has to be relatched by toggling AVD# for each reading cycle.
Table 10.17 DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
at any address at the bank being
programmed
programming,
toggles,
does not toggle.
at an address within a sector selected
for erasure,
toggles,
toggles,
also toggles.
does not toggle.
toggles.
actively erasing,
at an address within sectors not
selected for erasure,
at an address within a sector selected
for erasure,
does not toggle,
returns array data,
toggles,
erase suspended,
at an address within sectors not
returns array data. The system can read
from any sector not selected for erasure.
selected for erasure,
programming in erase
suspend
at any address at the bank being
programmed
is not applicable.
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Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the
program or erases operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial
two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the
program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is
toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this
case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to
Figure 10.4 on page 25 for more details.
Note: When verifying the status of a write operation (embedded program/erase) of a memory bank, DQ6 and DQ2 toggle between
high and low states in a series of consecutive and contiguous status read cycles. In order for this toggling behavior to be properly
observed, the consecutive status bit reads must not be interleaved with read accesses to other memory banks. If it is not possible to
temporarily prevent reads to other memory banks, then it is recommended to use the DQ7 status bit as the alternative method of
determining the active or inactive status of the write operation.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1, indicating that the program or erase cycle was not successfully completed. The device does not output a 1 on DQ5 if
the system tries to program a 1 to a location that was previously programmed to 0. Only an erase operation can change a 0 back to
a 1. Under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other
bits that were correctly requested to be changed from 1 to 0 are programmed. Attempting to program a 0 to a 1 is masked during the
programming operation. Under valid DQ5 conditions, the system must write the reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The
sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time
between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor
DQ3. See Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure
that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun;
all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts
additional sector erase commands. To ensure the command has been accepted, the system software should check the status of
DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command
might not have been accepted. Table 10.19 on page 28 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue
the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming
on page 15.
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Table 10.18 Write Operation Status
Status
DQ7 (2)
DQ7#
0
DQ6
Toggle
Toggle
INVALID
DQ5 (1)
DQ3
N/A
1
DQ2 (2)
No toggle
Toggle
DQ1 (4)
0
Embedded Program Algorithm
Standard
0
0
Mode
Embedded Erase Algorithm
N/A
INVALID
INVALID INVALID
(Not (Not
Allowed) Allowed)
INVALID
INVALID
Program
Reading within Program Suspended Sector
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
Suspend
Mode
(3)
Reading within Non-Program Suspended
Sector
Data
1
Data
No toggle
Data
Data
0
Data
N/A
Data
Toggle
Data
Data
N/A
Erase
Suspended Sector
Erase-Suspend-
Erase
Suspend
Mode
Read
Non-EraseSuspended
Data
Data
Data
Data
Sector
Erase-Suspend-Program
BUSY State
DQ7#
DQ7#
DQ7#
DQ7#
Toggle
Toggle
Toggle
Toggle
0
0
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
Write to
Buffer (5)
Exceeded Timing Limits
ABORT State
0
1
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more
information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for
DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
10.6 Simultaneous Read/Program or Erase
The simultaneous read/program or erase feature allows the host system to read data from one bank of memory while programming
or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the
same bank (except the sector being erased). Figure 14.19 on page 50 shows how read and write cycles may be initiated for
simultaneous operation with zero latency. Refer to DC Characteristics on page 38 for read-while-program and read-while-erase
current specification.
10.7 Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and CLK is ignored. During
an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command,
and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#.
An erase operation can erase one sector, multiple sectors, or the entire device. The device address space is divided into sixteen
banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to
64 Kword sectors. A bank address is the set of address bits required to uniquely select a bank. Similarly, a sector address is the
address bits required to uniquely select a sector. ICC2 in DC Characteristics on page 38 represents the active current specification
for the write mode. AC Characteristics-Asynchronous contain timing specification tables and timing diagrams for write operations.
10.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY pin which is
a dedicated output and is controlled by CE#.
10.9 Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at
least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration
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register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence.
When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby
current is greater.
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory
upon a system reset.
See Figure 14.5 on page 41 and Figure 14.12 on page 45 for timing diagrams.
10.10 Software Reset
Software reset is part of the command set (see Table 15.1 on page 51) that also returns the device to array read mode and must be
used for the following conditions:
to exit Autoselect mode
when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed
exit sector lock/unlock operation.
to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
after any aborted operations
Exiting Read Configuration Registration Mode
Software Functions and Sample Code
Table 10.19 Reset (LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Note:
Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is complete
The reset command may be written between the cycles in a program command sequence before programming begins
(prior to the third cycle). This resets the bank to which the system was writing to the read mode.
If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank
to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write the “Write to Buffer Abort Reset”
command sequence to RESET the device to reading array data. The standard RESET command does not work during this
condition.
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To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see
command table for details].
11. Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and
can be implemented through software and/or hardware methods, which are independent of each other. This section describes the
various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 11.1 on page 30.
Figure 11.1 Advanced Sector Protection/Unprotection
Hardware Methods
ACC = V
IL
All sectors locked)
(
WP# = V
IL
(All boot
sectors locked)
11.1 Lock Register
The Lock Register consists of 4 bits. The Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1,
Password Protection Mode Lock Bit is DQ2, Persistent Sector Protection OTP bit is DQ3. If DQ0 is ‘0’, it means that the Customer
Secured Silicon area is locked and if DQ0 is ‘1’, it means that it is unlocked. When DQ2 is set to ‘1’ and DQ1 is set to ‘0’, the device
can only be used in the Persistent Protection Mode. When the device is set to Password Protection Mode, DQ1 is required to be set
to ‘1’ and DQ2 is required to be set to ‘0’. DQ3 is programmed in the Spansion factory. When the device is programmed to disable all
PPB erase command, DQ3 outputs a ‘0’, when the lock register bits are read. Similarly, if the device is programmed to enable all
PPB erase command, DQ3 outputs a ‘1’ when the lock register bits are read. Likewise the DQ4 bit is also programmed in the
Spansion Factory. DQ4 is the bit which indicates whether Volatile Sector Protection Bit (DYB) is protected or not after boot-up. When
the device is programmed to set all Volatile Sector Protection Bit protected after power-up, DQ4 outputs a ‘0’ when the lock register
bits are read. Similarly, when the device is programmed to set all Volatile Sector Protection Bit un-protected after power-up, DQ4
outputs a ‘1’. Each of these bits in the lock register are non-volatile. DQ15-DQ5 are reserved and will be 1’s.
For programming lock register bits refer to Table 15.2 on page 54.
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Table 11.1 Lock Register
DQ15-5
DQ4
DQ3
DQ2
DQ1
DQ0
PPB One Time Programmable Bit
0 = All PPB Erase Command
disabled
Password
Protection
Persistent
Protection
Secured
Silicon Sector
1’s
Reserved (default = 1)
Mode Lock Bit Mode Lock Bit Protection Bit
1 = All PPB Erase Command
enabled
Notes:
1. If the password mode is chosen, the password must be programmed and verified before setting the corresponding lock register bit (DQ2). Failing to program and
verifying the password prior to setting lock register (DQ2), causes all sectors to lock out.
2. It is recommended a sector protection method to be chosen by programming DQ1 or DQ2 prior to shipment.
3. After the Lock Register Bits Command Set Entry sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting
this mode. Simultaneous operation is only valid as long as lock register program command is not executed.
4. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts.
5. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed.
Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled.
6. During erase/program suspend, ASP entry commands are not allowed.
7. Data Polling can be done immediately after the lock register programming command sequence (no delay required). Note that status polling can be done only in bank 0
8. Reads from other banks (simultaneous operation) are not allowed during lock register programming. This restriction applies to asynchronous read operations.
After selecting a sector protection method, each sector can operate in any of the following three states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a
password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Section 11.3.
11.2 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection
scheme for unprotected sectors that have their PPBs cleared (erased to 1). By issuing the DYB Set or Clear command sequences,
the DYBs are set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state
respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy
removal of protection when changes are needed.
Notes
1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to 1).
2. The default state of DYB is unprotected after power up and all sectors can be modified depending on the status of PPB bit
for that sector, (erased to 1). Then the sectors can be modified depending upon the PPB state of that sector.
3. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state.
4. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors
respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are
required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset.
The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and
the device operates normally again.
5. Data polling is not available for DYB program / erase.
6. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode.
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11.3 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a
64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB
Lock Bit is set 0 to maintain the password mode of operation. Successful execution of the Password Unlock command by entering
the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. If the password mode is chosen, the password must be programmed and verified before setting the corresponding lock
register bit (DQ2). Failing to program and verifying the password prior to setting lock register (DQ2), causes all sectors to
lock out.
2. There is no special addressing order required for programming the password. Once the Password is written and verified,
the Password Mode Locking Bit must be set in order to prevent access.
3. The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a
0 results in a time-out with the cell as a 0.
4. The password is all 1s when shipped from the factory.
5. All 64-bit password combinations are valid as a password.
6. There is no means to verify what the password is after it is set.
7. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password
programming.
8. The Password Mode Lock Bit is not erasable.
9. The lower two address bits (A1–A0) are valid during the Password Read, Password Program, and Password Unlock.
10.The exact password must be entered in order for the unlocking function to occur.
11. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a hacker from running through
all the 64-bit combinations in an attempt to correctly match a password.
12.Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to the device.
13.Password verification is only allowed during the password programming operation.
14.All further commands to the password region are disabled and all operations are ignored.
15.If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit.
16.Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads
and writes for other banks excluding Bank 0 are allowed.
17.If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode.
18.A program or erase command to a protected sector enables status polling and returns to read mode without having
modified the contents of the protected sector.
19.The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read
commands DYB Status, PPB Status, and PPB Lock Status to the device.
Document Number: 002-01310 Rev. *A
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PRELIMINARY
S99-50214
Figure 11.2 Lock Register Program Algorithm
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
* Not on future devices
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Yes
Error condition (Exceeded Timing Limits)
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
11.4 Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP# is at VIL, the four outermost sectors (including Secured Silicon Area) are locked.
When ACC is at VIL, all sectors (including Secured Silicon Area) are locked.
There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The
following subsections describes these methods:
Document Number: 002-01310 Rev. *A
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PRELIMINARY
S99-50214
11.4.1
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP#
pin and overrides the previously discussed Sector Protection/Unprotection method.
Table 11.2 S99-50214 Sector Protection
Dual Boot Configuration
Bank 0
Bank 1-7
Bank 8-14
Bank 15
SA000-SA003 WP# Protected
No Sector WP# Protection
No Sector WP# Protection
SA514-SA517 WP# Protected
If the system asserts VIL on the WP# pin, the device disables program and erase functions in the outermost boot sectors, as well as
Secured Silicon Area. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-
configured device.
If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result.
The WP# pin must be held stable during a command sequence execution
11.4.2
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all program and erase functions are
disabled and hence all sectors (including the Secured Silicon Area) are protected.
11.4.3
Low V Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent
writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent
unintentional writes when VCC is greater than VLKO
.
11.4.4
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
11.4.5
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#.
The internal state machine is automatically reset to the read mode on power-up.
12. Power Conservation Modes
12.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device
enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard
access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the
device draws active current until the operation is completed. ICC3 in DC Characteristics on page 38 represents the standby current
specification
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PRELIMINARY
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12.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption only while in asynchronous main array read mode. the
device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent
of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While
in sleep mode, output data is latched and always available to the system.
12.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at
least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence to ensure data integrity.
When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS
0.2 V, the standby current is greater.
±
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system
to read the boot-up firmware from the Flash memory.
12.4 Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
13. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic
Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words
for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when
shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector
is locked when shipped from the factory.
Please note the following general conditions:
While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space.
Reads can be performed in the Asynchronous mode.
Reads outside of sector 0 return memory array data.
Sector 0 is remapped from memory array to Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to
exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase
algorithm.
Table 13.1 Secured Silicon Sector Addresses
Sector
Customer
Factory
Sector Size
128 words
128 words
Address Range
000080h-0000FFh
000000h-00007Fh
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PRELIMINARY
S99-50214
13.1 Factory Secured Silicon Sector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7)
permanently set to a 1. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once
the product is shipped to the field.
These devices are available pre programmed with one of the following:
A random, 8 Word secure ESN only within the Factory Secured Silicon Sector
Customer code within the Customer Secured Silicon Sector through the Spansion programming service.
Both a random, secure ESN and customer code through the Spansion programming service.
Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the
customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured
Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using
Spansion programming services.
13.2 Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to utilize that sector in any
manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional
Flash memory space.
Please note the following:
Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to 1.
The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once.
The Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for
unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory
space can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer
Secured Silicon Sector, but reading in Banks 1 through 15 is available.
Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector
Region command sequence which return the device to the memory array at sector 0.
13.3 Secured Silicon Sector Entry/Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command
sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured
Silicon Sector command sequence.
The Secured Silicon Sector Entry Command allows the following commands to be executed
Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using
the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues
the Exit Secured Silicon Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands.
Refer to the Spansion Low Level Driver User’s Guide (available soon on www.spansion.com) for general information on Spansion
Flash memory software development guidelines.
Document Number: 002-01310 Rev. *A
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PRELIMINARY
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Table 13.2 Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Data
00AAh
0055h
0088h
Unlock Cycle 1
Unlock Cycle 2
Entry Cycle
Write
Write
Write
Base + 555h
Base + 2AAh
Base + 555h
Note:
Base = Base Address.
/* Example: Secured Silicon Sector Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secured Silicon Sector Entry Cmd
*/
*/
*/
Table 13.3 Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Program
Base + AAAh
Base + 554h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Write
0055h
Write
00A0h
Write
Data Word
Note:
Base = Base Address.
/* Once in the Secured Silicon Sector mode, you program */
/* words using the programming algorithm.
*/
Table 13.4 Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 554h
Base + AAAh
Any address
Word Address
Data
00AAh
0055h
0090h
0000h
Unlock Cycle 1
Unlock Cycle 2
Exit Cycle 3
Exit Cycle 4
Base + 555h
Base + 2AAh
Base + 555h
Any address
Write
Write
Write
Note:
Base = Base Address.
/* Example: Secured Silicon Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secured Silicon Sector Exit cycle 3 */
/* write Secured Silicon Sector Exit cycle 4 */
*/
*/
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PRELIMINARY
S99-50214
14. Electrical Specifications
14.1 Absolute Maximum Ratings
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
–65°C to +150°C
–65°C to +125°C
–0.5 V to + 2.5 V
–0.5 V to +2.5 V
–0.5 V to +9.5 V
100 mA
Voltage with Respect to Ground: All Inputs and I/Os except as noted below (1)
(1)
V
CC
ACC (2)
Output Short Circuit Current (3)
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V to –2.0 V for periods of up to 20 ns. See Figure 14.1.
SS
Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions outputs may overshoot to V + 2.0 V for periods up to 20 ns. See Figure 14.2.
CC
CC
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot V to –2.0 V for periods of up to 20 ns. See Figure 14.1. Maximum DC
SS
voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
Figure 14.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 14.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
1.0 V
20 ns
20 ns
14.2 Operating Ranges
Wireless (I) Devices
Supply Voltages
Note
Ambient Temperature (T )
–25°C to +85°C
1.8 V Typical
A
V
Supply Voltages
CC
Operating ranges define those limits between which the functionality of the device is guaranteed.
14.3 DC Characteristics
DC characteristics not 100% tested.
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PRELIMINARY
S99-50214
14.3.1
CMOS Compatible
Table 14.1 CMOS Compatible
Parameter
Description
Input Load Current
Output Leakage Current
Test Conditions (2)
Typ Min Typ Typ Max Unit
I
V
V
= V to V , V = V max
±1
±1
µA
µA
mA
mA
mA
µA
mA
µA
µA
µA
LI
IN
SS
CC
CC
CC
I
= V to V , V = V max
SS CC CC CC
LO
OUT
10 MHz
5 MHz
1 MHz
40
20
10
1
V
Active Asynchronous Read
CC
I
CE# = V , OE# = V , WE# = V
IL IH
CC1
IH
Current (3)
V
ACC
V
Active Program/Erase
CC
I
I
CE# = V , OE# = V , ACC = V
CC2
IL
IH
IH
Current (3)
V
20
1
CC
V
CE# = RESET# =
ACC
V
Standby Current (4)
CC3
CC
V
± 0.2 V
V
20
30
CC
CC
I
I
V
V
Reset Current
Active Current
RESET# = V CLK = V
IL, IL
CC4
CC
CC
CE# = V , OE# = V , ACC = V , 5 MHz
40
5
mA
µA
CC5
IL
IH
IH
(Read While Program/Erase)
CE# = V , OE# = V (V
or V biased at Rail
SSQ
IL
IH,
CCQ
I
I
V
V
Sleep Current
CC6
CC
CC
to Rail for all inputs)
Active Page Read Current
OE# = V , 8 word Page Read
10
7
mA
mA
mA
V
CC7
IH
V
ACC
CE# = V , OE# = V
IL
IH,
I
Accelerated Program Current(5)
ACC
V
= 9.5 V
ACC
V
15
CC
V
Input Low Voltage
–0.2
0.4
IL
V
0.4
–
V
0.4
+
CC
CC
V
Input High Voltage
IH
V
Output Low Voltage
I
I
= 100 µA, V = V
CC min
0.1
V
V
OL
OH
HH
OL
CC
V
0.1
–
CC
V
V
Output High Voltage
Voltage for Accelerated Program
= –100 µA, V = V
OH CC CC min
8.5
9.5
1.4
V
V
V
Low V Lock-out Voltage
CC
LKO
Notes:
1. DC Characteristics not 100% tested
2. Maximum I specifications are tested with V = V max.
CC
CC
CC
3.
I
active while Embedded Erase or Embedded Program is in progress.
CC
4. Device enters automatic sleep mode when addresses are stable for t
+ 20 ns. Typical sleep mode current is equal to I
.
ACC
CC3
5. Total current during accelerated programming is the sum of V
and V currents.
CC
ACC
6.
7.
V
V
= V during all I measurements.
CCQ CC CC
= V ± 0.2V and V
IL
0.1V
IH
CC
14.4 Test Conditions
Figure 14.3 Test Setup
Device
Under
Test
C
L
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PRELIMINARY
S99-50214
Table 14.2 Test Specifications
Test Condition
All Speed Options
Unit
Output Load Capacitance, C
(including jig capacitance)
L
30
pF
Input Rise and Fall Times
Input Pulse Levels
1.0 - 1.50
ns
V
0.0–V
CC
Input timing measurement reference levels
Output timing measurement reference levels
V
/2
V
CC
CC
V
/2
V
14.5 Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High-Z)
14.6 Switching Waveforms
Figure 14.4 Input Waveforms and Measurement Levels
VCC
All Inputs and Outputs
VCC/2
VCC/2
Input
Measurement Level
Output
0.0 V
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PRELIMINARY
S99-50214
Table 14.3 VCC Power-up
Parameter
Description
Setup Time
CC
Test Setup
Time
30
Unit
µs
t
V
Typ Min
VCS
t
Time between RESET# (high) and CE# (low)
Typ Min
200
ns
RH
14.7 Power-up/Initialization
Power supply must reach its minimum voltage range before applying/removing the next supply voltage.
RESET# must ramp down to VIL level before VCC/VCCQ can start ramp up.
VCC and VCCQ must be ramped simultaneously for proper power-up.
The S99-50214 device ramp rate is > 1V/400 µs. For VCC ramp rate <1V/400 µs, a hardware reset is required.
Figure 14.5 VCC Power-up Diagram
tVCS
VCC min
VCC/ VCCQ
VIH
RESET#
tRH
CE#
14.8 CLK Characterization
Parameter
Description
54 MHz
66 MHz
80 MHz
104 MHz
Unit
Typ Max
Typ Min
54
66
80
104
MHz
60 KHz in 8 word Burst,
f
CLK Frequency
CLK
120 KHz in 16 word Burst,
250 KHz in 32 word Burst,
1 MHz in Continuous Mode
t
CLK Period
Typ Min
Typ Min
Typ Max
18.5
3.0
15.1
3.0
12.5
9.62
1.5
ns
ns
CLK
0.45 t
0.55 t
CLK
CLK
t
/t
CLK Low/High Time
CL CH
t
CLK Rise Time
CLK Fall Time
CR
Typ Max
2.5
ns
t
CF
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PRELIMINARY
S99-50214
Figure 14.6 CLK Characterization
t
CLK
t
t
CL
CH
CLK
t
t
CF
CR
14.9 AC Characteristics
AC characteristics not 100% tested.
14.9.1
Asynchronous Mode Read
Parameter
JEDEC Standard
Description
Access Time from CE# Low
Asynchronous
Unit
ns
t
Typ Max
Typ Max
Typ Min
Typ Min
Typ Min
Typ Max
Typ Min
83
80
7.5
6
CE
t
Asynchronous Access Time
ns
ACC
t
AVD# Low Time
ns
AVDP
AAVDS
AAVDH
t
Address Setup Time to Rising Edge of AVD#
Address Hold Time from Rising Edge of AVD#
Output Enable to Output Valid
ns
t
4
ns
t
13.5
0
ns
OE
Read
ns
Output Enable Hold
t
OEH
Toggle and Data#
Time
Typ Min
4
ns
Polling
Output Enable to High-Z
CE# Setup Time to AVD#
Intra Page Access Time
Chip Enable to High-Z
t
t
Typ Max
Typ Min
Typ Max
Typ Max
7.6
0
ns
ns
ns
ns
OEZ
CAS
t
20
7.6
PACC
t
CEZ
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PRELIMINARY
S99-50214
Figure 14.7 Asynchronous Read Mode (AVD# Toggling - Case 1)
VIL or VIH
CLK
CE#
tCEZ
tAV DP
AVD#
OE#
tOE
tWEA
tOEH
WE#
tCE
tOEZ
DQ15-DQ0
RD
tAAVDH
tAAVDS
VA
Amax-A0
tCEZ
tRDY
Hi-Z
Hi-Z
RDY
Notes:
1. Valid Address and AVD# Transition occur before CE# is driven Low.
2. VA = Valid Read Address, RD = Read Data.
Figure 14.8 Asynchronous Read Mode (AVD# Toggling - Case 2)
VIL or VIH
CLK
CE#
tCAS
tCEZ
tAV DP
AVD#
OE#
tOE
tWEA
tOEH
WE#
tOEZ
DQ15-DQ0
RD
tAAVDH
tAAVDS
Amax-A0
RDY
VA
tACC
tCEZ
tRDY
Hi-Z
Hi-Z
Notes:
1. AVD# Transition occurs after CE# is driven to Low and Valid Address Transition occurs before AVD# is driven to Low.
2. VA = Valid Read Address, RD = Read Data.
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PRELIMINARY
S99-50214
Figure 14.9 Asynchronous Read Mode (AVD# Toggling - Case 3)
V
IL or VIH
CLK
CE#
tCAS
tCEZ
tAV DP
AVD#
OE#
tOE
tWEA
tOEH
WE#
tOEZ
DQ15-DQ0
RD
tAAVDH
tAAVDS
Amax-A0
RDY
VA
tACC
tCEZ
tRDY
Hi-Z
Hi-Z
Notes:
1. AVD# Transition occurs after CE# is driven to Low and AVD# is driven low before Valid Address Transition.
2. VA = Valid Read Address, RD = Read Data.
Figure 14.10 Asynchronous Read Mode (AVD# tied to CE#)
VIL or VIH
CLK
CE#
tRC
tCEZ
AVD#
OE#
tOE
tOEH
WE#
DQ15-DQ0
Amax-A0
tWEA
tCE
tOEZ
RD
tACC
VA
tCEZ
tRDY
Hi-Z
Hi-Z
RDY
Notes:
1. AVD# is tied to CE#
2. VA = Valid Read Address, RD = Read Data.
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PRELIMINARY
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Figure 14.11 Asynchronous Page Mode Read
Page
Amax-A3
A2-A0
Ax
A0
tACC
A1
tPACC
A2
tPACC
tPACC
Data Bus
D0
D1
Dx
D7
CE#
OE#
AVD#
Note:
RA = Read Address, RD = Read Data.
14.9.2
Hardware Reset (RESET#)
Table 14.4 Hardware Reset
Parameter
All Speed
Options
JEDEC
Std
Description
RESET# Pulse Width
Unit
µs
t
Typ Min
Typ Min
30
RP
RH
t
Reset High Time Before Read
200
ns
Figure 14.12 Reset Timings
CE#, OE#
tRH
RESET#
tRP
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Page 45 of 59
PRELIMINARY
S99-50214
14.9.3
Erase/Program Timing
Parameter
JEDEC Standard
54
MHz
66
MHz
80
MHz
104
MHz Unit
Description
t
t
Write Cycle Time (1)
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Min
Typ Max
Typ Max
Typ
60
ns
AVAV
WC
t
t
Address Setup Time (2)
Address Hold Time (2)
AVD# Low Time
Asynchronous
Asynchronous
6
7
6
7
6
6
6
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
AVWL
WLAX
AS
t
t
AH
t
6
20
0
AVDP
t
t
t
Data Setup Time
DVWH
DS
t
Data Hold Time
WHDX
DH
t
t
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
0
GHWL
GHWL
t
0
CAS
t
t
0
WHEH
WLWH
WHWL
CH
t
t
Write Pulse Width
25
20
0
WP
t
t
Write Pulse Width High
WPH
t
Latency Between Read and Write Operations
SR/W
t
V
Rise and Fall Time
500
1
VID
ACC
t
V
Setup Time (During Accelerated Programming)
VIDS
ACC
t
t
CE# Setup Time to WE#
4
ELWL
CS
t
AVD# Setup Time to WE#
4
AVSW
AVHW
t
AVD# Hold Time to WE#
4
t
AVD# Setup Time to CLK
5
5
5
5
5
5
3
3
AVSC
t
AVD# Hold Time to CLK
AVHC
t
Sector Erase Accept Time-out
Erase Suspend Latency
50
40
40
0
SEA
t
ESL
PSL
ASP
PSP
t
Program Suspend Latency
t
t
Toggle Time During Erase within a Protected Sector
Toggle Time During Programming Within a Protected Sector
Typ
0
Notes:
1. Sampled, not 100% tested.
2. In programming operations, addresses are latched on the rising edge of AVD# for programming asynchronously.
3. See the Erase and Programming Performance on page 51 for more information. Does not include the preprogramming time.
Document Number: 002-01310 Rev. *A
Page 46 of 59
PRELIMINARY
S99-50214
Figure 14.13 Asynchronous Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
VA
VA
PA
Addresses
Data
555h
In
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tWP
tCS
tWPH
tWC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. In progress and complete refer to status of program operation.
3. CLK can be either V or V
.
IL
IH
Document Number: 002-01310 Rev. *A
Page 47 of 59
PRELIMINARY
S99-50214
Figure 14.14 Chip/Sector Erase Command Sequence
Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
VA
VA
SA
555h for
chip erase
Addresses
Data
2AAh
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
Note:
SA is the sector address for Sector Erase.
Figure 14.15 Accelerated Unlock Bypass Programming Timing
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
tVIDS
A0h
Don't Care
PD
Don't Care
OE#
1 μs
V
HH
ACC
V
or V
IH
IL
Note:
Use setup and hold times from conventional program operation.
Document Number: 002-01310 Rev. *A
Page 48 of 59
PRELIMINARY
S99-50214
Figure 14.16 Data# Polling Timings (During Embedded Algorithm)
AVD#
CE#
tCEZ
tCE
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
High Z
High Z
Addresses
VA
VA
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data.
Figure 14.17 Toggle Bit Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
High Z
High Z
Addresses
Data
VA
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.
Figure 14.18 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note:
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Document Number: 002-01310 Rev. *A
Page 49 of 59
PRELIMINARY
S99-50214
Figure 14.19 Back-to-Back Read/Write Cycle Timings
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tGHWL
tOEH
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
Note:
Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the
busy bank. The system should read status twice to ensure valid information.
Document Number: 002-01310 Rev. *A
Page 50 of 59
PRELIMINARY
S99-50214
14.10 Erase and Programming Performance
Parameter
64 Kword
Typ (1)
Typ Max (2)
Unit
Comments
V
V
V
0.6
3.0
Excludes 00h
programming prior to
erasure (3)
CC
CC
CC
Sector Erase Time
Chip Erase Time
s
16 Kword
0.35
1.75
616
308.8
s
Excludes system level
overhead (4)
Single Word Programming Time
V
V
V
V
40
9.4
300
400
94
µs
CC
CC
CC
CC
Effective Word Programming Time
utilizing Program Write Buffer
µs
Total 32-Word Buffer Programming
Time
3000
1008
Chip Programming Time (using 32
word buffer)
Excludes system level
overhead (4)
201.6
40
s
Erase Suspend/Erase Resume (t
)
µs
µs
ERS
Program Suspend/Program Resume
(t
40
)
PRS
Notes:
1. Typical program and erase values are measured at T = 25°C, 1.8 V V , using checkerboard patterns. Sampled, but not 100% tested.
C
CC
2. Under worst case conditions of 90°C, V = 1.70 V.
CC
3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 15.1 on page 51 and Table 15.2
on page 54 for further information on command definitions.
14.10.1
BGA Ball Capacitance
Parameter
Parameter Symbol
Description
Test Setup
= 0
Typ
2
Max
10
Unit
pF
C
Input Capacitance
Output Capacitance
V
IN
IN
C
V
= 0
OUT
2
10
pF
OUT
Notes:
1. Sampled, not 100% tested.
2. Test conditions t - 25°C; f = 1.0 MHz.
A
15. Appendix A – Software Interface Reference
This section contains information relating to software control or interfacing with the Flash device. For additional information and
assistance regarding software, see Appendix C – Additional Resources on page 57, or explore the Web at www.spansion.com.
Table 15.1 Memory Array Commands
Bus Cycles (Note 1 - 6)
First
Data
Second
Data
Third
Data
Fourth
Data
Fifth
Data
Sixth
Data
Command Sequence
(Notes)
Addr
(19)
RD
F0
Addr
(19)
Addr
(19)
Addr
(19)
Addr
(19)
Addr
(19)
Asynchronous Read (7)
1
1
RA
Reset (8)
XXX
Document Number: 002-01310 Rev. *A
Page 51 of 59
PRELIMINARY
S99-50214
Table 15.1 Memory Array Commands
Bus Cycles (Note 1 - 6)
Third Fourth
Data Data
First
Data
Second
Data
Fifth
Data
Sixth
Data
Command Sequence
(Notes)
Addr
(19)
Addr
(19)
Addr
(19)
Addr
(19)
Addr
(19)
Addr
(19)
(BA)
555
(BA)
X00
Manufacturer ID
Device ID (10)
Indicator Bits
4
6
4
555
AA
2AA
55
90
0001
(BA)
555
(BA)
X01
(BA)X
0E
(BA)
X0F
555
555
AA
AA
2AA
2AA
55
55
90
90
227E
(12)
(10)
(10)
(BA)
555
(BA)
X03
(SA)
555
(SA)
X02
0000/
0001
Sector Unlock/Lock Verify
(11)
4
4
6
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
90
A0
25
Single word
555
PA
Data
PA
Write Buffer to Flash Program (17)
SA
SA
WC
PD
WBL
PD
(20)
Program Buffer to Flash
Write to Buffer Abort Reset (12)
Chip Erase
1
3
6
6
1
1
5
SA
555
555
555
BA
29
AA
AA
AA
B0
30
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (15)
Program/Erase Resume (16)
Set Configuration Register (21)
BA
555
AA
2AA
2AA
55
55
555
555
D0
C6
X00
CR0
X01
CR1
X0
(0 or
1)
CR
(0 or
1)
Read Configuration Register
4
555
AA
(BA)
55
CFI Query (17)
1
3
2
98
AA
A0
Unlock Bypass Entry (18)
555
XX
2AA
PA
55
555
20
Unlock Bypass Program (13,
14)
PD
Unlock Bypass Sector Erase
2
2
XX
XX
80
80
SA
30
10
Unlock Bypass
(13, 14)
Mode
Unlock Bypass Erase (13,
14)
XXX
Unlock Bypass CFI (13, 14)
Unlock Bypass Reset
1
2
XX
XX
98
90
XXX
00
Legend:
X = Don’t care
RA = Read Address
RD = Read Data
PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.
Notes:
1. See Table 10.1 on page 10 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register
verify and password verify commands, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0.
5. Unless otherwise noted, address bits Amax–A14 are don’t cares.
6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset
command to return the device to reading array data.
7. No unlock or command cycles required when bank is reading array data.
8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect
mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock.
Document Number: 002-01310 Rev. *A
Page 52 of 59
PRELIMINARY
S99-50214
9. The fourth cycle of the autoselect address is a read cycle. The system must provide the bank address.
10. (BA) + 0Eh ----> For WS128 = 2244h, WS256 = 2242h, WS512 = 223Dh. (BA) + 0Fh ----> For WS064/128/256/512 = 2200h
11. The data is 0000h for an unlocked sector and 0001h for a locked sector
12.See Table 10.3, Autoselect Addresses on page 11.
13.The Unlock Bypass command sequence is required prior to this command sequence.
14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
15.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Program/Erase Suspend command
is valid only during a program/ erase operation, and requires the bank address.
16. The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address.
17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the
command sequence is 37.
18. Write Buffer Programming can be initiated after Unlock Bypass Entry.
19.Data is always output at the rising edge of clock.
20. Must be the lowest address.
21. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous
settings
Document Number: 002-01310 Rev. *A
Page 53 of 59
PRELIMINARY
S99-50214
Table 15.2 Sector Protection Commands (Sheet 1 of 2)
Bus Cycles (Note 1 - 6)
Fourth
Data(
First
Data
Second
Data(
Third
Data(
Fifth
Data(
Sixth
Data(
Seventh
Data(
Command Sequence
(Notes)
Addr
555
555
SA
(10)
Addr
2AA
2AA
(10)
Addr
(10)
Addr
(10)
PD
00
Addr
(10)
Addr
(10)
Addr
(10)
Entry (5)
Program
3
4
1
4
AA
55
555
88
AA
55
555
A0
PA
Secured
Silicon Sector
Read
data
AA
Exit (7)
555
2AA
2AA
00
55
55
555
555
90
40
XX
Register Command Set
Entry (5)
3
555
AA
Register Bits Program (6)
Register Bits Read
2
1
XX
00
A0
data
Lock Register
data
Register Command Set
Exit (7)
2
3
XX
90
XX
00
55
Protection Command Set
Entry
555
AA
2AA
555
60
PWD
0/
00/
01/
02/
03
1/
2/
3/
Program (9)
2
XX
A0
PWD
0
PWD
1
PWD
2
PWD
3
Read Password (10)
Unlock (9)
4
7
2
00
00
01
00
XX
02
00
03
01
PWD
0
PWD
1
PWD
2
PWD
3
25
90
03
00
02
03
00
29
Protection Command Set
Exit
XX
Non-Volatile Sector
Protection Command Set
Entry (5)
(BA)
555
3
555
AA
2AA
55
C0
(BA)
SA
Program
2
2
1
XX
XX
A0
80
00
30
PPB
All Erase (8)
Status Read
XX
XX
(BA)
SA
RD(0)
Non-Volatile Sector
Protection Command Set
Exit (7)
2
3
XX
90
00
Global Volatile Sector
Protection Freeze
Command Set Entry (5)
555
AA
2AA
XX
55
00
555
50
Set
2
1
XX
XX
A0
PPB Lock Bit
Status Read
RD(0)
Global Volatile Sector
Protection Freeze
2
XX
90
XX
00
Command Set Exit (7)
Document Number: 002-01310 Rev. *A
Page 54 of 59
PRELIMINARY
S99-50214
Table 15.2 Sector Protection Commands (Sheet 2 of 2)
Bus Cycles (Note 1 - 6)
Fourth
Data(
First
Data
Second
Data(
Third
Data(
Fifth
Data(
Sixth
Data(
Seventh
Data(
Command Sequence
(Notes)
Addr
(10)
Addr
(10)
Addr
(10)
Addr
(10)
Addr
(10)
Addr
(10)
Addr
(10)
Volatile Sector Protection
Command Set Entry (5)
(BA)
555
3
2
2
1
2
555
AA
2AA
55
E0
(BA)
SA
Set
XX
XX
A0
A0
00
01
(BA)
SA
DYB
Clear
(BA)
SA
Status Read
RD(0)
90
Volatile Sector Protection
Command Set Exit (7)
XX
XX
00
Program
2
2
2
1
4
1
555
555
555
RA
SA
A0
80
80
RD
25
29
PA
SA
Data
30
Sector Erase
Chip Erase
555
10
Accelerated
Asynchronous Read
Write to Buffer
Program Buffer to Flash
SA
WC
PA
PD
WBL
PD
SA
Legend:
X = Don’t care
RA = Read Address
RD = Read Data
PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.
SA = Sector Address: WS128P = A22–A14, WS256P = 23–A14
BA = Bank Address: WS128P = A22-A20, and A19; WS256P = A23-A20
CR = Configuration Register data bits D15–D0
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password.
PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.
PWD = Password Data
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 10.1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register
verify and password verify commands, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0.
5. Entry commands are required to enter a specific mode to enable instructions only available within that mode.
6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns
the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the
WS512P only.
7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state.
8. “All PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure.
9. Entire two bus-cycle sequence must be entered for each portion of the password.
10. Full address range is required for reading password.
Document Number: 002-01310 Rev. *A
Page 55 of 59
PRELIMINARY
S99-50214
16. Appendix B – Errata
16.1 Erase Suspend
Device cannot perform a Program Operation after an Erase Suspend Command has been issued. After an Erase Suspend
Command has been issued only a Read Operation is allowed.
16.2 PPB - Persistent Protection Bits
Device cannot support the PPB functionality.
The user should use the DYB functionality (Dynamic Protection Bits) if Sector Protection is needed in the application.
16.3 Asynchronous Read Access Time
The Asynchronous Read Access Time tACC is 160 ns (max) for this device at 25°C.
16.4 Synchronous Burst Read Operation
The Synchronous Burst Read Operation is not supported by this device
16.5 Autoselect
The Autoselect values are not set for this device according to the data sheet.
The Autoselect values for this device are the following:
Autoselect @ (BA + 00) = 0001h
Autoselect @ other addresses = FFFFh
16.6 Initial Memory Array State
The Initial Memory Array State at the time of shipment is “Not Blank” or “not FFFFh”
The user is required to erase the required sectors or to erase the full chip before issuing any Program Command to the part.
16.7 Accelerated Mode
Accelerated mode is not available
16.8 Factory Secured Silicon Sector
The Factory Secured Silicon Sector has not been locked on this device.
16.9 AC / DC parameters.
Please note that wafer form Flash does not guarantee conformance to the AC/DC specifications mentioned in the standard data-
sheet.
16.10 Boot Sector Configurations
There is no Boot Sector Configuration for this device. The Sectors Size is Uniform 64 KB per sector.
Document Number: 002-01310 Rev. *A
Page 56 of 59
PRELIMINARY
S99-50214
17. Appendix C – Additional Resources
Visit www.spansion.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers
True Flash File System
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD® Schematic Symbols
Document Number: 002-01310 Rev. *A
Page 57 of 59
PRELIMINARY
S99-50214
18. Revision History
Spansion Publication Number: S98NS128PB0-001
Section
Revision 01 (December 15, 2009)
Initial release.
Description
Revision 02 (May 27, 2010)
Ordering Information
Added OPN S99-50214-01 for 300 mm wafer
Added OPN S99-50214-01 for 300 mm wafer
Product Selector Guide
Document History Page
Document Title: S99-50214 512 Mbit (32M x 16 bit) 1.8 V MirrorBit® Flash
Document Number: 002-01310
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
Initial release
12/15/2009 to
05/27/2010
**
WIOB
WIOB
Ordering Information: Added OPN S99-50214-01 for 300 mm wafer
Product Selector Guide: Added OPN S99-50214-01 for 300 mm wafer
*A
4961208
10/15/2015 Updated to Cypress template.
Document Number: 002-01310 Rev. *A
Page 58 of 59
PRELIMINARY
S99-50214
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
Automotive..................................cypress.com/go/automotive
Clocks & Buffers ................................ cypress.com/go/clocks
Interface......................................... cypress.com/go/interface
Lighting & Power Control............cypress.com/go/powerpsoc
Memory........................................... cypress.com/go/memory
PSoC ....................................................cypress.com/go/psoc
Touch Sensing.................................... cypress.com/go/touch
USB Controllers....................................cypress.com/go/USB
Wireless/RF.................................... cypress.com/go/wireless
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
© Cypress Semiconductor Corporation, 2009-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-01310 Rev. *A
Revised October 16, 2015
Page 59 of 59
Cypress®, Spansion®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp.
All products and company names mentioned in this document may be the trademarks of their respective holders.
相关型号：
S991A106KD1
CAPACITOR, TANTALUM, SOLID, POLARIZED, 10V, 10uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991A336KGA
CAPACITOR, TANTALUM, SOLID, POLARIZED, 10V, 33uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991C106KEA
CAPACITOR, TANTALUM, SOLID, POLARIZED, 16V, 10uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991C335KBA
CAPACITOR, TANTALUM, SOLID, POLARIZED, 16V, 3.3uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991C336KHA
CAPACITOR, TANTALUM, SOLID, POLARIZED, 16V, 33uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991D155KAA
CAPACITOR, TANTALUM, SOLID, POLARIZED, 20V, 1.5uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991E106MG1
CAPACITOR, TANTALUM, SOLID, POLARIZED, 25V, 10uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991V475KF1
CAPACITOR, TANTALUM, SOLID, POLARIZED, 35V, 4.7uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S991V684KAA
CAPACITOR, TANTALUM, SOLID, POLARIZED, 35V, 0.68uF, THROUGH HOLE MOUNT, RADIAL LEADED
NICHICON
S9970-0906
CCD area image sensor Low dark signal · low readout noise/front-illuminated FFT-CCD
HAMAMATSU
S9970-0906N
CCD Sensor, 512 Horiz pixels, 60 Vert pixels, 12-18V, Rectangular, Through Hole Mount, DIP-24
HAMAMATSU
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