SL811HST-AC [CYPRESS]
USB Bus Controller, CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-48;
| 型号： | SL811HST-AC |
| 厂家： | 
CYPRESS |
| 描述： | USB Bus Controller, CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-48 控制器 |
| 文件： | 总32页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL811HS
Embedded USB Host/Slave Controller
Features
Introduction
■ First USB Host/Slave controller for embedded systems in the
market with a standard microprocessor bus interface
The SL811HS is an Embedded USB Host/Slave Controller
capable of communicating in either full speed or low speed. The
SL811HS interfaces to devices such as microprocessors, micro-
controllers, DSPs, or directly to a variety of buses such as ISA,
PCMCIA, and others. The SL811HS USB Host Controller
conforms to USB Specification 1.1.
■ Supports both full speed (12 Mbps) and low speed (1.5 Mbps)
USB transfer in both master and slave modes
■ Conforms to USB Specification 1.1 for full- and low speed
■ Operates as a single USB host or slave under software control
■ Automatic detection of either low- or full speed devices
■ 8-bit bidirectional data, port I/O (DMAsupported inslave mode)
■ On-chip SIE asnd USB transceivers
The SL811HS incorporates USB Serial Interface functionality
along with internal full or low speed transceivers. The SL811HS
supports and operates in USB full speed mode at 12 Mbps, or in
low speed mode at 1.5 Mbps. When in host mode, the SL811HS
is the master and controls the USB bus and the devices that are
connected to it. In peripheral mode, otherwise known as a slave
device, the SL811HS operates as a variety of full- or low speed
devices.
■ On-chip single root HUB support
■ 256-byte internal SRAM buffer
The SL811HS data port and microprocessor interface provide an
8-bit data path I/O or DMA bidirectional, with interrupt support to
allow easy interface to standard microprocessors or microcon-
trollers such as Motorola or Intel CPUs and many others. The
SL811HS has 256-bytes of internal RAM which is used for
control registers and data buffer.
■ Ping-pong buffers for improved performance
■ Operates from 12 or 48 MHz crystal or oscillator (built-in DPLL)
■ 5 V-tolerant interface
■ Suspend/resume, wake up, and low-power modes are
supported
The available lead-free package is a 48-pin (SL811HST-AXC)
package. All packages operate at 3.3 VDC. The I/O interface
logic is 5 V-tolerant.
■ Auto-generation of SOF and CRC5/16
■ Auto-address increment mode, saves memory READ/WRITE
cycles
■ Development kit including source code drivers is available
■ 3.3 V power source, 0.35 micron CMOS technology
■ Available in 48-pin TQFP package
Logic Block Diagram
Master/Slave
INTERRUPT
Controller
INTR
CONTROLLER
256 Byte RAM
BUFFERS
D
+
SERIAL
INTERFACE
ENGINE
USB
nDRQ
Root HUB
XCVRS
D-
&
DMA
CONTROL
Interface
REGISTERS
nDACK
nWR
nRD
nCS
PROCESSOR
INTERFACE
CLOCK
GENERATOR
nRST
D0-7
X1
X2
Cypress Semiconductor Corporation
Document 38-08008 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 25, 2011
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SL811HS
Contents
Features .............................................................................1
Introduction .......................................................................1
Logic Block Diagram ........................................................1
Data Port, Microprocessor Interface ............................3
DMA Controller (slave mode only) ..............................3
Interrupt Controller ......................................................3
Buffer Memory .............................................................3
PLL Clock Generator ...................................................4
USB Transceiver .........................................................5
SL811HS Registers ...........................................................5
Physical Connections ....................................................20
48-Pin TQFP Physical Connections ..........................20
Electrical Specifications ................................................23
Absolute Maximum Ratings .......................................23
Recommended Operating Condition ........................23
External Clock Input Characteristics (X1) ..................23
DC Characteristics ....................................................24
USB Host Transceiver Characteristics ......................24
Bus Interface Timing Requirements ..........................25
Ordering Information ......................................................29
Ordering Code Definitions .........................................29
Package Diagram ............................................................30
Acronyms ........................................................................30
Document Conventions .................................................30
Units of Measure .......................................................30
Document History Page ................................................31
Sales, Solutions, and Legal Information ......................32
Worldwide Sales and Design Support .......................32
Products ....................................................................32
PSoC Solutions .........................................................32
Document 38-08008 Rev. *F
Page 2 of 32
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SL811HS
mode described in Auto Address Increment Mode, where direct
addressing is used to READ/WRITE to an individual address.
Data Port, Microprocessor Interface
The SL811HS microprocessor interface provides an 8-bit
bidirectional data path along with appropriate control lines to
interface to external processors or controllers. Programmed I/O
or memory mapped I/O designs are supported through the 8-bit
interface, chip select, read and write input strobes, and a single
address line, A0.
USB transactions are automatically routed to the memory buffer
that is configured for that transfer. Control registers are provided
so that pointers and block sizes in buffer memory are determined
and allocated.
Figure 1. Memory Map
Access to memory and control register space is a simple two
step process, requiring an address Write with A0 = ’0’, followed
by a register/memory Read or Write cycle with address line A0 =
’1’.
0x00 – 0x0F Control
and status registers
0x00 – 0x39
16 bytes
64 bytes
Control/status registers
and endpoint
control/status registers
In addition, a DMA bidirectional interface in slave mode is
available with handshake signals such as nDRQ, nDACK, nWR,
nRD, nCS and INTRQ.
0x10 – 0xFF
USB data buffer
0x40 – 0xFF
USB data buffer
240 bytes
192 bytes
The SL811HS WRITE or READ operation terminates when
either nWR or nCS goes inactive. For devices interfacing to the
SL811HS that deactivate the Chip Select nCS before the Write
nWR, the data hold timing must be measured from the nCS and
is the same value as specified. Therefore, both Intel®- and
Motorola-type CPUs work easily with the SL811HS without any
external glue logic requirements.
Host Mode Memory Map
Peripheral Mode Memory Map
DMA Controller (slave mode only)
Auto Address Increment Mode
In applications that require transfers of large amounts of data
such as scanner interfaces, the SL811HS provides a DMA inter-
face. This interface supports DMA READ or WRITE transfers to
the SL811HS internal RAM buffer, it is done through the micro-
processor data bus via two control lines (nDRQ - Data Request
and nDACK - Data Acknowledge), along with the nWR line and
controls the data flow into the SL811HS. The SL811HS has a
count register that allows selection of programmable block sizes
for DMA transfer. The control signals, both nDRQ and nDACK,
are designed for compatibility with standard DMA interfaces.
The SL811HS supports auto increment mode to reduce READ
and WRITE memory cycles. In this mode, the microcontroller
needs to set up the address only once. Whenever any subse-
quent DATA is accessed, the internal address counter advances
to the next address location.
Auto Address Increment Example. To fill the data buffer that is
configured for address 10h, follow these steps:
1. Write 10h to SL811HS with A0 LOW. This sets the memory
address that is used for the next operation.
Interrupt Controller
2. Write the first data byte into address 10h by doing a write
operation with A0 HIGH. An example is a Get Descriptor; the
first byte that is sent to the device is 80h (bmRequestType) so
you would write 80h to address 10h.
The SL811HS interrupt controller provides a single output signal
(INTRQ) that is activated by a number of programmable events
that may occur as result of USB activity. Control and status
registers are provided to allow the user to select single or
multiple events, which generate an interrupt (assert INTRQ) and
let the user view interrupt status. The interrupts are cleared by
writing to the Interrupt Status Register.
3. Now the internal RAM address pointer is set to 11h. So, by
doing another write with A0 HIGH, RAM address location 11h
is written with the data. Continuing with the Get Descriptor
example, a 06h is written to address 11h for the bRequest
value.
Buffer Memory
4. Repeat Step 3 until all the required bytes are written as
necessary for a transfer. If auto-increment is not used, you
write the address value each time before writing the data as
shown in Step 1.
The SL811HS contains 256 bytes of internal memory used for
USB data buffers, control registers, and status registers. When
in master mode (host mode), the memory is defined where the
first 16 bytes are registers and the remaining 240 bytes are used
for USB data buffers. When in slave mode (peripheral mode), the
first 64 bytes are used for the four endpoint control and status
registers along with the various other registers. This leaves 192
bytes of endpoint buffer space for USB data transfers.
The advantage of auto address increment mode is that it reduces
the number of required SL811HS memory READ/WRITE cycles
to move data to/from the device. For example, transferring 64
bytes of data to/from SL811HS, using auto increment mode,
reduces the number of cycles to 1 address WRITE and 64
READ/WRITE data cycles, compared to 64 address writes and
64 data cycles for random access.
Access to the registers and data memory is through the 8-bit
external microprocessor data bus, in either indexed or direct
addressing. Indexed mode uses the Auto Address Increment
Document 38-08008 Rev. *F
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SL811HS
Figure 3. Optional 12 MHz Crystal Circuit
PLL Clock Generator
Either a 12 MHz or a 48 MHz external crystal is used with the
SL811HS[1]. Two pins, X1 and X2, are provided to connect a low
cost crystal circuit to the device as shown in Figure 2 and
Figure 2. Use an external clock source if available in the appli-
cation instead of the crystal circuit by connecting the source
directly to the X1 input pin. When a clock is used, the X2 pin is
not connected.
X1
X2
Rf
1M
Rs
100
When the CM pin is tied to a logic 0, the internal PLL is bypassed
so the clock source must meet the timing requirements specified
by the USB specification.
X1
Figure 2. Full Speed 48 MHz Crystal Circuit
12 MHz , series, 20-pF load
X2
Cin
Cout
X1
22 pF
22 pF
Rf
1M
Typical Crystal Requirements
Rs
The following are examples of ‘typical requirements.’ Note that
these specifications are generally found as standard crystal
values and are less expensive than custom values. If crystals are
used in series circuits, load capacitance is not applicable. Load
capacitance of parallel circuits is a requirement. 48 MHz third
overtone crystals require the Cin/Lin filter to guarantee 48 MHz
operation.
X1
100
48 MHz, series, 20-pF load
Cbk
0.01 μF
12 MHz Crystals:
Cout
Frequency Tolerance:
Operating Temperature Range:
Frequency:
±100 ppm or better
0°C to 70°C
12 MHz
Lin
22 pF
Cin
2.2 μH
22 pF
Frequency Drift over Temperature:
ESR (Series Resistance):
Load Capacitance:
± 50 ppm
60Ω
10 pF min.
7 pF max.
0.1–0.5 mW
fundamental
Shunt Capacitance:
Drive Level:
Operating Mode:
48 MHz Crystals:
Frequency Tolerance:
Operating Temperature Range:
Frequency:
±100 ppm or better
0°C to 70°C
48 MHz
Frequency Drift over Temperature:
ESR (Series Resistance):
Load Capacitance:
± 50 ppm
40 Ω
10 pF min.
7 pF max.
Shunt Capacitance:
Drive Level:
0.1–0.5 mW
third overtone
Operating Mode:
Note
1. CM (Clock Multiply) pin of the SL811HS must be tied to GND when 48 MHz crystal circuit or 48 MHz clock source is used.
Document 38-08008 Rev. *F
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SL811HS
Table 1. SL811HS Master (Host) Mode Registers
USB Transceiver
The SL811HS has a built in transceiver that meets USB Specifi-
cation 1.1. The transceiver is capable of transmitting and
receiving serial data at USB full speed (12 Mbits) and low speed
(1.5 Mbits). The driver portion of the transceiver is differential
while the receiver section is comprised of a differential receiver
and two single-ended receivers. Internally, the transceiver inter-
faces to the Serial Interface Engine (SIE) logic. Externally, the
transceiver connects to the physical layer of the USB.
Register Name
SL811HS
SL811HS
(hex) Address
USB-A Host Control Register
USB-A Host Base Address
USB-A Host Base Length
00h
01h
02h
03h
USB-A Host PID, Device Endpoint
(Write)/USB Status (Read)
USB-A Host Device Address
(Write)/Transfer Count (Read)
04h
SL811HS Registers
Operation and control of the SL811HS is managed through
internal registers. When operating in Master/Host mode, the first
16 address locations are defined as register space. In
Slave/Peripheral mode, the first 64 bytes are defined as register
space. The register definitions vary greatly between each mode
of operation and are defined separately in this document (section
“Table 1 shows the memory map and register mapping of the
SL811HS in master/host mode.” on page 5 describes Host
register definitions, while section “SL811HS Slave Mode
Registers” on page 14 describes Slave register definitions).
Access to the registers are through the microprocessor interface
similar to normal RAM accesses (see “Bus Interface Timing
Requirements” on page 25) and provide control and status infor-
mation for USB transactions.
Control Register 1
05h
Interrupt Enable Register
Reserved Register
06h
Reserved
08h
USB-B Host Control Register
USB-B Host Base Address
USB-B Host Base Length
09h
0Ah
USB-B Host PID, Device Endpoint
(Write)/USB Status (Read)
0Bh
USB-B Host Device Address
(Write)/Transfer Count (Read)
0Ch
0Dh
Status Register
Any write to control register 0FH enables the SL811HS full
features bit. This is an internal bit of the SL811HS that enables
additional features.
SOF Counter LOW (Write)/HW Revision 0Eh
Register (Read)
SOF Counter HIGH and Control Register 2 0Fh
Table 1 shows the memory map and register mapping of the
SL811HS in master/host mode.
Memory Buffer
10H-FFh
The registers in the SL811HS are divided into two major groups.
The first group is referred to as USB Control registers. These
registers enable and provide status for control of USB transac-
tions and data flow. The second group of registers provides
control and status for all other operations.
Register Values on Power-up and Reset
The following registers initialize to zero on power-up and reset:
■ USB-A/USB-B Host Control Register [00H, 08H] bit 0 only
■ Control Register 1 [05H]
■ USB Address Register [07H]
■ Current Data Set/Hardware Revision/SOF Counter LOW
Register [0EH]
All other register’s power-up and reset in an unknown state and
firmware for initialization.
Document 38-08008 Rev. *F
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SL811HS
USB Control Registers
The SL811HS USB Host Control has two groups of five registers
each which map in the SL811HS memory space. These registers
are defined in the following tables.
Communication and data flow on the USB bus uses the
SL811HS’ USB A-B Control registers. The SL811HS communi-
cates with any USB Device function and any specific endpoint
via the USB-A or USB-B register sets.
Table 2. SL811HS Host Control Registers
SL811HS
Register Name SL811H
The USB A-B Host Control registers are used in an overlapped
configuration to manage traffic on the USB bus. The USB Host
Control register also provides a means to interrupt an external
CPU or microcontroller when one of the USB protocol transac-
tions is completed. Table 1 and Table 2 show the two sets of USB
Host Control registers, the ’A’ set and ’B’ set. The two register
sets allow for overlapping operation. When one set of param-
eters is being set up, the other is transferring. On completion of
a transfer to an endpoint, the next operation is controlled by the
other register set.
(hex) Address
USB-A Host Control Register
USB-A Host Base Address
USB-A Host Base Length
00h
01h
02h
03h
USB-A Host PID, Device Endpoint
(Write)/USB Status (Read)
USB-A Host Device Address
(Write)/Transfer Count (Read)
04h
Note The USB-B register set is used only when SL811HS mode
is enabled by initializing register 0FH.
USB-B Host Control Register
USB-B Host Base Address
USB-B Host Base Length
08h
09h
0Ah
0Bh
USB-B Host PID, Device Endpoint
(Write)/USB Status (Read)
USB-B Host Device Address
(Write)/Transfer Count (Read)
0Ch
Document 38-08008 Rev. *F
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SL811HS
USB-A/USB-B Host Control Registers [Address = 00h, 08h] .
Table 3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Preamble
Data Toggle Bit
SyncSOF
ISO
Reserved
Direction
Enable
Arm
Bit Position Bit Name
Function
7
Preamble
If bit = ’1’ a preamble token is transmitted before transfer of low speed packet. If bit = ’0’,
preamble generation is disabled.
■ The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only
used to send packets to a low speed device through a hub. To communicate to a full speed
device, this bit is set to ‘0’. For example, when SL811HS communicates to a low speed
device via the HUB:
— Set SL811HS SIE to operate at full speed, i.e., bit 5 of register 05h (Control Register 1)
= ’0’.
— Set bit 6 of register 0Fh (Control Register 2) = ’0’. Set correct polarity of DATA+ and
DATA– state for full speed.
— Set bit 7, Preamble bit, = ’1’ in the Host Control register.
■ When SL811HS communicates directly to a low speed device:
— Set bit 5 of register 05h (Control Register 1) = ’1’.
— Set bit 6 of register 0Fh (Control Register 2) = ’1’, DATA+ and DATA– polarity for low
speed.
— The state of bit 7 is ignored in this mode.
6
5
Data Toggle Bit
SyncSOF
’0’ if DATA0, ’1’ if DATA1 (only used for OUT tokens in host mode).
’1’ = Synchronize with the SOF transfer when operating in FS only.
The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted.
When bit 5 = ‘1’, the next enabled packet is sent after next SOF. If bit 5 = ‘0’ the next packet
is sent immediately if the SIE is free. If operating in low speed, do not set this bit.
4
3
2
1
ISO
When set to ’1’, this bit allows Isochronous mode for this packet.
Bit 3 is reserved for future use.
Reserved
Direction
Enable
When equal to ’1’ transmit (OUT). When equal to ’0’ receive (IN).
If Enable = ’1’, this bit allows transfers to occur. If Enable = ’0’, USB transactions are ignored.
The Enable bit is used in conjunction with the Arm bit (bit 0 of this register) for USB transfers.
0
Arm
Allows enabled transfers when Arm = ’1’. Cleared to ’0’ when transfer is complete (when
Done Interrupt is asserted).
Once the other SL811HS Control registers are configured (registers 01h-04h or 09h-0Ch) the Host Control register is programmed to
initiate the USB transfer. This register initiates the transfer when the Enable and Arm bit are set as described above.
USB-A/USB-B Host Base Address [Address = 01h, 09h] .
Table 4. USB-A/USB-B Host Base Address Definition [Address 01h, 09h]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HBADD7
HBADD6
HBADD5
HBADD4
HBADD3
HBADD2
HBADD1
HBADD0
The USB-A/B Base Address is a pointer to the SL811HS memory buffer location for USB reads and writes. When transferring data
OUT (Host to Device), the USB-A and USB-B Host Base Address registers can be set up before setting ARM on the USB-A or USB-B
Host Control register. When using a double buffer scheme, the Host Base Address could be set up with the first buffer used for DATA0
data and the other for DATA1 data.
Document 38-08008 Rev. *F
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SL811HS
USB-A/USB-B Host Base Length [Address = 02h, 0Ah].
Table 5. USB-A / USB-B Host Base Length Definition [Address 02h, 0Ah]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HBL7
HBL6
HBL5
HBL4
HBL3
HBL2
HBL1
HBL0
The USB A/B Host Base Length register contains the maximum packet size transferred between the SL811HS and a slave USB
peripheral. Essentially, this designates the largest packet size that is transferred by the SL811HS. Base Length designates the size
of data packet sent or received. For example, in full speed BULK mode, the maximum packet length is 64 bytes. In ISO mode, the
maximum packet length is 1023 bytes since the SL811HS only has an 8-bit length; the maximum packet size for the ISO mode using
the SL811HS is 255 – 16 bytes (register space). When the Host Base length register is set to zero, a Zero-Length packet is transmitted.
USB-A/USB-B USB Packet Status (Read) and Host PID, Device Endpoint (Write) [Address = 03h, 0Bh]. This register has two
modes dependent on whether it is read or written. When read, this register provides packet status and contains information relative
to the last packet that has been received or transmitted. This register is not valid for reading until after the Done interrupt occurs, which
causes the register to update.
Table 6. USB-A/USB-B USB Packet Status Register Definition when READ [Address 03h, 0Bh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STALL
NAK
Overflow
Setup
Sequence
Time-out
Error
ACK
Bit Position Bit Name
Function
7
6
5
STALL
NAK
Slave device returned a STALL.
Slave device returned a NAK.
Overflow
Overflow condition - maximum length exceeded during receives. For underflow, see
USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h,
0Ch].
4
3
2
Setup
This bit is not applicable for Host operation since a SETUP packet is generated by the host.
Sequence bit. ’0’ if DATA0, ’1’ if DATA1.
Sequence
Time-out
Timeout occurred. A timeout is defined as 18-bit times without a device response (in full
speed).
1
0
Error
ACK
Error detected in transmission. This includes CRC5, CRC16, and PID errors.
Transmission Acknowledge.
When written, this register provides the PID and Endpoint information to the USB SIE engine used in the next transaction.
All 16 Endpoints can be addressed by the SL811HS.
Table 7. USB-A / USB-B Host PID and Device Endpoint Register when WRITTEN [Address 03h, 0Bh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PID3
PID2
PID1
PID0
EP3
EP2
EP1
EP0
PID[3:0]: 4-bit PID Field (See following table), EP[3:0]: 4-bit Endpoint Value in Binary.
PID TYPE
SETUP
IN
D7-D4
1101 (D Hex)
1001 (9 Hex)
0001 (1 Hex)
0101 (5 Hex)
1100 (C Hex)
1010 (A Hex)
1110 (E Hex)
0011 (3 Hex)
1011 (B Hex)
OUT
SOF
PREAMBLE
NAK
STALL
DATA0
DATA1
Document 38-08008 Rev. *F
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SL811HS
USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register has two
different functions depending on whether it is read or written. When read, this register contains the number of bytes remaining (from
Host Base Length value) after a packet is transferred. For example, if the Base Length register is set to 0x040 and an IN Token was
sent to the peripheral device. If, after the transfer is complete, the value of the Host Transfer Count is 0x10, the number of bytes
actually transferred is 0x30. This is considered as an underflow indication.
Table 8. USB-A / USB-B Host Transfer Count Register when READ [Address 04h, 0Ch]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HTC7
HTC6
HTC5
HTC4
HTC3
HTC2
HTC1
HTC0
When written, this register contains the USB Device Address with which the Host communicates.
Table 9. USB-A / USB-B USB Address when WRITTEN [Address 04h, 0Ch]
Bit 7
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
Bit 0
0
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DA6-DA0
DA7
Device address, up to 127 devices can be addressed.
Reserved bit must be set to zero.
SL811HS Control Registers
The next set of registers are the Control registers and control more of the operation of the chip instead of USB packet type of transfers.
Table 10 is a summary of the control registers.
Table 10. Control Registers Summary
Register Name SL811H
SL811HS (hex) Address
Control Register 1
Interrupt Enable Register
Reserved Register
Status Register
05h
06h
07h
0Dh
SOF Counter LOW (Write)/HW Revision Register (Read)
SOF Counter HIGH and Control Register 2
Memory Buffer
0Eh
0Fh
10h-FFh
Document 38-08008 Rev. *F
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SL811HS
Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined as
follows.
Table 11. Control Register 1 [Address 05h]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Suspend
USB Speed J-K state force USB Engine
Reset
Reserved
Reserved
SOF ena/dis
Bit Position Bit Name
Function
7
6
5
4
3
Reserved
‘0’
Suspend
’1’ = enable, ’0’ = disable.
’0’ setup for full speed, ’1’ setup low speed.
See Table 12.
USB Speed
J-K state force
USB Engine Reset USB Engine reset = ’1’. Normal set ’0’.
When a device is detected, the first thing that to do is to send it a USB Reset to force it into
its default address of zero. The USB 2.0 specification states that for a root hub a device
must be reset for a minimum of 50 mS.
2
1
0
Reserved
Reserved
SOF ena/dis
Some existing firmware examples set bit 2, but it is not necessary.
‘0’
’1’ = enable auto Hardware SOF generation; ’0’ = disable.
In the SL811HS, bit 0 is used to enable hardware SOF autogeneration. The generation of
SOFs continues when set to ‘0’, but SOF tokens are not output to USB.
At power-up this register is cleared to all zeros.
There are two cases when communicating with a low speed
device. When a low speed device is connected directly to the
SL811HS, bit 5 of Register 05h is set to ’1’ and bit 6 of register
0Fh, Polarity Swap, is set to ’1’ in order to change the polarity of
D+ and D–. When a low speed device is connected via a HUB to
SL811HS, bit 5 of Register 05h is set to ’0’ and bit 6 of register
0Fh is set to ’0’ in order to keep the polarity of D+ and D– for full
speed. In addition, make sure that bit 7 of USB-A/USB-B Host
Control registers [00h, 08h] is set to ’1’ for preamble generation.
Low-power Modes [Bit 6 Control Register, Address 05h]
When bit 6 (Suspend) is set to ’1’, the power of the transmit
transceiver is turned off, the internal RAM is in suspend mode,
and the internal clocks are disabled.
Note Any activity on the USB bus (that is, K-State, etc.) resumes
normal operation. To resume normal operation from the CPU
side, a Data Write cycle (i.e., A0 set HIGH for a Data Write cycle)
is done. This is a special case and not a normal direct write
where the address is first written and then the data. To resume
normal operation from the CPU side, you must do a Data Write
cycle only.
J-K Programming States [Bits 4 and 3 of Control Register 1,
Address 05h]
The J-K force state control and USB Engine Reset bits are used
to generate a USB reset condition. Forcing K-state is used for
Peripheral device remote wake up, resume, and other modes.
These two bits are set to zero on power-up.
Low Speed/Full Speed Modes [Bit 5 Control Register 1,
Address 05h]
The SL811HS is designed to communicate with either full- or low
speed devices. At power-up bit 5 is LOW, i.e., for full speed.
Table 12. Bus Force States
USB Engine J-K Force
Function
Reset
State
0
0
1
1
0
1
0
1
Normal operating mode
Force USB Reset, D+ and D– are set LOW (SE0)
Force J-State, D+ set HIGH, D– set LOW[2]
Force K-State, D– set HIGH, D+ set LOW[3]
Notes
2. Force K-State for low speed.
3. Force J-State for low speed.
Document 38-08008 Rev. *F
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SL811HS
USB Reset Sequence
Interrupt Enable Register [Address = 06h]. The SL811HS
provides an Interrupt Request Output, which is activated for a
number of conditions. The Interrupt Enable register allows the
user to select conditions that result in an interrupt that is issued
to an external CPU through the INTRQ pin. A separate Interrupt
Status register reflects the reason for the interrupt. Enabling or
disabling these interrupts does not have an effect on whether or
not the corresponding bit in the Interrupt Status register is set or
cleared; it only determines if the interrupt is routed to the INTRQ
pin. The Interrupt Status register is normally used in conjunction
with the Interrupt Enable register and can be polled in order to
determine the conditions that initiated the interrupt (See the
description for the Interrupt Status Register). When a bit is set to
’1’ the corresponding interrupt is enabled. So when the enabled
interrupt occurs, the INTRQ pin is asserted. The INTRQ pin is a
level interrupt, meaning it is not deasserted until all enabled inter-
rupts are cleared.
After a device is detected, write 08h to the Control register (05h)
to initiate the USB reset, then wait for the USB reset time (root
hub should be 50 ms) and additionally some types of devices
such as a Forced J-state. Lastly, set the Control register (05h)
back to 0h. After the reset is complete, the auto-SOF generation
is enabled.
SOF Packet Generation
The SL811HS automatically computes the frame number and
CRC5 by hardware. No CRC or SOF generation is required by
external firmware for the SL811HS, although it can be done by
sending an SOF PID in the Host PID, Device Endpoint register.
To enable SOF generation, assuming host mode is configured:
1. Set up the SOF interval in registers 0x0F and 0x0E.
2. Enable the SOF hardware generation in this register by
setting bit 0 = ‘1’.
3. Set the Arm bit in the USB-A Host Control register.
Table 13. Interrupt Enable Register [Address 06h]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Device
Inserted/
SOF Timer
Reserved
Reserved
USB-B
DONE
USB-A
DONE
Detect/Resume Removed
Bit Position
Bit Name
Reserved
Device Detect/Resume Enable Device Detect/Resume Interrupt.
Function
7
6
‘0’
When bit 6 of register 05h (Control Register 1) is equal to ’1’, bit 6 of this register enables
the Resume Detect Interrupt. Otherwise, this bit is used to enable Device Detection
status as defined in the Interrupt Status register bit definitions.
5
4
Inserted/Removed
SOF Timer
Enable Slave Insert/Remove Detection is used to enable/disable the device
inserted/removed interrupt.
1 = Enable Interrupt for SOF Timer. This is typically at 1 mS intervals, although the
timing is determined by the SOF Counter high/low registers.
To use this bit function, bit 0 of register 05h must be enabled and the SOF counter
registers 0E hand 0Fh must be initialized.
3
2
1
0
Reserved
‘0’
Reserved
‘0’
USB-B DONE
USB-A DONE
USB-B Done Interrupt (see USB-A Done interrupt).
USB-A Done Interrupt. The Done interrupt is triggered by one of the events that are
logged in the USB Packet Status register. The Done interrupt causes the Packet Status
register to update.
USB Address Register, Reserved, Address [Address = 07h]. This register is reserved for the device USB Address in Slave
operation. It should not be written by the user in host mode.
Registers 08h-0Ch Host-B registers. Registers 08h-0Ch have the same definition as registers 00h-04h except they apply to Host-B
instead of Host-A.
Document 38-08008 Rev. *F
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SL811HS
Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE register providing interrupt
status. Interrupts are cleared by writing to this register. To clear a specific interrupt, the register is written with corresponding bit set
to ’1’.
Table 14. Interrupt Status Register [Address 0Dh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D+
Device
Detect/Resume
Insert/Remove SOF timer
Reserved
Reserved
USB-B
USB-A
Bit Position
Bit Name
Function
7
D+
Value of the Data+ pin.
Bit 7 provides continuous USB Data+ line status. Once it is determined that a device
is inserted (as described below) with bits 5 and 6, bit 7 is used to detect if the inserted
device is low speed (0) or full speed (1).
6
5
Device Detect/Resume Device Detect/Resume Interrupt.
Bit 6 is shared between Device Detection status and Resume Detection interrupt.
When bit-6 of register 05h is set to one, this bit is the Resume detection Interrupt bit.
Otherwise, this bit is used to indicate the presence of a device, ’1’ = device ‘Not present’
and ’0’ = device ‘Present.’ In this mode, check this bit along with bit 5 to determine
whether a device has been inserted or removed.
Insert/Remove
Device Insert/Remove Detection.
Bit 5 is provided to support USB cable insertion/removal for the SL811HS in host mode.
This bit is set when a transition from SE0 to IDLE (device inserted) or from IDLE to
SE0 (device removed) occurs on the bus.
4
3
2
1
0
SOF timer
Reserved
Reserved
USB-B
‘1’ = Interrupt on SOF Timer.
‘0’
‘0’
USB-B Done Interrupt. (See description in Interrupt Enable Register [address 06h].)
USB-A Done Interrupt. (See description in Interrupt Enable Register [address 06h].)
USB-A
Current Data Set Register/Hardware Revision/SOF Counter LOW [Address = 0Eh]. This register has two modes. Read from this
register indicates the current SL811HS silicon revision.
Table 15. Hardware Revision when Read [Address 0Eh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hardware Revision
Reserved
Bit Position
Bit Name
Function
7-4
3-2
1-0
Hardware Revision
Reserved
SL811HS rev1.2 Read = 1H; SL811HS rev1.5 Read = 2.
Read is zero.
Reserved
Reserved for slave.
Writing to this register sets up auto generation of SOF to all connected peripherals. This counter is based on the 12 MHz clock and
is not dependent on the crystal frequency. To set up a 1 ms timer interval, the software must set up both SOF counter registers to the
proper values.
Document 38-08008 Rev. *F
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SL811HS
Table 16. SOF Counter LOW Address when Written [Address 0Eh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SOF7
SOF6
SOF5
SOF4
SOF3
SOF2
SOF1
SOF0
Example: To set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h.
SOF Counter High/Control Register 2 [Address = 0Fh]. When read, this register returns the value of the SOF counter divided by
64. The software must use this register to determine the available bandwidth in the current frame before initiating any USB transfer.
In this way, the user is able to avoid babble conditions on the USB. For example, to determine the available bandwidth left in a frame
do the following.
Maximum number of clock ticks in 1 ms time frame is 12000 (1 count per 12 MHz clock period, or approximately 84 ns.) The value
read back in Register 0FH is the (count × 64) × 84 ns = time remaining in current frame. USB bit time = one 12 MHz period.
Value of register 0FH Available bit times left are between
BBH
BAH
12000 bits to 11968 (187 × 64) bits
11968 bits to 11904 (186 × 64) bits
Note: Any write to the 0Fh register clears the internal frame counter. Write register 0Fh at least once after power-up. The internal
frame counter is incremented after every SOF timer tick. The internal frame counter is an 11-bit counter, which is used to track the
frame number. The frame number is incremented after each timer tick. Its contents are transmitted to the slave every millisecond in
a SOF packet.
Table 17. SOF High Counter when Read [Address 0Fh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C13
C12
C11
C10
C9
C8
C7
C6
When writing to this register the bits definition are defined as follows.
Table 18. Control Register 2 when Written [Address 0Fh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SL811HS
SL811HS
SOF High Counter Register
Master/Slave D+/D– Data
selection
Polarity Swap
Bit Position
Bit Name
Function
7
6
SL811HS Master/Slave selection
Master = 1, Slave = 0.
SL811HS D+/D– Data Polarity Swap
’1’ = change polarity (low speed)
’0’ = no change of polarity (full speed).
5-0
SOF High Counter Register
Write a value or read it back to SOF High Counter Register.
Note Any write to Control register 0Fh enables the SL811HS full
features bit. This is an internal bit of the SL811HS that enables
additional features.
hardware SOF generation. To load both HIGH and LOW
registers with the proper values, the user must follow this
sequence:
1. Write E0h to register 0Eh. This sets the lower byte of the SOF
counter
The USB-B register set is used when SL811HS full feature bit is
enabled.
2. Write AEh to register 0Fh, AEh configures the part for full
speed (no change of polarity) Host with bits 5–0 = 2Eh for
upper portion of SOF counter.
Example. To set up host to generate 1 ms SOF time:
The register 0Fh contains the upper 6 bits of the SOF timer.
Register 0Eh contains the lower 8 bits of the SOF timer. The
timer is based on an internal 12 MHz clock and uses a counter,
which counts down to zero from an initial value. To set the timer
for 1 ms time, the register 0Eh is loaded with value E0h and
register 0Fh (bits 0–5) is loaded with 2Eh. To start the timer, bit
0 of register 05h (Control Register 1) is set to ’1’, which enables
3. Enablebit 0 in register 05h. Thisenableshardwaregeneration
of SOF.
4. Set the ARM bit at address 00h. This starts the SOF
generation.
Document 38-08008 Rev. *F
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SL811HS
Table 19. SL811HS Slave Mode Registers
Register Name
Endpoint specific register addresses
EP 0 – A EP 0 - B
EP 1 – A EP 1 - B EP 2 - A EP 2 - B EP 3 - A
EP 3 - B
0x38
EP Control Register
00h
01h
02h
03h
04h
08h
09h
0Ah
0Bh
0Ch
10h
11h
12h
13h
14h
18h
19h
1Ah
1Bh
1Ch
20h
21h
22h
23h
24h
28h
29h
2Ah
2Bh
2Ch
30h
31h
EP Base Address Register
EP Base Length Register
EP Packet Status Register
EP Transfer Count Register
Register Name
0x39
0x32
0x33
0x34
0x3A
0x3B
0x3C
Miscellaneous register addresses
Control Register 1
05h
06h
Interrupt Status Register
Current Data Set Register
Control Register 2
Reserved
0Dh
Interrupt Enable Register
USB Address Register
SOF Low Register (read only)
SOF High Register (read only)
Reserved
0Eh
07h
0Fh
15h
1Dh1Fh
25h-27h
2Dh-2Fh
16h
Reserved
17h
Reserved
DMA Total Count Low Register
DMA Total Count High Register
Reserved
35h
36h
37h
Memory Buffer
40h – FFh
When in slave mode, the registers in the SL811HS are divided
into two major groups. The first group contains Endpoint regis-
ters that manage USB control transactions and data flow. The
second group contains the USB Registers that provide the con-
trol and status information for all other operations.
Endpoints 0–3 Register Addresses
Each endpoint set has a group of five registers that are mapped
within the SL811HS memory. The register sets have address
assignmenEndpoint 0-3 Register Addressests as shown in the
following table.
Endpoint Registers
Table 20. Endpoint 0-3 Register Addresses
Communication and data flow on USB is implemented using
endpoints. These uniquely identifiable entities are the terminals
of communication flow between a USB host and USB devices.
Each USB device is composed of a collection of independently
operating endpoints. Each endpoint has a unique identifier,
which is the Endpoint Number. For more information, see USB
Specification 1.1 section 5.3.1.
Endpoint Register Set
Endpoint 0 – a
Endpoint 0 – b
Endpoint 1 – a
Endpoint 1 – b
Endpoint 2 – a
Endpoint 2 – b
Endpoint 3 – a
Endpoint 3 – b
Address (in Hex)
00 - 04
08 - 0C
10 - 14
18 - 1C
20 - 24
The SL811HS supports four endpoints numbered 0–3. Endpoint
0 is the default pipe and is used to initialize and generically
manipulate the device to configure the logical device as the
Default Control Pipe. It also provides access to the device's
configuration information, allows USB status and control access,
and supports control transfers.
28 - 2C
30 - 34
38 - 3C
For each endpoint set (starting at address Index = 0), the
registers are mapped as shown in the following table.
Endpoints 1–3 support Bulk, Isochronous, and Interrupt
transfers. Endpoint 3 is supported by DMA. Each endpoint has
two sets of registers—the 'A' set and the 'B' set. This allows
overlapped operation where one set of parameters is set up and
the other is transferring. Upon completion of a transfer to an
endpoint, the ‘next data set’ bit indicates whether set 'A' or set 'B'
is used next. The ‘armed’ bit of the next data set indicates
whether the SL811HS is ready for the next transfer without inter-
ruption.
Table 21. Endpoint Register Indices
Endpoint Register Sets
(for Endpoint n starting at register position Index=0)
Index
Endpoint n Control
Endpoint n Base Address
Endpoint n Base Length
Endpoint n Packet Status
Endpoint n Transfer Count
Index + 1
Index + 2
Index + 3
Index + 4
Document 38-08008 Rev. *F
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SL811HS
Endpoint Control Registers
Endpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]. Each endpoint set has a Control register defined as
follows:
Table 22. Endpoint Control Register [Address EP0a/b:00h/08h, EP1a/b:10h/18h, EP2a/b:20h/28h, EP3a/b:30h/38h]
7
6
5
4
3
2
1
0
Reserved
Sequence
Send STALL
ISO
Next Data Set
Direction
Enable
Arm
Bit Position Bit Name
Function
7
6
5
4
3
2
1
Reserved
Sequence
Send STALL
ISO
Sequence bit. '0' if DATA0, '1' if DATA1.
When set to ‘1’, sends Stall in response to next request on this endpoint.
When set to '1', allows Isochronous mode for this endpoint.
'0' if next data set is ‘A’, '1' if next data set is 'B'.
Next Data Set
Direction
Enable
When Direction = '1', transmit to Host (IN). When Direction = '0', receive from Host (OUT).
When Enable = '1', allows transfers for this endpoint. When set to ‘0’, USB transactions are
ignored. If Enable = '1' and Arm = '0', the endpoint returns NAKs to USB transmissions.
0
Arm
Allows enabled transfers when set =’1’. Clears to '0' when transfer is complete.
Endpoint Base Address [Address a = (EP# * 10h)+1, b = (EP# * 10h)+9]]. Pointer to memory buffer location for USB reads and
writes.
Table 23. Endpoint Base Address Reg [Address; EP0a/b:01h/09h, EP1a/b:11h/19h, EP2a/b:21h/29h, EP3a/b:31h/39h]
7
6
5
4
3
2
1
0
EPxADD7
EPxADD6
EPxADD5
EPxADD4
EPxADD3
EPxADD2
EPxADD1
EPxADD0
Endpoint Base Length [Address a = (EP# * 10h)+2, b = (EP# * 10h)+A]. The Endpoint Base Length is the maximum packet size
for IN/OUT transfers with the host. Essentially, this designates the largest packet size that is received by the SL811HS with an OUT
transfer, or it designates the size of the data packet sent to the host for IN transfers.
Table 24. Endpoint Base Length Reg [Address EP0a/b:02h/0Ah, EP1a/b:12h/1Ah, EP2a/b:22h/2Ah, EP3a/b:32h/3Ah]
7
6
5
4
3
2
1
0
EPxLEN7
EPxLEN6
EPxLEN5
EPxLEN4
EPxLEN3
EPxLEN2
EPxLEN1
EPxLEN0
Document 38-08008 Rev. *F
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SL811HS
Endpoint Packet Status [Address a = (EP# * 10h)+3, b = (EP# * 10h)+Bh]. The packet status contains information relative to the
packet that is received or transmitted. The register is defined as follows:
Table 25. Endpoint Packet Status Reg [Address EP0a/b:03h/0Bh, EP1a/b:13h/1Bh, EP2a/b:23h/2Bh, EP3a/b:33h/3Bh]
7
6
5
4
3
2
1
0
Reserved
Reserved
Overflow
Setup
Sequence
Time-out
Error
ACK
Bit Position Bit Name
Function
7
6
5
Reserved
Reserved
Overflow
Not applicable.
Not applicable.
Overflow condition - maximum length exceeded during receives. This is considered a
serious error. The maximum number of bytes that can be received by an endpoint is deter-
mined by the Endpoint Base Length register for each endpoint. The Overflow bit is only
relevant during OUT Tokens from the host.
4
3
2
1
0
Setup
'1' indicates Setup Packet. If this bit is set, the last packet received was a setup packet.
This bit indicates if the last packet was a DATA0 (0) or DATA1 (1).
This bit is not used in slave mode.
Sequence
Time-out
Error
Error detected in transmission, this includes CRC5/16 and PID errors.
Transmission Acknowledge.
ACK
Endpoint Transfer Count [Address a = (EP# * 10h)+4, b =
(EP# * 10h)+Ch]. As a peripheral device, the Endpoint Transfer
Count register is only important with OUT tokens (host sending
the slave data). When a host sends the peripheral data, the
Transfer Count register contains the difference between the
Endpoint Base Length and the actual number of bytes received
in the last packet. In other words, if the Endpoint Base Length
register was set for 64 (40h) bytes and an OUT token was sent
to the endpoint that only had 16 (10h) bytes, the Endpoint
Transfer Count register has a value of 48 (30h). If more bytes
were sent in an OUT token then the Endpoint Base Length
register was programmed for, the overflow flag is set in the
Endpoint Packet Status register and is considered a serious
error.
Table 26. Endpoint Transfer Count Reg [Address EP0a/b:04h/0Ch, EP1a/b:14h/1Ch, EP2a/b:24h/2Ch, EP3a/b:34h/3Ch]
7
6
5
4
3
2
1
0
EPxCNT7
EPxCNT6
EPxCNT5
EPxCNT4
EPxCNT3
EPxCNT2
EPxCNT1
EPxCNT0
USB Control Registers
The USB Control registers manage communication and data flow on the USB. Each USB device is composed of a collection of
independently operating endpoints. Each endpoint has a unique identifier, which is the Endpoint Number. For more details about USB
endpoints, refer to the USB Specification 1.1, Section 5.3.1.
The Control and Status registers are mapped as follows:
Table 27. USB Control Registers
Register Name
Address (in Hex)
Control Register 1
05h
06h
07h
0Dh
0Eh
0Fh
15h
16h
35h
36h
Interrupt Enable Register
USB Address Register
Interrupt Status Register
Current Data Set Register
Control Register 2
SOF Low Byte Register
SOF High Byte Register
DMA Total Count Low Byte Register
DMA Total Count High Byte Register
Document 38-08008 Rev. *F
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SL811HS
Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control bits.
Table 28. Control Register 1 [Address 05h]
7
6
5
4
3
2
1
0
Reserved
STBYD
SPSEL
J-K1
J-K0
DMA Dir
DMA Enable USB Enable
Bit Position Bit Name
Function
7
6
Reserved
STBYD
Reserved bit - must be set to '0'.
XCVR Power Control. ‘1’ sets XCVR to low power. For normal operation set this bit to ‘0’.
Suspend mode is entered if bit 6 = ‘1’ and bit ‘0’ (USB Enable) = ‘0’.
5
4
3
SPSEL
Speed Select. ‘0’ selects full speed. ‘1’ selects low speed (also see Table 33 on page 18).
J-K Force State
USB Engine Reset
J-K1 and J-K0 force state control bits are used to generate various USB bus conditions.
Forcing K-state is used for Peripheral device remote wake-up, Resume, and other modes.
These two bits are set to zero on power-up, see Table 12 on page 10 for functions.
2
1
0
DMA Dir
DMA Transfer Direction. Set equal to ‘1’ for DMA READ cycles from SL811HS. Set equal to
‘0’ for DMA WRITE cycles.
DMA Enable
USB Enable
Enable DMA operation when equal to ‘1’. Disable = ‘0’. DMA is initiated when DMA Count
High is written.
Overall Enable for Transfers. ‘1’ enables and’ ‘0 disables. Set this bit to ‘1’ to enable USB
communication. Default at power-up = ‘0’
JK-Force State
USB Engine Reset
Function
0
0
1
1
0
1
0
1
Normal operating mode
Force SE0, D+ and D– are set low
Force K-State, D– set high, D+ set low
Force J-State, D+ set high, D– set low
Interrupt Enable Register, Address [06h] . The SL811HS
provides an Interrupt Request Output that is activated resulting
from a number of conditions. The Interrupt Enable register allows
the user to select events that generate the Interrupt Request
Output assertion. A separate Interrupt Status register is read in
order to determine the condition that initiated the interrupt (see
the description in section Interrupt Status Register, Address
[0Dh]). When a bit is set to ‘1’, the corresponding interrupt is
enabled. Setting a bit in the Interrupt Enable register does not
effect the Interrupt Status register’s value; it just determines
which interrupts are output on INTRQ.
Table 29. Interrupt Enable Register [Address: 06h]
7
6
5
4
3
2
1
0
DMA Status
USB Reset SOF Received DMA Done
Endpoint 3
Done
Endpoint 2
Done
Endpoint 1
Done
Endpoint 0
Done
Bit Position Bit Name
Function
7
DMA Status
When equal to ‘1’, indicates DMA transfer is in progress. When equal to ‘0’, indicates DMA
transfer is complete.
6
5
4
3
2
1
0
USB Reset
Enable USB Reset received interrupt when = ‘1’.
Enable SOF Received Interrupt when = ‘1’.
Enable DMA done Interrupt when = ‘1’.
SOF Received
DMA Done
Endpoint 3 Done
Endpoint 2 Done
Endpoint 1 Done
Endpoint 0 Done
Enable Endpoint 3 done Interrupt when = ‘1’.
Enable Endpoint 2 done Interrupt when = ‘1’.
Enable Endpoint 1 done Interrupt when = ‘1’.
Enable Endpoint 0 done Interrupt when = ‘1’.
Document 38-08008 Rev. *F
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SL811HS
USB Address Register, Address [07h]
This register contains the USB Device Address after assignment by USB host during configuration. On power-up or reset, USB
Address register is set to Address 00h. After USB configuration and address assignment, the device recognizes only USB transactions
directed to the address contained in the USB Address register.
Table 30. USB Address Register [Address 07h]
7
6
5
4
3
2
1
0
USBADD7
USBADD6
USBADD5
USBADD4
USBADD3
USBADD2
USBADD1
USBADD0
Interrupt Status Register, Address [0Dh]
This read/write register serves as an Interrupt Status register when it is read, and an Interrupt Clear register when it is written. To clear
an interrupt, write the register with the appropriate bit set to ‘1’. Writing a ‘0’ has no effect on the status.
Table 31. Interrupt Status Register [Address 0Dh]
7
6
5
4
3
2
1
0
DMA Status
USB Reset SOF Received DMA Done
Endpoint 3
Done
Endpoint 2
Done
Endpoint 1
Done
Endpoint 0
Done
Bit Position Bit Name
Function
7
DMA Status
When equal to ‘1’, indicates DMA transfer is in progress. When equal to 0, indicates DMA
transfer is complete. An interrupt is not generated when DMA is complete.
6
5
4
3
2
1
0
USB Reset
USB Reset Received Interrupt.
SOF Received Interrupt.
DMA Done Interrupt.
SOF Received
DMA Done
Endpoint 3 Done
Endpoint 2 Done
Endpoint 1 Done
Endpoint 0 Done
Endpoint 3 Done Interrupt.
Endpoint 2 Done Interrupt.
Endpoint 1 Done Interrupt.
Endpoint 0 Done Interrupt.
Current Data Set Register, Address [0Eh]. This register indicates current selected data set for each endpoint.
Table 32. Current Data Set Register [Address 0Eh]
7
6
5
4
3
2
1
0
Reserved
Endpoint 3
Endpoint 2
Endpoint 1
Endpoint 0
Bit Position Bit Name
Function
7-4
3
Reserved
Not applicable.
Endpoint 3 Done
Endpoint 2 Done
Endpoint 1 Done
Endpoint 0 Done
Endpoint 3a = 0, Endpoint 3b = 1.
Endpoint 2a = 0, Endpoint 2b = 1.
Endpoint 1a = 0, Endpoint 1b = 1.
Endpoint 0a = 0, Endpoint 0b = 1.
2
1
0
Control Register 2, Address [0Fh]. Control Register 2 is used to control if the device is configured as a master or a slave. It can
change the polarity of the Data+ and Data- pins to accommodate both full- and low speed operation.
Table 33. Control Register 2 [Address 0Fh]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SL811HS
SL811HS
Reserved
Master/Slave D+/D– Data
selection Polarity Swap
Document 38-08008 Rev. *F
Page 18 of 32
[+] Feedback
SL811HS
Bit Position Bit Name
Function
7
SL811HS
Master/Slave
Master = ‘1’
Slave = ‘0’
selection
6
SL811HS D+/D–
Data Polarity Swap ’0’ = no change of polarity (full speed)
’1’ = change polarity (low speed)
5-0
Reserved NA
SOF Low Register, Address [15h]. Read only register
contains the 7 low order bits of Frame Number in positions: bit
7:1. Bit 0 is undefined. Register is updated when a SOF packet
is received. Do not write to this register.
ferred between a peripheral to the SL811HS. The count may
sometimes require up to 16 bits, therefore the count is repre-
sented in two registers: Total Count Low and Total Count High.
EP3 is only supported with DMA operation.
SOF High Register, Address [16h]. Read only register
contains the 4 low order bits of Frame Number in positions: bit
7:4. Bits 3:0 are undefined and should be masked when read by
the user. This register is updated when a SOF packet is received.
The user should not write to this register.
DMA Total Count High Register, Address [36h]. The DMA
Total Count High register contains the high order 8 bits of DMA
count. When written, this register enables DMA if the DMA
Enable bit is set in Control Register 1. The user should always
write Low Count register first, followed by a write to High Count
register, even if high count is 00h.
DMA Total Count Low Register, Address [35h]. The DMA
Total Count Low register contains the low order 8 bits of DMA
count. DMA total count is the total number of bytes to be trans-
Document 38-08008 Rev. *F
Page 19 of 32
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SL811HS
Physical Connections
These parts are offered in 48-pin TQFP package. The 48-pin TQFP package is the SL811HST-AXC.
48-Pin TQFP Physical Connections
48-Pin TQFP AXC Pin Layout
Figure 4. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout
NC
nDACK*
nDRQ*
D7
nRD
NC
VDD
[4]
NC
NC
A0
NC
M/S
37
1
36
48
NC
NC
NC
NC
NC
nWR
nCS
CM
D6
D5
D4
VDD1
Data+
Data-
48-Pin TQFP
GND
D3
USBGnd
NC
D2
D1
NC
NC
NC
12
24
NC
25
13
nRST
INTRQ
NC
GND
NC
NC
Clk/X1
VDD
NC
NC
D0
X2
*See Table 34 on page 21 for Pin and Signal Description for Pins 43 and 44 in Host Mode.
The diagram below illustrates a simple +3.3 V voltage source.
Figure 5. Sample VDD Generator
+5V (USB)
R1
45 Ohms
2N2222
Zener
+3.3 V (VDD)
3.9v, 1N52288CT-
GND
Note
4. NC. Indicates No Connection. NC Pins must be left unconnected.
Document 38-08008 Rev. *F
Page 20 of 32
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SL811HS
USB Host Controller Pins Description
The SL811HST-AXC is packaged in a 48-pin TQFP. These devices require a 3.3 VDC power source and an external 12 or 48 MHz
crystal or clock..
Table 34. Pin and Signal Description for Pins
48-Pin TQFP
Pin Type
Pin Name
Pin Description
AXC Pin No.
1
2
3
NC
NC
IN
NC
NC
No connection.
No connection.
nWR
Write Strobe Input. An active LOW input used with nCS to write to
registers/data memory.
4
IN
nCS
Active LOW 48-Pin TQFP Chip select. Used with nRD and nWr when
accessing the 48-Pin TQFP.
5[5]
6
IN
VDD1
BIDIR
BIDIR
GND
NC
CM
+3.3 VDC
DATA +
DATA -
USB GND
NC
Clock Multiply. Select 12 MHz/48 MHz Clock Source.
Power for USB Transceivers. VDD1 may be connected to VDD
USB Differential Data Signal HIGH Side.
USB Differential Data Signal LOW Side.
Ground Connection for USB.
No connection.
.
7
8
9
10
11
12
13
14
15[6]
16
NC
NC
No connection.
NC
NC
No connection.
NC
NC
No connection.
NC
NC
No connection.
VDD
IN
+3.3 VDC
CLK/X1
Device VDD Power.
Clock or External Crystal X1 connection. The X1/X2 Clock requires external
12 or 48 MHz matching crystal or clock source.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OUT
IN
X2
nRST
INTRQ
GND
D0
External Crystal X2 connection.
Device active low reset input.
Active HIGH Interrupt Request output to external controller.
Device Ground.
OUT
GND
BIDIR
NC
Data 0. Microprocessor Data/Address Bus.
No connection.
NC
NC
NC
No connection.
NC
NC
No connection.
NC
NC
No connection.
NC
NC
No connection.
BIDIR
BIDIR
BIDIR
GND
BIDIR
BIDIR
D1
Data 1. Microprocessor Data/Address Bus.
Data 2. Microprocessor Data/Address Bus.
Data 3. Microprocessor Data/Address Bus.
Device Ground.
D2
D3
GND
D4
Data 4. Microprocessor Data/Address Bus.
Data 5. Microprocessor Data/Address Bus.
D5
Notes
5. The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source.
6. VDD can be derived from the USB supply. See Figure 5 on page 20.
Document 38-08008 Rev. *F
Page 21 of 32
[+] Feedback
SL811HS
Table 34. Pin and Signal Description for Pins
48-Pin TQFP
Pin Type
Pin Name
Pin Description
AXC Pin No.
33
34
BIDIR
NC
D6
NC
Data 6. Microprocessor Data/Address Bus.
No connection.
35
NC
NC
No connection.
36
NC
NC
No connection.
37
NC
NC
No connection.
38
NC
NC
No connection.
39
BIDIR
IN
D7
Data 7. Microprocessor Data/Address Bus.
Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master.
Device VDD Power.
40
M/S
+3.3 VDC
A0
41
42[8]
VDD
IN
A0 = ’0’. Selects address pointer. Register A0 = ’1’. Selects data buffer or
register.
43
44
45
IN
OUT
IN
nDACK
nDRQ
nRD
DMA Acknowledge. An active LOW input used to interface to an external
DMA controller. DMA is enabled only in slave mode. In host mode, the pin
should be tied HIGH (logic ’1’).
DMA Request. An active LOW output used with an external DMA controller.
nDRQ and nDACK form the handshake for DMA data transfers. In host
mode, leave the pin unconnected.
Read Strobe Input. An active LOW input used with nCS to read
registers/data memory.
46
47
48
NC
NC
NC
NC
NC
NC
No connection.
No connection.
No connection.
Figure 6. Package Markings (48-Pin TQFP)
Part Number
YYWW-X.X
XXXX
YYWW = Date code
XXXX = Product code
X.X = Silicon revision number
Notes
7. VDD can be derived from the USB supply. Figure 5 on page 20 shows a simple method to provide 3.3 V/30 mA. Another option is to use a Torex Semiconductor,
Ltd. 3.3 V SMD regulator (part number XC62HR3302MR).
8. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications.
Document 38-08008 Rev. *F
Page 22 of 32
[+] Feedback
SL811HS
Electrical Specifications
Absolute Maximum Ratings
This section lists the absolute maximum ratings of the SL811HS. Exceeding maximum ratings may shorten the useful life of the device.
User guidelines are not tested..
Description
Condition
Storage Temperature
Voltage on any pin with respect to ground
Power Supply Voltage (VDD
Power Supply Voltage (VDD1
–40°C to 125°C
–0.3 V to 6.0 V
4.0 V
)
)
4.0 V
Lead Temperature (10 seconds)
180°C
Recommended Operating Condition
Parameter
Power Supply Voltage, VDD
Power Supply Voltage, VDD1
Operating Temperature
Min
Typical
Max
3.45 V
3.45 V
65°C
3.0 V
3.0 V
0°C
3.3 V
Crystal Requirements,
(X1, X2)
Min
Typical
Max
Operating Temperature Range
Parallel Resonant Frequency
Frequency Drift over Temperature
Accuracy of Adjustment
Series Resistance
0°C
65°C
48 MHz
±50 ppm
±30 ppm
100 Ohms
6 pF
Shunt Capacitance
3 pF
Load Capacitance
20 pF
Drive Level
20 μW
5 mW
Mode of Vibration Third Overtone[9]
External Clock Input Characteristics (X1)
Parameter
Clock Input Voltage at X1 (X2 Open)
Clock Frequency[10]
Min
Typical
Max
1.5 V
48 MHz
Notes
9. Fundamental mode for 12 MHz Crystal.
10. The SL811HS can use a 12 MHz Clock Source.
Document 38-08008 Rev. *F
Page 23 of 32
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SL811HS
DC Characteristics
Parameter
Description
Min
Typ
Max
0.8 V
6.0 V
0.4 V
VIL
Input Voltage LOW
–0.3 V
2.0 V
VIH
VOL
VOH
IOH
IOL
Input Voltage HIGH (5 V Tolerant I/O)
Output Voltage LOW (IOL = 4 mA)
Output Voltage HIGH (IOH = –4 mA)
Output Current HIGH
2.4 V
4 mA
4 mA
Output Current LOW
ILL
Input Leakage
±1 μA
10 pF
25 mA
5 mA
CIN
Input Capacitance
[11]
ICC
Supply Current (VDD) inc USB at FS
Supply Current (VDD) Suspend w/Clk & Pll Enb
Supply Current (VDD) Suspend no Clk & Pll Dis
21 mA
4.2 mA
50 μA
[12]
[13]
ICCsus1
ICCsus2
IUSB
60 μA
10 mA
10 μA
Supply Current (VDD1
)
IUSBSUS
Transceiver Supply Current in Suspend
USB Host Transceiver Characteristics
Parameter Description
VIHYS
Min
Typ[14]
Max
Differential
0.2 V
200 mV
Input Sensitivity (Data+, Data–)
VUSBIH
VUSBIL
VUSBOH
VUSBOL
USB Input Voltage HIGH Driven
USB Input Voltage LOW
2.0 V
0.8 V
USB Output Voltage HIGH
2.0 V
USB Output Voltage LOW
0.0 V
0.3 V
[15]
ZUSBH
Output Impedance HIGH STATE
Output Impedance LOW STATE
Transceiver Supply p-p Current (3.3 V)
36 Ohms
36 Ohms
42 Ohms
42 Ohms
[15]
ZUSBL
IUSB
10 mA
at FS
Every VDD pin, including USB VDD, must have a decoupling capacitor to ensure clean VDD (free of high frequency noise) at the chip
input point (pin) itself.
The best way to do this is to connect a ceramic capacitor (0.1 μF, 6 V) between the pin itself and a good ground. Keep capacitor leads
as short as possible. Use surface mount capacitors with the shortest traces possible (the use of a ground plane is strongly recom-
mended).
This product was tested as compliant to the USB-IF specification under the test identification number (TID) of 40000689 and is listed
on the USB-IF’s integrators list.
Notes
11. I measurement includes USB Transceiver current (I
) operating at full speed.
CC
USB
12. I
measured with 12 MHz Clock Input and Internal PLL enabled. Suspend set –(USB transceiver and internal Clocking disabled).
CCsus1
13. I
measured with external Clock, PLL disabled, and Suspend set. For absolute minimum current consumption, ensure that all inputs to the device are at
CCsus2
static logic level.
14. All typical values are V = 3.3 V and T
= 25°C.
DD
AMB
15. Z
impedance values includes an external resistor of 24 Ohms ± 1% (SL811HS revision 1.2 requires external resistor values of 33 Ohms ±1%).
USBX
Document 38-08008 Rev. *F
Page 24 of 32
[+] Feedback
SL811HS
Bus Interface Timing Requirements
I/O Write Cycle
twrhigh
twr
nWR
twasu
A0
twahld
twdhld
twdsu
twdsu
twdhld
Register or Memory
Address
DATA
D0-D7
twshld
twcsu
nCS
Tcscs See Note.
I/O Write Cycle to Register or Memory Buffer
Parameter
Description
Write pulse width
Min
85 ns
0 ns
0 ns
Typ
Max
tWR
tWCSU
Chip select set-up to nWR LOW
tWSHLD
Chip select hold time
After nWR HIGH
tWASU
A0 address set-up time
A0 address hold time
85 ns
10 ns
85 ns
5 ns
tWAHLD
tWDSU
tWDHLD
tCSCS
Data to Write HIGH set-up time
Data hold time after Write HIGH
nCS inactive to nCS* asserted
NWR HIGH
85 ns
85 ns
tWRHIGH
Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns
minimum.
Document 38-08008 Rev. *F
Page 25 of 32
[+] Feedback
SL811HS
I/O Read Cycle
twr
twrrdl
nWR
A0
twasu
twahld
trdp
nRD
D0-D7
nCS
tracc
trdhld
trshld
twdsu
twdhld
Register or Memory
Address
DATA
trcsu
Tcscs *Note
I/O Read Cycle from Register or Memory Buffer
Parameter
Description
Min
85 ns
85 ns
0 ns
Typ
Max
tWR
Write pulse width
Read pulse width
tRD
tWCSU
tWASU
tWAHLD
tWDSU
tWDHLD
tRACC
tRDHLD
tRCSU
tRSHLD
Chip select set-up to nWR
A0 address set-up time
85 ns
10 ns
85 ns
5 ns
A0 address hold time
Data to Write HIGH set-up time
Data hold time after Write HIGH
Data valid after Read LOW
Data hold after Read HIGH
Chip select LOW to Read LOW
NCS hold after Read HIGH
nCS inactive to nCS *asserted
nWR HIGH to nRD LOW
25 ns
40 ns
0 ns
85 ns
0 ns
TCSCS
*
85 ns
85ns
tWRRDL
Note nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 170 ns
minimum.
Document 38-08008 Rev. *F
Page 26 of 32
[+] Feedback
SL811HS
DMA Write Cycle
tackrq
tdakrq
nDRQ
tdack
nDACK
tdwrlo
D0-D7
nWR
DATA
tdsu
tdwrp
tdhld
tackwrh
DMA Write Cycle
Parameter
tdack
Description
Min
80 ns
5 ns
Typ
Max
nDACK low
tdwrlo
nDACK to nWR low delay
nDACK low to nDRQ high delay
nWR pulse width
tdakrq
5 ns
tdwrp
65 ns
5 ns
tdhld
Data hold after nWR high
Data set-up to nWR strobe low
NDACK high to nDRQ low
NDACK high to nDRQ low
DMA Write Cycle Time
tdsu
60 ns
5 ns
tackrq
tackwrh
twrcycle
5 ns
150 ns
Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the next
nDRQ is not inserted.
Document 38-08008 Rev. *F
Page 27 of 32
[+] Feedback
SL811HS
DMA Read Cycle
nDRQ
tdckdr
tdakrq
tdack
nDACK
D0-D7
tddrdlo
DATA
tdaccs
tdhld
tdrdp
nRD
SL811 DMA Read Cycle Timing
Parameter
Description
Min
100 ns
0 ns
Typ
Max
tdack
nDACK low
tddrdlo
tdckdr
tdrdp
nDACK to nRD low delay
nDACK low to nDRQ high delay
nRD pulse width
5 ns
90 ns
5 ns
tdhld
Date hold after nDACK high
Data access from nDACK low
nRD high to nDACK high
nDRQ low after nDACK high
DMA Read Cycle Time
tddaccs
tdrdack
tdakrq
trdcycle
85 ns
0 ns
5 ns
150 ns
Note Data is held until nDACK goes high regardless of state of nREAD.
Reset Timing
treset
nRST
tioact
nRD or nWR
Reset Timing
Parameter
tRESET
tIOACT
Description
nRst Pulse width
nRst HIGH to nRD or nWR active
Min
Typ
Max
16 clocks
16 clocks
Note Clock is 48 MHz nominal.
Document 38-08008 Rev. *F
Page 28 of 32
[+] Feedback
SL811HS
Clock Timing Specifications
tclk
tlow
CLK
thigh
tfall
trise
Clock Timing
Parameter
Description
Min
20.0 ns
9 ns
Typ
20.8 ns
Max
tCLK
Clock Period (48 MHz)
Clock HIGH Time
Clock LOW Time
Clock Rise Time
Clock Fall Time
tHIGH
tLOW
tRISE
tFALL
11 ns
11 ns
5.0 ns
5.0 ns
55%
9 ns
Clock Duty Cycle
45%
Ordering Information
Part Number
Package Type
SL811HST-AXC
48-pin Pb-free
–
Ordering Code Definitions
SL811
HST
-
A
C
X
Temperature range:
C = Commercial
X = Pb-free
Package Type: TQFP
Host/slave
Part number
Document 38-08008 Rev. *F
Page 29 of 32
[+] Feedback
SL811HS
Package Diagram
Figure 7. 48-Pin TQFP 7 × 7 × 1.4 mm
51-85135 *B
Acronyms
Document Conventions
Table 35. Acronyms Used in this Document
Units of Measure
Acronym
CMOS
Description
Complementary Metal Oxide Semiconductor
Central Processing Unit
Table 36. Units of Measure
Symbol
Unit of Measure
CPU
mA
Mbps
MHz
mV
mW
ns
milliamps
CRC
DMA
DPLL
I/O
Cyclical Redundancy Check
Direct Memory Access
Megabits per second
MegaHertz
Dynamic Phase Locked Loop
Input Output
millivolts
milliwatts
PCMCIA
Personal Computer Memory Card International
Association
nanoseconds
picofarads
pF
RAM
SIE
Random Access Memory
Serial Interface Engine
Start of Frame
ppm
V
parts per million
Volts
SOF
SRAM
USB
VDC
Volts (Direct Current)
Static Random Access Memory
Universal Serial Bus
Document 38-08008 Rev. *F
Page 30 of 32
[+] Feedback
SL811HS
Document History Page
Document Title: SL811HS Embedded USB Host/Slave Controller
Document Number: 38-08008
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
**
110850
112687
12/14/01
03/22/02
BHA
Converted to Cypress format from ScanLogic
*A
MUL
1) Changed power supply voltage to 4.0 V in section 7.1
2) Changed value of twdsu in section 7.6.2
3) Changed max. power supply voltage to 3.45 V in section 7.2
4) Changed accuracy of adjustment in section 7.2
5) Changed bits 0 and 1 to reserved in section 5.3.8
6) Changed bit 2 to reserved in section 5.3.5 and 5.3.7
7) Changed bit 2 to reserved in section 5.3.1
8) Changed definition of bit 6 in section 5.3.5 & 5.3.7
9) Added section 5.1, Register Values on Power-up and Reset
10) Changed bit description notes in section 5.3.7
11) Changed note about series termination resistors in section 7.5
12) Changed example in section 5.3.9
13) Changed J-K Programming States table in section 5.3.2
14) Added and removed comments for low-power modes in section 5.3.4
15) Removed sections specific to slave operation and SL11H
16) Removed duplicate tables
17) General formatting changes to section headings
18) Fixed all part number references
19) Added comments to section 7.5 and new definitions to section 2.0
*B
*C
381894
464641
See ECN
See ECN
VCS
ARI
Went from single column to 2-column format. Combined information from
SL811HS (38-08008) and SL811S/T (83-08009)
Added lead free part numbers to new section Ordering Information and
corrected references made to these parts. Corrected grammar. Added
compliance statement in section USB Host Transceiver Characteristics.
*D
749518
See ECN
ARI
Implemented the new template. Changed Figure 4. Labels on pins 2 and 3 were
swapped; this has been corrected.
Combined the 48-pin TQFP AXC Pin Assignment and Definition table with the
28-pin PLCC Pin Assignment and Definition table. Removed all instances of
SL811HST-AC. Corrected the variables. Removed references to the obsolete
SL11H.
*E
*F
2914091
3202147
04/15/2010
03/22/11
VRD
ODC
Removed inactive parts from Ordering Information.
Updated Packaging Information.
Template and style updates.
Added ordering code definitions, acroyms and units of measure.
Updated table titles and references.
Removed all references to 28-pin PLCC Package information as the package
is no longer offered.
Removed figure “Package Markings (28-pin PLCC)” on page 21 as it refers the
PLCC package.
Removed figure “48-Pin TQFP Mechanical Dimensions” as this is a duplicate
of the Package diagram later in the spec on page 31.
Document 38-08008 Rev. *F
Page 31 of 32
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SL811HS
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document 38-08008 Rev. *F
Revised March 25, 2011
Page 32 of 32
All products and company names mentioned in this document may be the trademarks of their respective holders.
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