STK16C68-W25 [CYPRESS]
8KX8 NON-VOLATILE SRAM, 25ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | STK16C68-W25 |
| 厂家： | 
CYPRESS |
| 描述： | 8KX8 NON-VOLATILE SRAM, 25ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK16C68
8K x 8 AutoStorePlus™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
DESCRIPTION
• Internal Capacitor Guarantees AutoStore™
Regardless of Power-Down Slew Rate
• Nonvolatile Storage without Battery Problems
• Directly Replaces 8K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 25ns, 35ns and 45ns Access Times
• STORE to Nonvolatile Elements Initiated by
Software or AutoStorePlus™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention over Full Industrial
Temperature Range
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin 600 mil PDIP Package
The STK16C68 is a fast SRAM with a nonvolatile ele-
ment incorporated in each static memory cell. The
SRAM can be read and written an unlimited number of
times, while independent nonvolatile data resides in
Nonvolatile Elements. Data transfers from the SRAM to
the Nonvolatile Elements (the STORE operation) can
take place automatically on power down. An internal
capacitor guarantees the STORE operation regardless
of power-down slew rate. Transfers from the Nonvola-
tile Elements to the SRAM (the RECALL operation) take
place automatically on restoration of power. Initiation
of STORE and RECALL cycles can also be controlled by
entering control sequences on the SRAM inputs. The
STK16C68 is pin-compatible with 8k x 8 SRAMs and
battery-backed SRAMs, allowing direct substitution
while enhancing performance. The STK12C68, which
uses an external capacitor, and the STK15C68, which
uses charge stored in system capacitance, are alter-
natives for systems needing AutoStore™ operation.
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
NC
28
27
26
25
24
23
22
21
20
V
CC
W
NC
2
A
A
A
A
A
A
A
A
A
DQ
DQ
DQ
12
QUANTUM TRAP
128 x 512
3
7
6
5
4
3
2
VCC
4
A
A
A
8
A5
5
9
6
STORE
11
G
A6
STORE/
RECALL
CONTROL
7
POWER
CONTROL
8
A7
A
E
10
STATIC RAM
ARRAY
9
RECALL
1
0
A8
10
11
12
13
14
19
18
17
16
15
DQ
DQ
7
6
5
128 x 512
A9
0
DQ
1
2
INTERNAL
CAPACITOR
28 - 600 PDIP
A11
A12
DQ
DQ
4
3
V
SS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
PIN NAMES
COLUMN I/O
SOFTWARE
DETECT
A0 - A12
A
- A
12
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
COLUMN DEC
0
W
DQ - DQ
0
7
A0 A1 A2 A3 A4 A10
G
E
G
E
V
W
CC
V
SS
March 2006
1
Document Control # ML0010 rev 0.2
STK16C68
a
ABSOLUTE MAXIMUM RATINGS
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS
(V = 5.0V 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V
Current
90
75
65
90
75
65
mA
mA
mA
t
t
t
= 25ns
= 35ns
= 45ns
CC
CC
AVAV
AVAV
AVAV
1
c
I
I
Average V
Average V
Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
CC
2
3
b
Current at t
AVAV
= 200ns
W ≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
10
10
5V, 25°C, Typical
d
d
I
Average V Current
27
23
20
28
24
21
mA
mA
mA
t
t
t
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
SB
SB
CC
(Standby, Cycling TTL Input Levels)
AVAV
AVAV
AVAV
IH
IH
IH
1
2
I
I
I
V
Standby Current
E ≥ (V
– 0.2V)
CC
CC
1.5
1
1.5
1
mA
μA
μA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
IN
SS CC
Off-State Output Leakage Current
V
V
= max
CC
OLK
5
5
= V to V , E or G ≥ V
IN
SS CC IH
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
– .5
V
+ .5
V
V
All Inputs
All Inputs
IH
CC
CC
V
– .5
0.8
V
0.8
IL
SS
SS
2.4
2.4
V
I
I
=–4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
5.0V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
e
480 Ohms
CAPACITANCE
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
OUTPUT
30 pF
C
Input Capacitance
Output Capacitance
8
7
pF
IN
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
C
pF
OUT
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
March 2006
2
Document Control # ML0010 rev 0.2
STK16C68
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK16C68-25 STK16C68-35 STK16C68-45
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
Read Cycle Time
25
35
45
AVAV
RC
AA
g
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DATA VALID
DQ (DATA OUT)
f
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
March 2006
3
Document Control # ML0010 rev 0.2
STK16C68
SRAM WRITE CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK16C68-25
STK16C68-35
STK16C68-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
t
t
t
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
WC
WP
CW
DW
t
t
WLWH
WLEH
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
WHAX
EHAX
WR
h, i
t
t
10
13
15
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
j
SRAM WRITE CYCLE #1: W Controlled
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
j
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
18
AVEL
19
t
EHAX
14
ELEH
t
t
E
1 7
AVEH
t
13
WLEH
t
W
16
EHDX
15
DVEH
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
March 2006
4
Document Control # ML0010 rev 0.2
STK16C68
AutoStorePlus™/POWER-UP RECALL
(V = 5.0V 10%)
CC
SYMBOLS
STK16C68
NO.
PARAMETER
UNITS NOTES
Standard
RESTORE
stg
MIN
MAX
22
23
24
25
t
t
Power-up RECALL Duration
550
μs
ns
V
k
Maximum V Slew Time to Ground
CC
500
4.0
f, h
V
Low Voltage Trigger Level
Low Voltage Reset Level
4.5
3.6
SWITCH
RESET
V
V
e
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
AutoStorePlus™/POWER-UP RECALL
V
CC
5V
24
V
SWITCH
25
RESET
V
23
t
stg
AutoStore™
POWER-UP RECALL
22
RESTORE
t
W
DQ (DATA OUT)
BROWN OUT
BROWN OUT
POWER-UP
BROWN OUT
AutoStorePlus™
AutoStorePlus™
RECALL
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
RECALL WHEN
NO RECALL
(VCC DID NOT GO
V
RETURNS
CC
(VCC DID NOT GO
BELOW VRESET
)
ABOVE VSWITCH
BELOW VRESET
)
March 2006
5
Document Control # ML0010 rev 0.2
STK16C68
SOFTWARE STORE/RECALL MODE SELECTION
E
W
G
A
- A (hex)
MODE
I/O with G Low
I/O with G High
NOTES
12
0
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
L
H
X
l
Nonvolatile STORE
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
L
H
X
l
Nonvolatile RECALL
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
m, n
SOFTWARE STORE/RECALL CYCLE
(V = 5.0V 10%)
CC
STK16C68-25
STK16C68-35
STK16C68-45
UNITS
NO.
SYMBOLS
PARAMETER
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
26
27
28
29
30
31
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
ns
ns
ns
ns
μs
ms
AVAV
m
m
AVEL
Clock Pulse Width
20
20
25
20
30
20
ELEH
g, m
Address Hold Time
ELAX
RECALL Cycle Duration
STORE Cycle Duration
20
10
20
10
20
10
RECALL
STORE
Note m: The software sequence is clocked with E controlled READs.
Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF,
10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive
cycles.
n
SOFTWARE STORE/RECALL CYCLE: E Controlled
26
AVAV
26
t
AVAV
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
t
ELEH
t
E
29
ELAX
t
31
30
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA OUT)
March 2006
6
Document Control # ML0010 rev 0.2
STK16C68
DEVICE OPERATION
The AutoStorePlus™ STK16C68 is a fast 8K x 8
AutoStorePlus™ OPERATION
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
Nonvolatile Elements while power is unavailable.
The nonvolatility of the STK16C68 does not require
any system intervention or support: AutoStore-
Plus™ on power-down and automatic RECALL on
power-up guarantee data integrity without the use of
batteries.
The STK16C68’s automatic STORE on power-down
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (VCC < VSWITCH) at which point the part
depends only on its internal capacitor for STORE
completion. This safe transfer of data from SRAM to
Nonvolatile Elements takes place regardless of
power supply slew rate.
In order to prevent unneeded STORE operations, the
automatic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software-initiated
STORE cycles are performed regardless of whether
or not a WRITE operation has taken place.
NOISE CONSIDERATIONS
Note that the STK16C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
SRAM READ
The STK16C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-12 determines which of the 8,192 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high or W is brought low.
If the STK16C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10kΩ resistor should
be connected either between W and system VCC or
between E and system VCC.
SOFTWARE NONVOLATILE STORE
The STK16C68 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
To initiate the software STORE cycle, the following
READ sequence must be performed:
March 2006
7
Document Control # ML0010 rev 0.2
STK16C68
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
The software sequence must be clocked with E
controlled READs.
HARDWARE PROTECT
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G be
low for the sequence to be valid. After the tSTORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
The STK16C68 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs
during low-voltage conditions. When VCC < VSWITCH
,
software STORE operations and SRAM WRITEs are
inhibited.
LOW AVERAGE ACTIVE POWER
The STK16C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for WRITE cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average cur-
rent drawn by the STK16C68 depends on the fol-
lowing items: 1) CMOS vs. TTL input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of READs to WRITEs; 5)
the operating temperature; 6) the VCC level; and 7) I/
O loading.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a
sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of READ
operations must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
150 200
0
0
50
100
150
200
50
100
Cycle Time (ns)
Cycle Time (ns)
Figure 3: I (max) Writes
Figure 2: I (max) Reads
CC
CC
March 2006
8
Document Control # ML0010 rev 0.2
STK16C68
ORDERING INFORMATION
- W F 45 I
STK16C68
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
W = Plastic 28-pin 600 mil DIP
March 2006
9
Document Control # ML0010 rev 0.2
Document Revision History
Revision
0.0
Date
December 2002
September 2003
March 2006
Summary
Publish new datasheet
0.1
Added lead-free lead finish
Marked as Obsolete, Not recommended for new design.
0.2
相关型号：
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