STK17TA8RF25 [CYPRESS]
REAL TIME CLOCK, PDSO48, 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, PLASTIC, SSOP-48;
| 型号： | STK17TA8RF25 |
| 厂家： | 
CYPRESS |
| 描述： | REAL TIME CLOCK, PDSO48, 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, PLASTIC, SSOP-48 光电二极管 |
| 文件： | 总27页 (文件大小：712K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK17TA8
nvTimeTM Event Data Recorder
128K x 8 AutoStoreTM nvSRAM
With Real-Time Clock
FEATURES
DESCRIPTION
• Data Integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock
• Watchdog Timer
The Simtek STK17TA8 combines a 1 Mbit nonvola-
tile static RAM with a full-featured real-time clock in
a reliable, monolithic integrated circuit. The embed-
ded nonvolatile elements incorporate Simtek’s
QuantumTrap™ technology producing the world’s
most reliable nonvolatile memory. The SRAM can
be read and written an unlimited number of times,
while independent, nonvolatile data resides in the
nonvolatile elements.
• Clock Alarm with programmable Interrupts
• Capacitor or battery backup for RTC
• 25ns and 45ns Access Times
• “Hands-off” Automatic STORE on Power Down
with only a small capacitor
• STORE to QuantumTrap™ Initiated by
Software , device pin, or on Power Down
• RECALL to SRAM Initiated by Software or
Power Up
The Real-Time Clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is pro-
grammable for one-time alarms or periodic seconds,
minutes, hours, or days. There is also a programma-
ble Watchdog Timer for process control.
• Unlimited READ, WRITE and RECALL Cycles
• High-reliability
o
o
Endurance to 200K Cycles
Retention to 20 years
• 10mA Typical ICC at 200ns Cycle Time
• Single 3V +20%, -10% Operation
• SSOP Package, ROHS compliant
BLOCK DIAGRAM
VCC
VCAP
Quantum Trap
1024 X 1024
A5
A6
A7
VRTCbat
VRTCcap
POWER
CONTROL
STORE
A8
A9
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
1024 X 1024
RECALL
A12
A13
A14
A15
A16
HSB
SOFTWARE
DETECT
A15 – A0
DQ0
COLUMN I/O
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
X1
COLUMN DEC
RTC
X2
INT
A0 A1 A2 A3 A4 A10 A11
A16 – A0
MUX
G
E
W
Figure 1. Block Diagram
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Document Control #ML0025 rev 1.4
STK17TA8
PACKAGES
VCAP
A16
A14
1
2
3
4
VCC
A15
48
47
HSB
46
45
A12
A7
W
A13
5
44
A6
6
A8
43
A5
INT
A4
7
8
9
10
11
12
13
14
15
16
A9
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A11
Approximate PCB area usage.
See website for detailed
package size specifications.
VSS
VSS
VRTCcap
DQ6
G
A10
E
DQ7
VRTCbat
DQ0
A3
A2
A1
A0
DQ1
DQ2
17
18
19
20
21
22
23
24
DQ5
DQ4
DQ3
VCC
X1
X2
48 Pin SSOP
PIN DESCRIPTIONS
Pin Name
A16 – A0
I/O
Input
I/O
Description
Address: The 17 address inputs select one of 131,056 bytes in the nvSRAM array or one of 16 bytes in the clock
register map.
DQ7 –DQ0
E
Data: Bi-directional 8-bit data bus for accessing the nvSRAM array and RTC.
Input
Chip Enable: The active low
Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the
falling edge of E
E
input selects the device.
W
G
Input
Input
.
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high
causes the DQ pins to tri-state.
X1
X2
Output
Input
Crystal Connection, drives crystal on startup.
Crystal Connection for 32.768 kHz crystal.
VRTCcap
VRTCbat
VCC
Power Supply
Power Supply
Power Supply
Capacitor supplied backup RTC supply voltage. (Left unconnected if VRTCbat is used.)
Battery supplied backup RTC supply voltage. (Left unconnected if VRTCcap is used.)
Power 3.0V +20%, -10%
Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external
to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not
connected. (Connection Optional)
HSB
I/O
Interrupt Output: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor.
Programmable to either active high (push/pull) or active low (open-drain).
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile
elements.
INT
Output
VCAP
Power Supply
VSS
(Blank)
Power Supply
No Connect
Ground
Unlabeled pins have no internal connection.
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Document Control #ML0025 rev 1.4
STK17TA8
ABSOLUTE MAXIMUM RATINGSa
Notes
-0.5V to +4.1V
Power Supply Voltage
Voltage on Input Relative to VSS
Voltage on Outputs
a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
-0.5V to (VCC + 0.5V)
-0.5V to (VCC + 0.5V)
–55°C to 125°C
–55°C to 140°C
–65°C to 150°C
1W
Temperature under Bias
Junction Temperature
Storage Temperature
Power Dissipation
DC Output Current (1 output at a time, 1s duration)
15mA
Package Thermal Characteristics see website: http://www.simtek.com/
DC CHARACTERISTICS
Commercial
Industrial
Symbol
Parameter
Units
mA
mA
mA
Notes
MIN
MAX
65
55
50
MIN
MAX
70
60
55
tAVAV = 25ns
tAVAV = 35ns
Average VCC Current
ICC1
t
AVAV = 45ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE).
Average VCC Current during STORE
Average VCC Current at tAVAV = 200ns
3V, 25°C, Typical
ICC2
ICC3
ICC4
ISB
3
3
mA
W
≥ (VCC – 0.2V)
All Others Inputs Cycling, at CMOS Levels.
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE).
10
3
10
3
mA
mA
Average VCAP Current during
AutoStore™ Cycle
VCC Standby Current
E
≥ (VCC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle is complete.
(Standby, Stable CMOS Input Levels)
3
3
mA
µA
VCC = max
Input Leakage Current
IILK
±1
±1
VIN = VSS to VCC
VCC = max
Off-State Output Leakage Current
IOLK
VIN = VSS to VCC
, E or G ≥ VIH
±1
VCC + 0.3
0.8
±1
VCC + 0.3
0.8
µA
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
VIH
VIL
2.0
VSS – 0.5
2.4
2.0
VSS – 0.5
2.4
All Inputs
V
All Inputs
VOH
V
IOUT = –2mA
IOUT = 4mA
VOL
0.4
70
0.4
85
V
TA
0
–40
2.7
17
oC
VCC
2.7
17
3.6
57
3.6
57
V
3.0V +20%, -10%
Storage Capacitor
VCAP
NVC
DATAR
µF
K
Between Vcap pin and Vss, 5V rated.
Nonvolatile STORE operations
Data Retention
200
20
200
20
Years
@ 55°C
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Document Control #ML0025 rev 1.4
STK17TA8
AC TEST CONDITIONS
0V to 3V
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
≤ 5ns
1.5V
Output Load
See Figure 2 and Figure 3
CAPACITANCEb
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
pF
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
CIN
Input Capacitance
Output Capacitance
7
7
COUT
pF
Notes
b: These parameters are guaranteed but not tested
3.0V
3.0V
577 Ohms
577 Ohms
OUTPUT
OUTPUT
5 pF
30 pF
INCLUDING
SCOPE AND
FIXTURE
F
789 Ohms
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 3. AC Output Loading,
for tristate specs (
Figure 2. AC Output Loading
tHZ, tLZ, tWLQZ, tWHQZ
tGLQX, tGHQZ
,
)
July 2006
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Document Control #ML0025 rev 1.4
STK17TA8
RTC DC CHARACTERISTICS
Commercial
Industrial
Symbol
Parameter
Units
Notes
MIN
MAX
MIN
MAX
RTC Backup Current
-
-
IBAK
300
350
3.3
2.7
nA
V
From either VRTCcap or VRTCbat
Typical = 3.0 Volts during normal
operation
Typical = 2.4 Volts during normal
operation
RTC Battery Pin Voltage
VRTCbat
VRTCcap
1.8
1.2
3.3
2.7
1.8
1.2
RTC Capacitor Pin Voltage
V
@ MIN Temperature from Power up
or Enable
-
-
-
-
10
5
10
5
sec
sec
tOSCS
RTC Oscillator time to start
@25ºC from Power up or Enable
RTC RECOMMENDED COMPONENT CONFIGURATION
X1
X2
Recommended Values
Y1 = 32.768 KHz
RF = 10M Ohm
C1 = 0
C2 = 56 pF
Figure 4. RTC COMPONENT CONFIGURATION
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Document Control #ML0025 rev 1.4
STK17TA8
SRAM READ CYCLES #1 & #2
SYMBOLS
STK17TA8-25
STK17TA8-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
tACS
MIN
MAX
MIN
MAX
tELQV
1
2
Chip Enable Access Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c
c
tAVAV
tAVAV
tRC
tAA
tOE
tOH
tLZ
Read Cycle Time
25
45
d
tAVQV
3
Address Access Time
25
12
45
20
tGLQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
d
tAXQX
5
3
3
3
3
tELQX
tEHQZ
tGLQX
6
e
tHZ
tOLZ
tOHZ
tPA
tPS
7
10
10
25
15
15
45
8
0
0
0
0
e
tGHQZ
9
b
tELICC
10
b
tEHICC
11
Notes
c:
W
must be high during SRAM READ cycles
and
d: Device is continuously selected with
E
G
both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledc,f
2
tAVAV
ADDRESS
1
tELQV
11
tEHICCL
6
tELQX
E
7
tEHQZ
G
9
tGHQZ
4
tGLQV
8
tGLQX
DQ (DATA OUT)
DATA VALID
10
tELICCH
ACTIVE
STANDBY
ICC
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Document Control #ML0025 rev 1.4
STK17TA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
STK17TA8-25 STK17TA8-45
UNITS
PARAMETER
#1
#2
Alt.
tWC
tWP
tCW
tDW
tDH
MIN
25
20
20
10
0
MAX
MIN
45
30
30
15
0
MAX
Write Cycle Time
12
13
14
15
16
17
18
19
20
21
tAVAV
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
tAW
tAS
20
0
30
0
tWR
tWZ
tOW
0
0
e,g
tWLQZ
tWHQX
10
15
3
3
Notes
g: If
h:
W
is low when E goes low, the outputs remain in the high-impedance state.
E
or
W
must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
13
tWLWH
tAVWL
W
15
16
tDVWH
tWHDX
DATA VALID
DATA IN
20
tWLQZ
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
SRAM WRITE CYCLE #2: E Controlledh,f
12
tAVAV
ADDRESS
18
14
tELEH
19
tEHAX
tAVEL
E
17
tAVEH
13
tWLEH
W
16
tEHDX
15
tDVEH
DATA VALID
DATA IN
HIGH IMPEDANCE
DATA OUT
July 2006
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Document Control #ML0025 rev 1.4
STK17TA8
AutoStore™ /POWER-UP RECALL
SYMBOLS
NO.
PARAMETER
STK17TA8
UNITS
NOTES
Standard
Alternate
MIN
MAX
22
23
24
25
tHRECALL
40
ms
ms
V
i
Power-up RECALL Duration
tSTORE
tHLHZ
12.5
j,k
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
VSWITCH
tVCCRISE
2.65
150
µs
Notes
i: tHRECALL starts from the time VCC rises above VSWITCH
j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
k: Industrial Grade Devices require 15ms MAX.
STORE occurs only if a
SRAM write has
happened.
No STORE occurs
without at least one
SRAM write.
AutoStore™/POWER-UP RECALL
VCC
24
VSWITCH
25
tVCCRISE
AutoStoreTM
23
tSTORE
23
tSTORE
POWER-UP RECALL
22
tHRECALL
22
tHRECALL
Read & Write Inhibited
POWER DOWN
BROWN OUT
POWER-UP
RECALL
POWER-UP
RECALL
AutoStoreTM
AutoStoreTM
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
July 2006
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Document Control #ML0025 rev 1.4
STK17TA8
SOFTWARE-CONTROLLED STORE/RECALL CYCLEl,m
SYMBOLS
STK17TA8-25
STK17TA8-45
NO.
PARAMETER
UNITS
NOTES
m
E
G
Alt.
tRC
MIN
MAX
MIN
MAX
cont
cont
26
27
tAVAV
tAVAV
25
0
45
0
ns
ns
ns
ns
µs
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
tAVEL
tAVGL
tAS
28
tELEH
tELAX
tGLGH
tGLAX
tCW
20
20
30
20
29
Address Hold Time
30
tRECALL
tRECALL
100
100
RECALL Duration
Notes
l: The software sequence is clocked with
E
controlled READs or G controlled READs.
m: The six consecutive addresses must be read in the order listed in the Mode Selection Table.
W
must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledm
26
tAVAV
26
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
27
tAVEL
28
tELEH
29
tELAX
G
23
30
/
tSTORE tRECALL
HIGH IMPEDENCE
DATA VALID
DATA VALID
DQ (DATA)
SOFTWARE STORE/RECALL CYCLE: G Controlledm
26
26
tAVAV
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
28
tGLGH
27
tAVGL
G
30
tRECALL
23
tSTORE
/
29
tGLAX
HIGH IMPEDENCE
DATA VALID
DATA VALID
DQ (DATA)
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STK17TA8
HARDWARE STORE CYCLE
SYMBOLS
NO.
STK17TA8
PARAMETER
UNITS
NOTES
n
Standard
tDELAY
tHLHX
tHLBL
Alternate
MIN
MAX
tHLQZ
31
32
33
Time Allowed to Complete SRAM Cycle
Hardware STORE Pulse Width
1
µs
ns
ns
15
Hardware STORE Low to STORE Busy
300
Notes
n: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete.
HARDWARE STORE CYCLE
32
tHLHX
HSB (IN)
23
tSTORE
33
tHLBL
HSB (OUT)
HIGH IMPEDENCE
DATA VALID
HIGH IMPEDENCE
31
tDELAY
DQ (DATA OUT)
DATA VALID
Soft Sequence Commands
SYMBOLS
STK17TA8
NO.
PARAMETER
UNITS
NOTES
Standard
MIN
MAX
tSS
34
Notes
Soft Sequence Processing Time
70
µs
o,p
o: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
p: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
34
tSS
34
tSS
Soft Sequence Command
Soft Sequence Command
ADDRESS #1
ADDRESS #1
ADDRESS #6
ADDRESS #6
ADDRESS
Vcc
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Document Control #ML0025 rev 1.4
STK17TA8
MODE SELECTION
E
W
G
A15 - A0
MODE
I/O
POWER
NOTES
H
L
L
X
H
L
X
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
X
Active
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
ICC2
L
L
H
H
L
L
q,r,s
q,r,s
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Nonvolatile Recall
Notes
q: The six consecutive addresses must be in the order listed.
r: While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes
s: I/O state depends on the state of . The I/O table shown assumes low.
W
must be high during all six consecutive cycles to enable a nonvolatile cycle.
G
G
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STK17TA8
nvSRAM
DEVICE OPERATION
SRAM WRITE
The STK17TA8 nvSRAM is made up of two
functional components paired in the same physical
cell. These are a SRAM memory cell and a
nonvolatile QuantumTrap™ cell. The SRAM
memory cell operates as a standard fast static
RAM. Data in the SRAM can be transferred to the
nonvolatile cell (the STORE operation), or from
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
the nonvolatile cell
to SRAM (the RECALL
operation). This unique architecture allows all cells
to be stored and recalled in parallel. During the
STORE and RECALL operations SRAM READ and
WRITE operations are inhibited. The STK17TA8
supports unlimited reads and writes just like a
typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 500K STORE operations.
It is recommended that
G
be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry will
turn off the output buffers tWLQZ after W goes low.
AutoStore™ OPERATION
The STK17TA8 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by HSB , Software Store,
actived by an address sequence, and AutoStore™, on
device power down.
SRAM READ
The STK17TA8 performs a READ cycle whenever
E and
G
are low while
W
and HSB are high.
The address specified on pins A16-0 determines
which of the 131,056 data bytes will be accessed.
When the READ is initiated by an address
transition, the outputs will be valid after a delay of
tAVQV (READ cycle #1). If the READ is initiated by
E or G , the outputs will be valid at tELQV or at
tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address
changes within the tAVQV access time without the
need for transitions on any control input pins, and
will remain valid until another address change or
AutoStore™ operation is a unique feature of Simtek
QuantumTrap™ technology and is enabled by default
on the STK17TA8.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc.
A
STORE operation will be initiated with power provided
by the Vcap capacitor.
until E or G is brought high, or
brought low.
W
or HSB is
Figure 5 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer to
the DC CHARACTERISTICS table for the size of Vcap.
The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip. A pull up should be
placed on W to hold it inactive during power up.
VCC
VCAP
VCC
W
To reduce unneeded nonvolatile stores, AutoStore™
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
HSB signal can be monitored by the system to detect
an AutoStore™ cycle is in progress.
Figure 5: AutoStoreTM Mode
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Document Control #ML0025 rev 1.4
STK17TA8
SOFTWARE STORE
HARDWARE STORE ( HSB )
Data can be transferred from the SRAM to the
nonvolatile memory by a software address sequence.
The STK17TA8 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations in exact order. During
the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the
cycle is completed.
OPERATION
The STK17TA8 provides the HSB pin for controlling
and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK17TA8 will conditionally initiate a STORE
operation after tDELAY. An actual STORE cycle will
only begin if a WRITE to the SRAM took place since
the last STORE or RECALL cycle. The HSB pin also
acts as an open drain driver that is internally driven
low to indicate a busy condition while the STORE
(initiated by any means) is in progress.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and no
STORE or RECALL will take place.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17TA8 will
To initiate the software STORE cycle, the following
READ sequence must be performed:
continue SRAM operations for tDELAY. During tDELAY
,
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
The software sequence may be clocked with
controlled READs or G controlled READs.
E
During any STORE operation, regardless of how it
was initiated, the STK17TA8 will continue to drive the
HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK17TA8 will remain disabled until the HSB pin
returns high.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition
(VCC < VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tHRECALL to complete.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory
to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence of
READ operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the
following sequence of E controlled READ operations
must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
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Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the
nonvolatile information is transferred into the SRAM
cells. After the tRECALL cycle time the SRAM will
once again be ready for READ and WRITE
operations. The RECALL operation in no way alters
the data in the nonvolatile elements.
NOISE CONSIDERATIONS
The STK17TA8 is a high-speed memory and so must
have
a
high-frequency bypass capacitor of
approximately 0.1µF connected between VCC and VSS,
using leads and traces that are as short as possible. As
with all high-speed CMOS ICs, careful routing of power,
ground and signals will reduce circuit noise.
DATA PROTECTION
LOW AVERAGE ACTIVE POWER
The STK17TA8 protects data from corruption
during low-voltage conditions by inhibiting all
externally initiated STORE and WRITE operations.
The low-voltage condition is detected when VCC
VSWITCH .
CMOS technology provides the STK17TA8 this the
benefit of drawing significantly less current when it is
cycled at times longer than 50ns. Figure 6 shows the
relationship between ICC and READ/WRITE cycle time.
Worst-case current consumption is shown for
commercial temperature range, VCC = 3.6V, and chip
enable at maximum frequency. Only standby current is
drawn when the chip is disabled. The overall average
current drawn by the STK17TA8 depends on the
following items:
<
If the STK17TA8 is in a WRITE mode (both E and
W low ) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a
negative transition on E or
protects against inadvertent writes during power up
or brown out conditions.
W
is detected. This
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. I/O loading.
50
40
30
Writes
20
10
Reads
0
50 100 150 200 300
Cycle Time (ns)
Figure 6 Current vs. Cycle time
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PREVENTING AUTOSTORETM
Because of the use of nvRAM to store critical RTC
data the AutoStore™ function can not be
disabled in the STK17TA8.
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REAL TIME CLOCK OPERATION
nvTIME OPERATION
SETTING THE CLOCK
The STK17TA8 offers internal registers that contain Setting the write bit “W” (in the flags register at
Clock, Alarm, Watchdog, Interrupt, and Control 0x1FFF0) to a “1” halts updates to the STK17TA8
functions. Internal double buffering of the clock and registers. The correct day, date and time can then be
the clock/timer information registers prevents written into the registers in 24-hour BCD format. The
accessing transitional internal clock data during a time written is referred to as the “Base Time.” This
read or write operation. Double buffering also cir- value is stored in nonvolatile registers and used in
cumvents disrupting normal timing counts or clock calculation of the current time. Resetting the write bit
accuracy of the internal clock while accessing clock to “0” transfers those values to the actual clock
data. Clock and Alarm Registers store data in BCD counters, after which the clock resumes normal
format.
operation.
BACKUP POWER
CLOCK OPERATIONS
The RTC in the STK17TA8 is intended for
permanently powered operation. Either the VRTCcap or
VRTCbat pin is connected depending on whether a
capacitor or battery is chosen for the application.
When primary power, Vcc, fails and drops below Vswitch
the device will switch to the backup power supply.
The clock registers maintain time up to 9,999 years in
one second increments. The user can set the time to
any calendar time and the clock automatically keeps
track of days of the week and month, leap years and
century transitions. There are eight registers
dedicated to the clock functions which are used to set
time with a write cycle and to read time during a read
cycle. These registers contain the Time of Day in
BCD format. Bits defined as “X” are currently not used
and are reserved for future use by Simtek.
The clock oscillator uses very little current, which
maximizes the backup time available from the backup
source. Regardless of clock operation with the
primary source removed, the data stored in nvSRAM
is secure, having been stored in the nonvolatile
elements as power was lost. Factors to be considered
when choosing a backup power source include: the
expected duration of power outages and the cost
trade-off of using a battery versus a capacitor.
READING THE CLOCK
While the double-buffered RTC register structure
reduces the chance of reading incorrect data from the
clock, the user should halt internal updates to the
STK17TA8 clock registers before reading clock data
to prevent the reading of data in transition. Stopping
the internal register updates does not affect clock
accuracy.
During backup operation the STK17TA8 consumes a
maximum of 300 nanoamps at 2 volts. Capacitor or
battery values should be chosen according to the
application. Backup time values based on maximum
current specs are shown below. Nominal times are
approximately 3 times longer.
The updating process is stopped by writing a “1” to
the read bit “R” (in the flags register at 0x1FFF0), and
will not restart until a “0” is written to the read bit. The
RTC registers can then be read while the internal
clock continues to run.
Capacitor Value
Backup Time
0.1 F
72 hours
14 days
30 days
0.47 F
1.0 F
Within 20ms after a “0” is written to the read bit, all
STK17TA8 registers are simultaneously updated.
Using a capacitor has the obvious advantage of
recharging the backup source each time the system is
powered up.
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STK17TA8
If a battery is used, a 3V lithium is recommended and calibration circuit adds or subtracts counts from the
the STK17TA8 will only source current from the bat- oscillator divider circuit.
tery when the primary power is removed. The battery
The number of times pulses are suppressed (sub-
will not, however, be recharged at any time by the
tracted, negative calibration) or split (added, positive
STK17TA8. The battery capacity should be chosen
calibration) depends upon the value loaded into the
for total anticipated cumulative down-time required
five calibration bits found in calibration register at
over the life of the system.
0x1FFF8. Adding counts speeds the clock up;
subtracting counts slows the clock down. The
Calibration bits occupy the five lower order bits in the
control register 8. These bits can be set to represent
STOPPING AND STARTING THE OSCIL-
LATOR
The OSCEN bit in calibration register at 0x1FFF8
controls the starting and stopping of the oscillator.
This bit is nonvolatile and shipped to customers in the
"enabled" (set to 0) state. To preserve battery life
while system is in storage OSCEN should be set to a
1. This will turn off the oscillator circuit extending the
battery life. If the OSCEN bit goes from disabled to
enabled, it will take approximately 5 seconds (10
seconds max) for the oscillator to start.
any value between 0 and 31 in binary form. Bit D5 is a
Sign bit, where a “1” indicates positive calibration and
a “0” indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the
cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so
on. Therefore each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register.
The STK17TA8 has the ability to detect oscillator
failure. This is recorded in the OSCF (Oscillator
Failed bit) of the flags register at address 0x1FFF0.
When the device is powered on (VCC goes above
Vswitch) the OSCEN bit is checked for "enabled" status.
If the OSCEN bit is enabled and the oscillator is not
active, the OSCF bit is set. The user should check for
this condition and then write a 0 to clear the flag. It
should be noted that in addition to setting the OSCF
flag bit, the time registers are reset to the “Base Time”
(see the section “Setting the Clock”), which is the
value last written to the timekeeping registers. The
Control/Calibration register and the OSCEN bit are not
affected by the oscillator failed condition.
In order to determine how to set the calibration one
may set the CAL bit in the flags register at 0x1FFF0 to
1, which causes the INT pin to toggle at a nominal
512 Hz. Any deviation measured from the 512 Hz will
indicate the degree and direction of the required
correction. For example, a reading of 512.010124 Hz
would indicate a +20 ppm error, requiring a -10
(001010) to be loaded into the Calibration register.
Note that setting or changing the calibration register
does not affect the frequency test output frequency.
If the voltage on the backup supply (either VRTCcap or
VRTCbat) falls below their respective minimum level the
oscillator may fail, leading to the oscillator failed
condition which can be detected when system power
is restored.
ALARM
The alarm function compares a user-programmable
alarm time/date (stored in registers 01xFFF1-5) with
the real time clock time-of-day/date values. When a
match occurs, the alarm flag (AF) is set and an
interrupt is generated if the alarm interrupt is
enabled. The alarm flag is automatically reset when it
is read.
The value of OSCF should be reset to 0 when the
time registers are written for the first time. This will
initialize the state of this bit which may have become
set when the system was first powered on.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal,
usually specified to 35 ppm limits at 25°C. This error
could equate to + 1.53 minutes per month. The
STK17TA8 employs a calibration circuit that can
improve the accuracy to +1/-2 ppm at 25°C. The
Each of the alarm registers has a match bit as its
MSB. Setting the match bit to a 1 disables this alarm
register from the alarm comparison. When the match
bit is 0, the alarm register is compared with the
equivalent real time clock register. Using the match
bits, the alarm can occur as specifically as one
particular second on one day of the month
or as frequently as once per minute.
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STK17TA8
controls the internal switch to backup power for the
clock and protects the memory from low-VCC access.
The power monitor is based on an internal band-gap
reference circuit that compares the VCC voltage to
various thresholds.
Setting all match bits to 0 will
require an exact time/date match. Note: The product
requires match bit for seconds alarm register
(1x1FFF2 – D7) be set to 0 for proper operation of
the Alarm Flag and Interrupt.
As described in the AutoStore™ section previously,
when Vswitch is reached as VCC decays from power
loss, a data store operation is initiated from SRAM to
the nonvolatile elements, securing the last SRAM
data state. Power is also switched from VCC to the
backup supply (battery or capacitor) to operate the
RTC oscillator.
The alarm value should be initialized on power-up by
software since the alarm registers are not non-
volatile.
WATCHDOG TIMER
When operating from the backup source no data may
be read or written and the clock functions are not
available to the user. The clock continues to operate
in the background. Updated clock data is available to
the user after tHRECALL delay (See AutoStore™
/POWER-UP RECALL) after VCC has been restored
to the device.
The watchdog timer is intended to interrupt to
processor should its program get hung in a loop and
not respond in a timely manner. The software must
reload the watchdog timer before it counts down to
zero to prevent this interrupt.
The watchdog timer is a free running down counter INTERRUPTS
that uses the 32 Hz clock (31.25 ms) derived from the
crystal oscillator. The watchdog timer function does
no operate unless the oscillator is running.
The STK17TA8 provides three potential interrupt
sources. They include the watchdog timer, the power
monitor, and the clock/calendar alarm. Each can be
individually enabled and assigned to drive the INT pin.
The watchdog counter is loaded with a starting value In addition, each has an associated flag bit that the
from the load register and then counts down to zero host processor can use to determine the cause of the
setting the watchdog flag (WDF) and generating an interrupt.
interrupt if the watchdog interrupt is enabled. The
Some of the sources have additional control bits that
watchdog flag bit is reset when the flag register is
determine functional behavior. In addition, the pin
read. The operating software would normally reload
driver has three bits that specify its behavior when an
the counter by setting and then resetting the
interrupt occurs. A functional diagram of the interrupt
watchdog strobe bit (WDS) within the timing interval
logic is shown below.
programmed in the load register.
WDF
Watchdog
Timer
WIE
The procedure to set a new value into the load
VCC
register begins when the watchdog write bit (/WDW)
PF
PFE
AF
P/L
is set to zero and then a new value is written into the
watchdog register at 01x1FFF7). Once the new value
is loaded, the watchdog write bit is set to 1 and the
watchdog strobe bit (WDS) is set to 1 to load this
value into the load register. The watchdog strobe bit
is then set to zero. Note: Setting the load register to
zero will disable the watchdog timer function.
The system software should initialize the watchdog
load register on power-up to the desired value since
the register is not non-volatile.
Power
Monitor
Pin
Driver
INT
H/L
VINT
VSS
Clock
Alarm
AIE
Figure 7. Interrupt Block Diagram
The three interrupts each have a source and an
enable. Both the source and the enable must be
active (true high) in order to generate an interrupt
output. Only one source is necessary to drive the pin.
The user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to 0
POWER MONITOR
The STK17TA8 provides a power management
scheme with power-fail interrupt capability. It also
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STK17TA8
when the register is read. The cycle must be a will be cleared when the register is read. If the INT pin
complete read cycle ( WE high); otherwise the flags is programmed for Level mode, then the condition will
will not be cleared. The power monitor has two pro- clear and the INT pin will return to its inactive state. If
grammable settings that are explained in the power the pin is programmed for Pulse mode, then reading
monitor section.
the flag also will clear the flag and the pin. The pulse
will not complete its specified duration if the
Flags/Control register is read. If the INT pin is used as
a host reset, then the Flags/Control register should
not be read during a reset.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register.
During a power-on reset with no battery, the interrupt
register is automatically loaded with the value 24h.
This causes power-fail interrupt to be enabled with an
active-low pulse.
According to the programming selections, the pin can
be driven in the backup mode for an alarm interrupt.
In addition, the pin can be an active low (open-drain)
or an active high (push-pull) driver. If programmed for
operation during backup mode, it can only be active
low. Lastly, the pin can provide a one-shot function so
that the active condition is a pulse or a level condition.
In one-shot mode, the pulse width is internally fixed at
approximately 200 ms. This mode is intended to reset
a host microcontroller. In level mode, the pin goes to
its active polarity until the Flags/Control register is
read by the user. This mode is intended to be used as
an interrupt to a host microcontroller. The control bits
are summarized as follows:
Watchdog Interrupt Enable - WIE. When set to 1, the
watchdog timer drives the INT pin as well as an
internal flag when a watchdog time-out occurs. When
WIE is set to 0, the watchdog timer affects only the
internal flag.
Alarm Interrupt Enable - AIE. When set to 1, the alarm
match drives the INT pin as well as an internal flag.
When set to 0, the alarm match only affects to internal
flag.
Power Fail Interrupt Enable - PFE. When set to 1, the
power fail monitor drives the pin as well as an internal
flag. When set to 0, the power fail monitor affects only
the internal flag.
High/Low - H/L. When set to a 1, the INT pin is active
high and the driver mode is push-pull. The INT pin
can drive high only when VCC>Vswitch. When set to a 0,
the INT pin is active low and the drive mode is open-
drain. Active low (open drain) is operational even in
battery backup mode.
Pulse/Level - P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
When an enabled interrupt source activates the INT
pin, an external host can read the Flags/Control reg-
ister to determine the cause. Remember that all flags
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STK17TA8
RTC Register Map
BCD Format Data
Register
0x1FFFF
0x1FFFE
Function / Range
Years: 00-99
D7
D6
D5
D4
D3
D2
D1
D0
10s Years
Years
10s
Months
0
0
0
0
Months
Months: 01-12
10s Day of
Month
0x1FFFD
0
Day of Month
Day of Month: 01-31
0x1FFFC
0x1FFFB
0x1FFFA
0x1FFF9
0
0
0
0
0
0
0
0
Day of Week
Day of week: 01-07
Hours: 00-23
Minutes: 00-59
Seconds: 00-59
10s Hours
10s Minutes
10s Seconds
Cal
Hours
Minutes
Seconds
0x1FFF8
0x1FFF7
0x1FFF6
0x1FFF5
OSCEN
WDS
WIE
0
Calibration
WDT
H/L
Calibration values*
Watchdog*
Sign
WDW
AIE
0
PFE
ABE
P/L
0
0
Interrupts*
10s Alarm
Date
Alarm, Day of Month:
01-31
M
Alarm Day
10s Alarm
Hours
0x1FFF4
0x1FFF3
0x1FFF2
M
M
M
0
Alarm Hours
Alarm, hours: 00-23
Alarm, minutes: 00-59
Alarm, seconds: 00-59
10 Alarm Minutes
10 Alarm Seconds
Alarm Minutes
Alarm Seconds
Centuries
0x1FFF1
0x1FFF0
10s Centuries
AF PF
Centuries: 00-99
Flags*
WDF
OSCF
0
CAL
W
R
* - Is a binary value, not a BCD value.
0 - Not implemented, reserved for future use.
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Register Map Detail
Timekeeping – Years
D4 D3
0x1FFFF
D7
D6
D5
10s Years
D2
D1
Years
D0
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper
nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the
register is 0-99.
Timekeeping – Months
0x1FFFE
0x1FFFD
0x1FFFC
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
10s Month
Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to
9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the
register is 1-12.
Timekeeping – Date
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Day of month
Day of month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and
operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for
the register is 1-31. Leap years are automatically adjusted for.
Timekeeping – Day
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter
that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the
day is not integrated with the date.
Timekeeping – Hours
0x1FFFB
0x1FFFA
D7
D6
D5
D4
D3
D2
D1
D0
12/24
0
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and
operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The
range for the register is 0-23.
Timekeeping – Minutes
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Minutes
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register
is 0-59.
Timekeeping – Seconds
0x1FFF9
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Seconds
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to
9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-
59.
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Calibration / Control
D4 D3
0x1FFF8
D7
D6
D5
D2
D1
D0
Calibration
Sign
OSCEN
0
Calibration
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs.
Disabling the oscillator saves battery/capacitor power during storage. On a no-battery power-up,
this bit is set to 0.
OSCEN
Calibration
Sign
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the
time-base.
These five bits control the calibration of the clock.
Calibration
Watchdog Timer
0x1FFF7
D7
D6
D5
D4
D3
D2
WDT
D1
D0
WDS
WDW
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0
has no affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is
write only. Reading it always will return a 0.
WDS
Watchdog Write Enable. Setting this bit to 1 masks the watchdog time-out value (WDT5-WDT0) so
it cannot be written. This allows the user to strobe the watchdog without disturbing the time-out
value. Setting this bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register.
The new value will be loaded on the next internal watchdog clock after the write cycle is complete.
This function is explained in more detail in the watchdog timer section.
WDW
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or time-out
value is 31.25 ms (a setting of 1) and the maximum time-out is 2 seconds (setting of 3Fh). Setting
the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit
was cleared to 0 on a previous cycle.
WDT
Interrupt Status / Control
0x1FFF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
ABE
H/L
P/L
0
0
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer
drives the INT pin as well as the WDF flag. When set to 0, the watchdog time-out affects only the
WDF flag.
WIE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag.
When set to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When
set to 0, the power-fail monitor affects only the PF flag.
AIE
PFIE
ABE
H/L
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function
even in battery backup mode. When set to 0, the alarm will occur only when Vcc>Vswitch
.
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open
drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L ) by an interrupt
source for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set
by H/L ) until the Flags/Control register is read.
P/L
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STK17TA8
Alarm – Day
D3
0x1FFF5
D7
D6
D5
D4
D2
D1
D0
M
0
10s Alarm Date
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date
value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
M
Alarm – Hours
0x1FFF4
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Hours
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to
1 causes the match circuit to ignore the hours value.
M
Alarm – Minutes
0x1FFF3
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Minutes
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit
to 1 causes the match circuit to ignore the minutes value.
M
Alarm – Seconds
0x1FFF2
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Seconds
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’
value.
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this
bit to 1 causes the match circuit to ignore the seconds value.
M
Timekeeping – Centuries
0x1FFF1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Centuries
Centuries
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STK17TA8
Flags
D3
0x1FFF0
D7
D6
D5
D4
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0
without being reset by the user. It is cleared to 0 when the Flags/Control register is read.
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the
alarm registers with the match bits = 0. It is cleared when the Flags/Control register is read.
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold
Vswitch. It is cleared to 0 when the Flags/Control register is read.
WDF
AF
PF
Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is not running in the first 5ms of
power-on operation. This indicates that time counts are no longer valid. The user must reset this
bit to 0 to clear this condition. The chip will not clear this flag. This bit survives power cycles.
Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0,
the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then
write them with updated values. Setting the W bit to 0 causes the contents of the time registers to
be transferred to the timekeeping counters.
OSCF
CAL
W
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places
them in a holding register. The user can then read them without concerns over changing values
causing system errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must
be returned to 0 prior to reading again.
R
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Document Control #ML0025 rev 1.4
STK17TA8
ORDERING INFORMATION
STK17TA8 – R F 45 I
Temperature Range
Blank = Commercial (0 to 70º C)
I = Industrial (-40 to 85ºC)
Access Time
25 = 25ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin) ROHS Compliant
Package
R = Plastic 48-pin 300 mil SSOP (25 mil pitch)
July 2006
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Document Control #ML0025 rev 1.4
STK17TA8
Document Revision History
Revision
Date
Summary
Publish new datasheet
0.0
February 2003
Remove 525 mil SOIC, Add 48 Pin SSOP and 40 Pin DIP packages; Modified Block
Diagram in AutoStore description section
0.1
March 2003
Modify 600 mil DIP pin-out (switch pins 32 and 33), Update Power-up Recall specs,
Update Software Controlled Store/Recall Cycle, Added Hardware Store Description,
Modified Mode Selection Table, Updated VSWITCH, Updated tSTORE, Modify IBAK and VBAK
0.2
0.3
June 2003
Change part number from STK17CA8 to STK17TA8; Add lead-free finish option
February 2004
Parameter
Vcap Min
tVCCRISE
ICC1 Max Com.
ICC1 Max Com.
ICC1 Max Com.
ICC1 Max Ind.
ICC1 Max Ind.
ICC1 Max Ind.
ICC2 Max
Old Value
10µF
New Value
17 µF
Notes
NA
150 µs
50 mA
55 mA
65 mA
55 mA
60 mA
70 mA
3.0 mA
3 mA
New Spec
35 mA
40 mA
50 mA
35 mA
45 mA
55 mA
1.5 mA
0.5 mA
5 ms
@ 45ns access
@ 35ns access
@ 25ns access
@ 45ns access
@ 35ns access
@ 25ns access
Com. & Ind.
1.0
December 2004
ICC4 Max
tHRECALL
Com & Ind.
20 ms
tSTORE
tRECALL
10 ms
20 µs
12.5 ms
40 µs
tGLQV
10 ns
12 ns
@ 25 ns access
Changed RTC register unused bits “X” to require zero “0” value when writing values.
1.1
April 2005
Parameter
ICC3 Max Com.
ICC3 Max Ind.
ISB Max Com.
ISB Max Ind.
tRECALL
Old Value
5 mA
New Value
10 mA
10 mA
3 mA
Notes
5 mA
3 mA
3 mA
40 µs
3 mA
60 µs
Soft Recall
Industrial Grade
Only
Contact Simtek for
details.
tSTORE
12.5 ms
1x106
15 ms
5x105
10 sec
5 sec
1.2
September 2005
Max. STORE
Cycles
@ MIN
tOSCS
tOSCS
1 min
Temperature
@ 25ºC from
Power up
10 sec
C1
C2
2.2 pF
47 pF
0 pF
56 pF
RTC Output Cap.
RTC Input Cap
Removed Plastic DIP 40 pin package offering. Package type “W”.
Parameter
tRECALL
Old Value
60 µs
Undefined
New Value
100 µs
Notes
Soft Recall
New Spec
tSS
70 µs
1.3
December 2005
100 Years at
Unspecified
Temperature
20 Years @ Max
Temperature
Data Retention
New Specification
DATAR
Discontinued 35 ns speed grade option.
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STK17TA8
Parameter
Old Value
New Value
Notes
Power-up RECALL
Duration
Nonvolatile
STORE operations
tHRECALL
20 ms
40 ms
1.4
July 2006
NVC
5x105
2x105
20 Years
@ Max Temperature
20 Years
@ 55ºC
Data Retention
DATAR
SIMTEK STK17TA8 Data Sheet, July 2006
Copyright 2006, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any other form or
means without express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but
changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or
transfer of any rights to any Simtek patent, copyright, trademark or other proprietary right.
July 2006
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Document Control #ML0025 rev 1.4
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