STK25CA8-D55 [CYPRESS]
Non-Volatile SRAM Module, 128KX8, 55ns, CMOS, 0.600 INCH, MODULE, DIP-32;
| 型号： | STK25CA8-D55 |
| 厂家： | 
CYPRESS |
| 描述： | Non-Volatile SRAM Module, 128KX8, 55ns, CMOS, 0.600 INCH, MODULE, DIP-32 静态存储器 |
| 文件： | 总7页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK25CA8
128K x 8 AutoStore™ nvSRAM
High Performance CMOS
Nonvolatile Static RAM Module
ADVANCE
FEATURES
DESCRIPTION
• Nonvolatile Storage Without Battery Problems
• Directly Replaces 128K x 8 static RAM, Battery
Backed RAM or EEPROM
• 45ns and 55ns Access Times
• Store to EEPROM Initiated by AutoStore™ on
Power Down
• Recall to SRAM by Power Restore
• 22mA ICC at 200ns Cycle Time
• Unlimited Read, Write and Recall Cycles
• 100,000 Store Cycles to EEPROM
• 10 Year Data Retention Over Full Industrial
Temperature Range
The Simtek STK25CA8 is a fast static RAM with a
nonvolatile, electrically-erasable PROM element
incorporated in each static memory cell. The SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place
automatically on power down using charge stored in
system capacitance. Transfers from the EEPROM to
the SRAM (the RECALL operation) take place auto-
matically on restoration of power.
• Commercial and Industrial Temp. Ranges
• 32 Pin 600 Dual In-Line Module
PIN CONFIGURATION
BLOCK DIAGRAM
NC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
A
2
15
16
MODULE
A15
A16
VCC
A
A
3
NC
W
14
12
DECODER
EEPROM ARRAY
512 x 512 x 4
4
A
5
A
POWER
7
6
13
A5
A6
A7
A8
A
6
A
A
A
8
CONTROL
STORE
A
A
7
5
9
8
4
11
STATIC RAM
ARRAY
STORE/
RECALL
CONTROL
A
9
G
3
RECALL
A9
A
10
11
12
13
14
15
16
A
E
2
10
A11
A12
A13
A14
A
512 x 512 x 4
1
A
DQ
DQ
DQ
DQ
DQ
0
7
6
5
4
3
DQ
DQ
DQ
0
1
2
DQ0
V
SS
COLUMN I/O
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
32 - 600 mil Dual In-Line Module
COLUMN DEC
PIN NAMES
A
- A
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+5V)
Ground
0
16
A0 A1 A2 A3 A4 A10
W
G
DQ - DQ
0
7
E
E
G
W
V
V
CC
SS
21 August 1998
5-35
STK25CA8
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Max-
mum Ratings” may cause permanent damage to the
device. This a stress rating only, and functional operation
of the device at conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on input relative to VSS. . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
DC CHARACTERISTICS
(V = 5.0V ± 10%)
cc
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average Current
UNITS
NOTES
MIN
MAX
MIN
MAX
b
1
I
125
110
133
120
mA
mA
t
t
= 45ns
= 55ns
CC
AVAV
AVAV
c
I
I
Average Current During STORE
Average VCC Current at t = 200ns
20
22
25
25
mA
mA
All inputs Don’t Care
CC
CC
2
b
3
W ≥ (V – 0.2V)
AVAV
CC
All others cycling, CMOS levels
c
I
I
I
I
Average Current During AutoStore™
Cycle
All inputs Don’t Care
CC
4
18
9
20
9
mA
mA
µA
d
Standby Current
(Standby, Stable CMOS Input Levels)
E ≥ (V – 0.2V)
CC
SB
All others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
= max
CC
ILK
±2
±10
±2
±10
V
= V to V
IN
SS
CC
Off-State Output Leakage Current
V
= max
CC
OLK
µA
V
= V to V , E or G ≥ V
IN
SS
CC
IH
V
V
V
Input Logic “1” Voltage
Input Logic “0” Voltage
2.2
V
+ .5
2.2
V + .5
CC
V
V
All inputs
All inputs
IH
CC
V
– .5
0.8
V
– .5
SS
0.8
IL
SS
OH OOuuttppuutt LLooggiicc““10”” VVoollttaaggee
2.4
2.4
V
I
I
=–4mA
= 8mA
OUT
OUT
V
0.4
70
0.4
85
V
OL
T
Operating Temperature
0
-40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and output timing reference levels . . . . . . . . . . . . . . . . . 1.5V
5.0V
Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
e
480 Ohms
30pF
INCLUDING
SCOPE
CAPACITANCE
(TA = 25°C, f = 1.0MHz)
Output
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
Input capacitance
Output capacitance
20
pF
IN
255 Ohms
AND FIXTURE
C
28
pF
OUT
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
21 August 1998
5-36
STK25CA8
SRAM READ CYCLES #1 & #2
(V = 5.0V ± 10%)
cc
SYMBOLS
NO.
STK25CA8-45 STK25CA8-55
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
45
55
AVAV
RC
AA
g
3
Address Access Time
Output Enable to Data Valid
45
20
55
AVQV
4
320
GLQV
OE
OH
LZ
g
5
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
3
5
3
5
AXQX
6
ELQX
h
7
15
15
45
25
25
55
EHQZ
HZ
8
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
d, e
EHICCL
PS
Note f: W must be high during SRAM read cycles and low during SRAM write cycles.
Note g: I/O state assumes E, G, < VIL and W > VIH; device is continuously selected
Note h: Measured + 200mV from steady state output voltage
f, g
SRAM READ CYCLE #1 (Address Controlled)
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ(Data Out)
DATA VALID
f
SRAM READ CYCLE #2 (E Controlled)
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ(Data Out)
DATA VALID
10
ELICCH
t
ACTIVE
I
STANDBY
CC
21 August 1998
5-37
STK25CA8
SRAM WRITE CYCLES #1 & #2
(V = 5.0V ± 10%)
cc
SYMBOLS
NO.
STK25CA8-45 STK25CA8-55
PARAMETER
UNITS
#1
#2
Alt.
MIN
45
30
30
15
0
MAX
MIN
55
40
40
12
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
DH
AW
t
t
t
30
0
40
0
AVWH
AVEH
t
t
t
AS
AVWL
WHAX
AVEL
EHAX
t
t
t
0
0
WR
h, i
WLQZ
t
t
15
25
WZ
t
t
5
5
WHQX
OW
Note i: If W is low when E goes low the outputs remain in the high impedance state.
Note j: E or W must be ≥ VIH during address transitions.
j
SRAM WRITE CYCLE #1: W CONTROLLED
12
t
AVAV
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDENCE
DATA OUT
PREVIOUS DATA
j
SRAM WRITE CYCLE #2: E CONTROLLED
12
t
AVAV
ADDRESS
19
EHAX
18
AVEL
14
t
ELEH
t
t
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDENCE
DATA OUT
21 August 1998
5-38
STK25CA8
AutoStore™ / POWER-UP RECALL
(V = 5.0V ± 10%)
cc
SYMBOLS
STK25CA8
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
26
t
t
t
Power Up RECALL Duration
STORE Cycle Duration
µs
ms
µs
V
k
g
g
RESTORE
STORE
Time allowed to Complete SRAM Cycle
Low Voltage Trigger Level
1
DELAY
V
4.0
4.5
3.9
SWITCH
RESET
V
Low Voltage Reset Level
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
AutoStore™ / POWER UP RECALL
VCC
5V
25
VSWITCH
26
VRESET
TM
AUTOSTORE
23
t STORE
POWER UP RECALL
22
t RESTORE
24
t DELAY
W
DQ
(Data Out)
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
BROWN OUT
AutoStore™
BROWN OUT
AutoStore™
NO RECALL
(VCC DID NOT GO
NO RECALL
(VCC DID NOT GO
RECALL WHEN
ABOVE VSWITCH
BELOW VRESET
)
BELOW VRESET)
21 August 1998
5-39
STK25CA8
DEVICE OPERATION
TM
The STK25CA8 is a versatile memory module that
provides several modes of operation. The
STK25CA8 can operate as a standard 128K x 8
SRAM. It has a 128K x 8 EEPROM shadow to which
the SRAM information can be copied, or from which
the SRAM can be updated in nonvolatile mode.
AutoStore OPERATION
The STK25CA8 uses the intrinsic system capaci-
tance to perform an automatic store on power down.
As long as the system power supply takes at least
tSTORE to decay from VSWITCH down to 3.6V the
STK25CA8 will safely and automatically store the
SRAM data in EEPROM on power-down.
NOISE CONSIDERATIONS
In order to prevent unneeded STORE operations,
automatic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether
a WRITE operation has taken place.
Note that the STK25CA8 is a high speed memory
and so must have a high frequency bypass capaci-
tor of approximately 0.1µF connected between DUT
VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, nor-
mal careful routing of power, ground and signals will
help prevent noise problems.
POWER UP RECALL
During power up, or after any low power condition
(VCC < VRESET) an internal recall request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
SRAM READ
The STK25CA8 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-16 determines which of the 131,072 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ CYCLE #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ CYCLE #2). The
data outputs will repeatedly respond to address
changes within the tAVQV access time without the
need for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
LOW AVERAGE ACTIVE POWER
The STK25CA8 draws significantly less current
when it is cycled at times longer than 50ns. If the
chip enable duty cycle is less than 100%, only
standby current is drawn when the chip is disabled.
The overall average current drawn by the
STK25CA8 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the duty cycle of chip
enable; 3) the overall cycle rate for accesses; 4) the
ratio of READ’s to WRITE’s; 5) the operating temper-
ature; 6) the VCC level and; 7) I/O loading.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
21 August 1998
5-40
STK25CA8
ORDERING INFORMATION
- D 45 I
STK25CA8
Temperature Range
blank = Commercial (0 to 70 degrees C)
I = Industrial (–40 to 85 degrees C)
Access Time
45 = 45ns
55 = 55ns
Package
D = 32 pin 600 mil Dual In-Line Module
21 August 1998
5-41
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