U62H824PA35G1 [CYPRESS]
8KX24 STANDARD SRAM, 35ns, PQCC52, PLASTIC, LCC-52;
| 型号： | U62H824PA35G1 |
| 厂家： | 
CYPRESS |
| 描述： | 8KX24 STANDARD SRAM, 35ns, PQCC52, PLASTIC, LCC-52 静态存储器 |
| 文件： | 总11页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U62H824
Fast 8K x 24 SRAM
Features
Description
! 196 608 bit static CMOS RAM
! 35 ns Access Time
! Fully static Read and Write
operations
The U62H824 is a static RAM
manufactured using a CMOS pro-
cess technology. The device inte-
grates an 8K x 24 SRAM core with
multiple chip enable inputs, output
enable, and an externally control-
led single address pin multiplexer.
These functions allow for direct
allows one physical static RAM
component to efficiently store pro-
gram and vector or scalar ope-
rands
by
dynamically
re-
! Equal address and chip
enable access times
partitioning the RAM array.
Typical applications will logically
map vector operands into upper
memory with scalar operands
being stored in lower memory.
An application example is at the
end of this document for additional
information.
! Single bit on-chip address
multiplexer
! Active high and active low
chip enable inputs
connection
to
the
Motorola
DSP56k Digital Signal Processor
Family and provide a very efficient
means for implementation of a
reduced parts count system requi-
ring no additional interface logic.
The avialability of multiple chip
enable (E1 and E2) and output
enable (G) inputs provides for
greater system flexibility when mul-
tiple devices are used. With either
chip enable unasserted, the device
will enter standby mode, useful in
low-power applications. A single
on-chip multiplexer selects A12 or
X/Y as the highest order address
input depending upon the state of
the V/S control input. This feature
! Output enable controlled three-
state outputs
! TTL/CMOS-compatible
! Low power standby mode
! Power supply voltage 5 V
! Operating temperature range
0 to 70 °C
Multiple power and ground pins
have been utilized to minimize
effectes induced by output noice.
-40 to 85 °C
-40 to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity > 100 mA
! Package: PLCC52
Pin Configuration
Pin Description
7
6
5
4
3
2
1 52 51 50 49 48 47
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
Signal Name Signal Description
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
8
9
10
46
45
44
A0 - A11
A12, X/Y
V/S
DQ0 - DQ23
E1, E2
G
Address Inputs
Multiplexed Address
Address Multiplexer Control
Data Input / Output
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Not Connected
11
12
13
14
15
16
17
18
19
20
43
42
41
40
39
38
37
36
35
34
W
VCC
VSS
NC
DQ14
DQ13
29 30
21 22 23 24 25 26 27 28
31 32 33
For proper operation of the device, all V
pins must be connected to ground.
SS
1
November 26, 2002
U62H824
Block Diagram
A0
VCC
VSS
Memory Cell
Array
Row
Decoder
A5
256 Rows x
768 Columns
A10
A11
DQ0
Input Data
Control
Column I/O
DQ23
Column Decoder
E1
E2
&
V/S
&
A12i
X/Y
A12
1
Q
0
W
G
&
2 to 1 MUX
A6
A9
(LSB)
(MSB)
Truth Table
Mode
Supply
Current
I/O
E1
H
*
E2
*
G
*
W
*
V/S
*
Status
High - Z
High - Z
High - Z
Data Out
Data Out
Data In
Not Selected
ICC(SB)
ICC(SB)
ICC(OP)
ICC(OP)
ICC(OP)
ICC(OP)
ICC(OP)
Not Selected
Output Disable
Read Using X/Y
Read Using A12
Write Using X/Y
Write Using A12
L
*
*
*
L
H
H
H
H
H
H
L
L
*
H
H
H
L
*
L
H
L
L
L
H
L
L
*
L
Data In
H or L
*
2
November 26, 2002
U62H824
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
a
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.5
-0.5
-
7
V
V
b
b
VCC + 0.5
VCC + 0.5
1.75
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
C-Type
K-Type
A-Type
0
70
85
°C
°C
°C
-40
-40
125
Storage Temperature
Tstg
-65
150
°C
Output Short-Circuit Current
at VCC = 5 V and VO = 0 V c
|IOS
|
20
mA
a
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b
c
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Symbol
VCC
Conditions
Min.
4.5
Max.
5.5
Unit
V
Operating Conditions
Power Supply Voltage
Input Low Voltage d
Input High Voltage
VIL
-0.3
2.2
0.8
V
VIH
VCC + 0.3
V
d -2 V at Pulse Width 10 ns
3
November 26, 2002
U62H824
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VE1
VE2
VG
= 5.5 V
= 0.8 V
= 2.2 V
= 2.2 V
other inputs = VIL or VIH
Iout
=
=
0 mA
35 ns
tcW
C/K-Type
A-Type
170
180
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
= 5.5 V
VE1
= VCC - 0.2 V
= 0.2 V
VE2
all inputs
≥ VCC - 0.2 V
or ≤ 0.2 V
C-Type
K-Type
A-Type
6
8
mA
mA
mA
10
Supply Current - Standby Mode
(TTL level)
ICC(SB)1
VCC
= 5.5 V
15
mA
VE1
= 2.2 V
VE2
= 0.8 V
all inputs
= VIH or VIL
Output High Voltage
VOH
VCC
IOH
IOL
= 4.5 V
2.4
V
= -4.0 mA
= 8.0 mA
Output Low Voltage
VOL
IIH
0.4
2
V
Input High Leakage Current
VCC
VIH
VIL
= 5.5 V
= 5.5 V
µA
Input Low Leakage Current
Output High Current
IIL
=
0 V
-2
8
µA
IOH
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
-4
2
mA
Output Low Current
IOL
mA
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VOL
VG
= 5.5 V
= 5.5 V
µA
µA
Low at Three-State Outputs
=
0 V
-2
= VIH
4
November 26, 2002
U62H824
Symbol
35
Switching Characteristics
Read Cycle
Unit
Alt.
tRC
tAA
IEC
tcR
Min.
Max.
Read Cycle Time
35
ns
Address Access Time to Data Valid
MUX Control to Data Valid
ta(A)
35
35
35
15
ns
ta(VS)
ta(E)
Chip Enable Access Time to Data Valid
G LOW to Data Valid
tACE
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ta(G)
Output Hold Time from Address Change
Output Hold Time from MUX Control Change
E1 LOW or E2 HIGH to Output in Low-Z
G LOW to Output in Low-Z
tOH
tv(A)
5
5
0
0
tv(VS)
ten(E)
ten(G)
tdis(E)
tdis(G)
tLZCE
tLZOE
tHZCE
tHZOE
E1 HIGH or E2 LOW to Output in High-Z
G HIGH to Output in High-Z
15
15
Symbol
35
Switching Characteristics
Write Cycle
Unit
Alt.
tWC
tWP
tWP
tAS
IEC
tcW
Min.
35
20
20
0
Max.
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
tw(W)
tsu(W)
tsu(A)
tsu(VS)
Write Pulse Width Setup Time
Address Setup Time
MUX Control Setup Time
Address Valid to End of Write
MUX Control Valid to End of Write
Adress Valid to End of Write
MUX Control Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable
Data Setup Time
0
tAW
tsu(A-WH)
tsu(VS-WH)
tsu(A-E)
tsu(VS-E)
tsu(E)
30
30
30
30
20
20
15
0
tCW
tCW
tDS
tDH
tAH
tw(E)
tsu(D)
Data Hold Time
th(D)
Address Hold from End of Write
MUX Control from End of Write
W HIGH to Output in Low-Z
W LOW to Output in High-Z
th(A)
0
th(VS)
0
tLZWE
tHZWE
ten(W)
tdis(W)
5
15
5
November 26, 2002
U62H824
Test Configuration for Functional Check
A0
VCC
A1
A2
A3
A4
DQ0
A5
A6
VIH
VIL
A7
A8
A9
A10
A11
A12
VO
DQ23
X/Y
Output Load
E1
E2
W
see Figure 1A
Unless Otherwise
Noted
VSS
G
V/S
AC Test Loads
5 V
480
RL = 50 Ω
Output
Output
Z0 = 50 Ω
5 pF
255
VL = 1.5 V
Figure 1A
Figure 1B
Measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W), ten(G) with Output Load from Figure 1B.
6
November 26, 2002
U62H824
Capacitance
Conditions
Symbol
CI
Min.
Max.
Unit
pF
Input Capacitance
VCC
= 5.0 V
= VSS
6
8
VI
f
= 1 MHz
= 25 °C
Output Capacitance
C0
pF
T
a
.
All pins not under test must be connected with ground by capacitors
IC Code Numbers
Example
U62H824
P
K
35
Internal Code
Type
Access Time
35 = 35 ns
Operating Temperature Range
Package
C = 0 to 70 °C
P = PLCC52
K = -40 to 85 °C
A = -40 to 125 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
7
November 26, 2002
U62H824
Read Cycle 1: Ai- or V/S-controlled (during Read Cycle: E1 = G = VIL, E2 = W = VIH)
tcR
Ai
Address Valid
ta(A)
DQi
Previous Data Valid
tv(A)
Output Data Valid
Output
tcR
V/S
MUX Control Valid
ta(VS)
DQi
Output Data Valid
Previous Data Valid
tv(VS)
Output
Read Cycle 2: E-, G-controlled (during Read Cycle: W = VIH)
E1 in the timing diagrams represents both E1 and E2 with E1 asserted Low and E2 asserted High.
tcR
Ai
Address Valid
V/S
E1
MUX Control Valid
ta(E)
ten(E)
tdis(E)
ta(G)
G
ten(G)
tdis(G)
Output Data
DQi
High-Z
High-Z
Output
8
November 26, 2002
U62H824
Write Cycle1: W-controlled
E1 in the timing diagram represents both E1 and E2 with E1 asserted Low and E2 asserted High.
tcW
Ai
Address Valid
tsu(VS-WH)
th(A)
V/S
MUX Control Valid
tsu(E)
tsu(VS)
th(VS)
E1
W
tsu(A-WH)
tw(W)
tsu(D)
tsu(A)
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(W)
DQi
High-Z
Output
G
Write Cycle 2: E-controlled
E1 in the timing diagram represents both E1 and E2 with E1 asserted Low and E2 asserted High.
tcW
Ai
Address Valid
tsu(A-E)
th(A)
tsu(A)
V/S
E1
MUX Control Valid
tsu(VS-E)
tw(E)
th(VS)
tsu(VS)
tsu(W)
tsu(D)
W
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(E)
High-Z
DQi
Output
G
undefined
L- to H-level
H- to L-level
9
November 26, 2002
U62H824
Application Example
DSP
SRAM
U62H824
DQ[0 ... 23]
1FFF
DSP56k
2 k
P :
D[0 ... 23]
1800
17FF
2 k
X :
A[0 ... 10]
A[0 ... 10]
1000
0FFF
A11
DS
PS
X/Y
A15
A14
A12
A11
V/S
X/Y
E1
2 k
P :
0800
07FF
2 k
Y :
E2
0000
DSP
SRAM
P : 4000 ... 47FF
P : 4800 ... 4FFF
X : 4000 ... 4700
Y : 4000 ... 47FF
0800 ... 0FFF
1800 ... 1FFF
1000 ... 17FF
0000 ... 07FF
No memory overlap with internal P-, X-, Y-memorys.
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
10
November 26, 2002
U62H824
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
November 26, 2002
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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