U630H04D1C45 [CYPRESS]
512X8 NON-VOLATILE SRAM, 45ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | U630H04D1C45 |
| 厂家： | 
CYPRESS |
| 描述： | 512X8 NON-VOLATILE SRAM, 45ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
U630H04
HardStore 512 x 8 nvSRAM
Packages: PDIP28 (300 mil)
PDIP28 (600 mil)
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H04 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
Features
SOP28 (300 mil)
High-performance CMOS nonvo-
latile static RAM 512 x 8 bits
25 and 45 ns Access Times
12 and 25 ns Output Enable
Access Times
Description
The U630H04 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
Unlimited Read and Write to
SRAM
Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Hardware RECALL Initiation
(RECALL Cycle Time < 20 µs)
Unlimited RECALL cycles from
EEPROM
The U630H04 is a fast static RAM
(25 and 45 ns), with a nonvolatile
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70°C
-40 to 85°C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
Pin Configuration
Pin Description
NE
n.c.
A7
VCC
W
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
n.c.
A8
3
Signal Name Signal Description
A6
4
A0 - A8
Address Inputs
A5
n.c.
n.c.
G
5
A4
DQ0 - DQ7
Data In/Out
6
A3
PDIP
SOP
Chip Enable
7
E
A2
n.c.
E
8
Output Enable
Write Enable
G
A1
9
W
DQ7
DQ6
DQ5
DQ4
DQ3
A0
10
11
12
13
14
NE
VCC
VSS
Nonvolatile Enable
Power Supply Voltage
Ground
DQ0
DQ1
DQ2
VSS
Top View
1
December 12, 1997
U630H04
Preliminary
VCC
VSS
Block Diagram
EEPROM Array
16 x (32 x 8)
STORE
RECALL
A5
A6
A7
A8
SRAM
Array
16 Rows x
(32 x 8) Columns
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Store/
Recall
Control
VCC
Column Decoder
A0 A1 A2 A3 A4
G
NE
E
W
Truth Table for SRAM Operations
Operating Mode
E
NE
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
*
*
*
H
H
H
High-Z
H
H
H
L
L
*
Data Outputs Low-Z
Data Inputs High-Z
Write
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
VO
PD
Output Voltage
V
Power Dissipation
Operating Temperature
W
C-Type
K-Type
0
-40
70
85
°C
°C
Ta
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
December 12, 1997
Preliminary
U630H04
Recommended
Operating Conditions
Symbol
VCC
Conditions
Min.
4.5
Max.
Unit
V
Power Supply Voltage
Input Low Voltage
Input High Voltage
5.5
0.8
-2 V at Pulse Width
10 ns permitted
VIL
-0.3
2.2
V
VIH
VCC+0.3
V
C-Type
K-Type
Symbol
Conditions
Unit
DC Characteristics
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC
VIL
VIH
= 5.5 V
= 0.8 V
= 2.2 V
tc
tc
= 25 ns
= 45 ns
90
75
95
80
mA
mA
Average Supply Current during
STOREc
ICC2
VCC
E
W
VIL
VIH
= 5.5 V
6
7
mA
≥ VCC-0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1 VCC
E
= 5.5 V
≥ VIH
tc
tc
= 25 ns
= 45 ns
30
20
34
23
mA
mA
Average Supply Current
at tCR = 200 nsb
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
15
15
mA
≥ VCC-0.2 V
Standby Supply Currentd
ICC(SB) VCC
= 5.5 V
1
1
mA
(Stable CMOS Input Levels)
E
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c:
ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
3
December 12, 1997
U630H04
Preliminary
C-Type
K-Type
Unit
DC Characteristics
Symbol
Conditions
Min. Max. Min. Max.
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
8
2.4
8
V
V
0.4
-4
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
1
µA
µA
=
0 V
-1
-1
-1
-1
Output Leakage Current
VCC
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
1
1
µA
µA
=
0 V
SRAM MEMORY OPERATIONS
Symbol
25
45
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min.
Max.
Min.
Max.
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQX
tGLQX
tAXQX
tELICCH
tEHICCL
tcR
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Zh
ta(A)
ta(E)
25
25
12
13
13
45
45
25
20
20
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
5
0
3
0
5
0
3
0
G LOW to Output in Low-Z
Output Hold Time after Addr. Changeg
10 Chip Enable to Power Activee
tPU
11 Chip Disable to Power Standbyd, e
tPD
25
45
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
4
December 12, 1997
Preliminary
U630H04
f
=
=
VIL, W = NE = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
1
t
cR
Ai
Address Valid
2
ta(A
)
Previos
Data Valid
Output Data
Valid
DQi
Output
9
tv(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
1
tcR
Ai
Address Valid
2
ta(A)
3
ta(E)
5
tdis(E)
E
7
ten(E)
4
G
ta(G)
6
tdis(G)
8
ten(G)
DQi
Output
High Impedance
Output Data
Valid
11
10
tPD
tPU
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
25
45
Switching Characteristics
Write Cycle
No.
Unit
IEC
Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
25
20
20
0
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tsu(W)
tsu(A-WH)
tsu(A-WH)
tsu(E)
tAVWL
tAVWH
tELWH
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
20
20
20
12
0
35
35
35
20
0
tELEH
tDVEH
tEHDX
tEHAX
tw(E)
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tsu(D)
th(D)
th(A)
0
0
tdis(W)
ten(W)
10
15
5
5
5
December 12, 1997
U630H04
Preliminary
Write Cycle #1: W-controlledj
12
tcW
Ai
E
Address Valid
21
th(A)
17
tsu(E)
16
tsu(A-WH)
13
tw(W)
W
15
19
20
tsu(A)
tsu(D)
th(D)
DQi
Input
Input Data
Valid
22
tdis(W)
23
ten(W)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
12
tcW
Ai
Address Valid
15
21
18
tw(E)
th(A)
tsu(A)
E
14
tsu(W)
W
19
20
tsu(D)
th(D)
DQi
Input
Input Data
Valid
DQi
Output
High Impedance
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
>
j: E or W and NE must be
VIH during address transitions.
6
December 12, 1997
Preliminary
U630H04
NONVOLATILE MEMORY OPERATIONS
Symbol
STORE CYCLE INHIBIT and
No.
Min.
Max.
Unit
AUTOMATIC POWER UP RECALL
Alt.
IEC
24 Power Up RECALL Durationk, e
Low Voltage Trigger Level
tRESTORE
VSWITCH
650
4.5
µs
4.0
V
k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE CYCLE INHIBIT and AUTOMATIC POWER UP RECALL
VCC
5.0 V
VSWITCH
t
STORE inhibit
24
Power Up
RECALL
tRESTORE
MODE SELECTION
E
W
G
NE
Mode
Power
Notes
L
L
H
L
L
L
L
Nonvolatile RECALL
Nonvolatile STORE
Active
ICC2
l
H
L
L
L
H
L
H
L
*
No operation
Active
*
H or L
l: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
7
December 12, 1997
U630H04
Preliminary
STORE CYCLES
Symbol
No. STORE CYCLE W-controlled
Min.
Max.
Unit
Alt.
IEC
25 STORE Cycle Timem
26 STORE Initiation Cycle Timen
27 Output Disable Setup to NE Fall
28 NE Setup
tWLQX
tWLNH
tGHNL
tNLWL
tELWL
td(W)S
tw(W)S
tsu(G)S
tsu(N)S
tsu(E)S
10
ms
ns
ns
ns
ns
25
5
5
29 Chip Enable Setup
5
STORE CYCLE: W-controlledo
NE
G
27
28
26
tw(W)S
tsu(G)S
tsu(N)S
W
E
29
tsu(E)S
25
td(W)S
High Impedance
DQi
Output
Symbol
No. STORE CYCLE E-controlled
Min.
Max.
Unit
Alt.
IEC
30 STORE Cycle Time
31 STORE Initiation Cycle Time
32 Output Disable Setup to E Fall
33 NE Setup
tELQXS
tELNHS
tGHEL
tNLEL
td(E)S
tw(E)S
10
ms
ns
ns
ns
ns
25
5
tsu(G)S
tsu(N)S
tsu(W)S
5
34 Write Enable Setup
tWLEL
5
STORE CYCLE: E-controlledo
33
tsu(N)S
NE
G
32
tsu(G)S
34
tsu(W)S
W
E
31
tw(E)S
30
td(E)S
High Impedance
DQi
Output
8
December 12, 1997
Preliminary
U630H04
RECALL CYCLES
Symbol
No. RECALL CYCLE NE-controlled
Min.
Max.
Unit
Alt.
IEC
35 RECALL Cycle Timep
36 RECALL Initiation Cycle Timeq
37 Output Enable Setup
38 Write Enable Setup
tNLQX
tNLNH
tGLNL
tWHNL
tELNL
tNLQZ
td(N)R
tw(N)R
20
µs
ns
ns
ns
ns
ns
25
5
tsu(G)R
tsu(W)R
tsu(E)R
tdis(N)R
5
39 Chip Enable Setup
5
40 NE Fall to Output Inactive
25
RECALL CYCLE: NE-controlledo
36
tw(N)R
NE
37
tsu(G)R
G
W
38
tsu(W)R
40
tdis(N)R
E
39
tsu(E)R
35
td(N)R
High Impedance
DQi
Output
Symbol
No. RECALL CYCLE E-controlled
Min.
Max.
Unit
Alt.
IEC
41 RECALL Cycle Time
42 RECALL Initiation Cycle Time
43 NE Setup
tELQXR
tELNHR
tNLEL
td(E)R
tw(E)R
tsu(N)R
tsu(G)R
tsu(W)R
20
µs
ns
ns
ns
ns
25
5
44 Output Enable Setup
45 Write Enable Setup
tGLEL
5
tWHEL
5
RECALL CYCLE: E-controlledo
43
tsu(N)R
NE
44
tsu(G)R
G
W
E
45
tsu(W)R
42
tw(E)R
41
td(E)R
High Impedance
DQi
Output
9
December 12, 1997
U630H04
Preliminary
Symbol
No. RECALL CYCLE G-controlled
Min.
Max.
Unit
Alt.
IEC
46 RECALL Cycle Time
47 RECALL Initiation Cycle Time
48 NE Setup
tGLQXR
tGLNH
tNLGL
tWHGL
tELGL
td(G)R
tw(G)R
tsu(N)R
tsu(W)R
tsu(E)R
20
µs
ns
ns
ns
ns
25
5
49 Write Enable Setup
50 Chip Enable Setup
5
5
RECALL CYCLE: G-controlledo, r
48
tsu(N)R
NE
G
47
tw(G)R
49
tsu(W)R
W
50
tsu(E)R
E
46
td(G)R
High Impedance
DQi
Output
m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are inhibited/aborted by VCC < VSWITCH
(STORE inhibit).
n: Once tw(W)S has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W and E may be used to
terminate the STORE initiation cycle.
o: If E is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated.
For E-controlled STORE during tw(E)S W, G, NE have to be static.
p: Measured with W and NE both HIGH, and G and E LOW.
q: Once tw(N)R has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to
terminate the RECALL initiation cycle.
r:
If W is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL.
10
December 12, 1997
Preliminary
U630H04
Test Configuration for Functional Check
5 V
t
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
480
VIH
VIL
VO
30 pF s
NE
E
W
G
255
VSS
s: In measurement of tdis-times and ten-times the capacitance is 5 pF.
t: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC = 5.0 V
Input Capacitance
CI
8
pF
VI
f
= VSS
= 1MHz
= 25 °C
Output Capacitance
CO
7
pF
Ta
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U630H04
B
D
C
25
Type
ESD Class
blank > 2000 V
B > 1000 V
Package
Access Time
25 = 25 ns
D
= PDIP (300 mil)
D1 = PDIP (600 mil)
= SOP (300 mil)
45 = 45 ns (on special request)
S
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indication the year, and the last 2
digits the calendar week.
11
December 12, 1997
U630H04
Preliminary
Device Operation
STORE cycle, previous nonvolatile data is erased and
the SRAM contents are then programmed into nonvola-
tile elements. Once a STORE cycle is initiated, further
input and output is disabled and the DQ0 - 7 pins are
tristated until the cycle is completed.
If E and G are LOW and W and NE are HIGH at the
end of the cycle, a READ will be performed and the out-
puts will go active, indicating the end of the STORE.
The U630H04 has two separate modes of operation:
SRAM mode and nonvolatile mode, determined by the
state of the NE pin. In SRAM mode, the memory opera-
tes as a standard fast static RAM. In nonvolatile mode,
data is transferred from SRAM to EEPROM (the
STORE operation) or from EEPROM to SRAM (the
RECALL operation). In this mode SRAM functions are
disabled.
HARDWARE NONVOLATILE RECALL
SRAM READ
A RECALL cycle is performed when E, G and NE are
LOW while W is HIGH. Like the STORE cycle, RECALL
is initiated when the last of the three clock-signals goes
to the RECALL state. Once initiated, the RECALL cycle
will take „RECALL Cycle Time“ to complete, during
which all inputs are ignored. When the RECALL com-
pletes, any READ or WRITE state on the input pins will
take effect.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL in no way alters the data in the nonvolatile
cells. The nonvolatile data can be recalled an unlimited
number of times.
The U630H04 performs a READ cycle whenever E and
G are LOW while W and NE are HIGH. The address
specified on pins A0 - A8 determines which of the 512
data bytes will be accessed. When the READ is initia-
ted by an address transition, the outputs will be valid
after a delay of tcR. If the READ is initiated by E or G,
the outputs will be valid at ta(E) or at ta(G), whichever is
later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W or NE is brought LOW.
Like the STORE cycle, a transition must occur on some
control pins to cause a RECALL, preventing inadver-
tend multi-triggering.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and NE is HIGH. The address inputs must be sta-
ble prior to entering the WRITE cycle and must remain
stable until either E or W goes HIGH at the end of the
cycle. The data on pins DQ0 - 7 will be written into the
memory if it is valid tsu(D) before the end of a W control-
led WRITE or tsu(D) before the end of an E controlled
WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis (W) after W goes LOW.
AUTOMATIC POWER UP RECALL
On power up, once VCC exceeds the sense voltage of
V
SWITCH, a RECALL cycle is automatically initiated. The
voltage on the VCC pin must not drop below VSWITCH
once it has risen above it in order for the RECALL to
operate properly. Due to this automatic RECALL,
SRAM operation cannot commence until tRESTORE after
VCC exceeds VSWITCH. If the U630H04 is in a WRITE
state at the end of power up RECALL, the SRAM data
will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
NOISE CONSIDERATION
connected between W and system VCC.
The U630H04 is a high speed memory and therefore
must have a high frequency bypass capacitor of appro-
ximately 0.1 µF connected between VCC and VSS using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise pro-
blems.
HARDWARE PROTECTION
The U630H04 offers two levels of protection to sup-
press inadvertent STORE cycles. If the control signals
(E, G, W and NE) remain in the STORE condition at the
end of a STORE cycle, a second STORE cycle will not
be started. The STORE (or RECALL) will be initiated
only after a transition on any one of these signals to the
required state. In addition to multi-trigger protection, the
U630H04 offers hardware protection through VCC
Sense. When VCC < VSWITCH the externally initiated
STORE operation will be inhibited.
HARDWARE NONVOLATILE STORE
A STORE cycle is performed when NE, E and W are
LOW while G is HIGH. While any sequence to achieve
this state will initiate a STORE, only W initiation and E
initiation are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
12
December 12, 1997
Preliminary
U630H04
LOW AVERAGE ACTIVE POWER
The U630H04 has been designed to draw significantly 1. CMOS or TTL input levels
less power when E is LOW (chip enabled) but the 2. the time during which the chip is disabled (E HIGH)
access cycle time is longer than 55 ns. 3. the cycle time for accesses (E LOW)
When E is HIGH the chip consumes only standby cur- 4. the ratio of READs to WRITEs
rent. 5. the operating temperature
The overall average current drawn by the part depends 6. the VCC level
on the following items:
13
December 12, 1997
Memory Products 1998
HardStore 512 x 8 nvSRAM U630H04
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
The information describes the type of component and shall not be considered as
assured characteristics.
Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH
Grenzstraße 28 • D-01109 Dresden• P. O.B. 800134 •D-01101 Dresden•Germany
Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de
Internet Web Site: http://www.zmd.de
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