U630H16D1C45 [CYPRESS]

2KX8 NON-VOLATILE SRAM, 45ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28;


型号：	U630H16D1C45
厂家：	CYPRESS
描述：	2KX8 NON-VOLATILE SRAM, 45ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 静态存储器光电二极管内存集成电路
文件：	总15页 (文件大小：152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Obsolete - Not Recommended for New Designs

U630H16

HardStore 2K x 8 nvSRAM

Features

Description

• High-performance CMOS nonvo- The U630H16 has two separate

further input or output are disabled

until the cycle is completed.

latile static RAM 2048 x 8 bits

• 25, 35 and 45 ns Access Times

• 12, 20 and 25 ns Output Enable

Access Times

modes of operation: SRAM mode

and nonvolatile mode, determined

by the state of the NE pin.

Internally, RECALL is a two step

procedure. First, the SRAM data is

cleared and second, the nonvola-

tile information is transferred into

the SRAM cells.

The RECALL operation in no way

alters the data in the EEPROM

cells. The nonvolatile data can be

recalled an unlimited number of

times.

In SRAM mode, the memory ope-

rates as an ordinary static RAM. In

nonvolatile operation, data is trans-

ferred in parallel from SRAM to

EEPROM or from EEPROM to

SRAM. In this mode SRAM

functions are disabled.

• Hardware STORE Initiation

(STORE Cycle Time < 10 ms)

• Automatic STORE Timing

• 10⁶STORE cycles to EEPROM

• 100 years data retention in

EEPROM

• Automatic RECALL on Power Up The U630H16 is a fast static RAM

• Hardware RECALL Initiation

(RECALL Cycle Time < 20 ms)

• Unlimited RECALL cycles from

EEPROM

(25, 35, 45 ns), with a nonvolatile

electrically erasable PROM

(EEPROM) element incorporated

in each static memory cell. The

SRAM can be read and written an

unlimited number of times, while

independent nonvolatile data resi-

des in EEPROM. Data transfers

from the SRAM to the EEPROM

(the STORE operation), or from the

EEPROM to the SRAM (the

RECALL operation) are initiated

through the state of the NE pin.

The U630H16 combines the high

performance and ease of use of a

fast SRAM with nonvolatile data

integrity.

• Unlimited Read and Write to

SRAM

• Single 5 V ± 10 % Operation

• Operating temperature ranges:

0to70 ×C

-40to85 ×C

-40to125 °C(only 35 ns)

• QS 9000 Quality Standard

• ESD protection > 2000 V

(MIL STD 883C M3015.7-HBM)

• RoHS compliance and Pb- free

• Packages:SOP28 (300 mil),

PDIP28 (300/600 mil)

Once a STORE cycle is initiated,

Pin Configuration

Pin Description

n.c.

VCC

Signal Name Signal Description

n.c.

A0 - A10

Address Inputs

Data In/Out

DQ0 - DQ7

n.c.

Chip Enable

PDIP

SOP

Output Enable

Write Enable

A10

VCC

VSS

Nonvolatile Enable

Power Supply Voltage

Ground

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

VSS

Top View

March 31, 2006

Rev 1.0

STK Control #ML0036

U630H16

Block Diagram

EEPROM Array

32 x (64 x 8)

V_CC

V_SS

STORE

SRAM

Array

RECALL

32 Rows x

64 x 8 Columns

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

Column I/O

Store/

Recall

Control

V_CC

Column Decoder

A0 A1 A2 A3 A4A10

DQ7

Truth Table for SRAM Operations

Operating Mode

DQ0 - DQ7

Standby/not selected

Internal Read

Read

High-Z

Data Outputs Low-Z

Data Inputs High-Z

Write

* H or L

Characteristics

All voltages are referenced to V_SS= 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V_I, as well as

input levels of V_IL= 0 V and V_IH= 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the t_dis-times and t_en-times, in which cases transition is measured ± ±200 mV from steady-state voltage.

Absolute Maximum Ratings^a

Symbol

Min.

Max.

Unit

Power Supply Voltage

Input Voltage

V_CC

V_I

-0.5

-0.3

V_CC+0.5

Output Voltage

V_O

P_D

Power Dissipation

Operating Temperature

C-Type

K-Type

A-Type

-40

°C

T_a

Storage Temperature

T_stg

-65

150

°C

a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Rev 1.0

March 31, 2006

STK Control #ML0036

U630H16

Recommended

Symbol

V_CC

Conditions

Min.

4.5

Max.

Unit

Operating Conditions

Power Supply Voltage

Input Low Voltage

Input High Voltage

5.5

0.8

-2 V at Pulse Width

10 ns permitted

V_IL

-0.3

2.2

V_IH

V_CC+0.3

C-Type

K-Type

A-Type

Symbol

Conditions

Unit

DC Characteristics

Min. Max. Min. Max. Min. Max.

Operating Supply Current^b

I_CC1

V_CC= 5.5 V

V_IL

V_IH

= 0.8 V

= 2.2 V

t_c

= 25 ns

= 35 ns

= 45 ns

Average Supply Current during

STORE^c

I_CC2

V_CC= 5.5 V

≥ V_CC-0.2 V

≤ 0.2 V

V_IL

V_IH

≥ V_CC-0.2 V

Standby Supply Current^d

(Cycling TTL Input Levels)

I_CC(SB)1V_CC= 5.5 V

≥±V_IH

t_c

= 25 ns

= 35 ns

= 45 ns

Average Supply Current

at t_cR= 200 ns^b

(Cycling CMOS Input Levels)

I_CC3

V_C

V_IL

V_IH

= 5.5 V

≥ V_CC-0.2 V

≤ 0.2 V

≥ V_CC-0.2 V

Standby Supply Current^d

I_CC(SB)V_CC= 5.5 V

(Stable CMOS Input Levels)

V_IL

V_IH

≥ V_CC-0.2 V

≤ 0.2 V

≥ V_CC-0.2 V

b: I_CC1and I_CC3are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

The current I_CC1is measured for WRITE/READ - ratio of 1/2.

c: I_CC2is the average current required for the duration of the STORE cycle (STORE Cycle Time).

d: Bringing E ≥±V_IHwill not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION

table. The current I_CC(SB)1is measured for WRITE/READ - ratio of 1/2.

March 31, 2006

Rev 1.0

STK Control #ML0036

U630H16

Symbol

Conditions

Min.

Max.

Unit

DC Characteristics

V_CC

I_OH

I_OL

= 4.5 V

=-4 mA

= 8 mA

Output High Voltage

Output Low Voltage

V_OH

V_OL

2.4

0.4

-4

V_CC

V_OH

V_OL

= 4.5 V

= 2.4 V

= 0.4 V

Output High Current

Output Low Current

I_OH

I_OL

Input Leakage Current

V_CC

= 5.5 V

High

Low

I_IH

I_IL

V_IH

V_IL

= 5.5 V

μA

0 V

-1

Output Leakage Current

V_CC

= 5.5 V

High at Three-State- Output

Low at Three-State- Output

I_OHZ

I_OLZ

V_OH

V_OL

= 5.5 V

μA

0 V

SRAM Memory Operations

Symbol

Switching Characteristics

No.

Unit

Read Cycle

Alt.

IEC

Min. Max. Min. Max. Min. Max.

Read Cycle Time^f

t_AVAV

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_ELQX

t_GLQX

t_AXQX

t_ELICCH

t_EHICCL

t_cR

t_a(A)

t_a(E)

t_a(G)

t_dis(E)

t_dis(G)

t_en(E)

t_en(G)

t_v(A)

Address Access Time to Data Valid^g

Chip Enable Access Time to Data Valid

Output Enable Access Time to Data Valid

E HIGH to Output in High-Z^h

G HIGH to Output in High-Z^h

E LOW to Output in Low-Z

G LOW to Output in Low-Z

Output Hold Time after Addr. Change^g

10 Chip Enable to Power Active^e

t_PU

11 Chip Disable to Power Standby^{d, e}

t_PD

e: Parameter guaranteed but not tested.

f: Device is continuously selected with E and G both LOW.

g: Address valid prior to or coincident with E transition LOW.

h: Measured ± 200 mV from steady state output voltage.

Rev 1.0

March 31, 2006

STK Control #ML0036

U630H16

V_IL, W = NE = V_IH)

Read Cycle 1: Ai-controlled (during Read cycle: E

t_cR

(1)

Address Valid

(2)

t_a(A)

DQi

Output

Output Data Valid

Previous Data Valid

t_v(A)

(9)

Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = V_IH)^g

t_cR

(1)

Address Valid

t_a(A)

(2)

t_a(E)

(3)

t_dis(E)

(5)

t_en(E)

(7)

t_a(G)

(4)

t_{dis(G) (6)}

t_{en(G) (8)}

DQi

Output

High Impedance

Output Data Valid

t_PD

_PU(10)

(11)

ACTIVE

I_CC

STANDBY

Symbol

Switching Characteristics

Write Cycle

No.

Unit

Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.

12 Write Cycle Time

t_AVAV

t_cW

13 Write Pulse Width

t_WLWH

t_w(W)

14 Write Pulse Width Setup Time

15 Address Setup Time

t_WLEHt_su(W)

t_AVWL

t_AVEL

t_su(A)

t_su(A-WH)

t_su(E)

16 Address Valid to End of Write

17 Chip Enable Setup Time

18 Chip Enable to End of Write

19 Data Setup Time to End of Write

20 Data Hold Time after End of Write

21 Address Hold after End of Write

22 W LOW to Output in High-Z^{h, i}

23 W HIGH to Output in Low-Z

t_AVWHt_AVEH

t_ELWH

t_ELE

t_w(E)

t_DVWHt_DVEH

t_WHDXt_EHDX

t_WHAXt_EHAX

t_WLQZ

t_su(D)

t_h(D)

t_h(A)

t_dis(W)

t_en(W)

t_WHQX

March 31, 2006

Rev 1.0

STK Control #ML0036

U630H16

Write Cycle #1: W-controlled^j

t_cW

(12)

Address Valid

t_su(E)

(17)

t_h(A)

(21)

t_su(A-WH)

(16)

t_w(W)

(13)

t_{su(D) (19)}

Input Data Valid

t_en(W)

t_su(A)

(15)

t_{h(D) (20)}

DQi

Input

t_dis(W)

(22)

(23)

DQi

Output

High Impedance

Previous Data

Write Cycle #2: E-controlled^j

t_cW

(12)

Address Valid

t_su(A)

(15)

t_w(E)

t_h(A)

(21)

(18)

(14)

t_su(W)

t_h(D)

t_su(D)

(19)

(20)

DQi

Input

Input Data Valid

High Impedance

t_{dis(W) (22)}

t_{en(E) (7)}

DQi

Output

undefined

L- to H-level

H- to L-level

i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.

j: E or W and NE must be

_IHduring address transitions.

Rev 1.0

March 31, 2006

STK Control #ML0036

U630H16

Nonvolatile Memory Operations

Symbol

Alt. IEC

STORE Cycle Inhibit and

No.

Min.

Max.

Unit

Automatic Power Up RECALL

24 Power Up RECALL Duration^{k, e}

t_RESTORE

V_SWITCH

650

4.5

μs

Low Voltage Trigger Level

4.0

k: t_RESTOREstarts from the time V_CCrises above V_SWITCH

STORE Cycle Inhibit and Automatic Power Up RECALL

V_CC

5.0 V

V_SWITCH

STORE inhibit

(24)

Power Up

RECALL

t_RESTORE

Mode Selection

Mode

Power

Notes

Nonvolatile RECALL

Nonvolatile STORE

Active

I_CC2

No operation

Active

* H or L

l: An automatic RECALL also takes place at power up, starting when V_CCexceeds V_SWITCHand takes t_RESTORE. V_CCmust not drop below

V_SWITCHonce it has been exceeded for the RECALL to function properly.

March 31, 2006

Rev 1.0

STK Control #ML0036

U630H16

STORE Cycles

Symbol

No. STORE Cycle W-controlled

Min.

Max.

Unit

Alt.

IEC

25 STORE Cycle Time^m

26 STORE Initiation Cycle Timeⁿ

27 Output Disable Setup to NE Fall

28 NE Setup

t_WLQX

t_WLNH

t_GHNL

t_NLWL

t_ELWL

t_d(W)S

t_w(W)S

t_su(G)S

t_su(N)S

t_su(E)S

29 Chip Enable Setup

STORE Cycle: W-controlled^o

t_su(G)S

(27)

t_su(N)S

(28)

t_w(W)S

(26)

t_su(E)S

(29)

t_d(W)S

(25)

DQi

High Impedance

Output

Symbol

IEC

No. STORE Cycle E-controlled

Min.

Max.

Unit

Alt.

30 STORE Cycle Time

31 STORE Initiation Cycle Time

32 Output Disable Setup to E Fall

33 NE Setup

t_ELQXS

t_ELNHS

t_GHEL

t_NLEL

t_d(E)S

t_w(E)S

t_su(G)S

t_su(N)S

t_su(W)S

34 Write Enable Setup

t_WLEL

STORE Cycle: E-controlled^o

t_su(N)S

(33)

_su(G)S(32)

t_su(W)S

(34)

t_{w(E)S (31)}

t_d(E)S

(30)

DQi

High Impedance

Output

Rev 1.0

March 31, 2006

STK Control #ML0036

U630H16

RECALL Cycles

Symbol

No. RECALL Cycle NE-controlled

Min.

Max.

Unit

Alt.

IEC

35 RECALL Cycle Time^p

36 RECALL Initiation Cycle Time^q

37 Output Enable Setup

38 Write Enable Setup

t_NLQX

t_NLNH

t_GLNL

t_WHNL

t_ELNL

t_NLQZ

t_d(N)R

μs

t_w(N)R

t_su(G)R

t_su(W)R

t_su(E)R

t_dis(N)R

39 Chip Enable Setup

40 NE Fall to Output Inactive

RECALL Cycle: NE-controlled^o

t_w(N)R

(36)

t_su(G)R

(37)

t_su(W)R

(38)

t_dis(N)R

(40)

t_su(E)R

t_d(N)R

(35)

(39)

High Impedance

DQi

Output

Symbol

No. RECALL Cycle E-controlled

Min.

Max.

Unit

Alt.

IEC

41 RECALL Cycle Time

42 RECALL Initiation Cycle Time

43 NE Setup

t_ELQXR

t_ELNHR

t_NLEL

t_d(E)R

t_w(E)R

μs

t_su(N)R

t_su(G)R

t_su(W)R

44 Output Enable Setup

45 Write Enable Setup

t_GLEL

t_WHEL

RECALL Cycle: E-controlled^o

t_su(N)R

(43)

t_{su(G)R (44)}

t_su(W)R

(45)

t_w(E)R

(42)

t_d(E)R

(41)

DQi

Output

High Impedance

March 31, 2006

Rev 1.0

STK Control #ML0036

U630H16

Symbol

No. RECALL Cycle G-controlled

Min.

Max.

Unit

Alt.

IEC

46 RECALL Cycle Time

47 RECALL Initiation Cycle Time

48 NE Setup

t_GLQXR

t_GLNH

t_NLGL

t_WHGL

t_ELGL

t_d(G)R

t_w(G)R

t_su(N)R

t_su(W)R

t_su(E)R

μs

49 Write Enable Setup

50 Chip Enable Setup

RECALL Cycle: G-controlled^{o, r}

t_su(N)R

(48)

t_w(G)R

(47)

t_su(W)R

(49)

t_su(E)R

(50)

t_d(G)R

(46)

High Impedance

DQi

Output

m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are inhibited/aborted by V_CC< V_SWITCH

(STORE inhibit).

n: Once t_w(W)Shas been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W and E may be used to

terminate the STORE initiation cycle.

o: If E is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated.

For E-controlled STORE during t_w(E)SW, G, NE have to be static.

p: Measured with W and NE both HIGH, and G and E LOW.

q: Once t_w(N)Rhas been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to

terminate the RECALL initiation cycle.

r: If W is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL.

Rev 1.0

March 31, 2006

STK Control #ML0036

U630H16

Test Configuration for Functional Check

5 V

V_CC

A10

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

480

V_IH

V_IL

V_O

30 pF

255

V_SS

s: In measurement of t_dis-times and t_en-times the capacitance is 5 pF.

t: Between V_CCand V_SSmust be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.

Capacitance^e

Conditions

Symbol

Min.

Max.

Unit

V_CC= 5.0 V

Input Capacitance

C_I

V_I

= V_SS

= 1 MHz

= 25 °C

Output Capacitance

C_O

T_a

All pins not under test must be connected with ground by capacitors.

Ordering Code

Example

Type

U630H16

25 G1

Leadfree Option

blank= Standard Package

Package

D = PDIP28 (300 mil)

G1 = Leadfree Green Package

D1= PDIP28 (600 mil)

S = SOP28 (300 mil)

Access Time

25 = 25 ns

35 = 35 ns (C/K Type on special request)

45 = 45 ns

Operating Temperature Range

C = 0 to 70 °C

K = -40 to 85 °C

A = -40 to 125 °C (only 35 ns and SOP28 package)

u: on special request

Device Marking (example)

ZMD

Product specification

Date of manufacture

U630H16SC

25 Z 0425

(The first 2 digits indicating

the year, and the last 2

digits the calendar week.)

Internal Code

Leadfree Green Package

March 31, 2006

Rev 1.0

STK Control #ML0036

U630H16

Device Operation

disturb SRAM data. During a STORE cycle, previous

nonvolatile data is erased and the SRAM contents are

then programmed into nonvolatile elements. Once a

STORE cycle is initiated, further input and output is

disabled and the DQ0 - 7 pins are tristated until the

cycle is completed.

If E and G are LOW and W and NE are HIGH at the

end of the cycle, a READ will be performed and the out-

puts will go active, indicating the end of the STORE.

The U630H16 has two separate modes of operation:

SRAM mode and nonvolatile mode, determined by the

state of the NE pin. In SRAM mode, the memory opera-

tes as a standard fast static RAM. In nonvolatile mode,

data is transferred from SRAM to EEPROM (the

STORE operation) or from EEPROM to SRAM (the

RECALL operation). In this mode SRAM functions are

disabled.

Hardware Nonvolatile RECALL

SRAM READ

A RECALL cycle is performed when E, G and NE are

LOW while W is HIGH. Like the STORE cycle, RECALL

is initiated when the last of the three clock-signals goes

to the RECALL state. Once initiated, the RECALL cycle

will take „RECALL Cycle Time“ to complete, during

which all inputs are ignored. When the RECALL com-

pletes, any READ or WRITE state on the input pins will

take effect.

Internally, RECALL is a two step procedure. First, the

SRAM data is cleared and second, the nonvolatile

information is transferred into the SRAM cells. The

RECALL in no way alters the data in the nonvolatile

cells. The nonvolatile data can be recalled an unlimited

number of times.

The U630H16 performs a READ cycle whenever E and

G are LOW while W and NE are HIGH. The address

specified on pins A0 - A10 determines which of the

2048 data bytes will be accessed. When the READ is

initiated by an address transition, the outputs will be

valid after a delay of t_cR. If the READ is initiated by E or

G, the outputs will be valid at t_a(E)or at t_a(G), whichever

is later. The data outputs will repeatedly respond to

address changes within the t_cRaccess time without the

need for transition on any control input pins, and will

remain valid until another address change or until E or

G is brought HIGH or W or NE is brought LOW.

SRAM WRITE

Like the STORE cycle, a transition must occur on some

control pins to cause a RECALL, preventing inadver-

tend multi-triggering.

A WRITE cycle is performed whenever E and W are

LOW and NE is HIGH. The address inputs must be sta-

ble prior to entering the WRITE cycle and must remain

stable until either E or W goes HIGH at the end of the

cycle. The data on pins DQ0 - 7 will be written into the

memory if it is valid t_su(D₎before the end of a W control-

led WRITE or t_su(D)before the end of an E controlled

WRITE.

It is recommended that G is kept HIGH during the en-

tire WRITE cycle to avoid data bus contention on the

common I/O lines. If G is left LOW, internal circuitry will

turn off the output buffers t_dis(W)after W goes LOW.

Automatic Power Up RECALL

On power up, once V_CCexceeds the sense voltage of

V_SWITCH, a RECALL cycle is automatically initiated. The

voltage on the V_CCpin must not drop below V_SWITCH

once it has risen above it in order for the RECALL to

operate properly. Due to this automatic RECALL,

SRAM operation cannot commence until t_RESTOREafter

V_CCexceeds V_SWITCH. If the U630H16 is in a WRITE

state at the end of power up RECALL, the SRAM data

will be corrupted.

Noise Consideration

To help avoid this situation, a 10 KΩ resistor should be

connected between W and system V_CC

The U630H16 is a high speed memory and therefore

must have a high frequency bypass capacitor of appro-

ximately 0.1 μF connected between V_CCand V_SSusing

leads and traces that are as short as possible. As with

all high speed CMOS ICs, normal carefull routing of

power, ground and signals will help prevent noise pro-

blems.

Hardware Protection

The U630H16 offers two levels of protection to sup-

press inadvertent STORE cycles. If the control signals

(E, G, W and NE) remain in the STORE condition at the

end of a STORE cycle, a second STORE cycle will not

be started. The STORE (or RECALL) will be initiated

only after a transition on any one of these signals to the

required state. In addition to multi-trigger protection, the

U630H16 offers hardware protection through V_CC

Sense. When V_CC< V_SWITCHthe externally initiated

STORE operation will be inhibited.

Hardware Nonvolatile STORE

A STORE cycle is performed when NE, E and W are

LOW while G is HIGH. While any sequence to achieve

this state will initiate a STORE, only W initiation and E

initiation are practical without risking an unintentional

SRAM WRITE that would

Rev 1.0

March 31, 2006

STK Control #ML0036

U630H16

Low Average Active Power

The U630H16 has been designed to draw significantly 1. CMOS or TTL input levels

less power when E is LOW (chip enabled) but the 2. the time during which the chip is disabled (E HIGH)

access cycle time is longer than 55 ns.

When E is HIGH the chip consumes only standby cur-

rent.

3. the cycle time for accesses (E LOW)

4. the ratio of READs to WRITEs

5. the operating temperature

The overall average current drawn by the part depends 6. the V_CClevel

on the following items:

The information describes the type of component and shall not be considered as assured characteristics. Terms of

delivery and rights to change design reserved.

March 31, 2006

Rev 1.0

STK Control #ML0036

U630H16

LIFE SUPPORT POLICY

Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which

the failure of the Simtek product could create a situation where personal injury or death may occur.

Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However, Simtek makes

no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or

damage of whatever nature resulting from the use of, or reliance upon it. The information in this document descri-

bes the type of component and shall not be considered as assured characteristics.

Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms

and conditions of sale.

Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.

March 31, 2006

Change record

Date/Rev

Name

Change

01.11.2001 Ivonne Steffens

format revision and release for „Memory CD 2002“

11.08.2003 Matthias Schniebel

adding A-Type with I_CC1= 85mA; I_CC2= 7mA; I_CC3= 15mA;

I_CC(SB)= 2mA; I_CC(SB)1= 27 mA

20.04.2004 Matthias Schniebel

adding „Leadfree Green Package“ to ordering information

adding „Device Marking“

7.4.2005

Stefan Günther

changing to 10 endurance cycles and 100a data retention, delete ESD

classes, change ordering code, PDIP 300 on special request, RoHS

and Pb- free added, C/K limitation for PDIP deleted

31.3.2006

1.0

Troy Meester

Simtek

changed to obsolete status

Assigned Simtek Document Control Number

U630H16D1C45 [CYPRESS]

相关型号：

U630H16D1C45G1

U630H16D1C45G1

U630H16D1K25

U630H16D1K25

U630H16D1K25G1

U630H16D1K25G1

U630H16D1K35

U630H16D1K35

U630H16D1K35G1

U630H16D1K35G1

U630H16D1K45

U630H16D1K45