U634H256CSA35 [CYPRESS]
32KX8 NON-VOLATILE SRAM, 35ns, PDSO32, 0.300 INCH, SOP-32;
| 型号： | U634H256CSA35 |
| 厂家： | 
CYPRESS |
| 描述： | 32KX8 NON-VOLATILE SRAM, 35ns, PDSO32, 0.300 INCH, SOP-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U634H256xSA
Automotive PowerStore 32K x 8 nvSRAM
Features
Description
F High-performance CMOS non-
The U634H256xSA has two sepa- high performance and ease of use
volatile static RAM 32768 x 8 bits rate modes of operation: SRAM of a fast SRAM with nonvolatile
F 35 ns Access Time mode and nonvolatile mode. In data integrity.
F 15 ns Output Enable Access Time SRAM mode, the memory operates STORE cycles also may be initia-
F ICC = 15 mA at 200 ns Cycle Time as an ordinary static RAM. In non- ted under user control via a soft-
F Automatic STORE to EEPROM
on Power Down using external
capacitor
F Hardware or Software initiated
STORE
volatile operation, data is transfer- ware sequence or via a single pin
red in parallel from SRAM to (HSB).
EEPROM or from EEPROM to Once a STORE cycle is initiated,
SRAM. In this mode SRAM further input or output are disabled
functions are disabled.
until the cycle is completed.
(STORE Cycle Time < 10 ms)
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
The U634H256xSA is a fast static Because a sequence of addresses
RAM (35 ns), with a nonvolatile is used for STORE initiation, it is
electrically
erasable
PROM important that no other read or
(EEPROM) element incorporated write accesses intervene in the
in each static memory cell. The sequence or the sequence will be
F Automatic RECALL on Power Up SRAM can be read and written an aborted.
F Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
F Unlimited RECALL cycles from
EEPROM
F Single 5 V ± 10 % Operation
F Operating temperature ranges:
--40 to 125 °C
unlimited number of times, while RECALL cycles may also be initia-
independent nonvolatile data resi- ted by a software sequence.
des in EEPROM. Data transfers Internally, RECALL is a two step
from the SRAM to the EEPROM procedure. First, the SRAM data is
(the STORE operation) take place cleared and second, the nonvola-
automatically upon power down tile information is transferred into
using charge stored in an external the SRAM cells.
F CECC 90000 Quality Standard
F ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
100 µF capacitor.
The RECALL operation in no way
Transfers from the EEPROM to the alters the data in the EEPROM
SRAM (the RECALL operation) cells. The nonvolatile data can be
take place automatically on power recalled an unlimited number of
up.
times.
F Package: SOP32 (300 mil)
The U634H256xSA combines the
Pin Description
Pin Configuration
VCAP
A14
A12
A7
1
2
3
4
5
6
7
8
VCCX
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HSB
W
Signal Name Signal Description
A0 - A14
Address Inputs
Data In/Out
A13
A8
A6
DQ0 - DQ7
A5
A9
Chip Enable
E
A4
A11
Output Enable
Write Enable
A3
G
G
SOP
n.c.
A2
9
n.c.
A10
E
W
10
11
12
13
14
VCCX
VSS
VCAP
Power Supply Voltage
Ground
A1
A0
DQ7
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
Capacitor
Hardware Controlled Store/Busy
HSB
15
16
DQ4
DQ3
Top View
1
April 22, 2002
U634H256xSA
Block Diagram
VCCX
VSS
EEPROM Array
512 x (64 x 8)
A5
A6
VCAP
STORE
A7
A8
A9
SRAM
Array
RECALL
VCCX
VCAP
Power
Control
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
Store/
Recall
Control
HSB
DQ0
DQ1
Column I/O
DQ2
DQ3
Software
Detect
A0 - A13
Column Decoder
DQ4
DQ5
DQ6
G
A0 A1 A2 A3 A4 A10
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
HSB
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
H
H
H
H
High-Z
High-Z
*
*
H
H
H
L
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
*H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
VCC+0.5
VCC+0.5
1
V
V
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
Storage Temperature
W
°C
°C
-40
-65
125
Tstg
150
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
April 22, 2002
U634H256xSA
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltageb
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
Input Low Voltage
Input High Voltage
VIH
VCC+0.3
DC Characteristics
Symbol
Conditions
Min.
Max.
Unit
Operating Supply Currentc
ICC1
VCC
VIL
VIH
= 5.5 V
= 0.8 V
= 2.2 V
tc
= 35 ns
80
7
mA
mA
Average Supply Current during
STOREc
ICC2
VCC
E
= 5.5 V
≤ 0.2 V
W
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Average Supply Current during
PowerStore Cycle
ICC4
VCC
VIL
= 4.5 V
= 0.2 V
4
mA
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1
VCC
E
= 5.5 V
= VIH
tc
= 35 ns
38
15
mA
mA
Operating Supply Current
at tcR = 200 nsc
ICC3
VCC
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
(Cycling CMOS Input Levels)
≥ VCC-0.2 V
Standby Supply Currentd
(Stable CMOS Input Levels)
ICC(SB)
VCC
E
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
4
mA
≥ VCC-0.2 V
b: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is con-
nected to ground.
c:
I
CC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
CC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
I
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION able.
The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
3
April 22, 2002
U634H256xSA
DC Characteristics
Symbol
Conditions
Min.
Max.
Unit
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
V
V
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
8
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
µA
µA
=
0 V
-1
-1
Output Leakage Current
VCC
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
1
µA
µA
=
0 V
SRAM Memory Operations
Symbol
Switching Characteristics
No.
Min.
Max.
Unit
Read Cycle
Alt.
IEC
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Zh
35
35
15
13
13
tGLQV
tEHQZ
tGHQZ
tELQX
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
5
0
3
0
G LOW to Output in Low-Z
tGLQX
tAXQX
tELICCH
tEHICCL
Output Hold Time after Address Change
10 Chip Enable to Power Activee
tPU
11 Chip Disable to Power Standbyd, e
tPD
35
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
4
April 22, 2002
U634H256xSA
f
=
=
Read Cycle 1: Ai-controlled (during Read cycle: E
G
VIL, W = VIH)
tcR
(1)
Ai
Address Valid
(2)
ta(A)
DQi
Output
Output Data Valid
Previous Data Valid
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
(1)
Ai
E
Address Valid
tPD
ta(A)
(11)
(2)
ta(E)
(3)
t
dis(E) (5)
ten(E) (7)
G
ta(G)
(4)
tdis(G)
(6)
ten(G)
(8)
DQi
Output
High Impedance
Output Data Valid
tPU
(10)
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
Switching Characteristics
Write Cycle
No.
Min.
Max.
Unit
IEC
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tAVWL
tAVWH
tELWH
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
25
25
25
12
0
tELEH
tDVEH
tEHDX
tEHAX
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tsu(D)
th(D)
th(A)
0
tdis(W)
ten(W)
13
5
5
April 22, 2002
U634H256xSA
Write Cycle #1: W-controlledj
tcW
(12)
Ai
E
Address Valid
(17)
tsu(E)
th(A)
(21)
tsu(A-WH)
(16)
tw(W)
(13)
W
tsu(A)
(15)
tsu(D)
th(D)
(20)
(19)
Input Data Valid
ten(W)
DQi
Input
tdis(W)
(22)
(23)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
tw(E)
th(A)
(18)
(21)
tsu(A)
(15)
tsu(W)
(14)
W
tsu(D)
th(D)
(19)
(20)
DQi
Input
Input Data Valid
DQi
High Impedance
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
6
April 22, 2002
U634H256xSA
Nonvolatile Memory Operations
Mode Selection
A13 - A0
(hex)
E
W
HSB
Mode
I/O
Power
Notes
H
L
L
L
X
H
L
H
H
H
H
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
l
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
k, l
k, l
k, l
k, l
k, l
k
Nonvolatile STORE
L
H
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
Nonvolatile RECALL
X
X
L
X
STORE/Inhibit
Output High Z
I
CC2/Standby
m
k: The six consecutive addresses must be in order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a Store cycle or (0E38, 31C7, 03E0,
3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables
and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any)
completes, the part will go into standby mode inhibiting all operation until HSB rises.
Symbol
PowerStore Power Up RECALL/
No.
Conditions
Min.
Max. Unit
Hardware Controlled STORE
Alt.
IEC
24 Power Up RECALL Durationn, e
25 STORE Cycle Duration
26 HSB Low to Inhibit One
27 HSB High to Inhibit Offe
28 External STORE Pulse Widthe
HSB Output Low Currente,o
HSB Output High Currente, o
Low Voltage Trigger Level
tRESTORE
tHLQX
650
10
µs
ms
µs
ns
ns
mA
µA
V
>
td(H)S
tdis(H)S
ten(H)S
tw(H)S
VCC 4.5 V
tHLQZ
1
tHHQX
700
tHLHX
20
3
IHSBOL
IHSBOH
VSWITCH
HSB = VOL
HSB = VIL
5
60
4.0
4.5
n: tRESTORE starts from the time VCC rises above VSWITCH
.
o: HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 U634H256xSA to be ganged
together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other U634H256xSA HSB pins.
7
April 22, 2002
U634H256xSA
PowerStore and automatic Power Up RECALL
VCAP
5.0 V
VSWITCH
t
PowerStore
p
tPDSTORE
Power Up
RECALL
(24)
(24)
tRESTOR
tRESTORE
E
W
p
tDELAY
DQi
BROWN OUT
POWER UP BROWN OUT
RECALL
PowerStore
NO STORE
(NO SRAM WRITES)
Hardware Controlled STORE
q
tw(H)S
(28)
HSB
DQi
t
en(H)S (27)
tdis(H)S
(26)
High Impedance
td(H)S
Previous Data Valid
Data Valid
Output
(25)
Symbol
Software Controlled STORE/
RECALL Cycle
No.
Min.
Max.
Unit
Alt.
IEC
29 STORE/RECALL Initiation Time
30 Chip Enable to Output Inactives
31 STORE Cycle Time
tAVAV
tELQZ
tELQXS
tELQXR
tcR
35
ns
ns
ms
µs
ns
ns
ns
tdis(E)SR
td(E)S
600
10
32 RECALL Cycle Timer
td(E)R
20
33 Address Setup to Chip Enablet
34 Chip Enable Pulse Widths, t
35 Chip Disable to Address Changet
tAVELN tsu(A)SR
tELEHN tw(E)SR
tEHAXN th(A)SR
0
25
0
p: tPDSTORE approximate td(E)S or td(H)S; tDELAY approximate tdis(H)S
.
q: After tw(H)S HSB is hold down internal by STORE operation.
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
SWITCH once it has been exceeded for the RECALL to function properly.
V
s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
t: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
8
April 22, 2002
U634H256xSA
Software Controlled STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation)
tcR
tcR
(29)
(29)
ADDRESS 6
th(A)SR
tw(E)SR
Ai
E
ADDRESS 1
(35)
tw(E)SR
(34)
t
dis(E) (5)
(34)
tsu(A)SR
(33)
(33)
tsu(A)SR
th(A)SR
(35)
td(E)S (31) td(E)R (32)
DQi
Output
High Impedance
VALID
VALID
tdis(E)SR
(30)
Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)
tcR
(29)
ADDRESS 1
ADDRESS 6
th(A)SR
Ai
E
(35)
(32)
tw(E)SR
(34)
tsu(A)SR
(33)
(33)
th(A)SR
(35)
td(E)S
td(E)R
(31)
tsu(A)SR
DQi
Output
High Impedance
VALID
tdis(E)SR
VALID
(30)
u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256xSA performs a
STORE or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
9
April 22, 2002
U634H256xSA
Test Configuration for Functional Check
5 V
Y
A0
A1
VCCX
VCAP
A2
A3
A4
A5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
480
A6
A7
A8
A9
A10
A11
A12
A13
VIH
VIL
VO
A14
30 pF x
HSB
E
HSB
W
255
G
VSS
x: In measurement of tdis-times and ten-times the capacitance is 5 pF.
y: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC
VI
f
= 5.0 V
= VSS
= 1 MHz
= 25 °C
Input Capacitance
CI
8
pF
Output Capacitance
CO
7
pF
Ta
All Pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U634H256
S
A
35
C
Type
ESD Class
Vz
blank > 2000
B > 1000 Vz
C > 500 V
Access Time
Package
S = SOP (300 mil)
35 = 35 ns
Operating Temperature Range
A= -40 to 125°C
z: ESD protection > 1000 and 2000 V under development
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
10
April 22, 2002
U634H256xSA
Device Operation
will automatically disconnect the VCAP pin from VCCX
and initiate a STORE operation.
The U634H256xSA has two separate modes of opera-
tion:
Figure 1 shows the proper connection of capacitors for
automatic STORE operation. The charge storage capa-
citor should have a capacity of 100 µF (± 20 %) at 6 V.
Each U634H256xSA must have its own 100 µF capaci-
tor. Each U634H256xSA must have a high quality, high
frequency bypass capacitor of 0.1 µF connected bet-
ween VCAP and VSS, using leads and traces that are
short as possible. This capacitor do not replace the nor-
mal expected high frequency bypass capacitor bet-
SRAM mode and nonvolatile mode. The memory ope-
rates In SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also auto-
matically initiated when the power supply voltage level
of the chip falls below VSWITCH. RECALL operations are
automatically initiated upon power up and may also
occur when the VCCX rises above VSWITCH, after a low
power condition. RECALL cycles may also be initiated
by a software sequence.
ween the power supply voltage and VSS
.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITES have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
SRAM READ
The U634H256xSA performs a READ cycle whenever
E and G are LOW and HSB and W are HIGH. The
address specified on pins A0 - A14 determines which of
the 32768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of tcR. If the READ is initiated
Automatic RECALL
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < VSWITCH
)
by E or G, the outputs will be valid at ta(E) or at ta(G)
,
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
whichever is later. The data outputs will repeatedly
respond to address changes within the tcR access time
without the need for transition on any control input pins,
and will remain valid until another address change or
until E or G is brought HIGH or W or HSB is brought
LOW.
V
SWITCH, a requested RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the U634H256xSA is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
SRAM WRITE
Software Nonvolatile STORE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pins DQ0 - 7 will be written
into the memory if it is valid tsu(D) before the end of a W
controlled WRITE or tsu(D) before the end of an E con-
trolled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
The U634H256xSA software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U634H256xSA implements nonvolatile opera-
tion while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
Automatic STORE
During normal operation, the U634H256xSA will draw
current from VCCX to charge up a capacitor connected
to the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the VCCX pin drops below VSWITCH, the part
To initiate the STORE cycle the following READ
sequence must be performed:
11
April 22, 2002
U634H256xSA
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex) Valid READ
31C7 (hex) Valid READ
03E0 (hex) Valid READ
3C1F (hex) Valid READ
303F (hex) Valid READ
0FC0 (hex) Initiate STORE
the STORE operation will begin immediately.
HARDWARE-STORE-BUSY (HSB) is a high speed,
low drive capability bidirectional control line.
In order to allow a bank of U634H256xSAs to perform
synchronized STORE functions, the HSB pin from a
number of chips may be connected together. Each chip
contains a small internal current source to pull HSB
HIGH when it is not being driven LOW. To decrease the
sensitivity of this signal to noise generated on the PC
board, it may optionally be pulled to power supply via
an external resistor with a value such that the combi-
ned load of the resistor and all parallel chip connections
does not exceed IHSBOL at VOL (see Figure 1 and 2).
Only if HSB is to be connected to external circuits, an
external pull-up resistor should be used.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
During any STORE operation, regardless of how it was
initiated, the U634H256xSA will continue to drive the
HSB pin LOW, releasing it only when the STORE is
complete.
Upon completion of a STORE operation, the part will be
disabled until HSB actually goes HIGH.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
Hardware Protection
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex) Valid READ
31C7 (hex) Valid READ
03E0 (hex) Valid READ
3C1F (hex) Valid READ
303F (hex) Valid READ
0C63 (hex) Initiate RECALL
The U634H256xSA offers hardware protection against
inadvertent STORE operation during low voltage condi-
tions. When VCAP < VSWITCH, all software or HSB initia-
ted STORE operations will be inhibited.
Preventing Automatic STORES
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
The PowerStore function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15 mA at VOH of at least 2.2 V as it will have to overpo-
wer the internal pull-down device that drives HSB LOW
for 50 ns at the onset of a PowerStore.
When the U634H256xSA is connected for PowerStore
operation (see Figure 1) and VCCX crosses VSWITCH on
the way down, the U634H256xSA will attempt to pull
HSB LOW; if HSB doesn′t actually get below VIL, the
part will stop trying to pull HSB LOW and abort the
PowerStore attempt.
HSB Nonvolatile STORE
The hardware controlled STORE Busy pin (HSB) is
connected to an open drain circuit acting as both input
and output to perform two different functions. When
driven LOW by the internal chip circuitry it indicates that
a STORE operation (initiated via any means) is in pro-
gress within the chip. When driven LOW by external cir-
cuitry for longer than tw(H)S, the chip will conditionally
Disabling Automatic STORES
If the PowerStore function is not required, then VCAP
should be tied directly to the power supply and VCCX
should by tied to ground. In this mode, STORE opera-
tion may be triggered through software control or the
HSB pin. In either event, VCAP (Pin 1) must always
have a proper bypass capacitor connected to it
(Figure 2).
initiate a STORE operation after tdis(H)S
.
READ and WRITE operations that are in progress
when HSB is driven LOW (either by internal or external
circuitry) will be allowed to complete before the STORE
operation is performed, in the following manner.
After HSB goes LOW, the part will continue normal
SRAM operation for tdis(H)S. During tdis(H)S, a transition
on any address or control signal will terminate SRAM
operation and cause the STORE to commence.
Note that if an SRAM WRITE is attempted after HSB
has been forced LOW, the WRITE will not occur and
12
April 22, 2002
U634H256xSA
Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL
VCAP
5.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Power
Supply
VCCX
VCAP
VCAP
VCCX
HSB
10 kΩ
Power
Supply
1
32
31
30
29
28
27
26
25
24
23
1
32
(optional,
2
2
31
30
29
28
27
26
25
24
23
see description HSB
nonvolatile store)
HSB
10 kΩ
3
3
(optional,
see description HSB
nonvolatile store)
4
4
5
5
6
6
+
7
7
8
8
100 µF
± 20 % Bypass
0.1 µF
0.1 µF
Bypass
9
10
9
10
11
12
13
14
15
16
11
12
13
14
15
16
22
21
20
19
18
17
22
21
20
19
18
17
VSS
VSS
Figure 1: Automatic STORE Operation
Figure 2: Disabling Automatic STORES
Schematic Diagram
Schematic Diagram
Low Average Active Power
The U634H256xSA has been designed to draw signifi-
1. CMOS or TTL input levels
cantly less power when E is LOW (chip enabled) but 2. the time during which the chip is disabled (E HIGH)
the access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
The overall average current drawn by the part depends
on the following items:
6. the power supply voltage level
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
13
April 22, 2002
U634H256xSA
U634H256xSA
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
April 22, 2002
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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