U634H256XSC25 [CYPRESS]
32K X 8 NON-VOLATILE SRAM, 25 ns, UUC35, DIE-35;
| 型号： | U634H256XSC25 |
| 厂家： | 
CYPRESS |
| 描述： | 32K X 8 NON-VOLATILE SRAM, 25 ns, UUC35, DIE-35 静态存储器 |
| 文件： | 总17页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Obsolete - Not Recommended for New Designs
U634H256XS
PowerStore 32K x 8 nvSRAM Die
Features
Description
• High-performance CMOS non-
The U634H256XS has two sepa- STORE cycles also may be initia-
volatile static RAM 32768 x 8 bits rate modes of operation: SRAM ted under user control via a soft-
• 25, 35 and 45 ns Access Times
• 10, 15 and 20 ns Output Enable
Access Times
mode and nonvolatile mode. In ware sequence or via a single pad
SRAM mode, the memory operates (HSB).
as an ordinary static RAM. In non- Once a STORE cycle is initiated,
volatile operation, data is transfer- further input or output are disabled
red in parallel from SRAM to until the cycle is completed.
EEPROM or from EEPROM to Because a sequence of addresses
SRAM. In this mode SRAM is used for STORE initiation, it is
• ICC = 15 mA typ. at 200 ns Cycle
Time
• Automatic STORE to EEPROM
on Power Down using external
capacitor
functions are disabled.
important that no other read or
• Hardware or Software initiated
The U634H256XS is a fast static write accesses intervene in the
RAM (25, 35, 45 ns), with a nonvo- sequence or the sequence will be
latile electrically erasable PROM aborted.
(EEPROM) element incorporated RECALL cycles may also be initia-
in each static memory cell. The ted by a software sequence.
SRAM can be read and written an Internally, RECALL is a two step
unlimited number of times, while procedure. First, the SRAM data is
STORE
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 105 STORE cycles to EEPROM
• 10 years data retention in
EEPROM
• Automatic RECALL on Power Up independent nonvolatile data resi- cleared and second, the nonvola-
• Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
des in EEPROM. Data transfers tile information is transferred into
from the SRAM to the EEPROM the SRAM cells.
(the STORE operation) take place The RECALL operation in no way
automatically upon power down alters the data in the EEPROM
using charge stored in an external cells. The nonvolatile data can be
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
100 μF capacitor.
recalled an unlimited number of
Transfers from the EEPROM to the times.
SRAM (the RECALL operation)
take place automatically on power
-40 to 85 °C
• QS 9000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
The chips are tested with a
up.
restricted wafer probe program
at room temperature only. Unte-
sted parameters are marked with
a number sign (#).
The U634H256XS combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
Pad Description
Pad Configuration
A14
A13
HSB W
A8
VCAP
VCCX
A6
A7 A12
A9
A5
Signal Name Signal Description
A0 - A14
Address Inputs
Data In/Out
A4
A11
G
DQ0 - DQ7
A3
Chip Enable
E
Output Enable
Write Enable
G
W
VCCX
VSS
VCAP
Power Supply Voltage
Ground
A2
A1
A10
E
Capacitor
DQ7
A0
DQ1 DQ2 VSS VCAPDQ3 DQ4 DQ5 DQ6
DQ0
Hardware Controlled Store/Busy
HSB
March 31, 2006
STK Control #ML0049
1
Rev 1.0
U634H256XS
Block Diagram
VCCX
VSS
EEPROM Array
512 x (64 x 8)
A5
A6
VCAP
STORE
A7
A8
A9
SRAM
Array
RECALL
VCCX
VCAP
Power
Control
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
Store/
Recall
Control
HSB
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
Column I/O
Software
Detect
Column Decoder
A0 - A13
A0 A1 A2 A3 A4A10
G
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
HSB
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
H
H
H
H
High-Z
High-Z
*
*
H
H
H
L
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
*H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± ±200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
Output Voltage
VO
PD
Ta
V
Power Dissipation
W
Operating Temperature
C-Type
K-Type
0
-40
70
85
°C
°C
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Rev 1.0
March 31, 2006
STK Control #ML0049
2
U634H256XS
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltageb
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
Input Low Voltage
Input High Voltage
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentc
ICC1
VCC
VIL
VIH
= 5.5 V
= 0.8 V
= 2.2 V
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
95#
75#
65#
100# mA
80# mA
70# mA
Average Supply Current during
STOREc
ICC2
VCC
E
W
VIL
VIH
= 5.5 V
≤ 0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥±VCC-0.2 V
6#
7# mA
Average Supply Current during
PowerStore Cycle
ICC4
VCC
VIL
= 4.5 V
= 0.2 V
4#
4# mA
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1
VCC
E
= 5.5 V
= VIH
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
40#
36#
33#
42# mA
38# mA
35# mA
Operating Supply Current
at tcR = 200 nsc
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 5.5 V
20#
20# mA
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Standby Supply Curentd
(Stable CMOS Input Levels)
ICC(SB)
VCC
E
VIL
VIH
= 5.5 V
3#
3# mA
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
b: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is con-
nected to ground.
c:
ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E±≥±VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION able.
The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
March 31, 2006
STK Control #ML0049
3
Rev 1.0
U634H256XS
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4#
8#
-1
2.4#
8#
-1
V
V
0.4#
-4#
0.4#
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
-4# mA
mA
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
1
μA
μA
=
0 V
Output Leakage Current
VCC
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
1
1
μA
μA
=
0 V
-1
-1
SRAM Memory Operations
Symbol
25
35
45
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1 Read Cycle Timef
tAVAV
tAVQV
tELQV
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
25#
35#
45#
ns
45# ns
45# ns
20# ns
15# ns
15# ns
ns
2 Address Access Time to Data Validg
25#
25#
10#
10#
10#
35
35
3 Chip Enable Access Time to Data Valid
4 Output Enable Access Time to Data Valid tGLQV
15#
13#
13#
5 E HIGH to Output in High-Zh
6 G HIGH to Output in High-Zh
7 E LOW to Output in Low-Z
tEHQZ
tGHQZ
tELQX
5#
0#
3#
0#
5#
0#
3#
0#
5#
0#
3#
0#
8 G LOW to Output in Low-Z
tGLQX
ns
9 Output Hold Time after Address Change
10 Chip Enable to Power Activee
11 Chip Disable to Power Standbyd, e
tAXQX
tELICCH
tEHICCL
ns
tPU
ns
tPD
25#
35#
45# ns
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
Rev 1.0
March 31, 2006
STK Control #ML0049
4
U634H256XS
f
=
=
VIL, W = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
tcR
(1)
Ai
Address Valid
(2)
ta(A)
DQi
Output
Output Data Valid
Previous Data Valid
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
(1)
Ai
E
Address Valid
ta(A)
tPD
(2)
(3)
(11)
ta(E)
tdis(E)
(5)
ten(E)
(7)
G
t
a(G) (4)
t
dis(G) (6)
ten(G)
(8)
DQi
Output
High Impedance
Output Data Valid
t
PU (10)
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
25
35
45
Switching Characteristics
Write Cycle
No.
Unit
IEC
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
25#
20#
20#
0#
35#
25#
25#
0#
45#
30#
30#
0#
ns
13 Write Pulse Width
tWLWH
ns
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
ns
tAVWL
tAVWH
tELWH
ns
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20#
20#
20#
10#
0#
25#
25#
25
30#
30#
30#
15#
0#
ns
ns
tELEH
tDVEH
tEHDX
tEHAX
ns
tDVWH
tsu(D)
th(D)
12
ns
ns
20 Data Hold Time after End of Write tWHDX
0#
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
tWHAX
tWLQZ
tWHQX
th(A)
0#
0#
0#
ns
tdis(W)
ten(W)
10#
13#
15# ns
ns
5#
5#
5#
March 31, 2006
STK Control #ML0049
5
Rev 1.0
U634H256XS
Write Cycle #1: W-controlledj
tcW
(12)
Ai
Address Valid
(17)
tsu(E)
th(A)
(21)
E
tsu(A-WH)
(16)
W
tw(W)
(13)
tsu(A)
(15)
tsu(D)
th(D)
(19)
Input Data Valid
ten(W)
(20)
DQi
Input
t
dis(W) (22)
(23)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
tw(E)
th(A)
(21)
(18)
tsu(A)
(15)
tsu(W)
(14)
W
t
th(D)
Input Data Valid
High Impedance
su(D) (19)
(20)
DQi
Input
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
Rev 1.0
March 31, 2006
STK Control #ML0049
6
U634H256XS
Nonvolatile Memory Operations
Mode Selection
A13 - A0
(hex)
E
W
HSB
Mode
I/O
Power
Notes
H
L
L
L
X
H
L
H
H
H
H
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
l
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
k, l
k, l
k, l
k, l
k, l
k
Nonvolatile STORE
L
H
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
Nonvolatile RECALL
X
X
L
X
STORE/Inhibit
Output High Z
I
CC2/Standby
m
k: The six consecutive addresses must be in order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a Store cycle or (0E38, 31C7, 03E0,3C1F,
303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: I/O state assumes that G±≤±VIL. Activation of nonvolatile cycles does not depend on the state of G.
m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any)
completes, the part will go into standby mode inhibiting all operation until HSB rises.
Symbol
PowerStore Power Up RECALL/
No.
Conditions
Min. Max. Unit
Hardware Controlled STORE
Alt.
IEC
24 Power Up RECALL Durationn, e
25 STORE Cycle Duration
tRESTORE
tHLQX
tHLQZ
650# μs
>
td(H)S
tdis(H)S
ten(H)S
tw(H)S
VCC 4.5 V
10# ms
26 HSB Low to Inhibit One
1#
μs
700# ns
ns
27 HSB High to Inhibit Offe
tHHQX
tHLHX
28 External STORE Pulse Widthe
HSB Output Low Currente,o
20#
3#
IHSBOL
IHSBOH
VSWITCH
.
HSB = VOL
HSB = VIL
mA
HSB Output High Currente, o
5#
60# μA
Low Voltage Trigger Level
4.0
4.5
V
n: tRESTORE starts from the time VCC rises above VSWITCH
o: HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 U634H256XS to be ganged
together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other U634H256XS HSB pads.
March 31, 2006
STK Control #ML0049
7
Rev 1.0
U634H256XS
PowerStore and Automatic Power Up RECALL
VCAP
5.0 V
VSWITCH
t
PowerStore
p
tPDSTORE
Power Up
(24)
(24)
RECALL
tRESTOR
tRESTORE
E
W
p
tDELAY
DQi
BROWN OUT
NO STORE
(NO SRAM WRITES)
BROWN OUT
PowerStore
POWER UP
RECALL
Hardware Controlled STORE
q
tw(H)S
(28)
HSB
DQi
t
en(H)S (27)
tdis(H)S
(26)
High Impedance
Previous Data Valid
Data Valid
Output
td(H)S
(25)
Symbol
25
35
45
Software Controlled STORE/RECALL
Cycle
No.
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
29 STORE/RECALL Initiation Time
30 Chip Enable to Output Inactives
31 STORE Cycle Time
tAVAV
tELQZ
tcR
25#
35#
45#
ns
600# ns
10# ms
20# μs
ns
tdis(E)SR
td(E)S
600#
10#
600#
10
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
32 RECALL Cycle Timer
td(E)R
20#
20
33 Address Setup to Chip Enablet
34 Chip Enable Pulse Widths, t
35 Chip Disable to Address Changet
tsu(A)SR
tw(E)SR
th(A)SR
0#
20#
0#
0#
25#
0#
0#
30#
0#
ns
ns
p: tPDSTORE approximate td(E)S or td(H)S; tDELAY approximate tdis(H)S
q: After tw(H)S HSB is hold down internal by STORE operation.
.
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
t: Noise on the E pad may trigger multiple READ cycles from the same address and abort the address sequence.
Rev 1.0
March 31, 2006
STK Control #ML0049
8
U634H256XS
Software Controlled STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation)
tcR
ADDRESS 6
tcR
(29)
(29)
Ai
E
ADDRESS 1
th(A)SR
tw(E)SR
(34)
(35)
dis(E)(5)
tw(E)SR
(34)
t
tsu(A)SR
(35)
th(A)SR
(33)
(33)
tsu(A)SR
td(E)S
t
(31)
d(E)R (32)
DQi
Output
High Impedance
VALID
tdis(E)SR
VALID
(30)
Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)
tcR
(29)
Ai
E
ADDRESS 1
tw(E)SR
ADDRESS 6
th(A)SR
(35)
(34)
tsu(A)SR
th(A)SR
(35)
(33)
High Impedance
(33)
tsu(A)SR
td(E)S
td(E)R
(31)
(32)
DQi
Output
VALID
VALID
tdis(E)SR (30)
u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at the end
of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256XS performs
a STORE or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
March 31, 2006
STK Control #ML0049
9
Rev 1.0
U634H256XS
Test Configuration for Functional Check
5 V
y
VCCX VCAP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
480
VIH
VIL
VO
30 pF x
HSB
HSB
E
W
G
255
VSS
x: In measurement of tdis-times and ten-times the capacitance is 5 pF.
y: Between VCap and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC
VI
f
= 5.0 V
= VSS
= 1MHz
= 25 °C
Input Capacitance
CI
8
pF
Output Capacitance
CO
7
pF
Ta
All Pads not under test must be connected with ground by capacitors.
Bonding Instructions
The U634H256XS has 31 relevant bond pads and 4 additional pads.
The 4 additional pads must not be bonded.
Refer to the bond pad location and identification table for a complete list of pads and coordinates.
Always both VCAP pads have to be connected.
It is mandatory to use two bond wires on VCAP and VSS doublebond pads for noise immunity.
The backside of the die is connected to VCAP and can be contacted with the substrate in case of the same potential.
In case that automatic STORES should be disabled, the VCCX bond pad has to be connected with VSS potential and
the external VCC has to be connected with VCAP
.
Rev 1.0
March 31, 2006
STK Control #ML0049
10
U634H256XS
Bond pad location and identification table (origin: down left corner)
Pad
x / μm
y / μm
Pad
x / μm
y / μm
A2
A1
135
135
365
175
140
140
140
140
140
140
140
140
140
140
140
140
175
365
8885
9050
9240
VSEF
A9
3505
3275
3085
2875
2685
2405
2165
1740
1576,8
1419,2
1295
1120
910
9410
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9357,5
9125
A0
405
A8
DQ0
DQ1
DQ2
VSS
VSS
VCAP
DQ3
DQ4
DQ5
DQ6
DQ7
E
960
A13
W
1170
1445
1653,2
1810,8
2000
2215
2490
2700
2975
3185
3460
3460
3510
3510
3510
HSB
VCCX
VBND
VCAP
VCAP
VBG
A14
A12
A7
720
A6
510
A10
VSE
G
A5
320
A4
85
A3
85
A11
The pads VSE, VSEF, VBND, VBG must not be bonded.
Applying any signal or voltage to these pads could damage the chip or influence the functionality.
March 31, 2006
STK Control #ML0049
11
Rev 1.0
U634H256XS
A5
HSB
A9
A6 A7 A12 A14 VCAP
A13 A8
W
VCCX
A4
A3
A11
G
Waferdiameter : 125 mm
Waferthickness : (390 ±10) μm
Die size :
(3,73 x 9,62) mm2
(stepping interval)
Bond pad size : (110 x 110) μm2
Passivation
openings :
(100 x 100) μm2
(4 ± 0.5) μm
Polyimid-
passivation :
A2
A1
A10
E
DQ6
DQ7
A0
DQ3 DQ4DQ5
DQ1 DQ2 VSS
DQ0
VCAP
Rev 1.0
March 31, 2006
STK Control #ML0049
12
U634H256XS
Device Operation
STORE operation.
Figure 1 shows the proper connection of capacitors for
automatic STORE operation. The charge storage capa-
citor should have a capacity of 100 μF (± ±20 %) at 6 V.
Each U634H256XS must have its own 100 μF capaci-
tor. Each U634H256XS must have a high quality, high
frequency bypass capacitor of 0.1 μF connected bet-
ween VCAP and VSS, using leads and traces that are
short as possible. This capacitor does not replace the
normal expected high frequency bypass capacitor bet-
ween the power supply voltage VCCX and VSS.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITES have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
The U634H256XS has two separate modes of opera-
tion:SRAM mode and nonvolatile mode. The memory
operates In SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also auto-
matically initiated when the power supply voltage level
of the chip falls below VSWITCH. RECALL operations are
automatically initiated upon power up and may also
occur when the VCCX rises above VSWITCH, after a low
power condition. RECALL cycles may also be initiated
by a software sequence.
SRAM READ
The U634H256XS performs a READ cycle whenever E
and G are LOW and HSB and W are HIGH. The
address specified on pads A0 - A14 determines which
of the 32768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of tcR. If the READ is initiated
Automatic RECALL
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < VSWITCH
)
by E or G, the outputs will be valid at ta(E) or at ta(G)
,
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
whichever is later. The data outputs will repeatedly
respond to address changes within the tcR access time
without the need for transition on any control input
pads, and will remain valid until another address
change or until E or G is brought HIGH or W or HSB is
brought LOW.
VSWITCH, a requested RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the U634H256XS is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
SRAM WRITE
Software Nonvolatile STORE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pads DQ0 - 7 will be written
into the memory if it is valid tsu(D) before the end of a W
controlled WRITE or tsu(D) before the end of an E con-
trolled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
The U634H256XS software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U634H256XS implements nonvolatile opera-
tion while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
Automatic STORE
During normal operation, the U634H256XS will draw
current from VCCX to charge up a capacitor connected
to VCAP . This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the VCCX pad drops below VSWITCH, the part will auto-
matically disconnect VCAP from VCCX and initiate a
To initiate the STORE cycle the following READ
sequence must be performed:
March 31, 2006
STK Control #ML0049
13
Rev 1.0
U634H256XS
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex) Valid READ
31C7 (hex) Valid READ
03E0 (hex) Valid READ
3C1F (hex) Valid READ
303F (hex) Valid READ
0FC0 (hex) Initiate STORE
has been forced LOW, the WRITE will not occur and
the STORE operation will begin immediately.
HARDWARE-STORE-BUSY (HSB) is a high speed,
low drive capability bidirectional control line.
In order to allow a bank of U634H256XSs to perform
synchronized STORE functions, the HSB pad from a
number of chips may be connected together. Each chip
contains a small internal current source to pull HSB
HIGH when it is not being driven LOW. To decrease the
sensitivity of this signal to noise generated on the PC
board, it has to be pulled to power supply via an exter-
nal resistor with a value such that the combined load of
the resistor and all parallel chip connections does not
exceed IHSBOL at VOL (see Figure 1 and 2).
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
If HSB is to be connected to external circuits other than
other U634H256XSs, an external pull-up resistor has to
be used.
Software Nonvolatile RECALL
During any STORE operation, regardless of how it was
initiated, the U634H256XS will continue to drive the
HSB pad LOW, releasing it only when the STORE is
complete.
Upon completion of a STORE operation, the part will be
disabled until HSB actually goes HIGH.
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex) Valid READ
31C7 (hex) Valid READ
03E0 (hex) Valid READ
3C1F (hex) Valid READ
303F (hex) Valid READ
0C63 (hex) Initiate RECALL
Hardware Protection
The U634H256XS offers hardware protection against
inadvertent STORE operation during low voltage condi-
tions. When VCAP < VSWITCH, all software or HSB initia-
ted STORE operations will be inhibited.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Preventing Automatic STORES
The PowerStore function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15 mA at VOH of at least 2.2 V as it will have to overpo-
wer the internal pull-down device that drives HSB LOW
for 50 ns at the onset of a PowerStore.
HSB Nonvolatile STORE
When the U634H256XS is connected for PowerStore
operation (see Figure 1) and VCCX crosses VSWITCH on
the way down, the U634H256XS will attempt to pull
HSB LOW; if HSB doesn′t actually get below VIL, the
part will stop trying to pull HSB LOW and abort the
PowerStore attempt.
The hardware controlled STORE Busy pad (HSB) is
connected to an open drain circuit acting as both input
and output to perform two different functions. When
driven LOW by the internal chip circuitry it indicates that
a STORE operation (initiated via any means) is in pro-
gress within the chip. When driven LOW by external cir-
cuitry for longer than tw(H)S, the chip will conditionally
Disabling Automatic STORES
initiate a STORE operation after tdis(H)S
.
If the PowerStore function is not required, then VCAP
should be tied directly to the power supply and VCCX
should by tied to ground. In this mode, STORE opera-
tion may be triggered through software control or the
HSB pad. In either event, VCAP (Pad 1) must always
have a proper bypass capacitor connected to it
(Figure 2).
READ and WRITE operations that are in progress
when HSB is driven LOW (either by internal or external
circuitry) will be allowed to complete before the STORE
operation is performed, in the following manner.
After HSB goes LOW, the part will continue normal
SRAM operation for tdis(H)S. During tdis(H)S, a transition
on any address or control signal will terminate SRAM
operation and cause the STORE to commence.
Note that if an SRAM WRITE is attempted after HSB
Rev 1.0
March 31, 2006
STK Control #ML0049
14
U634H256XS
Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL
VCAP
5.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Power
Supply
VCAP
VCCX
HSB
VCAP
VCCX
HSB
10 kΩ
Power
Supply
1
1
32
31
30
29
28
27
26
25
24
23
32
31
30
29
28
27
26
25
24
23
(optional,
2
2
mandatory if HSB
is used with
external circuitry)
10 kΩ
3
3
(optional,
4
4
mandatory if HSB
is used with
external circuitry)
5
5
6
6
+
7
7
8
8
100±μF
0.1 μF
0.1 μF
Bypass
9
10
9
10
± ±20% Bypass
11
12
13
14
15
16
22
21
20
19
18
17
11
12
13
14
15
16
22
21
20
19
18
17
VSS
VSS
Figure 1: AUTOMATIC STORE OPERATION
Figure 2: DISABLING AUTOMATIC STORES
Schematic Diagram
Schematic Diagram
Low Average Active Power
The U634H256XS has been designed to draw signifi- 1. CMOS or TTL input levels
cantly less power when E is LOW (chip enabled) but 2. the time during which the chip is disabled (E HIGH)
the access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur- 4. the ratio of READs to WRITEs
rent. 5. the operating temperature
3. the cycle time for accesses (E LOW)
The overall average current drawn by the part depends 6. the power supply voltage level
on the following items:
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
March 31, 2006
STK Control #ML0049
15
Rev 1.0
U634H256XS
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance
upon it. The information in this document describes the type of component and shall not be considered as assu-
red characteristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms
and conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
March 31, 2006
Change record
Date/Rev
Name
Change
01.11.2001 Ivonne Steffens
format revision
22.04.2002 Thomas Wolf
Matthias Schniebel
removing „at least“ for the 100 μF capacitor on page 11 (Automatic
STORE)
04.12.2003 Matthias Schniebel
ICC = 15 mA typ. at 200 ns Cycle Time
Operating Supply Current at tcR = 200 ns: ICC3 = 20 mA
1.0
Simtek
Assigned Simtek Document Control Number
相关型号：
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