U635H16BSK25G1 [CYPRESS]
2KX8 NON-VOLATILE SRAM, 25ns, PDSO24, 0.300 INCH, SOP-24;
| 型号： | U635H16BSK25G1 |
| 厂家： | 
CYPRESS |
| 描述： | 2KX8 NON-VOLATILE SRAM, 25ns, PDSO24, 0.300 INCH, SOP-24 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U635H16
PowerStore 2K x 8 nvSRAM
Description
Features
! High-performance CMOS non-
volatile static RAM 2048 x 8 bits
! 25, 35 and 45 ns Access Times
! 12, 20 and 25 ns Output Enable
Access Times
The U635H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
! ICC = 15 mA at 200 ns Cycle Time operation, data is transferred in
! Automatic STORE to EEPROM
on Power Down using system
capacitance
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
! Software initiated STORE
(STORE Cycle Time < 10 ms)
! Automatic STORE Timing
! 105 STORE cycles to EEPROM
! 10 years data retention in
EEPROM
The U635H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
(EEPROM) element incorporated
in each static memory cell. The
! Automatic RECALL on Power Up SRAM can be read and written an
! Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
! Unlimited RECALL cycles from
EEPROM
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
! Single 5 V ± 10 % Operation
! Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
! QS 9000 Quality Standard
! ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up. The U635H16 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
! Packages:PDIP24 (600 mil)
SOP24 (300 mil)
Pin Description
Pin Configuration
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCC
A8
A9
W
G
Signal Name Signal Description
A0 - A10
DQ0 - DQ7
Address Inputs
Data In/Out
PDIP
SOP
24
A10
E
Chip Enable
E
Output Enable
Write Enable
Power Supply Voltage
Ground
G
W
VCC
VSS
DQ7
DQ6
DQ5
DQ4
DQ3
9
10
11
12
Top View
1
April 20, 2004
U635H16
Block Diagram
EEPROM Array
32 x (64 x 8)
VCC
VSS
STORE
A5
A6
A7
A8
SRAM
RECALL
Power
Array
VCC
Control
32 Rows x
64 x 8 Columns
A9
Store/
Recall
Control
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
Column I/O
Software
Detect
A0 - A10
Column Decoder
G
A0 A1 A2 A3 A4A10
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
High-Z
*
*
H
H
H
L
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of
V
IL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
Output Voltage
VO
PD
Ta
V
Power Dissipation
W
Operating Temperature
C-Type
K-Type
0
70
85
°C
°C
-40
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
April 20, 2004
U635H16
Recommended
Symbol
Conditions
Min.
Max.
Unit
Operating Conditions
Power Supply Voltage
Input Low Voltage
Input High Voltage
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC
VIL
= 5.5 V
= 0.8 V
= 2.2 V
VIH
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
90
80
75
95
85
80
mA
mA
mA
Average Supply Current during
STOREc
ICC2
VCC
E
= 5.5 V
6
7
mA
≤ 0.2 V
W
≥ VCC-0.2 V
≤ 0.2 V
VIL
VIH
≥ VCC-0.2 V
Average Supply Current during
ICC4
VCC
VIL
= 4.5 V
4
4
mA
PowerStore Cyclec
= 0.2 V
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1
VCC
E
= 5.5 V
= VIH
tc
= 25 ns
= 35 ns
= 45 ns
30
23
20
34
27
23
mA
mA
mA
tc
tc
Operating Supply Current
at tcR = 200 nsb
ICC3
VCC
W
= 5.5 V
15
15
mA
≥ VCC-0.2 V
≤ 0.2 V
(Cycling CMOS Input Levels)
VIL
VIH
≥ VCC-0.2 V
Standby Supply Curentd
ICC(SB)
VCC
E
= 5.5 V
3
3
mA
(Stable CMOS Input Levels)
≥ VCC-0.2 V
≤ 0.2 V
VIL
VIH
≥ VCC-0.2 V
b: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c:
ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (STORE Cycle Time).
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
3
April 20, 2004
U635H16
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
8
2.4
8
V
V
0.4
-4
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
1
1
1
µA
µA
=
0 V
-1
-1
-1
-1
Output Leakage Current
VCC
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
µA
µA
=
0 V
SRAM Memory Operations
Symbol
25
35
45
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
tPU
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Zh
25
25
12
13
13
35
35
20
17
17
45
45
25
20
20
G HIGH to Output in High-Zh
tGHQZ
tELQX
E LOW to Output in Low-Z
5
0
3
0
5
0
3
0
5
0
3
0
G LOW to Output in Low-Z
tGLQX
Output Hold Time after Address Change
tAXQX
10 Chip Enable to Power Activee
11 Chip Disable to Power Standbyd, e
tELICCH
tEHICCL
tPD
25
35
45
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
4
April 20, 2004
U635H16
f
=
=
VIL, W = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
tcR
(1)
Ai
Address Valid
ta(A)
(2)
DQi
Previous Data Valid
Output
Output Data Valid
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
(1)
Ai
E
Address Valid
ta(A) (2)
tPD
(11)
(5)
ta(E)
(3)
tdis(E)
ten(E)
(7)
G
ta(G)
(4)
tdis(G)
(6)
ten(G)
(8)
DQi
High Impedance
Output
Output Data Valid
t
PU (10)
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
25
35
45
Switching Characteristics
Write Cycle
No.
Unit
IEC
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
25
20
20
0
35
30
30
0
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tAVWL
tAVWH
tELWH
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
20
20
20
12
0
30
30
30
18
0
35
35
35
20
0
tELEH
tDVEH
tEHDX
tEHAX
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tsu(D)
th(D)
th(A)
0
0
0
tdis(W)
ten(W)
10
13
15
5
5
5
5
April 20, 2004
U635H16
Write Cycle #1: W-controlledj
tcW
(12)
Ai
Address Valid
th(A)
t
(21)
su(E) (17)
E
tsu(A-WH)
(16)
tw(W)
W
(13)
tsu(D)
tsu(A)
(15)
th(D)
(19)
Input Data Valid
ten(W)
(20)
DQi
Input
tdis(W)
(22)
(23)
DQi
High Impedance
Previous Data
Output
Write Cycle #2: E-controlledj
tcW
(12)
Address Valid
tw(E)
Ai
E
tsu(A)
(15)
th(A)
(21)
(20)
(18)
tsu(W) (14)
W
t
th(D)
su(D) (19)
DQi
Input
Input Data Valid
High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
6
April 20, 2004
U635H16
Nonvolatile Memory Operations
Mode Selection
A10 - A0
E
W
Mode
I/O
Power
Notes
(hex)
H
L
L
L
X
H
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
m
H
000
555
2AA
7FF
0F0
70F
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
k, l
k, l
k, l
k, l
k, l
k
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
L
H
000
555
2AA
7FF
0F0
70E
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
k: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA, 7FF,0F0, 70E) for
a RECALL cycle. W must be high during all six consecutive cycles.
See STORE cycle and RECALL cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C.
l: Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤ VIL.
Symbol
PowerStore
No.
Conditions
Min.
Max.
Unit
Power Up RECALL
Alt.
IEC
24 Power Up RECALL Durationn, e
tRESTORE
650
µs
the power supply vol-
tage must stay above
3.6 V at least
25 STORE Cycle Durationf
tPDSTORE
10
ms
10 ms after the start
of the STORE opera-
tion
26 time allowed to Complete SRAM Cyclef, e tDELAY
1
µs
Low Voltage Trigger Level
VSWITCH
4.0
4.5
V
n: tRESTORE starts from the time VCC rises above VSWITCH
.
7
April 20, 2004
U635H16
PowerStore and automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
PowerStore
(25)
p
tPDSTORE
Power Up
RECALL
(24)
(24)
tRESTORE
tRESTORE
W
(26)
tDELAY
DQi
BROWN OUT
NO STORE
(NO SRAM WRITES)
BROWN OUT
PowerStore
POWER UP
RECALL
Symbol
25
35
45
Software Controlled STORE/
No.
Unit
RECALL Cyclek, o
Alt.
IEC
Min. Max. Min. Max. Min. Max.
27 STORE/RECALL Initiation Time
28 Chip Enable to Output Inactivep
29 STORE Cycle Timeq
tAVAV
tELQZ
tcR
25
35
45
ns
ns
ms
µs
ns
ns
ns
tdis(E)SR
td(E)S
600
10
600
10
600
10
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
30 RECALL Cycle Timer
td(E)R
20
20
20
31 Address Setup to Chip Enables
32 Chip Enable Pulse Widths, t
33 Chip Disable to Address Changes
tsu(A)SR
tw(E)SR
th(A)SR
0
20
0
0
25
0
0
35
0
o: The software sequence is clocked with E controlled READs.
p: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
q: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
V
SWITCH once it has been exceeded for the RECALL to function properly.
s: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
t: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
8
April 20, 2004
U635H16
Software Controlled STORE/RECALL Cycles, t, u, v (E = HIGH after STORE initiation)
tcR
tcR
(27)
(27)
ADDRESS 1
ADDRESS 6
Ai
E
th(A)SR
(33)
tdis(E)
tw(E)SR
(32)
tw(E)SR
(32)
t
(31)
tsu(A)SR
(31)
(5)
th(A)SR
(33)
tsu(A)SR
t
d(E)S(30)
d(E)R (29)
DQi
High Impedance
Output
VALID
dis(E)SR (28)
VALID
t
Software Controlled STORE/RECALL Cycles, t, u, v (E = LOW after STORE initiation)
tcR
(27)
ADDRESS 1
Ai
E
ADDRESS 6
th(A)SR
(33)
tw(E)SR
(32)
(31)
tsu(A)SR
tsu(A)SR
High Impedance
(31)
th(A)SR
(33)
t
t
d(E)R (30)
d(E)S (29)
DQi
VALID
VALID
dis(E)SR (28)
Output
t
u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U635H16 performs a STORE
or RECALL.
v: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
9
April 20, 2004
U635H16
Test Configuration for Functional Check
5 V
x
VCC
A0
A1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A2
480
A3
A4
VIH
VIL
A5
A6
A7
A8
A9
A10
VO
30 pF w
E
W
G
255
VSS
w: In measurement of tdis-times and ten-times the capacitance is 5 pF.
x: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC = 5.0 V
Input Capacitance
CI
8
pF
VI
f
= VSS
= 1 MHz
= 25 °C
Output Capacitance
CO
7
pF
Ta
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
U635H16
S
C
25
Type
Leadfree Option
blank= Standard Package
ESD Class
G1 = Leadfree Green Package y
blank > 2000 V
B
> 1000 V
Access Time
25 = 25 ns
Package
35 = 35 ns y
45 = 45 ns y
D = PDIP24 (600 mil)
S = SOP24 (300 mil)
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
y: on special request
Device Marking (example)
ZMD
Product specification
Internal Code
Date of manufacture
U635H16SC
25 Z 0425
G1
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Leadfree Green Package
10
April 20, 2004
U635H16
Device Operation
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
The U635H16 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
Automatic RECALL
During power up an automatic RECALL takes place.
After any low power condition (VCC < VSWITCH) an inter-
nal RECALL request may be latched. When VCC once
again exceeds the sense voltage of VSWITCH, a reque-
sted RECALL cycle will automatically be initiated and
will take tRESTORE to complete.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
If the U635H16 is in a WRITE state at the end of a
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W and system VCC
.
SRAM READ
Software Nonvolatile STORE
The U635H16 performs a READ cycle whenever E and
G are LOW and W are HIGH. The address specified on
pins A0 - A10 determines which of the 2048 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of tcR. If the READ is initiated by E or G, the outputs will
be valid at ta(E) or at ta(G), whichever is later. The data
outputs will repeatedly respond to address changes
within the tcR access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
The U635H16 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U635H16 implements nonvolatile operation
while remaining compatible with standard 2K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
SRAM WRITE
To initiate the STORE cycle the following READ
sequence must be performed:
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
000
555
(hex) Valid READ
(hex) Valid READ
2AA (hex) Valid READ
7FF
0F0
70F
(hex) Valid READ
(hex) Valid READ
(hex) Initiate STORE
t
su(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
Automatic STORE
The U635H16 uses the intrinsic system capacitance to
perform an automatic STORE on power down. As long
as the system power supply take at least tPDSTORE to
decay from VSWITCH down to 3.6 V the U635H16 will
safely and automatically STORE the SRAM data in
EEPROM on power down.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
11
April 20, 2004
U635H16
Software Nonvolatile RECALL
Hardware Protection
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
The U635H16 offers hardware protection against inad-
vertent STORE operation through VCC Sense. When
VCC < VSWITCH all software controllod STORE operati-
ons will be inhibited.
Low Average Active Power
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
000
555
(hex) Valid READ
(hex) Valid READ
The U635H16 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
2AA (hex) Valid READ
7FF
0F0
70E
(hex) Valid READ
(hex) Valid READ
(hex) Initiate RECALL
The overall average current drawn by the part depends
on the following items:
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
12
April 20, 2004
U635H16
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon
it. The information in this document describes the type of component and shall not be considered as assured cha-
racteristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms
and conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
April 20, 2004
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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