UL62H1616AKA35 [CYPRESS]
Standard SRAM, 64KX16, 35ns, CMOS, PBGA48, 6 X 8 MM, BGA-48;
| 型号： | UL62H1616AKA35 |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 64KX16, 35ns, CMOS, PBGA48, 6 X 8 MM, BGA-48 静态存储器 |
| 文件： | 总10页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UL62H1616A
Low Voltage Automotive Fast 64K x 16 SRAM
Features
Description
! 65536 x 16 bit static CMOS RAM
! 15, 20 and 35 ns Access Time
! Common data inputs and
data outputs
The UL62H1616A is a static RAM
change leads to a new Read cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G. If LB = L the data lower byte will
be available at the outputs DQ0-
DQ7, on UB = L the data upper
byte appear at the outputs DQ8-
DQ15. After the address change,
the data outputs go High-Z until the
new information is available. The
data outputs have no preferred
state. The Read cycle is finished by
the falling edge of W, or by the
rising edge of E, respectively.
manufactured using a CMOS pro-
cess technology with the following
operating modes:
! Three-state outputs
- Lower / Upper Byte Read
- Word Read
! Standby current < 150 µA
at 125°C
- Lower / Upper Byte Write
- Word Write
! TTL/CMOS-compatible
! Power supply voltage 3.3 V
! Operating temperature range
K-Type:-40 °C to 85 °C
- Standby
- Data Retention
The memory array is based on a
6-Transistor cell.
A-Type:-40 °C to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity >100 mA
! Package: TSOP II 44 (400 mil)
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L and W = H each address
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Pin Configuration
Pin Description
BGA
A5
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
A6
A7
G
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
Signal Name Signal Description
LB
G
A0
A3
A1
A4
A6
A7
n.c.
A2
E
A0 - A15
Address Inputs
DQ8
UB
DQ0
DQ2
DQ0 - DQ15 Data In/Out
DQ9 DQ10 A5
VSS DQ11 n.c.
VCC DQ12 n.c.
DQ1
Chip Enable
E
E
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
W
A15
A14
A13
A12
n.c.
Output Enable
Write Enable
G
W
DQ3 VCC
9
n.c. DQ4 VSS
UB
LB
VCC
VSS
n.c.
Upper Byte Enable
Lower Byte Enable
Power Supply Voltage
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ14 DQ13 A14 A15 DQ5 DQ6
TSOPII
DQ15 n.c.
n.c. A8
A12 A13
A9 A10
W
DQ7
n.c.
A11
not connected
DQ9
DQ8
Top View
n.c.
A8
A9
A10
A11
n.c.
Top View
April 21, 2004
1
UL62H1616A
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
DQ0
DQ1
DQ2
Memory Cell
Array
512 Rows x
DQ3
DQ4
DQ5
128 x 16 Columns
DQ6
DQ7
A10
A11
A12
A13
DQ8
DQ9
Sense Amplifier/
Write Control Logic
A14
A9
DQ10
DQ11
DQ12
A15
Address
DQ13
DQ14
DQ15
Clock
Change
Detector
Generator
VCC
VSS
E
W
G UB LB
Truth Table
Operating Mode
E
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Standby/not selected
Internal Read
H
L
L
L
L
L
L
L
L
*
H
*
*
H
*
*
*
*
*
High-Z
High-Z
High-Z
High-Z
High-Z
H
L
H
L
L
H
L
H
High-Z
Lower Byte Read
Upper Byte Read
Word Read
H
H
H
L
L
L
L
*
H
L
L
H
L
L
Data Outputs Low-Z
High-Z
High-Z
Data Outputs Low-Z
Data Outputs Low-Z Data Outputs Low-Z
Lower Byte Write
Upper Byte Write
Word Write
Data Inputs High-Z
High-Z
High-Z
L
*
Data Inputs High-Z
Data Inputs High-Z
L
*
Data Inputs High-Z
H or L
*
2
April 21, 2004
UL62H1616A
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
a
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.5
-0.5
-
4.6
VCC + 0.5
VCC + 0.5
1
V
V
b
b
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
°C
K-Type
A-Type
-40
-40
85
125
Storage Temperature
Tstg
-65
150
°C
Output Short-Circuit Current
| IOS
|
100
mA
c
at VCC = 3.3 V and VO = 0 V
a
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b
c
Maximum voltage is 4.6 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Symbol
VCC
Conditions
Min.
3.0
Max.
3.6
Unit
V
Operating Conditions
Power Supply Voltage
Input Low Voltage d
VIL
-0.3
2.0
0.8
V
Input High Voltage
VIH
VCC + 0.3
V
d
-2 V at Pulse Width 10 ns
April 21, 2004
3
UL62H1616A
15
20
35
Electrical Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max. Min. Max.
Supply Current -
Operating Mode
ICC(OP) VCC
= 3.6 V
= 0.8 V
= 2.0 V
= 15 ns
= 20 ns
= 35 ns
= 55 ns
= 70 ns
VIL
VIH
tcW
tcW
tcW
tcW
tcW
65
-
-
-
mA
mA
mA
mA
mA
e
55
40
30
20
55
e
e
e
e
40
30
20
40
e
e
e
30
20
e
Supply Current -
Standby Mode
(CMOS level)
ICC(SB) VCC
VE
K-Type
A-Type
= 3.6 V
= VCC - 0.2 V
1000
1000
1000
1000
100
150
µA
µA
Supply Current -
Standby Mode
(LVTTL level)
ICC(SB)1 VCC
= 3.6 V
= 2.0 V
VE
K-Type
A-Type
1
2
1
2
1
2
mA
mA
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 3.0 V
2.2
2.2
2.2
V
V
= -0.5 mA
= 3.0 V
0.4
2
0.4
2
0.4
2
= 0.5 mA
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 3.6 V
= 3.6 V
= 3.6 V
µA
µA
-2
-2
-2
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 3.0 V
= 2.2 V
= 3.0 V
= 0.4 V
-0.5
2
-0.5
2
-0.5 mA
mA
0.5
0.5
0.5
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 3.6 V
= 3.6 V
= 3.6 V
2
µA
µA
Low at Three-State Outputs
-2
-2
-2
=
0 V
e This parameter is guaranteed, but not tested.
4
April 21, 2004
UL62H1616A
Symbol
15
20
35
Switching Characteristics
Read Cycle
Unit
Min. Max. Min. Max. Min. Max.
Alt.
tRC
tAA
tACE
tOE
IEC
tcR
Read Cycle Time
15
20
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
ta(A)
15
15
7
20
20
9
35
35
15
15
12
12
12
ta(E)
ta(G)
ta(B)
LB, UB LOW to Data Valid
tB
7
9
E HIGH to Output in High-Z
G HIGH to Output in High-Z
LB, UB HIGH to Output in High-Z
E LOW to Output in Low-Z
tHZCE
tHZOE
tHZB
tLZCE
tLZOE
tLZB
tOH
tdis(E)
tdis(G)
tdis(B)
ten(E)
ten(G)
ten(B)
tv(A)
7
8
7
8
7
8
4
0
0
3
0
4
0
0
3
0
5
0
0
3
0
G LOW to Output in Low-Z
LB, UB LOW to Output in Low-Z
Output Hold Time from Address Change
E LOW to Power-Up Time
tPU
E HIGH to Power-Down Time
tPD
15
20
35
Symbol
15
20
35
Switching Characteristics
Write Cycle
Unit
Min. Max. Min. Max. Min. Max.
Alt.
tWC
tWP
IEC
tcW
Write Cycle Time
15
10
10
0
20
12
12
0
35
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
tw(W)
tsu(W)
tsu(A)
Write Setup Time
tWP
Address Setup Time
tAS
t
Address Valid to End of Write
Chip Enable Setup Time
Byte Enable Setup Time
Pulse Width Chip Enable to End of Write
Pulse Width Byte Enable to End of Write
Data Setup Time
tAW
10
10
10
10
10
7
12
12
12
12
12
9
20
25
25
25
25
15
0
su(A-WH)
tCW
tBW
tCW
tBW
tsu(E)
tsu(B)
tw(E)
tw(B)
tDS
tsu(D)
th(D)
Data Hold Time
tDH
0
0
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
tAH
th(A)
0
0
0
tHZWE
tHZOE
tLZWE
tLZOE
tdis(W)
tdis(G)
ten(W)
ten(G)
7
7
8
8
15
12
3
0
3
0
3
0
April 21, 2004
5
UL62H1616A
Data Retention Mode
E - controlled
VCC
3.0 V
VCC(DR) ≥ 1.5 V
2.0 V
2.0 V
tsu(DR)
trec
Data Retention
E
0 V
V
- 0.2 V ≤ V
≤ V
+ 0.3 V
CC(DR)
CC(DR)
E(DR)
Data Retention
Characteristics
Symbol
Conditions
Min. Typ. Max.
Unit
Alt.
IEC
Data Retention Supply Voltage
Data Retention Supply Current
VCC(DR)
1.5
3.6
30
V
ICC(DR) VCC(DR) = 1.5 V
VE = VCC(DR) - 0.2 V
µA
Data Retention Setup Time
Operating Recovery Time
tCDR
tR
tsu(DR) See Data Retention
0
ns
ns
Waveforms (above)
trec
tcR
Test Configuration for Functional Check
3.3 V
A0
VCC
A1
DQ0
DQ1
A2
A3
DQ2
A4
481
A5
DQ3
A6
DQ4
VIH
VIL
A7
DQ5
A8
DQ6
A9
DQ7
A10
A11
A12
A13
A14
A15
DQ8
DQ9
VO
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
30 pF1)
E
W
G
255
LB
UB
VSS
1)
In measurement of t
,t
, t
, t
, t
the capacitance is 5 pF.
dis(E) dis(W) en(E) en(W) en(G)
6
April 21, 2004
UL62H1616A
Capacitance
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
VCC
= 3.3 V
= VSS
CI
7
pF
VI
f
= 1 MHz
= 25 °C
Output Capacitance
Co
7
pF
T
a
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
UL62H1616A
T
A
15
Type
Leadfree Option
blank= Standard Package
G1 = Leadfree Green Package f
Package
T = TSOP II 44 (400 mil)
K = BGA 48 (6 x 8) f
Access Time
15 = 15 ns
20 = 20 ns
35 = 35 ns
Operating Temperature Range
K = -40 to 85 °C
A = -40 to 125 °C
f on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
UL62H1616ATA
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
15
C
0425
G1
Assembly location and
trace code
1 ZZ
Internal Code
Leadfree Green Package
April 21, 2004
7
UL62H1616A
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)
tcR
Ai
Address Valid
ta(A)
DQi
Previous Data Valid
Output Data Valid
Output
tv(A)
Read Cycle 2: G-, E-, LB-, UB-controlled (during Read Cycle: W = VIH)
tcR
Ai
E
Address Valid
ta(E)
tsu(A)
tdis(E)
ten(E)
tdis(G)
ta(G)
G
ten(G)
tdis(B)
ta(B)
LB, UB
ten(B)
DQi
High-Z
tPU
Output Data Valid
Output
tPD
ICC(OP)
ICC(SB)
50 %
50 %
Write Cycle1: W-controlled
tcW
Ai
E
Address Valid
tsu(E)
th(A)
tsu(B)
LB, UB
W
tsu(A-WH)
tw(W)
tsu(A)
tsu(D)
Input Data Valid
ten(W)
th(D)
DQi
Input
tdis(W)
DQi
High-Z
Output
G
8
April 21, 2004
UL62H1616A
Write Cycle 2: E-controlled
tcW
Ai
E
Address Valid
tw(E)
tsu(A)
th(A)
tsu(B)
LB, UB
W
tsu(W)
tsu(D)
th(D)
DQi
Input Data Valid
tdis(W)
Input
ten(E)
High-Z
DQi
Output
tdis(G)
G
Write Cycle 3: LB-, UB-controlled
tcW
Ai
E
Address Valid
tsu(E)
tsu(A)
th(A)
tw(B)
LB, UB
W
tsu(W)
tsu(D)
th(D)
DQi
Input Data Valid
tdis(W)
Input
ten(B)
High-Z
DQi
tdis(G)
Output
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
April 21, 2004
9
UL62H1616A
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
April 21, 2004
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden •P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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