W137 [CYPRESS]

Bx Notebook System Frequency Synthesizer; BX笔记本系统频率合成器


型号：	W137
厂家：	CYPRESS
描述：	Bx Notebook System Frequency Synthesizer BX笔记本系统频率合成器
文件：	总10页 (文件大小：177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W137

Bx Notebook System Frequency Synthesizer

PCI_F, PCI1:5 Output to Output Skew:........................500 ps

Features

PCI_F, PCI1:5 Cycle to Cycle Jitter:............................250 ps

• Maximized EMI suppression using Cypress’s Spread

Spectrum Technology

• Two copies of CPU output

• Six copies of PCI output (Synchronous w/CPU output)

• One 48-MHz output for USB support

• One selectable 24-/48-MHz output

• Two Buffered copies of 14.318-MHz input reference

signal

CPU to PCI Output Skew: ............... 1.5–4.0 ns (CPU Leads)

Output Duty Cycle: .................................................... 45/55%

PCI_F, PCI Edge Rate:.............................................. >1 V/ns

CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#,

PWR_DWN# all have a 250-kΩ pull-up resistor.

Table 1. Pin Selectable Frequency

• Supports 100-MHz or 66-MHz CPU operation

• Power management control input pins

• Available in 28-pin SSOP (209 mils)

• SS function can be disabled

SEL100/66#

CPU

HI-Z

PCI

HI-Z

33.3

Spread%

Don’t Care

See Table 2

0/1

66.6 MHz

100 MHz

• See W40S11-02 for 2 SDRAM DIMM support

Key Specifications

Table 2. Spread Spectrum Feature

SPREAD#

Spread Profile

Supply Voltages: ....................................... V

= 3.3V±5%

= 2.5V±5%

DDQ3

DDQ2

–0.5% (down spread)

0% (spread disabled)

CPU0:1 Output to Output Skew: ................................ 175 ps

CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps

Block Diagram

Pin Configuration

XTAL

OSC

GND

VDDQ3

REF0:1

CPU0:3

REF0/SEL48#

REF1/SPREAD#

VDDQ2

CPU_STOP#

PCI_F

PCI1

CPU0

STOP

Clock

Logic

PCI2

CPU1

GND

VDDQ3

PCI3

GND

PCI_STOP#

VDDQ3

PCI4

PCI5

CPU_STOP#

PWR_DWN#

SEL100/66#

GND

÷2

CPUdiv2_0:1

3V66_0:3

SPREAD#

SEL0

VDDQ3

48MHz

24/48MHz/OE

PLL 1

SEL1

STOP

Clock

Logic

SEL133/100#

÷2/÷1.5

PCI_F

PCI1:7

STOP

Clock

Logic

÷2

PWRDWN#

PCI_STOP#

Power

Down

Logic

÷2

IOAPIC0:2

Three-state

Logic

PLL2

48MHz

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 12, 1999, rev. **

W137

Pin Definitions

No.

Type

Pin Name

Pin Description

CPU0:1

24, 23

CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the

CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to

VDDQ2. Frequency is selected per Table 1.

PCI1:5

5, 6, 9, 10,

PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled

by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied

to VDDQ3. Frequency is selected per Table 1.

PCI_F

Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the

PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage

swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1.

CPU_STOP#

PCI_STOP#

REF0/SEL48#

CPU_STOP# Input: When brought LOW, clock outputs CPU0:1 are stopped LOW

after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,

clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency).

PCI_STOP# Input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH

and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched

on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.

I/O

I/O Dual-Function REF0 and SEL48# Pin: Upon power-up, the state of SEL48# is

latched. The state is set by either a 10K resistor to GND or to V . A 10K resistor to

GND causes pin 14 to provide a 48-MHz clock. If the pin is strapped to V , pin 14

will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that

produces a copy of 14.318 MHz.

REF1/SPREAD#

24/48MHz/OE

I/O

I/O Dual-Function REF1 and SPREAD# Pin: Upon power-up, the state of

SPREAD# is latched. The state is set by either a 10K resistor to GND or to V . A

10K resistor to GND enables Spread Spectrum function. If the pin is strapped to V

Spread Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that

produces a copy of 14.318 MHz.

I/O Dual-Function 24-MHz or 48-MHz Output and Output Enable Input: Upon

power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to

GND or to V . A 10K resistor to GND latches OE LOW, and all outputs are three-

stated. If the pin is strapped to V , OE is latched HIGH and all outputs are active.

After 2 ms, the pin becomes an output whose frequency is set by the state of pin 27

on power-up.

48MHz

SEL100/66#

48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by

voltage applied to VDDQ3.

Frequency Selection Input:Selectpower-up defaultCPU clock frequency as shown

in Table 1.

Crystal Connection or External Reference Frequency Input: This pin can either

be used as a connection to a crystal or to a reference signal.

Crystal Connection: An input connection for an external 14.318-MHz crystal. If

using an external reference, this pin must be left unconnected.

PWR_DWN#

Power Down Control: When this input is LOW, device goes into a low-power standby

condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW

after completing a full clock cycle (2–3 CPU clock cycle latency). When brought

HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency

(3 ms maximum latency).

VDDQ3

VDDQ2

GND

8, 12, 19, 28

Power Connection: Connected to 3.3V.

Power Connection: Power supply for CPU0:1 output buffers. Connected to 2.5V.

Ground Connection: Connect all ground pins to the common system ground plane.

1, 7, 15, 21,

W137

Figure 2 show two suggested methods for strapping resistor

connection.

Overview

The W137 was developed to meet the Intel® Mobile Clock

specification for the BX chipset, including Super I/O and USB

support. The W40S11-02 is the Intel-defined companion part

used for driving 2 SDRAM DIMM modules. Please see that

data sheet for additional information.

Upon W137 power-up, the first 2 ms of operation is used for

input logic selection. During this period, the output buffers are

three-stated, allowing the output strapping resistor on each l/O

pin to pull the pin and its associated capacitive clock load to

either a logic HIGH or logic LOW state. At the end of the 2-ms

period, the established logic 0 or 1 condition of each l/O pin is

then latched. Next, the output buffers are enabled, which con-

verts both l/O pins into operating clock outputs. The 2-ms timer

Cypress’s proprietary spread spectrum frequency synthesis

technique is a feature of the CPU and PCI outputs. When en-

abled, this feature reduces the peak EMI measurements of not

only the output signals and their harmonics, but also of any

other clock signals that are properly synchronized to them.

The –0.5% modulation profile matches that defined as accept-

able in Intel’s clock specification.

is started when V reaches 2.0V. The input latches can only

be reset by turning V off and then back on again.

It should be noted that the strapping resistors have no signifi-

cant effect on clock output signal integrity. The drive imped-

ance of the clock output is <40Ω (nominal) which is minimally

Functional Description

affected by the 10-kΩ strap to ground or V . As with the se-

ries termination resistor, the output strapping resistor should

be placed as close to the l/O pin as possible in order to keep

the interconnecting trace short. The trace from the resistor to

I/O Pin Operation

Pins 14, 26, and 27 are dual-purpose l/O pins. Upon power-up

these pins act as logic inputs, allowing the determination of

assigned device functions. A short time after power-up, the

logic state of each pin is latched and the pins then become

clock outputs. This feature reduces device pin count by com-

bining clock outputs with input select pins.

ground or V should be kept less than two inches in length to

prevent system noise coupling during input logic sampling.

When the clock outputs are enabled following the 2-ms input

period, target (normal) output frequency is delivered assuming

that V has stabilized. If V

has not yet reached full value,

An external 10-kΩ “strapping” resistor is connected between

each l/O pin and ground or V . Connection to ground sets a

latch to “0”, connection to V sets a latch to “1”. Figure 1 and

output frequency initially may be below target but will increase

to target once V voltage has stabilized. In either case, a

short output clock cycle may be produced from the CPU clock

outputs when the outputs are enabled.

Output Strapping Resistor

Series Termination Resistor

10 k

Ω

(Load Option 1)

Clock Load

W137

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10 k

(Load Option 0)

Ω

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

Jumper Options

Output Strapping Resistor

Series Termination Resistor

10 kΩ

Clock Load

W137

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

Data

Latch

Figure 2. Input Logic Selection Through Jumper Option

W137

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

Spread Spectrum Clocking

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the am-

plitudes of the radiated electromagnetic emissions are re-

duced. This effect is depicted in Figure 3.

The output clock is modulated with a waveform depicted in

Figure 4. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is –0.5% of the selected fre-

quency. Figure 4 details the Cypress spreading pattern.

Cypress does offer options with more spread and greater EMI

reduction. Contact your local Sales representative for details

on these devices.

As shown in Figure 3, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is

dB = 6.5 + 9*log (P) + 9*log (F)

Spread Spectrum clocking is activated or deactivated through

I/O pin #26.

EMI Reduction

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX

MIN

Figure 4. Typical Modulation Profile

W137

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-

manent damage to the device. These represent a stress rating

above those specified in the operating sections of this specifi-

cation is not implied. Maximum conditions for extended peri-

ods may affect reliability.

only. Operation of the device at these or any other conditions

Parameter

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

–0.5 to +7.0

–65 to +150

0 to +70

Unit

, V

DD IN

°C

STG

Operating Temperature

Ambient Temperature under Bias

Input ESD Protection

–55 to +125

2 (min.)

ESD

PROT

DC Electrical Characteristics:

T = 0°C to +70°C; V

= 3.3V±5%; V = 2.5V±5%; CPU0:1 = 66.6/100 MHz

DDQ3

DDQ2

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

3.3V Supply Current in Power-down mode

3.3V Supply Current

PWR_DWN# = 0

100

DD3PD

DD3

[1]

Outputs Loaded

[1]

2.5V Supply Current

DD2

2.5V Supply Current in Power-down mode

PWR_DWN# = 0

0.2 µA

DD2PD

Logic Inputs

Input Low Voltage

Input High Voltage

GND – 0.3

0.8

2.0

+ 0.3

[2]

Input Low Current

–25

µA

[2]

Input High Current

Input Low Current (SEL100/66#)

Input High Current (SEL100/66#)

–5

Clock Outputs

Output Low Voltage

Output High Voltage

= 1 mA

PCI_F, PCI1:5,

REF0:1

= –1 mA

3.1

Output High Voltage

Output Low Current:

CPU0:1

= –1 mA

2.2

CPU0:1

= 1.25V

= 1.5V

= 1.25V

= 1.5V

120

110

180

140

PCI_F, PCI1:5

REF0:1

Output High Current

CPU0:1

120

110

180

140

PCI_F, PCI1:5

REF0:1

Crystal Oscillator

X1 Input Threshold Voltage

[3]

VDDQ3 = 3.3V

1.65

[4]

Load Capacitance, As Seen by External Crystal

LOAD

IN,X1

[5]

X1 Input Capacitance

Pin X2 unconnected

Notes:

1. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors.

2. CPU_STOP#, PCI_STOP#, PWR_DWN#, SPREAD#, and SEL48# logic inputs have internal pull-up resistors (not CMOS level).

3. X1 input threshold voltage (typical) is V_DD/2.

4. The W137 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is

14 pF; this includes typical stray capacitance of short PCB traces to crystal.

5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

W137

DC Electrical Characteristics: (continued)

T = 0°C to +70°C; V

= 3.3V±5%; V = 2.5V±5%; CPU0:1 = 66.6/100 MHz

DDQ3

DDQ2

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Pin Capacitance/Inductance

Input Pin Capacitance

Except X1 and X2

Output Pin Capacitance

Input Pin Inductance

OUT

AC Electrical Characteristics

T = 0°C to +70°C; V

= 3.3V±5%; V

= 2.5V±5%; f

= 14.31818 MHz

XTL

DDQ3

DDQ2

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output.

CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)

CPU = 66.6 MHz

CPU = 100 MHz

Parameter

Description

Period

Test Condition/Comments

Measured on rising edge at 1.25V

Duration of clock cycle above 2.0V

Duration of clock cycle below 0.4V

Min. Typ. Max. Min. Typ. Max. Unit

5.2

5.0

15.5

3.0

2.8

10.5

High Time

Low Time

Output Rise Edge Rate Measured from 0.4V to 2.0V

Output Fall Edge Rate Measured from 2.0V to 0.4V

V/ns

Duty Cycle

Measured on rising and falling edge at

1.25V

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.25V. Max-

imum difference of cycle time between

two adjacent cycles.

200

Output Skew

Measured on rising edge at 1.25V

175

FrequencyStabilization Assumes full supply voltage reached

from Power-up (cold

start)

within 1 ms from power-up. Shortcycles

exist prior to frequency stabilization.

AC Output Impedance Average value during switching transi-

tion. Used for determining series termi-

nation value.

13.5

Ω

W137

PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF)

CPU = 66.6/100 MHz

Parameter

Description

Period

Test Condition/Comments

Measured on rising edge at 1.5V

Duration of clock cycle above 2.4V

Duration of clock cycle below 0.4V

Min.

Typ.

Max.

Unit

High Time

Low Time

12.0

Output Rise Edge Rate Measured from 0.4V to 2.4V

Output Fall Edge Rate Measured from 2.4V to 0.4V

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

250

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum differ-

ence of cycle time between two adjacent cycles.

Output Skew

Measured on rising edge at 1.5V

500

4.0

CPU to PCI Clock

Offset

Covers all CPU/PCI outputs. Measured on rising

edge at 1.5V. CPU leads PCI output.

1.5

Frequency Stabiliza-

tion from Power-up

(cold start)

Assumes full supply voltage reached within 1 ms

from power-up. Short cycles exist prior to frequency

stabilization.

AC Output Impedance Average value during switching transition. Used for

determining series termination value.

Ω

REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 66.6/100 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Determined by crystal oscillator frequency

Measured from 0.4V to 2.4V

Min.

Typ.

Max.

Unit

MHz

V/ns

14.318

0.5

Measured from 2.4V to 0.4V

Measured on rising and falling edge at 1.5V

Frequency Stabilization

Assumes full supply voltage reached within

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

AC Output Impedance

Average value during switching transition.

Ω

Used for determining series termination value.

W137

48-MHz and 24-MHz Clock Outputs (Lump Capacitance Test Load = 20 pF)

CPU = 66.6/100 MHz

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Determined by PLL divider ratio (see n/m below)

48.008

24.004

MHz

Deviation from 48 MHz

PLL Ratio

(48.008 – 48)/48

+167

ppm

m/n

(14.31818 MHz x 57/17 = 48.008 MHz)

Measured from 0.4V to 2.4V

57/17, 57/34

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

0.5

V/ns

Measured from 2.4V to 0.4V

Measured on rising and falling edge at 1.5V

Assumes full supply voltage reached within 1 ms

Frequency Stabilization

from Power-up (cold start) from power-up. Short cycles exist prior to

frequency stabilization.

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

Ω

Ordering Information

Package

Name

Ordering Code

Package Type

28-pin SSOP (209 mils)

28-pin TSSOP (173 mils)

W137

Intel is a registered trademark of Intel Corporation.

Document #: 38-00821

W137

Package Diagrams

28-Pin Thin Small Shrink Outline Package (TSSOP, 173 mils)

W137

Package Diagrams (continued)

28-Pin Small Shrink Outline Package (SSOP, 209 mils)

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

W137 [CYPRESS]

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