W144H_技术文档

W144

440BX AGPset Spread Spectrum Frequency Synthesizer

Features

Table 1. Pin Selectable Frequency

Input Address

FS3 FS2 FS1 FS0

• Maximized electromagnetic interference (EMI)

suppression using Cypress’ Spread Spectrum

technology

• Single chip system frequency synthesizer for Intel^®

440BX AGPset

CPU_F, CPU1

(MHz)

PCI_F, 1:5 (MHz)

33.4 (CPU/4)

31 (CPU/4)

37.5 (CPU/4)

35 (CPU/4)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

133.6

124

150

140

105

110

• Two copies of CPU output

• Six copies of PCI output 1

• One 48-MHz output for USB

• One 24-MHz output for SIO

• Two buffered reference outputs

• One IOAPIC output

35 (CPU/3)

36.7 (CPU/3)

38.3 (CPU/3)

40 (CPU/3)

115

120

100.2

133.3

112

103

66.8

83.3

75

33.4 (CPU/3)

44.43 (CPU/3)

37.3 (CPU/3)

34.3 (CPU/3)

33.4 (CPU/2)

41.7 (CPU/2)

37.5 (CPU/2)

41.3 (CPU/3)

• Thirteen SDRAM outputs provide support for three

DIMMs

• Supports frequencies up to 150 MHz

• I²C interface for programming

• Power management control inputs

124

Pin Configuration^[1]

Logic Block Diagram

VDDQ3

REF0/(PCI_STOP#)

GND

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

VDDQ2

1

REF0/(PCI_STOP#)

REF1/FS2

IOAPIC

2

REF1/FS2*

GND

CPU_F

CPU1

VDDQ2

CLK_STOP#

SDRAM_F

GND

SDRAM0

SDRAM1

VDDQ3

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDDQ3

3

X1

X2

XTAL

OSC

X1

4

PLL Ref Freq

X2

5

VDDQ2

IOAPIC

VDDQ3

PCI_F/MODE

**PCI1/FS3

GND

6

Stop

Clock

I/O Pin

Control

7

Control

8

9

PCI2

PCI3

PCI4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

CLK_STOP#

VDDQ2

Stop

Clock

Control

CPU1

PCI5

PLL 1

÷2,3,4

VDDQ3

SDRAMIN

GND

CPU_F

VDDQ3

PCI_F/MODE

PCI1/FS3

PCI2

SDRAM11

SDRAM10

VDDQ3

SDRAM9

SDRAM8

GND

Stop

Clock

SDRAM6

SDRAM7

VDDQ3

48MHz/FS0*

24MHz/FS1*

PCI3

Control

PCI4

PCI5

2

SDATA

I C

{

2

SDATA

SCLK

I C

Logic

SCLK

VDDQ3

48MHz/FS0

PLL2

÷2

24MHz/FS1

VDDQ3

Stop

Clock

Control

SDRAMIN

SDRAM0:11

12

SDRAM_F

Note:

1. * Has an internal pull-up resistors. It should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping

while ** has an internal pull down resistor.

Cypress Semiconductor Corporation

Document #: 38-07153 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 16, 2004

W144

Pin Description

Pin Name

No.

Type

Description

CPU_F

44

O

Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to

VDDQ2. See Tables 1 and 6 for detailed frequency information.

CPU1

43

O

CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control

pin. Output voltage swing is controlled by voltage applied to VDDQ2.

PCI2:5

10, 11, 12,

13

PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the

PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3.

PCI1/FS3

8

I/O

Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through

serial input interface, see Tables 1 and 6. This output is affected by the PCI_STOP# input.

When an input, latches data selecting the frequency of the CPU and PCI outputs.

PCI_F/MODE

CLK_STOP#

7

I/O

I

Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through

serial input interface, see Tables 1 and 6. This output is not affected by the PCI_STOP#

input. When an input, sets function of pin 2.

41

CLK_STOP# input: When brought LOW, affected clock outputs are stopped LOW after

completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected clock

outputs start, beginning with a full clock cycle (2–3 CPU clock latency).

IOAPIC

47

26

O

IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing

is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW.

48MHz/FS0

I/O

48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output

can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will

be latched, which will set clock frequencies as described in Table 1.

24MHz/FS1

REF1/FS2

25

46

2

I/O

24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output

can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be

latched, which will set clock frequencies as described in Table 1.

I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched, which

will set clock frequencies as described in Table 1. When an output, this pin provides a

fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins.

REF0/

(PCI_STOP#)

Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.

The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to

remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F.

Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a

fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins.

SDRAMIN

15

I

Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs

(SDRAM0:11, SDRAM_F).

SDRAM0:11

38, 37, 35,

34, 32, 31,

29, 28, 21,

20, 18, 17

O

Buffered Outputs: These twelve dedicated outputs provide copies of the signal provided

at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when

CLK_STOP# input is set LOW.

SDRAM_F

40

O

Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN

input which is not affected by the CLK_STOP# input

SCLK

SDATA

X1

24

23

4

I

I/O

I

Clock pin for I²C Circuitry

Data pin for I²C Circuitry

Crystal Connection or External Reference Frequency Input: This pin has dual

functions. It can be used as an external 14.318-MHz crystal connection or as an external

reference frequency input.

X2

5

I

Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an

external reference, this pin must be left unconnected.

VDDQ3

1, 6, 14,

19, 27, 30,

36

P

Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI

outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply.

VDDQ2

GND

42, 48

P

Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers.

Connect to 2.5V or 3.3V.

3, 9, 16,

22, 33, 39,

45

G

Ground Connections: Connect all ground pins to the common system ground plane.

Document #: 38-07153 Rev. *B

Page 2 of 14

W144

nation of assigned device functions. A short time after

power-up, the logic state of each pin is latched and the pins

become clock outputs. This feature reduces device pin count

by combining clock outputs with input select pins.

Key Specifications

CPU Cycle-to-Cycle Jitter: ......................................... 250 ps

CPU to CPU Output Skew: ........................................ 175 ps

PCI to PCI Output Skew: ............................................ 500 ps

V_DDQ3:..................................................................... 3.3V±5%

V_DDQ2:..................................................................... 2.5V±5%

SDRAMIN to SDRAM0:11 Delay: ......................... 3.7 ns typ.

SDRAM0:11 (leads) to SDRAM_F Skew: ............. 0.4 ns typ.

Table 2. Mode Input Table

An external 10-kΩ “strapping” resistor is connected between

the l/O pin and ground or V_DD. Connection to ground sets a

latch to “0,” connection to V_DDsets a latch to “1.” Figure 1 and

Figure 2 show two suggested methods for strapping resistor

connections.

Upon W144 power up, the first 2 ms of operation is used for

input logic selection. During this period, the five I/O pins (7, 8,

25, 26, 46) are three-stated, allowing the output strapping

resistor on the l/O pins to pull the pin and their associated

capacitive clock load to either a logic HIGH or LOW state. At

the end of the 2ms period, the established logic “0” or “1”

condition of the l/O pin is latched. Next the output buffer is

enabled converting the l/O pins into operating clock outputs.

The 2-ms timer starts when VDD reaches 2.0V. The input bits

can only be reset by turning VDD off and then back on again.

Mode

Pin2

0

1

PCI_STOP#

REF0

Overview

It should be noted that the strapping resistors have no signif-

icant effect on clock output signal integrity. The drive

impedance of clock outputs are <40Ω (nominal) which is

minimally affected by the 10-kΩ strap to ground or V_DD. As

with the series termination resistor, the output strapping

resistor should be placed as close to the l/O pin as possible in

order to keep the interconnecting trace short. The trace from

the resistor to ground or V_DDshould be kept less than two

inches in length to prevent system noise coupling during input

logic sampling.

The W144 was developed as a single-chip device to meet the

clocking needs of the Intel 440BX AGPset. In addition to the

typical outputs provided by standard 100-MHz 440BX FTGs,

the W144 adds a thirteen output buffer, supporting SDRAM

DIMM modules in conjunction with the chipset.

Cypress’s proprietary spread spectrum frequency synthesis

technique is a feature of the CPU and PCI outputs. When

enabled, this feature reduces the peak EMI measurements of

not only the output signals and their harmonics, but also of any

other clock signals that are properly synchronized to them.

When the clock outputs are enabled following the 2-ms input

period, the specified output frequency is delivered on the pin,

assuming that V_DDhas stabilized. If V_DDhas not yet reached

full value, output frequency initially may be below target but will

increase to target once V_DDvoltage has stabilized. In either

case, a short output clock cycle may be produced from the

CPU clock outputs when the outputs are enabled.

Functional Description

I/O Pin Operation

Pins 7, 8, 25, 26, and 46 are dual-purpose l/O pins. Upon

power-up these pins act as logic inputs, allowing the determi-

V

DD

Output Strapping Resistor

Series Termination Resistor

10 k

Ω

(Load Option 1)

Clock Load

W144

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10 k

Ω

(Load Option 0)

Q

D

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

Document #: 38-07153 Rev. *B

Page 3 of 14

W144

Jumper Options

Output Strapping Resistor

Series Termination Resistor

V

DD

10 k

Ω

Clock Load

W144

R

Output

Buffer

Power-on

Reset

Timer

Resistor Value R

Hold

Output

Low

Output Three-state

Q

D

Data

Latch

Figure 2. Input Logic Selection Through Jumper Option

Spread Spectrum clocking is activated or deactivated by

selecting the appropriate values for bits 1–0 in data byte 0 of

the I²C data stream. Refer to Table 7 for more details.

Spread Spectrum Feature

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the ampli-

tudes of the radiated electromagnetic emissions are reduced.

This effect is depicted in Figure 3.

5dB/div

SSFTG

Typical Clock

As shown in Figure 3, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is

dB = 6.5 + 9*log10(P) + 9*log10(F)

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in

Figure 4. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is specified in Table 7. Figure 4

details the Cypress spreading pattern. Cypress does offer

options with more spread and greater EMI reduction. Contact

your local Sales representative for details on these devices.

Frequency Span (MHz)

-S- S%

+SS%

Figure 3. Clock Harmonic with and without SSCG

Modulation Frequency Domain Representation

MAX (+0.5%)

MIN (–0.5%)

Figure 4. Typical Modulation Profile

Document #: 38-07153 Rev. *B

Page 4 of 14

W144

Operation

Serial Data Interface

Data is written to the W144 in eleven bytes of eight bits each.

Bytes are written in the order shown in Table 4.

The W144 features a two-pin, serial data interface that can be

used to configure internal register settings that control

particular device functions. Upon power-up, the W144

initializes with default register settings, therefore the use of this

serial data interface is optional. The serial interface is

write-only (to the clock chip) and is the dedicated function of

device pins SDATA and SCLOCK. In motherboard applica-

tions, SDATA and SCLOCK are typically driven by two logic

outputs of the chipset. Clock device register changes are

normally made upon system initialization, if any are required.

The interface can also be used during system operation for

power management functions. Table 3 summarizes the control

functions of the serial data interface.

Table 3. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Clock Output Disable

Any individual clock output(s) can be disabled.

Disabled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI

andsystem power. Examples are clock outputs

to unused PCI slots.

CPU Clock Frequency

Selection

Provides CPU/PCI frequency selections through

software. Frequency is changed in a smooth and

controlled fashion.

For alternate microprocessors and power

management options. Smooth frequency

transition allows CPU frequency change under

normal system operation.

Spread Spectrum

Enabling

Enables or disables spread spectrum clocking.

For EMI reduction.

Output Three-state

(Reserved)

Puts clock output into a high-impedance state.

Production PCB testing.

Reserved function for future device revision or

production device testing.

No user application. Register bit must be

written as 0.

Table 4. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

1

Slave Address

11010010

Commands the W144 to accept the bits in Data Bytes 0–6 for internal

register configuration. Since other devices may exist on the same

common serial data bus, it is necessary to have a specific slave address

for each potential receiver. The slave receiver address for the W144 is

11010010. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver).

2

3

Command Code

Byte Count

Don’t Care

Unused by the W144, therefore bit values are ignored (“don’t care”). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Command Code Byte is part of the standard serial

communication protocol and may be used when writing to another

addressed slave receiver on the serial data bus.

Unused by the W144, therefore bit values are ignored (“don’t care”). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Byte Count Byte is part of the standard serial communi-

cation protocolandmay be used whenwritingto anotheraddressed slave

receiver on the serial data bus.

Document #: 38-07153 Rev. *B

Page 5 of 14

W144

Table 4. Byte Writing Sequence (continued)

Byte

Sequence

Byte Name

Data Byte 0

Bit Sequence

Byte Description

4

5

Refer to Table 5

The data bits in Data Bytes 0–7 set internal W144 registers that control

device operation. The data bits are only accepted when the Address Byte

bit sequence is 11010010, as noted above. For description of bit control

functions, refer to Table 5, Data Byte Serial Configuration Map.

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

6

7

8

9

10

11

Writing Data Bytes

Table 6 details additional frequency selections that are

available through the serial data interface.

Each bit in Data Bytes 0–7 controls a particular device function

except for the “reserved” bits, which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit 7.

Table 5 gives the bit formats for registers located in Data Bytes

0–7.

Table 7 details the select functions for Byte 0, bits 1 and 0.

Table 5. Data Bytes 0-7 Serial Configuration Map

Affected Pin

Bit Control

Bit(s)

Pin No.

Pin Name

Control Function

0

1

Default

Data Byte 0

7

6

–

(Reserved)

SEL_2

–

0

–

See Table 6

5

SEL_1

0

4

SEL_0

0

3

Hardware/Software Frequency Select

SEL_3

Hardware

Software

0

2

See Table 6

0

1–0

Bit 1Bit 0Function (See Table 7 for function details)

00Normal Operation

00

01(Reserved)

10Spread Spectrum On

11All Outputs Three-stated

Data Byte 1

7

6

5

4

3

2

1

0

–

(Reserved)

–

0

1

0

1

–

(Reserved)

–

(Reserved)

–

(Reserved)

–

40

–

SDRAM_F

–

Clock Output Disable

(Reserved)

Low

–

Active

–

43

44

CPU1

CPU_F

Clock Output Disable

Low

Active

Document #: 38-07153 Rev. *B

Page 6 of 14

W144

Data Byte 2

7

6

5

4

3

2

1

0

–

7

–

(Reserved)

–

0

1

0

1

PCI_F

–

Clock Output Disable

(Reserved)

Low

–

Active

–

13

12

11

10

8

PCI5

PCI4

PCI3

PCI2

PCI1

Clock Output Disable

Low

Active

Data Byte 3

7

6

5

4

3

–

(Reserved)

–

0

1

0

1

(Reserved)

–

26

25

–

48MHz

24MHz

–

Clock Output Disable

(Reserved)

Low

–

Active

–

2

1

0

21, 20,

18, 17

SDRAM8:11 Clock Output Disable

Low

Active

32, 31,

29, 28

SDRAM4:7

SDRAM0:3

Clock Output Disable

Low

Active

1

38, 37,

35, 34

Data Byte 4

7

6

5

4

3

2

1

0

–

(Reserved)

–

0

Data Byte 5

7

6

5

4

3

2

1

0

–

(Reserved)

–

0

1

0

1

–

(Reserved)

–

(Reserved)

–

47

–

IOAPIC

–

Clock Output Disable

(Reserved)

Low

–

Active

–

(Reserved)

–

46

2

REF1

REF0

Clock Output Disable

Low

Active

Data Byte 6

7

6

5

4

3

–

(Reserved)

–

0

Document #: 38-07153 Rev. *B

Page 7 of 14

W144

Data Byte 6 (continued)

2

1

0

–

(Reserved)

–

0

Data Byte 7

7

6

5

4

3

2

1

0

–

(Reserved)

–

0

Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes^[2]

Input Conditions

Output Frequency

Data Byte 0, Bit 3 = 1

Bit 2

Bit 6

Bit 5

Bit 4

CPU, SDRAM Clocks PCI Clocks

SEL_3

SEL_2

SEL_1

SEL_0

(MHz)

133.6

124

150

140

105

110

(MHz)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

33.4 (CPU/4)

31 (CPU/4)

37.5 (CPU/4)

35 (CPU/4)

35 (CPU/3)

36.7 (CPU/3)

39.3 (CPU/3)

40 (CPU/3)

115

120

100.2

133

112

33.4 (CPU/3)

44.3 (CPU/3)

37.3 (CPU/3)

34.3 (CPU/3)

33.4 (CPU/2)

41.7 (CPU/2)

37.5 (CPU/2)

41.3 (CPU/3)

103

66.8

83.3

75

124

Table 7. Select Function for Data Byte 0, Bits 0:1

Input Conditions

Data Byte 0

Output Conditions

CPU_F,

PCI_F,

PCI1:5

REF0:1,

IOAPIC

Function

Bit 1

Bit 0

CPU1

Note 1

±0.5%

Hi-Z

48MHZ

24MHZ

24 MHz

Hi-Z

Normal Operation

Spread Spectrum

0

1

0

1

Note 1

±0.5%

Hi-Z

14.318 MHz

Hi-Z

48 MHz

Hi-Z

Three-state

Note:

2. CPU and PCI frequency selections are listed in Table 1 and Table 6.

Document #: 38-07153 Rev. *B

Page 8 of 14

W144

Absolute Maximum Conditions^[3]

rating only. Operation of the device at these or any other condi-

tions above those specified in the operating sections of this

specification is not implied. Maximum conditions for extended

periods may affect reliability.

Stresses greater than those listed in this table may cause

permanent damage to the device. These represent a stress

Parameter

V_DD, V_IN

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

–0.5 to +7.0

–65 to +150

–55 to +125

0 to +70

Unit

V

T_STG

T_B

°C

kV

Ambient Temperature under Bias

Operating Temperature

T_A

ESD_PROT

Input ESD Protection

2 (min)

DC Electrical Characteristics T_A= 0°C to +70°C; V_DDQ3= 3.3V±5%; V_DDQ2= 2.5V±5%

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

I_DD

Logic Inputs

3.3V Supply Current

CPU_F, CPU1 = 100.2 MHz

Outputs Loaded^[4]

–

260

25

–

mA

2.5V Supply Current

CPU_F, CPU1 = 100.2 MHz

Outputs Loaded^[4]

V_IL

Input Low Voltage

Input High Voltage

GND –

0.3

–

0.8

V

V_IH

2.0

V_DDQ3

0.3

+

I_IL

I_IH

I_IL

I_IH

Input Low Current^[5]

Input High Current^[5]

–

–25

10

µA

Input Low Current (SEL100/66#)

Input High Current (SEL100/66#)

–5

+5

Clock Outputs

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 1 mA

I_OH= 1 mA

I_OH= –1 mA

–

50

–

mV

V

3.1

2.2

Output High Voltage CPU_F,1,

IOAPIC

–

V

I_OL

Output Low Current

CPU_F, CPU1 V_OL= 1.25V

PCI_F, PCI1:5 V_OL= 1.5V

27

20.5

40

25

31

40

27

25

57

53

85

37

55

87

44

37

97

139

140

76

mA

IOAPIC

REF0:1

48MHz

24MHz

V_OL= 1.25V

V_OL= 1.5V

76

I_OH

Output High Current CPU_F, CPU1 V_OH= 1.25V

PCI_F, PCI1:5 V_OH= 1.5V

97

139

155

94

IOAPIC

REF0:1

48MHz

24MHz

V_OH= 1.25V

V_OH= 1.5V

94

76

Notes:

3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

4. All clock outputs loaded with 6" 60Ω traces with 22-pF capacitors.

5. W144 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.

Document #: 38-07153 Rev. *B

Page 9 of 14

W144

DC Electrical Characteristics T_A= 0°C to +70°C; V_DDQ3= 3.3V±5%; V_DDQ2= 2.5V±5% (continued)

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Crystal Oscillator

V_TH

X1 Input threshold Voltage^[6]

V_DDQ3= 3.3V

–

1.65

14

–

V

C_LOAD

Load Capacitance, Imposed on

External Crystal^[7]

pF

C_IN,X1

X1 Input Capacitance^[8]

Pin X2 unconnected

Except X1 and X2

–

28

–

pF

Pin Capacitance/Inductance

C_INInput Pin Capacitance

–

5

6

7

pF

nH

C_OUT

L_IN

Output Pin Capacitance

Input Pin Inductance

AC clock parameters are tested and guaranteed over stated

operating conditions using the stated lump capacitive load at

the clock output; Spread Spectrum clocking is disabled.

AC Electrical Characteristics

T_A= 0°C to +70°C; V_DDQ3= 3.3V±5%; V_DDQ2= 2.5V±5%;

f_XTL= 14.31818 MHz

CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF)

CPU = 66.6 MHz CPU = 100.2 MHz

Parameter

t_P

Description

Period

Test Condition/Comments

Measured on rising edge at 1.25

Duration of clock cycle above 2.0V

Duration of clock cycle below 0.4V

Min. Typ. Max. Min. Typ. Max. Unit

15

5.6

5.3

1.5

–

15.5 9.98

–

10.5

–

ns

t_H

t_L

High Time

Low Time

–

3.3

3.1

1.5

45

–

ns

t_R

t_F

t_D

Output Rise Edge Rate Measured from 0.4V to 2.0V

Output Fall Edge Rate Measured from 2.0V to 0.4V

4

V/ns

%

4

Duty Cycle

Measured on rising and falling edge at 45

1.25V

55

t_JC

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.25V.

Maximum difference of cycle time

between two adjacent cycles.

–

200

–

200

ps

t_SK

f_ST

Output Skew

Measured on rising edge at 1.25V

–

250

3

250

3

ps

Frequency Stabilization Assumes full supply voltage reached

from Power-up (cold

start)

–

ms

within 1 ms from power-up. Short cycles

exist prior to frequency stabilization.

Z_o

AC Output Impedance Average value during switching

transition. Used for determining series

termination value.

–

20

–

20

–

Ω

Notes:

6. X1 input threshold voltage (typical) is V_DDQ3/2.

7. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;

this includes typical stray capacitance of short PCB traces to crystal.

8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

Document #: 38-07153 Rev. *B

Page 10 of 14

W144

SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)

CPU = 66.6 MHz

CPU = 100.2 MHz

Parameter

t_P

t_H

Description

Period

Test Condition/Comments

Min.

Typ. Max. Min. Typ. Max. Unit

Measured on rising edge at 1.5V

30

–

30

–

ns

High Time

Duration of clock cycle above 2.4V, 5.6

at min. edge rate (1.5V/ns)

3.3

t_L

Low Time

Duration of clock cycle below 0.4V,

at min. edge rate (1.5V/ns

5.3

–

4

3.1

1.5

–

4

ns

t_R

Output Rise Edge

Rate

Measured from 0.4V to 2.4V

1.5

V/ns

t_F

Output Fall Edge Rate Measured from 2.4V to 0.4V

1.5

1

–

4

5

1.5

1

–

4

5

V/ns

ns

t_PLH

t_PHL

t_D

Prop Delay LH

Prop Delay HL

Duty Cycle

Input edge rate faster than 1V/ns

Input edge rate faster than 1 V/ns

1

5

1

5

ns

Measuredon rising and fallingedge

at 1.5V,at min. edge rate (1.5 V/ns)

45

55

45

55

%

t_JC

Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V.

Maximum difference of cycle time

–

250

–

250

ps

between two adjacent cycles.

t_SK

t_O

Output Skew

Measured on rising edge at 1.5V

–

250

4

–

250

4

ps

ns

CPU to PCI Clock

Skew

Covers all CPU/PCI outputs.

Measured on rising edge at 1.5V.

CPU leads PCI output.

1.5

f_ST

Frequency

Stabilization from

Power-up (cold start) Short cycles exist prior to frequency

stabilization.

Assumes full supply voltage

reachedwithin1msfrom power-up.

–

3

–

3

–

ms

Z_o

AC Output

Impedance

Average value during switching

transition. Used for determining

series termination value.

30

Ω

PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)

CPU = 66.6/100.2 MHz

Parameter

t_P

Description

Test Condition/Comments

Measured on rising edge at 1.5V

Duration of clock cycle above 2.4V

Duration of clock cycle below 0.4V

Measured from 0.4V to 2.4V

Min.

29.9

12.0

1

Typ.

–

Max.

Unit

ns

Period

–

t_H

t_L

High Time

–

ns

Low Time

–

ns

t_R

t_F

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

–

4

V/ns

%

Measured from 2.4V to 0.4V

1

–

4

t_D

t_JC

Measured on rising and falling edge at 1.5V

45

–

55

250

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum

difference of cycle time between two

adjacent cycles.

–

ps

t_SK

t_O

Output Skew

Measured on rising edge at 1.5V

–

500

4.0

ps

ns

CPU to PCI Clock Skew

Covers all CPU/PCI outputs. Measured on

rising edge at 1.5V. CPU leads PCI output.

1.5

f_ST

Frequency Stabilization

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior

to frequency stabilization.

Assumes full supply voltage reached within

–

3.0

–

ms

Z_o

AC Output Impedance

Average value during switching transition.

Used for determining series termination

value.

30

Ω

Document #: 38-07153 Rev. *B

Page 11 of 14

W144

IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 66.6/100.2 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.0V

Min.

Typ.

Max.

Unit

MHz

V/ns

%

f

14.31818

t_R

1

–

4

t_F

Measured from 2.0V to 0.4V

t_D

Measured on rising and falling edge at 1.25V

Assumes full supply voltage reached within

45

–

55

1.5

f_ST

Frequency Stabilization

ms

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z_o

AC Output Impedance

Average value during switching transition.

Used for determining series termination value.

–

15

–

Ω

REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 66.6/100.2 MHz

Parameter

Description

Test Condition/Comments

Min.

Typ.

14.318

–

Max. Unit

f

Frequency, Actual

Frequency generated by crystal oscillator

MHz

t_R

Output Rise Edge Rate Measured from 0.4V to 2.4V

0.5

45

–

2

V/ns

%

–

t_F

Output Fall Edge Rate

Duty Cycle

Measured from 2.4V to 0.4V

t_D

Measured on rising and falling edge at 1.5V

–

55

3

f_ST

Frequency Stabilization Assumes full supply voltage reached within 1 ms from

ms

from Power-up (cold

start)

power-up. Short cycles exist prior to frequency stabili-

zation.

Z_o

AC Output Impedance

Average value during switching transition. Used for

determining series termination value.

–

40

–

Ω

48-MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz

CPU = 66.6/100.2 MHz

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

MHz

ppm

f

Frequency, Actual

Determined by PLL divider ratio (see p/q below)

–48.008–

f_D

Deviation from 48 MHz (48.008 – 48)/48

+167

p/q

t_R

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

–57/17

Output Rise Edge Rate Measured from 0.4V to 2.4V

Output Fall Edge Rate Measured from 2.4V to 0.4V

0.5

45

–

2

V/ns

%

t_F

t_D

Duty Cycle

Measured on rising and falling edge at 1.5V

55

3

f_ST

FrequencyStabilization Assumes full supply voltage reached within 1 ms from

ms

from Power-up (cold

start)

power-up. Short cycles exist prior to frequency stabili-

zation.

Z_o

AC Output Impedance Average value during switching transition. Used for

determining series termination value.

–

40

–

Ω

24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz

CPU = 66.6/100.2 MHz

Parameter

Description

Test Condition/Comments

Min.

Typ.

24.004

+167

57/34

–

Max.

Unit

MHz

ppm

f

Frequency, Actual

Determined by PLL divider ratio (see p/q below)

f_D

Deviation from 24 MHz (24.004 – 24)/24

p/q

t_R

PLL Ratio

(14.31818 MHz x 57/34 = 24.004 MHz)

Output Rise Edge Rate Measured from 0.4V to 2.4V

Output Fall Edge Rate Measured from 2.4V to 0.4V

0.5

45

2

V/ns

%

t_F

–

t_D

Duty Cycle

Measured on rising and falling edge at 1.5V

–

55

Document #: 38-07153 Rev. *B

Page 12 of 14

W144

24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz (continued)

CPU = 66.6/100.2 MHz

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max. Unit

f_ST

Frequency Stabilization Assumes full supply voltage reached within 1 ms from

–

3

ms

from Power-up (cold

start)

power-up. Short cycles exist prior to frequency stabili-

zation.

Z_o

AC Output Impedance Average value during switching transition. Used for

determining series termination value.

–

40

–

Ω

Ordering Information

Ordering Code

W144H

Package Type

48-Pin SSOP (300-mil)

48-Pin SSOP (300-mil) – Tape and Reel

W144HT

Package Drawing and Dimension

48-Lead Shrunk Small Outline Package O48

51-85061-*C

Intel is a registered trademark of Intel Corporation. Purchase of I²C components from Cypress, or one of its sublicensed

Associated Companies, conveys a license under the Philips I²C Patent Rights to use these components in an I²C system,

provided that the system conforms to the I²C Standard Specification as defined by Philips. All product and company names

mentioned in this document are the trademarks of their respective holders.

Document #: 38-07153 Rev. *B

Page 13 of 14

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

W144

DocumentHistory PageDocument History Page

Document Title: W144 440BX AGPset Spread Spectrum Frequency Synthesizer

Document Number: 38-07153

Orig. of

REV.

**

ECN No. Issue Date

Change

Description of Change

110263

122800

131400

12/15/01

12/14/02

01/20/04

SZV

Change from Spec number: 38-00791 to 38-07153

*A

RBI

Added Power-up Requirements to Operating Conditions information

*B

RGL/TUJ Changed the frequency of FS(3:0), 1111 address(CPU_F,CPU1) from 133.3

MHz to 133.6 MHz, (PCI_F) from 33.3 MHz to 33.4 MHz in the

pin-selectable Frequency table and in Additional Frequency Selection

tables respectively.

Changed the frequency of FS(3:0), 0111 address(CPU_F,CPU1) from 100

MHzto100.2MHz, (PCI_F) from 33.3MHz to33.4MHz inthe Pinselectable

Frequency table and in Additional Frequency Selection tables respectively.

Changed the min. t_P(period) parameter for 100.2 MHz frequency from 10.0

ns to 9.98 ns in the CPU Clock Outputs table.

hanged the min. t_P(period) parameter for 100.2 MHz frequency from 30 ns

to 29.9 ns in the PCI Clock Outputs table.

Removed “PRELIMINARY”

Document #: 38-07153 Rev. *B

Page 14 of 14


型号：	W144H
厂家：	CYPRESS
描述：	440BX AGPset Spread Spectrum Frequency Synthesizer 440BX AGPset扩频频率合成器光电二极管
文件：	总14页 (文件大小：159K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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