W164 [CYPRESS]
Spread Spectrum Desktop/Notebook System Frequency Generator; 扩频台式机/笔记本电脑系统频率发生器型号: | W164 |
厂家: | CYPRESS |
描述: | Spread Spectrum Desktop/Notebook System Frequency Generator |
文件: | 总11页 (文件大小:139K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
W164
Spread Spectrum Desktop/Notebook System
Frequency Generator
Features
Key Specifications
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Supply Voltages:....................................... V
V
= 3.3V±5%
= 2.5V±5%
DDQ3
DDQ2
• Reduces measured EMI by as much as 10 dB
• I C programmable to 153 MHz (16 selectable
frequencies)
CPU Cycle to Cycle Jitter:...........................................200 ps
CPU, PCI Output Edge Rate:.........................................≥1 V/ns
CPU0:1 Output Skew: ................................................175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: .............................. 1 to 4 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA ................ 250-kΩ pull-up
2
• Two skew-controlled copies of CPU output
• SEL100/66# selects CPU frequency (100 or 66.8 MHz)
• Seven copies of PCI output (synchronous w/CPU
output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz output is determined by resistor
straps on power-up
Note:
Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.
Table 1. Pin Selectable Frequency
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
SEL100/66#
CPU(0:1)
100 MHz
66.8 MHz
PCI
1
0
33.3 MHz
33.4 MHz
Block Diagram
Pin Configuration
VDDQ3
X1
X2
GND
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REF2X/SEL48#
GND
2
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
GND
3
PCI_F
PCI1
4
X1
X2
XTAL
OSC
VDDQ3
IOAPIC
5
PCI2
6
PLL Ref Freq
PCI3
7
PCI4
CPU1
8
VDDQ3
PCI5
VDDQ3
GND
9
10
11
12
13
14
PCI6
SDATA
VDDQ3
48MHz
24/48MHz
SCLOCK
SEL100/66#
GND
VDDQ2
CPU0
CPU1
GND
100/66#_SEL
PLL 1
÷2/÷3/÷4
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
GND
2
SDATA
SCLOCK
I C
LOGIC
VDDQ3
48MHz
PLL2
24/48MHz
GND
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 16, 1999, rev. **
W164
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
CPU0:1
22, 21
O
O
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.
PCI1:6
PCI_F
5, 6, 7, 8, 10,
11, 4
PCI Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run
synchronously to the CPU clock. Voltage swing is set by the power connection to
VDDQ3.
IOAPIC
48MHz
24
13
O
O
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24/48MHz
14
27
O
24-MHz or 48-MHz Output: Frequency is set by the state of pin 27 on power-up.
REF2X/SEL48#
I/O
I/O Dual-Function REF2X and SEL48# pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to V . A 10K
DD
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to V , pin
DD
14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
SEL100/66#
SDATA
SCLOCK
X1
16
I
I/O
I
Frequency Selection Input: Selects CPU clock frequency as shown in Table 1 on
page 1.
2
2
18
I C Data Pin: Data should be presented to this input as described in the I C section
of this data sheet. Internal 250-kΩ pull-up resistor.
2
2
17
I C Clock Pin: The I C data clock should be presented to this input as described in
2
the I C section of this data sheet.
1
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
X2
2
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
VDDQ2
GND
9, 12, 20, 26
23, 25
P
P
G
Power Connection: Power supply for core logic and PLL circuitry, PCI, 48-/24-MHz,
and Reference output buffers. Connect to 3.3V supply.
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.
3, 15, 19, 28
Ground Connections: Connect all ground pins to the common system ground
plane.
l/O pin is then latched. Next the output buffer is enabled which
converts the l/O pin into an operating clock output. The 2-ms
Functional Description
I/O Pin Operation
timer is started when V reaches 2.0V. The input bit can only
DD
be reset by turning V off and then back on again.
DD
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with input
select pins.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 25Ω (nominal) which is minimally affected by
the 10-kΩ strap to ground or V . As with the series termina-
DD
tion resistor, the output strapping resistor should be placed as
close to the l/O pin as possible in order to keep the intercon-
necting trace short. The trace from the resistor to ground or
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V . Connection to ground sets a
latch to “0,” connection to V sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
DD
DD
V
should be kept less than two inches in length to prevent
DD
system noise coupling during input logic sampling.
connections.
When the clock output is enabled following the 2-ms input pe-
riod, a 14.318-MHz output frequency is delivered on the pin,
Upon W164 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the Reference clock
output buffer is three-stated, allowing the output strapping re-
sistor on the l/O pin to pull the pin and its associated capacitive
clock load to either a logic HIGH or LOW state. At the end of
the 2-ms period, the established logic “0” or “1” condition of the
assuming that V has stabilized. If V has not yet reached
DD
DD
full value, output frequency initially may be below target but will
increase to target once V voltage has stabilized. In either
DD
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
2
W164
VDD
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
Clock Load
W164
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 kΩ
(Load Option 0)
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
VDD
Series Termination Resistor
10 kΩ
Clock Load
W164
R
Output
Buffer
Power-on
Reset
Timer
Resistor Value R
Hold
Output
Low
Output Three-state
Q
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management func-
tions. Table 2 summarizes the control functions of the serial
data interface.
Serial Data Interface
The W164 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W164 initializes with
default register settings. Therefore, the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
Operation
Data is written to the W164 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
ProvidesCPU/PCIfrequency selections beyond the For alternate microprocessors and power
100- and 66.6-MHz selections that are provided by management options. Smooth frequency tran-
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.
sition allows CPU frequency change under
normal system operation.
Output Three-state
Test Mode
Puts all clock outputs into a high-impedance state. Production PCB testing.
All clock outputs toggle in relation to X1 input, inter- Production PCB testing.
nal PLL is bypassed. Refer to Table 4.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
3
W164
Table 3. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W164 to accept the bits in Data Bytes 3–6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W164 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
3
Command
Code
Don’t Care
Don’t Care
Unused by the W164, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
Byte Count
Unused by the W164, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Don’t Care
Refer to Cypress SDRAM drivers.
6
7
Refer to Table 4
The data bits in these bytes set internal W164 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 4, Data Byte Serial Configuration Map.
8
9
10
4
W164
Writing Data Bytes
Table 5 details additional frequency selections that are avail-
able through the serial data interface.
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 3–6.
Table 6 details the select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 3–6 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
SEL_3
0
1
Default
Data Byte 3
7
6
5
4
3
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
SEL_2
SEL_1
SEL_0
Refer to Table 5
Refer to Table 5
Refer to Table 5
Frequency Table
Selection
Frequency Controlled Frequency Controlled
by external SEL100/
by BYT3 SEL_(3:0)
66# pin Table 1
Table 5
2
--
--
--
--
(Reserved)
Bit 1 Bit 0
--
--
0
1–0
Function (See Table 6 for function details)
Normal Operation
00
0
0
1
1
0
1
0
1
Test Mode
Spread Spectrum on
All Outputs Three-stated
Data Byte 4
7
--
14
--
--
(Reserved)
--
--
Active
--
0
1
0
0
0
1
0
1
6
24/48MHz Clock output Disable
Low
--
5
--
--
(Reserved)
4
--
(Reserved)
--
--
3
--
--
(Reserved)
--
--
2
21
--
CPU1
--
Clock Output Disable
(Reserved)
Low
--
Active
--
1
0
22
CPU0
Clock Output Disable
Low
Active
Data Byte 5
7
4
11
10
-
PCI_F
PCI6
PCI5
--
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
Low
Low
Low
--
Active
Active
Active
--
1
1
1
0
1
1
1
1
6
5
4
3
8
PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
2
7
1
6
0
5
Data Byte 6
7
6
5
4
3
2
1
--
--
--
(Reserved)
--
--
--
--
0
0
1
0
0
0
--
IOAPIC
--
(Reserved)
24
--
Clock Output Disable
(Reserved)
Low
--
Active
--
--
--
(Reserved)
--
--
--
--
(Reserved)
--
--
[1]
27
27
REF2X
REF2X
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
1
[1]
0
1
Note:
1. Both Bits 0 and 1 of Byte 6 in Table 4 must be programmed as the same value.
5
W164
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
If Spread Is On
Data Byte 3, Bit 3 = 1
Bit 7
Bit 6
Bit 5
Bit 4
CPU, SDRAM
PCI Clocks
(MHz)
SEL_3
SEL_2
SEL_1
SEL_0
Clocks (MHz)
68.5
75
Spread Percentage
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
34.25
37.5
83.3
66.8
103
41.6
33.4
34.25
37.3
112
133.3
100
33.3
33.3
117
39.0
117
29.25
31.0
124
129
32.25
34.5
138
143
35.75
37.0
148
153
38.25
Table 6. Select Function for Data Byte 3, Bits 0:1
Input Conditions
Output Conditions
REF2X,
Data Byte 3
Function
Normal Operation
Test Mode
Bit 1
Bit 0
CPU0:1
Note 2
X1/2
PCI_F, PCI1:6
IOAPIC
14.318 MHz
X1
48MHZ
24MHZ
24 MHz
X1/4
0
0
1
1
0
1
0
1
Note 2
48 MHz
X1/2
CPU/2, 3, or 4
Spread Spectrum
±0.5%
Hi-Z
±0.5%
Hi-Z
14.318 MHz
Hi-Z
48 MHz
Hi-Z
24 MHz
Hi-Z
Three-state
Note:
2. CPU and PCI frequency selections are listed in Table 1 and Table 5.
6
W164
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
kV
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Input ESD Protection
–55 to +125
2 (min.)
B
ESD
PROT
DC Electrical Characteristics: T = 0°C to +70°C, V
= 3.3V±5%, V = 2.5V±5%
DDQ2
A
DDQ3
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
I
Combined 3.3V Supply Current
CPU0:1 =100 MHz
Outputs Loaded
85
30
mA
mA
DDQ3
[3]
I
Combined 2.5V Supply Current
CPU0:1 =100 MHz
DDQ3
[3]
Outputs Loaded
Logic Inputs
V
Input Low Voltage
Input High Voltage
GND –
0.3
0.8
V
V
IL
V
2.0
V
+
DD
IH
0.3
[4]
I
I
I
I
Input Low Current
–25
10
–5
5
µA
µA
µA
µA
IL
[4]
Input High Current
IH
IL
Input Low Current (SEL100/66#)
Input High Current (SEL100/66#)
IH
Clock Outputs
V
Output Low Voltage
I
I
I
= 1 mA
= –1 mA
= –1 mA
= 1.25V
= 1.5V
50
mV
V
OL
OL
OH
OH
V
Output High Voltage
3.1
2.2
50
OH
V
Output High Voltage CPU0:1/IOAPIC
V
OH
I
Output Low Current
CPU0:1
V
V
V
V
V
V
V
V
V
V
70
80
100
120
140
152
76
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OL
OL
OL
OL
OL
OL
OH
OH
OH
OH
OH
PCI_F, PCI1:6
IOAPIC
60
= 1.25V
= 1.5V
40
85
REF2X
100
40
130
50
48MHz, 24MHz
= 1.5V
I
Output High Current CPU0:1
PCI_F, PCI1:6
= 1.25V
= 1.5V
= 1.25V
= 1.5V
= 1.5V
50
70
100
120
155
150
94
OH
60
70
IOAPIC
40
87
REF2X
100
40
130
50
48MHz, 24MHz
Notes:
3. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.
4. W164 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
7
W164
DC Electrical Characteristics: T = 0°C to +70°C, V
= 3.3V±5%, V
= 2.5V±5% (continued)
DDQ2
A
DDQ3
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
[5]
V
X1 Input Threshold Voltage
V
= 3.3V
DDQ3
1.65
13
V
TH
C
Load Capacitance, as seen by
pF
LOAD
[6]
External Crystal
[7]
C
X1 Input Capacitance
Pin X2 unconnected
Except X1 and X2
26
pF
IN,X1
Pin Capacitance/Inductance
C
C
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
pF
pF
nH
IN
OUT
IN
L
7
AC Electrical Characteristics
T = 0°C to +70°C, V
= 3.3V±5%,V
= 2.5V± 5%, f
= 14.31818 MHz
XTL
A
DDQ3
DDQ2
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
t
t
t
t
t
t
15
5.2
5.0
1
15.5
10
3.0
2.8
1
10.5
ns
ns
P
H
L
High Time
Low Time
ns
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
%
R
F
D
1
1
Duty Cycle
Measured on rising and falling edge at
45
55
45
55
1.25V
t
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
200
250
ps
JC
t
f
Output Skew
Measured on rising edge at 1.25V
175
3
175
3
ps
SK
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
ms
ST
Z
AC Output Impedance Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
20
Ω
o
Notes:
5. X1 input threshold voltage (typical) is VDD/2.
6. The W164 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
8
W164
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF
CPU = 66.8/100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Min.
30
12
12
1
Typ.
Max.
Unit
ns
t
t
t
t
t
t
t
P
High Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
ns
H
L
Low Time
ns
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
R
F
Measured from 2.4V to 0.4V
1
Measured on rising and falling edge at 1.5V
45
55
250
D
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
ps
difference of cycle time between two adjacent cycles.
t
t
Output Skew
Measured on rising edge at 1.5V
500
4
ps
ns
SK
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1
O
f
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
ST
Z
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
20
Ω
o
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
14.31818
t
t
t
f
1
1
4
4
R
Measured from 2.0V to 0.4V
F
Measured on rising and falling edge at 1.25V
45
55
1.5
D
Frequency Stabilization
Assumes full supply voltage reached within
ms
ST
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
15
Ω
o
REF2X Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
14.318
MHz
t
t
t
f
0.5
0.5
45
2
2
V/ns
V/ns
%
R
Measured from 2.4V to 0.4V
F
Measured on rising and falling edge at 1.5V
55
3
D
FrequencyStabilizationfrom Assumes full supply voltage reached within
ms
ST
Power-up (cold start)
AC Output Impedance
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z
Average value during switching transition. Used
for determining series termination value.
15
Ω
o
9
W164
48-MHz and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max. Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
24.004
MHz
f
Deviation from 48 MHz
PLL Ratio
(48.008 – 48)/48
+167
ppm
D
m/n
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17, 57/34
t
t
t
f
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
R
Measured from 2.4V to 0.4V
F
Measured on rising and falling edge at 1.5V
55
3
D
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
ST
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Z
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
Ω
o
Ordering Information
Package
Name
Ordering Code
Package Type
W164
G
28-pin SOIC (300 mils)
Document #: 38-00841
10
W164
Package Diagram
28-Pin Small Outline Integrated Circuit (SOIC, 300 mils)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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