W181-01G [CYPRESS]
Peak Reducing EMI Solution; 峰值抑制EMI解决方案
| 型号： | W181-01G |
| 厂家： | 
CYPRESS |
| 描述： | Peak Reducing EMI Solution |
| 文件： | 总9页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W181
Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the out-
put
•
W181-01, 02, 03
Output
W181-51, 52, 53
Output
SS%
0
F
≥ F ≥ F
–
F + 0.625% ≥ F ≥
in
out
in
in
in
• Selectable input to output frequency
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
• Available in 8-pin SOIC (Small Outline Integrated Cir-
cuit) or 14-pin TSSOP (Thin Shrink Small Outline Pack-
age select options only)
1.25%
– 0.625%
1
F
≥ F ≥ F
–
F + 1.875% ≥ F ≥
in
out
in
in
in
3.75%
–1.875%
Table 2. Frequency Range Selection
W181 Option#
-02, 52
-01, 51
(MHz)
-03, 53
(MHz)
Key Specifications
FS2 FS1
(MHz)
0
0
1
1
0
1
0
1
28 ≤ F ≤ 38 28 ≤ F ≤ 38
IN IN
N/A
Supply Voltages: ...........................................V = 3.3V±5%
DD
or V = 5V±10%
DD
38 ≤ F ≤ 48 38 ≤ F ≤ 48
N/A
IN
IN
Frequency Range: ............................ 28 MHz ≤ F ≤ 75 MHz
in
46 ≤ F ≤ 60
N/A
46 ≤ F ≤ 60
IN
IN
Crystal Reference Range.................. 28 MHz ≤ F ≤ 40 MHz
in
58 ≤ F ≤ 75
N/A
58 ≤ F ≤ 75
IN
IN
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
Pin Configurations
3.3 or 5.0V
SOIC
CLKIN or X1
NC or X2
GND
FS2
1
2
3
4
8
7
6
5
FS1
X1
VDD
XTAL
SS%
CLKOUT
Input
X2
Spread Spectrum
Output
(EMI suppressed)
W181
40 MHz
Max.
CLKIN or X1
NC or X2
SSON#
FS1
1
2
8
7
GND
SS%
VDD
3
4
6
5
CLKOUT
3.3 or 5.0V
TSSOP
14
13
12
FS2
CLKIN or X1
NC or X2
NC
NC
FS1
NC
VDD
NC
1
2
3
Oscillator or
Reference Input
11
10
9
GND
NC
SS%
4
5
6
Spread Spectrum
W181
Output
(EMI suppressed)
NC
CLKOUT
7
8
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 21, 2000, rev. *B
W181
Pin Definitions
Pin No.
(SOIC)
Pin No.
(TSSOP)(-01)
Pin
Type
Pin Name
Pin Description
CLKOUT
5
8
2
O
I
Output Modulated Frequency: Frequency modulated copy
of the unmodulated input clock (SSON# asserted).
CLKIN or X1
1
Crystal Connection or External Reference Frequency In-
put: This pin has dual functions. It may either be connected
to an external crystal, or to an external reference clock.
NC or X2
SSON#
2
3
I
I
Crystal Connection: If using an external reference, this pin
must be left unconnected.
8(02/03/52/
53)
--
Spread Spectrum Control (Active LOW): Asserting this sig-
nal (active LOW) turns the internal modulation waveform on.
This pin has an internal pull-down resistor.
FS1:2
SS%
7, 8 (01/51)
4
12, 1
6
I
I
Frequency Selection Bit(s) 1 and 2: These pins select the
frequency range of operation. Refer to Table 2. These pins
have internal pull-up resistors.
Modulation Width Selection: When Spread Spectrum fea-
ture is turned on, this pin is used to select the amount of
variation and peak EMI reduction that is desired on the output
signal. This pin has an internal pull-up resistor.
VDD
GND
6
3
10
4
P
Power Connection: Connected to 3.3V or 5V power supply.
G
Ground Connection: Connect all ground pins to the com-
mon system ground plane.
NC
5, 7, 9, 11, 13,
14
NC
No Connection.
2
W181
times the reference frequency. (Note: For the W181 the output
frequency is equal to the input frequency.) The unique feature
of the Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.
Overview
The W181 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low-
frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram on page 1 shows a simple implementa-
tion.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Functional Description
Using frequency select bits (FS1:2 pins), the frequency range
can be set. Spreading percentage is set to be 1.25% or 3.75%
(see Table 1).
The W181 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.
VDD
Clock Input
CLKOUT
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Post
Dividers
Reference Input
(EMI suppressed)
VCO
Σ
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
3
W181
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing Genera-
tion
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log (P) + 9*log (F)
10
10
EMI Reduction
SSFTG
Typical Clock
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
4
W181
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
W
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
B
P
D
: 0°C < T < 70°C, V = 3.3V ±5%
DC Electrical Characteristics
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
Unit
mA
ms
I
18
32
5
DD
ON
t
Power-Up Time
First locked clock cycle after Power
Good
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
0.8
0.4
V
V
IL
2.4
2.4
IH
V
OL
OH
V
I
I
I
I
Note 1
Note 1
–100
µA
µA
mA
mA
pF
pF
kΩ
Ω
IL
10
IH
@ 0.4V, V = 3.3V
15
15
OL
OH
DD
@ 2.4V, V = 3.3V
DD
C
C
R
All pins except CLKIN
CLKIN pin only
7
I
6
10
I
500
25
P
Z
OUT
Note:
1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
5
W181
DC Electrical Characteristics: 0°C < T < 70°C, V = 5V ±10%
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
50
Unit
mA
ms
I
t
30
DD
ON
Power-Up Time
First locked clock cycle after
Power Good
5
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
0.15V
0.4
V
V
IL
DD
0.7V
IH
DD
V
OL
OH
2.4
V
I
I
I
I
Note 1
Note 1
–100
µA
µA
mA
mA
pF
pF
kΩ
Ω
IL
10
IH
@ 0.4V, V = 5V
24
24
OL
OH
DD
@ 2.4V, V = 5V
DD
C
C
R
All pins except CLKIN
CLKIN pin only
7
I
6
10
I
500
25
P
Z
OUT
AC Electrical Characteristics: T = 0°C to +70°C, V = 3.3V ±5% or 5V±10%
A
DD
Parameter
Description
Input Frequency
Test Condition
Min.
28
Typ.
Max.
Unit
MHz
MHz
ns
f
f
t
t
t
t
t
Input Clock
Spread Off
75
75
5
IN
Output Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-Cycle
Harmonic Reduction
28
OUT
R
V
V
, 15-pF load 0.8V–2.4V
2
2
DD
, 15-pF load 2.4V–0.8V
DD
5
ns
F
15-pF load
40
40
60
60
300
%
OD
ID
%
250
ps
JCYC
f
= 40 MHz, third harmonic
8
dB
out
measured, reference board,
15-pF load
6
W181
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
Application Information
Recommended Circuit Configuration
type. For further EMI protection, the V
made via a ferrite bead, as shown.
connection can be
DD
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
Recommended Board Layout
V
decoupling is important to both reduce phase jitter and
DD
Figure 5 shows a recommended 2-layer board layout.
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V
pin as possible, otherwise the in-
DD
Reference Input
1
2
3
4
8
7
6
5
NC
GND
Clock
Output
R1
C1
µF
0.1
3.3 or 5V System Supply
FB
C2
10
µF Tantalum
Figure 4. Recommended Circuit Configuration
C1 =
C2 =
High frequency supply decoupling
µF recommended).
capacitor (0.1-
Common supply low frequency
µF tantalum
decoupling capacitor (10-
recommended).
R1 =
Match value to line impedance
Ferrite Bead
FB
=
G
Via To GND Plane
=
Reference Input
NC
C1
G
G
Clock Output
R1
G
C2
Power Supply Input
(3.3 or 5V)
FB
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Freq. Mask
Code
Package
Name
Ordering Code
Package Type
W181
01, 02, 03
51, 52, 53
G
8-pin Plastic SOIC (150-mil)
W181
01
X
14-pin Plastic TSSOP
Document #: 38-00790-B
7
W181
Package Diagram
14-pin Thin Shrink Small Outline Package
8
W181
Package Diagram (continued)
8-Pin Small Outline Integrated Circuit (SOIC, 150 mils)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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