W182 [CYPRESS]
Full Feature Peak Reducing EMI Solution; 全功能峰值抑制EMI解决方案
| 型号： | W182 |
| 厂家： | 
CYPRESS |
| 描述： | Full Feature Peak Reducing EMI Solution |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W182
Full Feature Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
•
W182
W182-5
Output
SS%
Output
0
F
≥ F ≥ F
F + 0.625% ≥ F ≥
in in
– 0.625%
in
out
in
– 1.25%
1
F
≥ F ≥ F
F
+ 1.875% ≥ F ≥
–1.875%
in
out
in
in
in
– 3.75%
Table 2. Frequency Range Selection
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
FS2
0
FS1
0
Frequency Range
Key Specifications
8 MHz ≤ F ≤ 10 MHz
IN
0
1
10 MHz ≤ F ≤ 15 MHz
Supply Voltages: ...........................................V = 3.3V±5%
IN
DD
or V = 5V±10%
DD
1
0
15 MHz ≤ F ≤ 18 MHz
IN
Frequency Range: .............................. 8 MHz ≤ F ≤ 28 MHz
in
1
1
18 MHz ≤ F ≤ 28 MHz
IN
Cycle to Cycle Jitter:........................................ 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
Pin Configuration
3.3V or 5.0V
SOIC
FS2
CLKIN or X1
NC or X2
GND
REFOUT
OE#
1
2
3
4
5
6
7
14
13
12
11
10
9
X1
SSON#
Reset
VDD
XTAL
Input
X2
Spread Spectrum
Output
(EMI suppressed)
W182
GND
VDD
SS%
FS1
CLKOUT
8
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W182
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 8, 2000, rev. *A
W182
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CLKOUT
8
O
O
Output Modulated Frequency: Frequency modulated copy of the input clock
(SSON# asserted).
REFOUT
14
2
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
CLKIN or X1
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
NC or X2
SSON#
3
I
I
Crystal Connection: Input connection for an external crystal. If using an ex-
ternal reference, this pin must be left unconnected.
12
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
SS%
OE#
6
I
I
I
I
Modulation Width Selection: When Spread Spectrum feature is turned on,
this pin is used to select the amount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull-up resistor.
13
Output Enable (Active LOW): When this pin is held HIGH, the output buffers
are placed in a high-impedance mode.This pin has an internal pull-down re-
sistor.
Reset
FS1:2
11
ModulationProfileRestart: A rising edgeon thisinputrestarts the modulation
pattern at the beginning of its defined path. This pin has an internal pull-down
resistor.
7, 1
Frequency Selection Bit(s): These pins select the frequency range of oper-
ation. Refer to Table 2. These pins have internal pull-up resistors.
VDD
GND
9,10
4,5
P
Power Connection: Connected to 3.3V or 5V power supply.
G
Ground Connection: Connect all ground pins to the common ground plane.
2
W182
times the reference frequency. (Note: For the W182 the output
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Overview
The W182 product is one of a series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low-fre-
quency carrier, peak EMI is greatly reduced. Use of this tech-
nology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Functional Description
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pin
SS% as shown in Table 1.
The W182 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
VDD
Clock Input
CLKOUT
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Post
Dividers
Reference Input
(EMI suppressed)
VCO
Σ
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
3
W182
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing
Generation
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log (P) + 9*log (F)
10
10
EMI Reduction
SSFTG
Typical Clock
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
4
W182
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
W
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
B
P
D
: 0°C < T < 70°C, V = 3.3V ±5%
DC Electrical Characteristics
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
Unit
mA
ms
I
18
32
5
DD
ON
t
Power Up Time
First locked clock cycle after Power
Good
V
V
V
V
Input Low Voltage
0.8
0.4
V
V
IL
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
2.4
IH
V
OL
OH
2.4
V
I
I
I
I
Note 1
Note 1
–50
µA
µA
mA
mA
pF
kΩ
Ω
IL
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
50
7
IH
@ 0.4V, V = 3.3V
15
15
OL
OH
DD
@ 2.4V, V = 3.3V
DD
C
R
I
500
25
P
Z
OUT
Note:
1. Inputs FS2:1 have a pull-up resistor; Input SSON# has a pull-down resistor.
5
W182
DC Electrical Characteristics: 0°C < T < 70°C, V = 5V ±10%
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
50
Unit
mA
ms
I
t
30
DD
ON
Power Up Time
First locked clock cycle after
Power Good
5
V
V
V
V
Input Low Voltage
0.15V
0.4
V
V
IL
DD
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
0.7V
DD
IH
V
OL
OH
2.4
V
I
I
I
I
Note 2
Note 2
–50
µA
µA
mA
mA
pF
kΩ
Ω
IL
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
50
7
IH
@ 0.4V, V = 5V
24
24
OL
OH
DD
@ 2.4V, V = 5V
DD
C
R
I
500
25
P
Z
OUT
AC Electrical Characteristics: T = 0°C to +70°C, V = 3.3V ±5% or 5V±10%
A
DD
Symbol
Parameter
Input Frequency
Test Condition
Min.
Typ.
Max.
Unit
MHz
MHz
ns
f
Input Clock
8
8
28
28
5
IN
f
t
t
t
t
t
Output Frequency
Output Rise Time
Output Fall Time
Spread Off
OUT
R
15-pF load, 0.8V–2.4V
15-pF load, 2.4 –0.8V
15-pF load
2
2
5
ns
F
Output Duty Cycle
Input Duty Cycle
40
40
60
60
300
%
OD
ID
%
Jitter, Cycle-to-Cycle
Harmonic Reduction
250
ps
JCYC
f
= 20 MHz, third harmonic
8
dB
out
measured, reference board,
15-pF load
Note:
2. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
6
W182
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
Application Information
Recommended Circuit Configuration
type. For further EMI protection, the V
made via a ferrite bead, as shown.
connection can be
DD
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
Recommended Board Layout
V
decoupling is important to both reduce phase jitter and
DD
Figure 5 shows a recommended a 2-layer board layout.
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V pin as possible, otherwise the in-
DD
1
2
3
14
13
12
Xtal Connection or Reference Input
Xtal Connection or NC
GND
4
5
6
7
11
10
9
C3
µF
0.1
Clock
8
Output
R1
C1
0.1
µF
3.3V or 5V System Supply
FB
C2
10
µF Tantalum
Figure 4. Recommended Circuit Configuration
C1, C3 = High-frequency supply decoupling
µF recommended).
capacitor (0.1-
C2 =
Common supply low frequency
µF tantalum
decoupling capacitor (10-
recommended).
R1 =
Match value to line impedance
Ferrite Bead
FB
=
Xtal Connection or Reference Input
Xtal Connectionor NC
G
=
Via To GND Plane
G
G
C3
C1
G
G
Clock Output
R1
G
Power Supply Input
(3.3V or 5V)
FB
C2
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Package
Name
Ordering Code
W182
Package Type
G
14-Pin Plastic SOIC (150-mil)
W182-5
Document #: 38-00789-A
7
W182
Package Diagram
14-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
©2020 ICPDF网 联系我们和版权申明