W224BXT [CYPRESS]
Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, 6.10 MM, TSSOP-56;
| 型号： | W224BXT |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, 6.10 MM, TSSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总18页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W224B
133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology (–0.5% and –1.0%)
CPU Output Skew: ......................................................150 ps
3V66 Output Skew: .....................................................175 ps
APIC, SDRAM Output Skew: ......................................250 ps
PCI Output Skew:........................................................500 ps
VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM: ..........3.3V±5%
VDDQ2 (CPU, APIC):..............................................2.5V±5%
• Single chip system FTG for Mobile Intel® Platforms
• Three CPU outputs
• Seven copies of PCI clock (one Free Running)
• Seven SDRAM clock (one DCLK for Memory Hub)
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video DOT clock
• Three 3V66 Hublink/AGP outputs
• One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)
• Two APIC outputs
Table 1. Pin Selectable Functions
TEST#
FS1
x
FS0
0
CPU
SDRAM
0
0
1
1
1
1
Three-state Three-state
• One buffered reference output
• Supports frequencies up to 133 MHz
• Supports 5% and 10% overclocking
• SMBus interface for programming
• Power management control inputs
x
1
Test
Test
0
0
66 MHz
100 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
0
1
1
0
Key Specifications
1
1
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
Pin Configuration[1]
Block Diagram
VDD_REF
X1
X2
XTAL
OSC
REF
REF
VDD_REF
X1
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
GND_APIC
APIC0
APIC1
VDD_APIC
CPU0
VDD_CPU
CPU_F1
PLL Ref Freq
Divider
Network
PLL 1
VDD_CPU
CPU0
Stop
Clock
Control
X2
FS0:1
GND_REF
GND_3V66
3V66_0
CPU_F1:2
CPU_STP#
VDD_SDRAM
SDRAM0:5
DCLK
3V66_1
CPU_F2
3V66_AGP
VDD_3V66
*PCI_STP#
PCI_F
PCI1
GND_PCI
PCI2
PCI3
VDD_PCI
GND_CPU
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
DCLK
VDD_SDRAM
VCH_CLK
VDD_VCH
CPU_STP#*
TEST#*
PWR_DWN#*
SCLK
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD_APIC
APIC0:1
PWR_DWN#
PCI_STP#
VDD_PCI
PCI_F
PCI4
PCI5
PCI6
Stop
Clock
Control
PCI1:6
GND_PCI
VDD_CORE
GND_CORE
GND_48MHz
USB
DOT
VDD_48MHz
FS0
VDD_3V66
3V66_0:1
34
33
32
31
30
29
3V66_AGP
25
26
27
28
VDD_48MHz
USB (48MHz)
PLL2
SDATA
FS1
DOT (48MHz)
VCH_CLK
SDATA
SCLK
SMBus
Logic
Note:
1. Internal pull-up resistors present on inputs marked with [*].
Design should not rely solely on internal pull-up to set I/O pins
HIGH.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07191 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 22, 2002
W224B
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CPU0,
CPU_F1:2
52, 50, 49
O
O
O
O
O
O
CPU Clock Outputs: Frequency is set by the FS0:1 inputs or through serial
input interface. The CPU0 output is gated by the CLK_STOP# input.
PCI1:6, PCI_F
APIC0:1
13, 15, 16, 18,
19, 20, 12
33-MHz PCI Outputs: Except for the PCI_F output, these outputs are gated by
the PCI_STOP# input.
55, 54
APIC Output: 2.5V fixed 33.33-MHz clock. This output is synchronous to the
CPU clock.
SDRAM0:5,
DCLK
46, 45, 43, 42,
40, 39, 38
SDRAM Output Clocks: 3.3V outputs running at either 100MHz or 133MHz
depending on the setting of FS0:1 inputs. DCLK is a free-running clock.
3V66_0:1,
3V66_AGP
7, 8, 9
66MHz Clock Outputs: 3.3V fixed 66-MHz clock.
USB
25
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock out-
put.
DOT
26
1
O
O
O
Dot Clock Output: 3.3V fixed 48-MHz, non-spread spectrum signal.
Reference Clock: 3.3V 14.318-MHz clock output.
REF
VCH_CLK
36
Video Control Hub Clock Output: 3.3V selectable 48MHz non-spread spec-
trum or 66.67 MHz spread spectrum clock output.
PWR_DWN#
CPU_STP#
PCI_STP#
TEST#
32
34
I
I
I
I
I
Power Down Control: 3.3V LVTTL-compatible input that places the device in
power down mode when held low.
CPU Output Control: 3.3V LVTTL-compatible input that stops only the CPU0
clock. Output remains in the low state.
11
PCI Output Control: 3.3V LVTTL-compatible input that stops PCI1:6 clocks.
Output remains in the low state.
33
Test Mode Control: 3.3V LVTTL-compatible input to place the device into test
mode.
FS0:1
28, 29
Frequency Selection Input: 3.3V LVTTL-compatible input used to select the
CPU and SDRAM frequencies. See Frequency Table.
SCLK
SDATA
X1
31
30
3
I
I/O
I
SMBus Clock Input: Clock pin for SMBus circuitry.
SMBus Data Input: Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
X2
4
O
P
Crystal Connection: Connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
VDD_REF,
VDD_3V66,
VDD _PCI,
2, 10, 17, 27,
35, 37, 44
3.3V Power Connection: Power supply for core logic, PLL circuitry, SDRAM
outputs buffers, PCI output buffers, reference output buffers and 48-MHz output
buffers. Connect to 3.3V.
VDD_48MHz,
VDD_VCH,
VDD_SDRAM,
VDD_SDRAM
VDD_APIC,
VDD_CPU
51, 53
P
2.5V Power Connection: Power supply for APIC and CPU output buffers. Con-
nect to 2.5V.
Document #: 38-07191 Rev. *A
Page 2 of 18
W224B
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
GND_REF,
GND_3V66,
GND_PCI,
5, 6, 14, 21, 24,
41, 47, 48, 56
G
Ground Connection: Connect all ground pins to the common system ground
plane.
GND_PCI,
GND_48MHz,
GND_SDRAM,
GND_SDRAM,
GND_CPU,
GND_APIC
VDD_CORE
22
23
P
3.3V Analog Power Connection: Power supply for core logic, PLL circuitry.
Connect to 3.3V.
GND_CORE
G
Analog Ground Connection: Ground for core logic, PLL circuitry.
Overview
CPU/SDRAM Frequency Selection
The W224 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel architec-
ture platform using graphics integrated core logic.
CPU output frequency is selected through pins 28 and 29. For
CPU/SDRAM frequency programming information, refer to Ta-
ble 2. Alternatively, frequency selections are available through
the serial data interface.
Table 2. Frequency Select Truth Table
Notes
2
TEST#
FS1
X
FS0
0
CPU
Hi-Z
SDRAM
Hi-Z
3V66
Hi-Z
PCI
48MHz
Hi-Z
REF
Hi-Z
APIC
Hi-Z
0
0
1
1
1
1
Hi-Z
X
1
TCLK/2
66 MHz
TCLK/2
TCLK/3
TCLK/6
33 MHz
33 MHz
33 MHz
33 MHz
TCLK/2
TCLK
TCLK/6
3, 4
0
0
100 MHz 66 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
5, 6, 7
5, 6, 7
5, 6, 7
5, 6, 7
0
1
100 MHz 100 MHz 66 MHz
133 MHz 133 MHz 66 MHz
133 MHz 100 MHz 66 MHz
1
0
1
1
Notes:
2. Provided for board-level “bed of nails” testing.
3. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
4. Required for DC output impedance verification.
5. “Normal” mode of operation.
6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Document #: 38-07191 Rev. *A
Page 3 of 18
W224B
Offsets Among Clock Signal Groups
spectively. It should be noted that when CPU clock is operating
at 100 MHz, CPU clock output is 180 degrees out of phase
with SDRAM clock outputs.
Figure 1 and Figure 2 represent the phase relationship among
the different groups of clock outputs from W224 when it is pro-
viding a 66-MHz CPU clock and a 100-MHz CPU clock, re-
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 1. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM Clock)
Table 3. 66 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM to
3V66
SDRAM CPU to 3V66
3V66 to PCI
1.5–3.5 ns
500 ps
PCI to APIC
0.0 ns
USB & DOT
Async
Offset
–2.5 ns
7.5 ns
0.0 ns
Tolerance
500 ps
500 ps
500 ps
1.0 ns
N/A
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 2. Group Offset Waveforms (100-MHz CPU/100-MHz SDRAM Clock)
Document #: 38-07191 Rev. *A
Page 4 of 18
W224B
Table 4. 100-MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to
3V66
SDRAM to
3V66
3V66 to PCI PCI to APIC
USB & DOT
Offset
5.0 ns
5.0ns
0.0 ns
1.5–3.5 ns
0.0 ns
1.0 ns
Async
N/A
Tolerance
500 ps
500 ps
500 ps
500 ps
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 3. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock)
Table 5. 133-MHz/SDRAM 100-MHz Group Timing Relationships and Tolerances
CPU to
SDRAM to
3V66
SDRAM CPU to 3V66
3V66 to PCI
1.5–3.5 ns
500 ps
PCI to APIC
0.0 ns
USB & DOT
Async
Offset
0.0 ns
500 ps
0.0 ns
500 ps
0.0 ns
500 ps
Tolerance
1.0 ns
N/A
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 133-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock)
Document #: 38-07191 Rev. *A
Page 5 of 18
W224B
Table 6. 133 MHz/SDRAM Test Mode Group Timing Relationships and Tolerance
CPU to
SDRAM to
3V66
SDRAM CPU to 3V66
3V66 to PCI
1.5–3.5 ns
500 ps
PCI to APIC
0.0 ns
USB& DOT
Offset
3.75 ns
500 ps
0.0 ns
500 ps
3.75 ns
500 ps
Async
N/A
Tolerance
1.0 ns
Power Down Control
W224 provides one PWR_DWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0 ns
25 ns
50 ns
75 ns
Center
1
2
VCO Internal
CPU 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
PwrDwn
SDRAM 100-MHz
REF 14.318-MHz
USB 48-MHz
Figure 5. W224 PWR_DWN# Timing Diagram[8, 9, 10, 11]
Table 7. W224 Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2 = 2.625V
Max. 3.3V supply consumption
Max. discrete cap loads
VDDQ3 = 3.465V
W224
Condition
All static inputs = VDDQ3 or VSS
All static inputs = VDDQ3 or VSS
Powerdown Mode
(PWR_DWN# = 0)
< 1 mA
60 mA
75 mA
90 mA
< 1 mA
160 mA
160 mA
160 mA
Full Active 66 MHz
FS1:0 = 00 (PWR_DWN# = 1)
Full Active 100 MHz
FS1:0 = 01 (PWR_DWN# = 1)
Full Active 133 MHz
FS1:0 = 11 (PWR_DWN# = 1)
Notes:
8. Once the PWR_DWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
9. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W224.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Document #: 38-07191 Rev. *A
Page 6 of 18
W224B
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing
Generation
The output clock is modulated with a waveform depicted in
Figure 7. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% or -1.0% of the select-
ed frequency. Figure 7 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 6.
As shown in Figure 6, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate value for bit 3 in data byte 0 of the
SMBus data stream. Refer to page 9 for more details.
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Spread
Non-
Spread
Spectrum
Spectrum
Enabled
Figure 6. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 7. Typical Modulation Profile
Document #: 38-07191 Rev. *A
Page 7 of 18
W224B
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Byte Count = N
Ack
1 bit
Data Byte 1
8 bits
Ack
Data Byte 2
8 bits
Ack
1
...
Data Byte N
8 bits
Ack
1
Stop
1
1
Figure 8. An Example of a Block Write[12]
Serial Data Interface
the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
transfer a maximum of 32 data bytes. The slave receiver ad-
dress for W224 is 11010010. Figure 8 shows an example of a
block write.
The W224 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions.
Data Protocol
The command code and the byte count bytes are required as
the first two bytes of any transfer. W224 expects a command
code of 0000 0000. The byte count byte is the number of ad-
ditional bytes required for the transfer, not counting the com-
mand code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 8 shows an
example of a possible byte count value.
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the mes-
sage. If the host had 20 bytes to send, the first byte would be
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Table 8. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
LSB
0000
0001
0010
0011
0100
0101
0110
0111
0000
Not allowed. Must have at least one byte
Data for functional and frequency select register (currently byte 0 in spec)
Writes first two bytes of data (byte 0 then byte 1)
Writes first three bytes (byte 0, 1, 2 in order)
Writes first four bytes (byte 0, 1, 2, 3 in order)
Writes first five bytes (byte 0, 1, 2, 3, 4 in order)
Writes first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
Writes first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
Max. byte count supported = 32
Note:
12. The acknowledgment bit is returned by the slave/receiver (W224).
Document #: 38-07191 Rev. *A
Page 8 of 18
W224B
W224 Serial Configuration Map
1. The serial bits willbereadby theclock driver inthe following
order:
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current.
Byte 0: Control Register (1 = Enable, 0 = Disable)[13]
Bit
Pin#
36
49
50
52
-
Name
Pin Description
(Disabled/Enabled)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCH
CPU_F2
CPU_F1
CPU0
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
Spread Spectrum (1=On/0=Off)
(Active/Inactive)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
26
25
--
DOT
USB
Reserved Drive to ‘0’
Byte 1: Control Register (1 = Enable, 0 = Disable)[13]
Bit
Pin#
--
Name
Reserved Drive to ‘0’
Reserved Drive to ‘0’
SDRAM5
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Active/Inactive)
--
(Active/Inactive)
39
40
42
43
45
46
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 2: Control Register (1 = Enable, 0 = Disable)[13]
Bit
Pin#
9
Name
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
3V66_AGP
3V66_1
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
((Active/Inactive)
8
7
3V66_0
--
Reserved Drive to ‘0’
Reserved Drive to ‘0’
Reserved Drive to ‘0’
Reserved Drive to ‘0’
Reserved Drive to ‘0’
--
--
--
Bit 0
Note:
--
13. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Document #: 38-07191 Rev. *A
Page 9 of 18
W224B
Byte 3: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
-
Name
Reserved Drive to ’0’
Pin Description
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
18
16
15
13
--
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
SDRAM 133 MHz Mode Enable
Default is Disabled = ‘0’, Enabled = ‘1’
Byte 4: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Pin Description
Bit 7
36
VCH_CLK SSC Mode Enable
(Disabled/Enabled)
Default is Disabled = ‘0’
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
-
Byte 5: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Reserved Drive to ‘0’
Pin Description
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
SpreadSpectrumandOverclockingMode (Active/Inactive)
Select. See Table 9
(Active/Inactive)
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ‘0’
Reserved Drive to ‘0’
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
-
Byte 5 has been provided as an optional register to enable a
greater degree of spread spectrum and overclocking perfor-
mance for all PLL1 outputs. (CPU, SDRAM, DCLK, APIC, PCI,
3V66 and VCH_CLK)
programming both bits 5 and 6 to ‘1’. The part will enter this
mode irrespective of pin 33, TEST#.
It is not necessary to access Byte 5 if these additional features
are not implemented. All outputs will default to 0% overclock-
ing upon power up, with either 0% or –0.5% spread spectrum.
(Spread spectrum ON/OFF remains under Byte 0, bit 3 con-
trol). Note that 10% overclocking can only be enabled with
Spread Spectrum turned OFF.
By enabling Byte 5, (bits 5 and 6) spread spectrum can be
increased to –1.0% and /or overclocking of either 5% or 10%
can be enabled. Although the default values are ‘0’ for all bits,
the part can be placed into either Tri-State or Test Mode by
Document #: 38-07191 Rev. *A
Page 10 of 18
W224B
Table 9. Spread Spectrum and Overclocking Mode Select[14]
Byte 0
Bit 3
Byte 5
Bit 5
Bit 6
SS %
–0.5%
–1.0%
–0.5%
–1.0%
-
Overclock %
0%
Description and Comments
No overclocking
No overclocking
Spread
Spectrum
ON
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0%
5%[14]
5%[14]
0%
10%[13]
5%[14]
Spread
Spectrum
OFF
-
-
Three-state or Test Mode Mode determined by FS0 (see Table 1)
Note:
14. Overclocking not tested; characterized at room temperature only. Base Frequency determined through hardware select pins, FS0 & FS1.
Document #: 38-07191 Rev. *A
Page 11 of 18
W224B
DC Electrical Characteristics[15]
Absolute Maximum DC Power Supply
Parameter
Description
Min.
–0.5
–0.5
–0.5
–65
Max.
4.6
Unit
V
VDD3
VDDQ2
VDDQ3
TS
3.3V Core Supply Voltage
2.5V I/O Supply Voltage
3.6
V
3.3V Supply Voltage
Storage Temperature
4.6
V
150
°C
Absolute Maximum DC I/O
Parameter
Description
Min.
–0.5
–0.5
2000
Max.
Unit
V
Vih3
3.3V Input High Voltage
3.3V Input Low Voltage
Input ESD Protection
4.6
Vil3
V
ESD prot.
V
DC Operating Requirements
Parameter
Description
Condition
3.3V±5%
3.3V±5%
2.5V±5%
Min.
Max.
Unit
V
VDD3
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
2.5V I/O Supply Voltage
3.135
3.135
2.375
3.465
3.465
2.625
VDDQ3
V
VDDQ2
V
VDD3 = 3.3V±5%
Vih3
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current[16]
VDD3
2.0
VSS – 0.3
–5
VDD + 0.3
0.8
V
V
Vil3
Iil
0<Vin<VDD3
+5
µA
VDDQ2 = 2.5V±5%
Voh2
2.5V Output High Voltage
2.5V Output Low Voltage
Ioh=(–1 mA)
2.0
2.4
2.4
V
V
Vol2
Iol=(1 mA)
0.4
0.4
VDDQ3 = 3.3V±5%
Voh3
3.3V Output High Voltage
3.3V Output Low Voltage
Ioh=(–1 mA)
V
V
Vol3
Iol=(1 mA)
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
PCI Bus Output Low Voltage
Ioh=(–1 mA)
V
V
Vpol3
Iol=(1 mA)
0.55
Cin
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
22.5
6
pF
pF
pF
nH
°C
Cxtal
Cout
Lpin
13.5
0
0
7
Ta
Ambient Temperature
No Airflow
70
Note:
15. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
16. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
Document #: 38-07191 Rev. *A
Page 12 of 18
W224B
AC Electrical Characteristics[15]
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[17]
AC Electrical Characteristics
66.6-MHz Host
100-MHz Host
133-MHz Host
Parameter
TPeriod
THIGH
Description
Host/CPUCLK Period
Min.
15.0
5.2
Max.
15.5
N/A
N/A
1.6
Min.
10.0
3.0
Max.
10.5
N/A
N/A
1.6
Min.
7.5
Max.
8.0
Unit Notes
ns
ns
ns
ns
ns
17
16
17
19
19
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
1.87
1.67
0.4
N/A
N/A
1.6
TLOW
5.0
2.8
TRISE
0.4
0.4
TFALL
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
SDRAM CLK Period (100-MHz)
SDRAM CLK High Time (100-MHz)
SDRAM CLK Low Time (100-MHz)
SDRAM CLK Rise Time (100-MHz)
SDRAM CLK Fall Time (100-MHz)
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
ns
ns
ns
ns
ns
17
16
17
19
19
1.6
1.6
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
APIC 33-MHz CLK Period
APIC 33-MHz CLK High Time
APIC 33-MHz CLK Low Time
APIC CLK Rise Time
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
ns
ns
ns
ns
ns
17
16
17
19
19
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
3V66 CLK Period
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
ns
ns
ns
ns
ns
17
16
17
19
19
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
TPeriod
THIGH
TLOW
TRISE
TFALL
PCI CLK Period
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
17
16
17
19
19
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
tpZL, tpZH
tpLZ, tpZH
Output Enable Delay (All outputs)
Output Disable Delay (All outputs)
All Clock Stabilization from Power-Up
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
ns
ns
tstable
ms 18
Notes:
17. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
18. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
19.
TLOW is measured at 0.4V for all outputs.
20. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable
and operating within specification.
21.
TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification for 2.5V outputs and VOL
= 0.4V and VOH = 2.4V for 3.3V outputs.
Document #: 38-07191 Rev. *A
Page 13 of 18
W224B
Group Skew and Jitter Limits
Skew, Jitter
Output Group
CPU
Pin-Pin Skew Max.
Cycle-Cycle Jitter
250 ps
Duty Cycle
45/55
Nom Vdd
2.5V
Measure Point
1.25V
1.5V
150 ps
250 ps
250 ps
N/A
SDRAM
APIC
250 ps
45/55
3.3V
500 ps
45/55
2.5V
1.25V
1.5V
48MHz
3V66
500 ps
45/55
3.3V
175 ps
500 ps
N/A
500 ps
45/55
3.3V
1.5V
PCI
500 ps
45/55
3.3V
1.5V
REF
1000 ps
250ps
45/55
3.3V
1.5V
VCH_CLK
N/A
45/55
3.3V
1.5V
Test Point
Output
Buffer
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
1.25
2.5V Clocking
Interface
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
1.5
0.4
3.3V Clocking
Interface
TLOW
TRISE
TFALL
Figure 9. Output Buffer
Ordering Information
Package
Name
Ordering Code
Package Type
W224B
H
X
56-pin SSOP (7.5 mm)
56-pin TSSOP (6.1 mm)
Document #: 38-07191 Rev. *A
Page 14 of 18
W224B
Layout Example
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ2
VDDQ3
10 µF
0.005
µ
F C2
10 µF
µ
F
C4 0.005
C1
C3
G
G
G
G
G
V
1
G 56
G
2
3
4
55
G
G
54
53
V
G
5
52
G
V
G
6
7
8
9
51
G
50
49
48
G
G
V
G
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47
46
G
G
45
44
43
42
41
40
39
38
37
V
G
G
G
G
G
V
G
G
V
G
G
G
G
36
35
34
33
32
31
30
29
V
G
V
G
VDDQ3
10Ω
PLL2
G
G
C5
C6
G
G
FB = Dale ILB1206 - 300 (300
Ω
@ 100 MHz)
C2 & C4 = 0.005
Ceramic Caps: C1, C3 & C5 = 10-22
µF
µF C6 = 0.1 µF
= VIA to GND plane layer V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
Document #: 38-07191 Rev. *A
Page 15 of 18
W224B
Package Diagrams
56-Pin Thin Shrink Small Outline Package (TSSOP, 6.1 mm)
Document #: 38-07191 Rev. *A
Page 16 of 18
W224B
Package Diagrams (continued)
56-Pin Shrink Small Outline Package (SSOP, 7.5 mm)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.725
Body Height: 0.102
Document #: 38-07191 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W224B
Revision History
Document Title: W224B 133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms
Document Number: 38-07191
Issue
Date
Orig. of
REV.
**
ECN NO.
110592
Change Description of Change
12/16/01
12/22/02
DSG
RBI
Change from Spec number: 38-00926 to 38-07191
Add Power up Requirements to Electrical Characteristics Information
*A
122822
Document #: 38-07191 Rev. *A
Page 18 of 18
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