W42C27-41G [CYPRESS]
Clock Generator, CMOS, PDSO8,;
| 型号： | W42C27-41G |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, CMOS, PDSO8, 光电二极管 |
| 文件： | 总6页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W42C27
Specialty Clock Generator
Features
Table 1. Input/Output Frequency Selection
W42C27-41
Reference
• Supports 3.3V and 5V operation
• W42C27-36 provides the same functionality but stron-
ger output drive than the W42C27-13 (obsolete)
• ProprietarycrystaloscillatorcircuitryprovideslowREF
jitter, excellent duty cycle
• Integral PLL loop filter components ensure stable PLL
operation in noisy system environments
• Output clocks are TTL or CMOS-level compatible
• Custom options available with metal layer changes
• Low power CMOS design available in:
FS1
0
FS0
0
(input)
17.734
17.734
14.318
14.318
CLK
48.625
96.059
48.682
96.016
Ratio (P/Q)
85/31
0
1
65/12
1
0
17/5
1
1
114/17
Table 2. Product Selection Guide
— 8-pin SOIC (Small Outline Integrated Circuit)
Input
Output
(MHz)
Part
-36
(MHz)
Application
Fibre Channel
17
106.25
-41
14.318
Selectable Digital Cameras
Functional Block Diagram: W42C27 Base Feature Set
STOPCPU
SLOWCPU
FS0
FS1
Frequency
Selection
FS2
ROM
FS3
÷P
–
PFD
+
Latched
Gate
VCO
÷d
÷2
OUT A
OUT B
Loop
Filter
÷Q
Crystal
Oscillator
OUT C
OE
÷2
W42C27-41
Pin Configurations
W42C27-36
AGND
GND
X1
1
2
3
4
8
7
6
5
106.25MHz
FS0
GND
X1
1
2
3
4
8
7
6
5
FS1
REF
AV
DD
V
V
DD
DD
X2
OE
X2
CLK
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 28, 1999, rev. **
W42C27
Pin Definitions
Pin Name
106.25MHz
AGND
Pin Type
Pin Description
106.25-MHz reference clock for FC-AL chipsets
O
G
P
O
I
Analog ground connection
AV
Analog Power Connection
DD
CLK
FS0:1
GND
OE
Clock output (refer to Table 1 on page 1)
[1]
Frequency Selection inputs
G
I
Ground connection
[1]
Output Enable, puts clock outputs in high-impedance state when LOW
Reference Clock output, outputs crystal or input clock frequency
Power supply connection
REF
O
P
I
V
DD
[1]
X1
Crystal connection or external clock frequency input
X2
I
Crystal connection, leave this pin unconnected when using external clock
Note:
1. All inputs, except X1/X2 have an internal pull-up resistor. Unconnected inputs will assume a logic HIGH condition.
are implemented at device pin X1 and X2 (again unlike other
Cypress clock devices). The required load capacitance value
for accurate crystal oscillation frequency is specified by the
crystal manufacturer. Stray capacitance of X1 and X2 is about
5 pF.
Overview
The W42C27 is a general-purpose device that features a sin-
gle phase-locked loop. Through the use of metal masks, the
chip can be tailored to a wide variety of applications.
The W42C27 can have up to three output frequencies. A wide
variety of input functions are available through mask options.
Improved Crystal Oscillator Circuit
The W42C27 incorporates a new crystal oscillator circuit de-
signed to provide 50% duty cycle over a range of operating
conditions including the addition of external crystal load ca-
pacitors to pins X1 and X2. (Crystal load capacitance is some-
times increased to match a particular crystal load requirement
when absolute frequency accuracy is important.) Duty cycle is
also maintained when using an external clock source (con-
nected to pin X1, pin X2 is left open), as long as the external
clock has good duty cycle.
W42C27-36 Option Description
The standard W42C27-36 option provides a fixed 106.25-MHz
clock output that is useful in FC-AL (Fiber Channel Arbitrated
Loop) applications. FC-AL chip sets, such as the Vitesse
VSC7105/7106, require a 106.25-MHz input reference clock.
Unlike other Cypress clock products, the W42C27-36 requires
a 17.0-MHz crystal or reference clock source. To maintain the
106.25-MHz ±50 ppm accuracy required by FC-AL applica-
tions, the 17.0-MHz crystal needs to be controlled to within ±50
ppm (the 106.25-MHz output is derived by the PLL ratio of 25/4
x 17.0 MHz). To facilitate precise frequency control of the crys-
tal oscillator, external crystal load capacitors are used and re-
quired with the W42C27-36 option; no internal load capacitors
Crystal load capacitance of the W42C27 is about 10 pF (ex-
cluding the W42C27-36 option), which is becoming an industry
standard. This helps to control frequency accuracy, assuming
that a crystal which specifies a 10-pF load condition is used.
The circuit exhibits about 50% less clock jitter from the REF
output when compared to similar devices.
2
W42C27
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
Unit
V
V
, V
–0.5 to +7.0
–65 to +150
0 to +70
DD IN
T
°C
°C
°C
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
–55 to +125
B
Electrical Characteristics at 5.0V
DC Electrical Characteristics: T = 0°C to +70°C; V = 5V ± 10%
A
DD
Parameter
Description
Operating Supply Current
Input Low Voltage
Conditions
Min
Typ
Max
Unit
mA
V
I
Note 2
25
DD
V
0.8
IL
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input Capacitance
Load Capacitance
Input Low Current
2.0
V
IH
V
I
I
I
= 8 mA
0.4
10
V
OL
OL
OH
OH
V
= –0.1 mA
= –4 mA
V
– 0.4V
DD
V
OH
V
2.4
V
OH
C
Except X1, X2
pF
pF
µA
µA
kΩ
I
C
Pins X1, X2 (except for -36)
10
L
I
V
V
V
= 0V (includes pull-up resistor)
–100
IL
IH
IN
IN
IN
I
Input High Current
Input Pull-Up Resistor
= V
10
DD
R
= 0V
250
P
AC Characteristics: T = 0°C to +70°C; V = 5V ± 10%
A
DD
Parameter
Description
Min
2
Typ
Max
120
32
Unit
MHz
MHz
ns
F
F
T
T
T
T
Output Frequency
Input Frequency
O
I
2
14.318
Output Rise Time, 0.8 to 2.0V, 25-pF Load
1
2
2
R
R
F
F
Output Rise Time, 20 to 80% V , 25-pF Load
4
ns
CC
Output Fall Time, 2.0 to 0.8V, 25-pF Load
1
2
ns
Output Fall Time, 80 to 20% V , 25-pF Load
2
4
ns
CC
D
Duty Cycle, 15-pF Load
40
50
60
%
T
T
T
T
Jitter, 1 Sigma, All Frequencies
Jitter, Absolute, All Frequencies
Powerup Time, Off to stated output frequency
±150
±250
30
ps
J1S
JABS
PU
ps
15
ms
Note:
2. W42C27 with no load. Power supply current varies with frequency.
3
W42C27
Electrical Characteristics at 3.3V
DC Electrical Characteristics: T = 0°C to +70°C; V = 3.3V ± 5%
A
DD
Parameter
Description
Operating Supply Current
Input Low Voltage
Conditions
Min
Typ
Max
Unit
mA
V
I
Note 2
20
DD
V
0.8
IL
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input Capacitance
Load Capacitance
Input Low Current
2.0
2.4
V
IH
V
I
I
= 8 mA
0.4
10
V
OL
OL
V
= –4 mA
V
OH
OH
C
Except X1, X2
Pins X1, X2
pF
pF
µA
µA
kΩ
I
C
10
L
I
I
V
V
V
= 0V (includes pull-up resistor)
–100
IL
IH
IN
IN
IN
Input High Current
Input Pull-Up Resistor
= V
10
DD
R
= 0V
250
P
AC Characteristics: T = 0°C to +70°C; V = 3.3V ± 5%
A
DD
Parameter
Description
Min
Typ
Max
110
32
Unit
MHz
MHz
ns
F
F
Output Frequency
Input Frequency
2
2
O
I
14.318
ICLK
ICLK
Input Clock Rise Time
Input Clock Fall Time
20
R
20
ns
F
T
T
Output Rise Time, 20 to 80% V , 25-pF Load
2
2
4
ns
R
F
CC
Output Fall Time, 80 to 20% V , 25-pF Load
4
ns
CC
D
Duty Cycle, 15-pF Load
40
50
60
%
T
T
T
T
Jitter, 1 Sigma, All Frequencies
Jitter, Absolute, All Frequencies
Powerup Time, Off to stated output frequency
±150
±250
30
ps
J1S
ps
JABS
PU
15
ms
4
W42C27
Recommended Circuit Configuration
VDD
Optional
Ferrite
Bead
AGND
GND
AVDD
VDD
0.1
F
F
µ
2.2
F
µ
0.1
µ
power supply rejection. For further EMI protection, the V
connection can be made via a ferrite bead, as shown.
Recommended Circuit Configuration
DD
For optimum performance in system applications, the above
power supply decoupling scheme should be used. GND pins
are connected directly to the ground plane.
When using the W42C27, unused input select pins may be tied
to either ground or V , or may be left unconnected. Since
DD
internal pull-up resistors are incorporated on all logic input
pins, an unconnected input will assume a logic 1 condition.
Output clocks should use a series termination resistor (about
33Ω) placed as close to the clock outputs as possible; this will
also help to decrease jitter, EMI and clock signal ringing.
V
decoupling is important to reduce phase jitter and EMI
DD
F
radiation. The 0.1-µ decoupling capacitor should be placed
as close to the V pins as possible, otherwise the increased
DD
trace inductance will negate its decoupling capability. The
F
2.2-µ decoupling capacitor shown is optional but will improve
Ordering Information
Freq. Mask
Code
Package
Name
Ordering Code
W42C27
Package Type
36, 41
G
8-pin SOIC (150-mil)
Document #: 38-00804
5
W42C27
Package Diagrams
8-Pin Small Outline Integrated Circuit, Narrow (SOIC, 0.150 inch)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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