W42S51-01H [CYPRESS]
Clock Generator, CMOS, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | W42S51-01H |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, CMOS, PDSO48, 0.300 INCH, SSOP-48 光电二极管 |
| 文件： | 总18页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W42S51-01
3 DIMM Desktop System Clock
Features
• Maximized EMI suppression using IC WORKS’ Spread
Spectrum Technology
• Separate supply pins for CPU and IOAPIC output buffers:
VDDQ2 = 2.5V ± 5%
• Generates system clocks for 2.5/3.3V based designs:
VDDQ3 = 3.3V ± 5%
- 4 CPU clocks with 2.5V output swing
- 12 SDRAM clocks; supports up to 3DIMM modules
- 7 PCI clocks
• No power supply sequence requirements
• Uses external 14.318MHz crystal
• Available in 48-pin SSOP (300 mils)
- 2 IOAPIC clock: supports dual processor applications
• One copy of Ref. Clock @ 14.31818MHz
• Serial data interface (SDATA, SCLOCK inputs) provides
additional CPU/PCI clock frequency selections, individual
output clock disabling and other functions
Figure 1 Block Diagram
Figure 2 Pin Diagram
VDDQ3
REF0
GND
X1
X2
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
SDATA
SCLOCK
VDDQ3
REF0
IOAPIC0
IOAPIC1
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5/PWR_DWN#
VDDQ3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
GND
Serial Port
Device Control
VDDQ2
IOAPIC0-1
XTAL
OSC
X1
X2
2
4
PLL Ref Freq
Stop
Clock
9
CPU0-3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDQ3
12
SDRAM0-11
PLL
GND
PCI_F
PCI0-5
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
÷2
6
Stop
Clock
OE
I/O Control
MODE
SDATA
SCLOCK
OE
MODE
Table 2 Order Information
Table 1 Power-Up Frequency Selection
Freq. Mask
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Part Number
Code
Package
H = SSOP (300 mils)
OE
W42S51
01
0
1
Hi-Z
66.6
Hi-Z
33.3
October 1998
IC WORKS · 3725 North First Street · San Jose, CA 95134-1700 · (408) 922-0202
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 1 of 18
W42S51-01
Pin Definitions
Pin
Pin
Pin Name
No.
Type
Pin Description
CPU0:3
44, 43
41, 40
O
O
O
O
CPU Clock Outputs 0 through 3: These four CPU clock outputs are con-
trolled by the CPU_STOP# control pin. Output voltage swing is controlled by
voltage applied to VDDQ2.
PCI0:5
PCI_F
8, 10, 11,
12, 13, 15
PCI Bus Clock Outputs 0 through 5: These six PCI clock outputs are con-
trolled by the PCI_STOP# control pin. Output voltage swing is controlled by
voltage applied to VDDQ3.
7
Fixed PCI Clock Output: Unlike PCI0:5 outputs, this output is not controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM0:4 &
SDRAM8:11
38, 37, 35,
34, 32,21,
20, 18, 17
SDRAM Clock Outputs: These nine SDRAM clock outputs run synchronous
to the CPU clock outputs. Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM5/
PWR_DWN#
31
I/O
SDRAM Clock Output 5 or Power Down Control: This pin has dual func-
tions, selectable by the MODE input pin. When MODE = 0, this pin becomes
the PWR_DWN# input. When MODE = 1, this pin becomes SDRAM clock
output 5, and behaves like the dedicated SDRAM ouputs.
Power Down Control: When this input is low, device goes into a low power
standby condition. All outputs are actively held low while in power down.
CPU, SDRAM and PCI clock outputs are stopped low after completing a full
clock cycle (2-4 CPU clock cycle latency). When brought high, CPU, SDRAM
and PCI outputs start with a full clock cycle at full operating frequency (3ms
maximum latency)
SDRAM6/
CPU_STOP#
29
I/O
SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the CPU_STOP# input. When MODE = 1, this pin becomes
SDRAM clock output 6, and behaves like the dedicated SDRAM ouputs.
Regarding use as a CPU_STOP# input: When brought low, clock outputs
CPU0:3 are stopped low after completing a full clock cycle (2-3 CPU clock
latency). When brought high, clock outputs CPU0:3 are starting beginning
with a full clock cycle (2-3 CPU clock latency). Refer to timing diagram xx.
SDRAM7/
PCI_STOP#
28
I/O
SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the PCI_STOP# input. When MODE = 1, this pin becomes
SDRAM clock output 7, and behaves like the dedicated SDRAM ouputs.
PCI_STOP# input: When brought low, clock outputs PCI0:5 are stopped low
after completing a full clock cycle. When brought high, clock outputs PCI0:5
are starting beginning with a full clock cycle. Clock latency provides one
PCI-F rising edge of PCI clock following PCI_STOP# state change.
IOAPIC0:1
REF0
47, 46
2
O
O
I
I/O APIC Clock Output: Provides 14.318MHz fixed frequency. The output
voltage swing is controlled by VDDQ2
Fixed 14.318MHz Outputs: Used for various system applications. Output
voltage swing is controlled by voltage applied to VDDQ3.
OE
26
Output Enable Control: When this pin is low it puts all outputs into a high
impedance state. When brought high, outputs are active.
3 DIMM Desktop System Clock
Page 2 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
Pin Definitions (cont.)
Pin
Pin
Pin Name
No.
Type
Pin Description
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318MHz crystal connection
or as an external reference frequency input.
X2
5
I
I
Crystal Connection: An input connection for an external 14.318MHz crystal.
If using an external reference, this pin must be left unconnected.
MODE
25
Mode Control: This input selects the function of device pin 28
(SDRAM7/PCI_STOP#), pin 29 (SDRAM6/CPU_STOP#) and pin 31
(SDRAM5/PWR_DWN#). Refer to descriptions for those pins.
SDATA
SCLOCK
VDDQ3
VDDQ2
GND
23
24
I/O
I
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
1, 6, 14,
19, 30, 36
P
Power Connection: Power supply for PCI, REF, and SDRAM output buffers.
Connected to 3.3V supply.
42, 48
P
Power Connection: Power supply for CPU0:3 & IOAPIC0:1output buffers.
Connected to 2.5V supply.
3, 9, 16,
22, 27, 33,
39, 45
G
Ground Connection: Connect all ground pins to the common system
ground plane.
3 DIMM Desktop System Clock
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 3 of 18
W42S51-01
Spread Spectrum Clock Generation
The benefits of using Spread Spectrum Clock Generation are
depicted in Figure 3. An EMI emission profile of a clock har-
monic is shown.
clock. This spike can make systems fail quasi-peak EMI test-
ing. The FCC and other regulatory agencies test for peak
emissions. With the IC Works clock, the peak energy is much
lower (at least 8dB) because the energy is spread out across
a wider bandwidth.
Contrast the typical clock EMI with the IC WORKS Spread
Spectrum Clock Generation. Notice the spike in the typical
Figure 3 Typical Clock and SSCG Comparison
5dB/div
SSFTG
Typical Clock
3 DIMM Desktop System Clock
Page 4 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
Serial Data Interface
The W42S51-01 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W42S51-01
initializes with default register settings, therefore the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are nor-
mally made upon system initialization, if any are required.
The interface an also be used during system operation for
power management functions. Table 3 summarizes the con-
trol functions of the serial data interface.
Table 3 Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held low.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond
the selections that are otherwise provided.
For alternate CPU devices, and power man-
agement options.
Output Tristate
Puts all clock outputs into a high impedance
state.
Production PCB testing.
Test Mode
All clock outputs toggle in relation with X1 input,
internal PLL is bypassed. Refer to Table 5.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be
written as 0.
3 DIMM Desktop System Clock
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Page 5 of 18
W42S51-01
Operation
Data is written to the W42S51-01 in ten bytes of eight bits each. Bytes are written in the order shown in Table 4.
Table 4 Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W42S51-01 to accept the bits in Data Bytes 0-6 for
internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to have a specific slave
address for each potential receiver. The slave receiver address for
the W42S51-01 is 11010010. Register setting will not be made if the
Slave Address is not correct (or is for an alternate slave receiver).
2
3
Command Code
Byte Count
Don’t Care
Unused by the W42S51-01, therefore bit values are ignored (don’t
care). This byte must be included in the data write sequence to main-
tain proper byte allocation. The Command Code Byte is part of the
standard serial communication protocol and may be used when writ-
ing to another addressed slave receiver on the serial data bus.
Don’t Care
Unused by the W42S51-01, therefore bit values are ignored (don’t
care). This byte must be included in the data write sequence to main-
tain proper byte allocation. The Byte Count Byte is part of the stan-
dard serial communication protocol and may be used when writing to
another addressed slave receiver on the serial data bus.
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Refer to Table 5
The data bits in Data Bytes 0-6 set internal W42S51-01 registers that
control device operation. The data bits are only accepted when the
Address Byte bit sequence is 11010010, as noted above. For descrip-
tion of bit control functions, refer to Table 5, Data Byte Serial Configu-
ration Map.
6
7
8
9
10
3 DIMM Desktop System Clock
Page 6 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
W42S51-01Writing Data Bytes
Each bit in Data Bytes 0-6 control a particular device function
except for the "reserved" bits which must be writting as a
logic 0. Bits are written MSB (most significant bit) first, which
is bit 7. Table 5 gives the bit formats for registers located in
Data Bytes 0-6. Table 7 details the select functions for Byte
0, bits 1 and 0.
Table 5 Data Bytes 0-7 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
5
4
3
--
--
--
--
--
--
--
--
--
--
(Reserved)
(SEL_2)
--
--
0
0
0
0
0
Refer to Table 6
Refer toTable 6
Refer toTable 6
(SEL_1)
(SEL-0)
(BYTE0-FS#)
Refer to Table 1
Frequency controlled
by BYTE0-SEL(2:0)
2
--
--
--
--
(Reserved)
--
--
0
1-0
Bit 1
0
Bit 0
0
Function
00
Normal Operation
1
0
1
0
1
1
Spread Spectrum ON
Test Mode (Refer to Table 7)
All Outputs Tristated
Data Byte 1
7
6
5
4
3
2
1
0
--
--
--
--
(Reserved)
--
--
--
--
0
0
0
0
1
1
1
1
(Reserved)
--
--
(Reserved)
--
--
--
--
(Reserved)
--
--
40
41
43
44
CPU3
CPU2
CPU1
CPU0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
Data Byte 2
7
6
5
4
3
2
1
0
--
7
--
(Reserved)
--
--
0
1
1
1
1
1
1
1
PCI_F
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
15
13
12
11
10
8
Data Byte 3
7
28
SDRAM7
Clock Output Disable
Low
Active
1
3 DIMM Desktop System Clock
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 7 of 18
W42S51-01
Table 5 Data Bytes 0-7 Serial Configuration Map (cont.)
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
6
5
4
3
2
1
0
29
31
32
34
35
37
38
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
1
Data Byte 4
7
6
5
4
3
2
1
0
--
--
--
--
(Reserved)
--
--
--
--
0
0
0
0
1
1
1
1
(Reserved)
--
--
(Reserved)
--
--
--
--
(Reserved)
--
--
17
18
20
21
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
Data Byte 5
7
6
5
4
3
2
1
0
--
--
--
(Reserved)
--
--
--
--
0
0
1
1
0
0
0
1
--
(Reserved)
46
47
--
IOAPIC1
Clock Output Disable
Clock Output Disable
(Reserved)
Low
Low
--
Active
Active
--
IOAPIC0
--
--
--
(Reserved)
--
--
--
--
(Reserved)
--
--
2
REF0
Clock Output Disable
Low
Active
Data Byte 6
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
3 DIMM Desktop System Clock
Page 8 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
Table 6 Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Data Byte 0, Bit 3 = 1
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM Clocks
(MHz)
PCI Clocks
(MHz)
Spread %
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
60
30
30
± 0.5%
±0.9%
±0.5%
±0.9%
±0.5%
±0.9%
-1%
60
68.5
68.5
66.8
66.8
66.6
66.6
34.25
34.25
33.4
33.4
33.3
33.3
-0.5%
Table 7 Select Function for Byte 0, Bits 0:1
Input Conditions
Byte 0
Output Conditions
PCI_F,
CPU0:3,
REF0,
Function
Bit 1
Bit 0
SDRAM0:11
PCI0:5
IOAPIC0:1
Normal Operation
Test Mode
0
0
1
0
1
0
Note 1
X1/2
Note 1
X1/4
14.318MHz
X1
Spread Spectrum
On
Note 1 and
Table 6
Note 1 and
Table 6
14.318MHz
Tristate
1
1
Hi-Z
Hi-Z
Hi-Z
Notes: 1. CPU, SDRAM and PCI frequency selections are listed in Tables 1, 6.
3 DIMM Desktop System Clock
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 9 of 18
W42S51-01
How To Use the Serial Data Interface
Electrical Requirements
Figure 4 illustrates electrical characteristics for the serial interface bus used with the W42S51-01. Devices send data over the
bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. The pull-up resistor on
the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data.
Although the W42S51-01 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse
after each byte is received. Thus, the SDATA line can both transmit and receive data.
The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total
bus line capacitance.
Figure 4 Serial Interface Bus Electrical Characteristics
VDD
VDD
~ 2k
W
~ 2kW
SERIAL BUS DATA LINE
SERIAL BUS CLOCK LINE
SDCLK
SDATA
SCLOCK
SDATA
CLOCK IN
DATA IN
CLOCK IN
DATA IN
DATA OUT
N
N
N
CLOCK OUT
DATA OUT
CHIP SET
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
(SERIAL BUS MASTER TRANSMITTER)
3 DIMM Desktop System Clock
Page 10 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
Signaling Requirements
Sending Data to the W42S51-01
As shown in Figure 5, valid data bits are defined as stable
logic 0 or 1 condition on the data line during a clock high
(logic 1) pulse. A transitioning data line during a clock high
pulse may be interpreted as a start or stop pulse (it will be
interpreted as a start or stop pulse if the start/stop timing
parameters are met).
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double
buffered). Partial transmission is allowed meaning that a
transmission can be truncated as soon as the desired data
bits are transmitted (remaining registers will be unmodified).
Transmission is truncated with either a stop bit or new startbit
(restart condition).
A write sequence is initiated by a "start bit" as shown in Fig-
ure 6. A "stop bit" signifies that a transmission has ended.
As stated previously, the W42S51-01 sends an "acknowl-
edge" pulse after receiving eight data bits in each byte as
shown in Figure 7.
Figure 5 Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 6 Serial Data Bus Start and Stop Bit
SDATA
SCLOCK
Start
Bit
Stop
Bit
3 DIMM Desktop System Clock
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 11 of 18
W42S51-01
Figure 7 Serial Data Bus Write Sequence
Figure 8 Serial Data Bus Timing Diagram
3 DIMM Desktop System Clock
Page 12 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other con-
ditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Symbol
VDD, VIN
TSTG
Parameter
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
Voltage on any pin with respect to GND
Storage Temperature
°C
°C
°C
kV
TB
Ambient Temperature under Bias
Operating Temperature
Input ESD Protection
TA
ESDPROT
2 (min)
DC Electrical Characteristics:
T = 0°C to +70°C, VDDQ3 = 3.3V±5% , VDDQ2 = 2.5V±5%
A
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
Supply Current
IDD
3.3V Supply Current
2.5V Supply Current
300
50
mA
mA
CPU0:3 = 66.6MHz
Outputs Loaded (Note 1)
IDD
CPU0:3= 66.6MHz
Outputs Loaded (Note 1)
Logic Inputs
VIL
VIH
IIL
Input Low Voltage
0.8
V
V
Input High Voltage
2.0
Input Low Current (Note 2)
Input High Current (Note 2)
10
10
µA
µA
IIH
Clock Outputs
VOL
VOH
VOH
IOL
Output Low Voltage
50
mV
V
IOL = 1mA
Output High Voltage
3.1
2.2
IOH = –1mA
IOH = –1mA
VOL = 1.25V
Output High Voltage (CPU, IOAPIC)
V
Output Low Current:
CPU0:3
55
80
75
110
75
105
155
105
190
90
mA
SDRAM0:11
PCI_F, PCI0:5
IOAPIC0:1
REF0
55
100
60
135
75
IOH
Output High Current:
CPU0:3
55
85
125
mA
VOH = 1.25V
SDRAM0:11
PCI_F, PCI0:5
IOAPIC0:1
REF0
80
55
120
85
175
125
220
110
100
60
150
85
Crystal Oscillator
3 DIMM Desktop System Clock
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 13 of 18
W42S51-01
DC Electrical Characteristics:
T = 0°C to +70°C, VDDQ3 = 3.3V±5% , VDDQ2 = 2.5V±5% (cont.)
A
Symbol
VTH
Parameter
Min
Typ
1.65
14
Max
Unit
V
Test Condition
X1 Input threshold Voltage (Note 3)
CLOAD
Load Capacitance, As seen by
External Crystal (Note 4)
pF
CIN,X1
X1 Input Capacitance (Note 5)
28
pF
Pin X2 unconnected
Except X1 and X2
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
5
6
7
pF
pF
nH
COUT
LIN
Output Pin Capacitance
Input Pin Inductance
Serial Input Port
VIL
VIH
IIL
Input Low Voltage
0.3VDD
V
V
VDD = 3.3V
VDD = 3.3V
Input High Voltage
Input Low Current
Input High Current
0.7VDD
10
10
µA
µA
mA
IIH
IOL
Sink Current into SDATA or SCLOCK,
Open Drain N-Channel Device On
6
IOL = 0.3VDD
CIN
Input Capacitance of SDATA and SCLOCK
Total Capacitance of SDATA Bus
10
pF
pF
pF
CSDATA
CSCLOCK
--
--
--
--
400
400
Total Capacitance of SCLOCK Bus
Notes: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
2. W42S51-01 logic inputs have internal pull-up devices (not CMOS level).
3. X1 input threshold voltage (typical) is VDDQ3/2.
4. The W42S51-01 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2
and ground. Total load placed on crystal is 14pF; this includes typical stray capacitance of short PCB traces to
crystal.
5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
3 DIMM Desktop System Clock
Page 14 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
AC Electrical Characteristics:
T = 0°C to +70°C, VDDQ3 = 3.3V±5% , VDDQ2 = 2.5V±5%
A
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load
at the clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz
CPU = 60MHz
Symbol Parameter
Min
Typ
Max
Min
Typ
Max Unit Test Condition/Comments
ns Measured on rising edge at 1.5V.
MHz Determined by PLL divider ratio.
tP
Period
15
16.7
f
Frequency, Actual
High Time
66.6
59.876
tH
5.2
5
6
5.8
1
ns
ns
Duration of clock cycle above 2.0V.
Duration of clock cycle below 0.4V.
tL
Low Time
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
1
4
4
4
4
V/ns Measured from 0.4V to 2.0V.
V/ns Measured from 2.0V to 0.4V.
1
1
tD
tJC
45
55
250
45
55
250
%
Measured on rising and falling edge at 1.25V.
Jitter, Cycle-to-Cycle
ps
Measured on rising edge at 1.25V. Maximum
difference of cycle time between two adjacent
cycles.
tSK
fST
Output Skew
250
3
250
3
ps
Measured on rising edge at 1.25V.
Frequency Stabilization
from Power-up (cold start)
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
22
22
ohm Average value during switching transition. Used
for determining series termination value.
SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30pF)
CPU = 66.6MHz
CPU = 60MHz
Symbol Parameter
Min
Typ
Max
Min
Typ
Max Unit Test Condition/Comments
ns Measured on rising edge at 1.5V.
tP
Period
15
16.7
f
Frequency, Actual
66.6
59.876
MHz Determined by PLL divider ratio.
V/ns Measured from 0.4V to 2.4V.
tR
Output Rise Edge Rate
1
1
4
4
1
1
4
4
tF
Output Fall Edge Rate
Duty Cycle
V/ns Measured from 2.4V to 0.4V.
tD
45
55
250
45
55
250
%
Measured on rising and falling edge at 1.5V.
tJC
Jitter, Cycle-to-Cycle
ps
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
tSK
tSK
Output Skew
100
100
ps
ps
Measured on rising edge at 1.5V.
CPU to SDRAM Clock
Skew
500
3
500
3
Covers all CPU/SDRAM outputs. Measured on
rising edge at 1.5V.
fST
Frequency Stabilization
from Power-up (cold start)
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
16
16
ohm Average value during switching transition. Used
for determining series termination value.
3 DIMM Desktop System Clock
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 15 of 18
W42S51-01
AC Electrical Characteristics:
T
= 0°C to +70°C, VDDQ3 = 3.3V±5% , VDDQ2 = 2.5V±5% (cont.)
A
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30pF)
CPU = 66.6MHz
CPU = 60MHz
Symbol Parameter
Min
Typ
Max
Min
Typ
Max Unit Test Condition/Comments
ns Measured on rising edge at 1.5V.
MHz Determined by PLL divider ratio.
tP
Period
30
33.3
f
Frequency, Actual
High Time
33.3
29.938
tH
12
12
1
13.3
13.3
1
ns
ns
Duration of clock cycle above 2.4V.
Duration of clock cycle below 0.4V.
tL
Low Time
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
4
4
V/ns Measured from 0.4V to 2.4V.
V/ns Measured from 2.4V to 0.4V.
1
1
tD
tJC
45
55
250
45
55
250
%
Measured on rising and falling edge at 1.5V.
Jitter, Cycle-to-Cycle
ps
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
tSK
tO
Output Skew
250
4
250
4
ps
ns
Measured on rising edge at 1.25V.
CPU to PCI Clock Offset
1
1
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
fST
Frequency Stabilization
from Power-up (cold start)
3
3
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
30
30
ohm Average value during switching transition. Used
for determining series termination value.
IOAPIC0:1 Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 60/66.6MHz
Symbol Parameter
Min
Typ
Max
Unit
Test Condition/Comments
f
Frequency, Actual
14.31818
MHz
V/ns
Frequency generated by crystal oscillator.
Measured from 0.4V to 2.0V.
tR
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
1
1
4
4
tF
V/ns
%
Measured from 2.0V to 0.4V.
tD
45
55
1.5
Measured on rising and falling edge at 1.5V.
fST
Frequency Stabilization from
Power-up (cold start)
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
15
ohm
Average value during switching transition. Used
for determining series termination value.
Serial Input Port
Symbol Parameter
Min
0
Typ
Max
Unit
kHz
µs
Test Condition
fSCLOCK SCLOCK Frequency
100
Normal Mode
tSTHD
tLOW
tHIGH
Start Hold Time
4.0
4.7
4.0
SCLOCK Low Time
SCLOCK High Time
µs
µs
3 DIMM Desktop System Clock
Page 16 of 18
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
W42S51-01
Serial Input Port
Symbol Parameter
Min
250
0
Typ
Max
Unit
ns
Test Condition
tDSU
tDHD
Data Setup Time
Data Hold Time
ns
(Transmitter should provide a 300ns hold time to
ensure proper timing at the receiver.)
tR
tF
Rise Time, SDATA and
SCLOCK
1000
300
ns
ns
From 0.3VDD to 0.7VDD
Fall Time, SDATA and
SCLOCK
From 0.7VDD to 0.3VDD
tSTSU
tSPF
Stop Setup Time
4.0
4.7
µs
µs
Bus Free Time between Stop
and Start Condition
tSP
Allowable Noise Spike Pulse
Width
50
ns
3 DIMM Desktop System Clock
IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
Page 17 of 18
W42S51-01
Mechanical Package Outline
Figure 948-Pin SSOP (300 mils) - Shrink Small Outline Package
:
IC WORKS, Inc. reserves the right to amend or discontinue this product without notice. Cir-
cuit and timing diagrams used the describe IC WORKS product operations and applications
are included as a means of illustrating a typical product application. Complete information
for design purposes is not necessarily given. This information has been carefully checked
and is believed to be entirely reliable. IC WORKS, however, will not assume any responsibil-
ity for inaccuracies.
Life Support Applications:
IC WORKS products are not designed for use in life support applications, devices, or sys-
tems where malfunctions of the IC WORKS product can reasonably be expected to result in
personal injury. IC WORKS customers using or selling IC WORKS products for use in such
applications do so at their own risk and agree to fully indemnify IC WORKS for any damages
resulting in such improper use or sale.
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IC WORKS DOCUMENT CONTROL : FDS-016 : REV 0
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