ES51998中文资料_数据手册_规格书

ES51998(60000counts)

DMM Analog front end/Insulation

Description

Features

ES51998 is an analog frond end chip of

DMM built-in 60000(SADC)/600(FADC)

counts dual ADCs. The SADC is operated at

slower speed for higher resolution. The

FADC is operated at higher speed for lower

resolution. ES51998 provides voltage &

current (AC/DC) measurement, resistance

measurement, capacitance measurement,

diode/continuity measurement, frequency

measurement, duty cycle measurement and

voltage peak-hold function. An analog

switches network is built-in for insulation

resistance application. The ES51998 also

supports multi-level battery detection,

low-pass-filter feature for AC mode and dual

mode measurement for V+F & A+F. A 3-wire

serial bus for MPU I/O port will be used

easily for firmware design. Flexible function

design is supported for different kinds of

DMM or Clamp-on meter application.

• 60000 counts dual-slope SADC (2 cnvs/s.)

• Input signal full scale: 630mV (Max. 63000 count)

• Built-in 600 counts fast speed (x10) FADC

• Fast ADC conversion rate: 20 times/s

• 100L LQFP package

• 3V DC regulated power supply

• Support digital multi-meter function

*Voltage measurement (AC/DC)

*Current measurement (AC/DC)

*Dual mode for frequency with voltage or current

*Resistance measurement (600.00Ω – 60.000MΩ)

*Conductance measurement (60.00nS)

*Capacitance measurement (6.000nF – 60.00mF)

(Taiwan patent no.: 323347, 453443)

*Diode or continuity mode measurement

*Frequency counter with duty cycle display:

60.000Hz – 60.000MHz

5.0% – 95.0%

• ADP mode (AC or DC mode is available)

• 3dB BW selectable for low pass filter at AC mode

(Taiwan patent no.: 362409)

(China patent no.: 1363073)

.

• Band-gap reference voltage output

• Peak-hold measurement

(Taiwan patent no.:476418)

• 3-wire serial bus for MPU I/O port

• MPU I/O power level selectable by external pins

• On-chip buzzer driver and frequency selectable by

MPU command

• High-crest-factor signal detection

(Taiwan patent no.: 234661)

• Multi-level battery voltage detection

• Support sleep mode by external chip select pin

Application

Clamp-on meter

Digital multi-meter

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12/01/12

ES51998(60000counts)

DMM Analog front end/Insulation

Pin Assignment

1

2

3

4

5

6

D

C

B

A

1

75

BUFH

2

NC

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CAZH

3

NC

4

CL+

5

CL-

6

CIL

7

CAZL

8

BUFL

RAZ

C

B

A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

OHMC3

OHMC2

OHMC1

VRH

FREQ

STBEEP

CPKIN

P MA X

P MI N

LPFOUT

LPC3

LPC2

LPC1

R1K

ES51998

VA+

VA-

EXTSRC

I RVH1

I RVH0

OR1

VR5

VR4

R9K

VR3

NC

VR2

NC

OVSG

VR1

NC

1

2

3

4

5

6

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12/01/12

ES51998(60000counts)

DMM Analog front end/Insulation

Pin Description

Pin No

Symbol

BUFH

CAZH

NC

Type

Description

1

2

3

O

-

High-speed buffer output pin. Connect to integral resistor.

High-speed auto-zero capacitor connection.

Not connected

4

5

CL+

CL-

IO Positive connection for reference capacitor of high-resolution A/D.

IO Negative connection for reference capacitor of high- resolution A/D.

6

7

8

9

10

11

12

13

14

CIL

O

I

High-resolution integrator output. Connect to integral capacitor.

High-resolution auto-zero capacitor connection.

High-resolution Buffer output pin. Connect to integral resistor

Buffer output pin in AZ and ZI phase.

Filter capacitor connection for resistance mode.

Output of band-gap voltage reference. Typically –1.23V

De-integrating voltage positive input. The input should be higher than

VA-.

CAZL

BUFL

RAZ

OHMC3

OHMC2

OHMC1

VRH

VA+

15

VA-

I

De-integrating voltage negative input. The input should be lower than

VA+.

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

EXTSRC

IRVH1

IRVH0

OR1

VR5

VR4

VR3

VR2

OVSG

VR1

OVX

OVH

OVH1

IRR5

IRR4

IRR3

IRR2

IRR1

IRVG

IRVL

SGND

IVSH

I

O

I

External source input available for Res/Diode/ADP mode

High voltage measurement range1 for insulation R mode

High voltage measurement range0 for insulation R mode

Reference resistor connection for 600.00Ω range

Voltage measurement ÷10000 attenuator(1000.0V)

Voltage measurement ÷1000 attenuator(600.00V)

Voltage measurement ÷100 attenuator(60.000V)

Voltage measurement ÷10 attenuator(6.0000V)

Sense low voltage for resistance/voltage measurement

Measurement Input. Connect to a precise 10MΩ resistor.

Sense input for resistance/capacitance measurement

Output connection for resistance measurement

Output connection1 for resistance measurement (optional)

Test mode used (optional)

Current shunt resistor4 connection for insulation R mode

Current shunt resistor3 connection for insulation R mode

Current shunt resistor2 connection for insulation R mode

Current shunt resistor1 connection for insulation R mode

Voltage measurement terminal low-side of shunt resistor

Voltage measurement terminal high-side of shunt resistor

Signal Ground.

I

O

I

G

I

Current measurement input for 6000.0μA, 600.00mA and 60.000A

modes.

38

39

40

41

42

43

IVSL

ADP

OPIN-

OPIN+

OPOUT

ACVL

I

O

Current measurement input for 600.00μA, 60.000mA.

Measurement input in ADP mode.

Independent operational amplifier negative input

Independent operational amplifier positive input

Independent operational amplifier output

DC signal low input in ACV/ACA mode. Connect to negative output

of external AC to DC converter.

44

ACVH

O

DC signal high input in ACV/ACA mode. Connect to positive output

of external AC to DC converter.

45

46

47

48

ADI

ADO

TEST5

CA-

I

O

Negative input of internal AC-to-DC OPAMP.

Output of internal AC-to-DC OPAMP.

Buffer output of OVSG

IO Negative auto-zero capacitor connection for capacitor measurement

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ES51998(60000counts)

DMM Analog front end/Insulation

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

CA+

OHMC4

NC

R9K

IO Positive auto-zero capacitor connection for capacitor measurement

O

-

Filter capacitor connection for resistance mode.

Not connected

-

Not connected

-

Not connected

-

Not connected

O

I

Connect to a precise 9KΩ resister for capacitor measurement.

Connect to a precise 1KΩ resister for capacitor measurement.

Capacitor C1 connection for internal low-pass filter

Capacitor C2 connection for internal low-pass filter

Capacitor C3 connection for internal low-pass filter

Capacitor C1 connection for internal low-pass filter

Minimum peak hold output

R1K

LPC1

LPC2

LPC3

LPFOUT

PMIN

PMAX

CPKIN

STBEEP

Maximum peak hold output.

Bypass capacitor for peak mode

O

Fast low-impedance sensed output for CONT./Diode mode Build-in a

internal comparator for OVX pin.

65

66-77

78

79

80

81

82

83

FREQ

NC

OSC2

OSC1

CS

IO_CTRL

BZOUT

NC

I

-

O

I

Frequency counter input, offset V-/2 internally by the chip.

Not connected

Crystal oscillator output connection

Crystal oscillator input connection

Set to high to enable ES51998. Set to low to enter sleep mode

MPU I/O level LOW setting. Connect to DGND or V-.

Buzzer frequency output. Normal low state.

Not connected

I

-

84

85

86

87

88

89

90

DATA_NEW

SCLK

SDATA

C+

O

I

New ADC data ready

Serial clock input

IO Serial data input/output

O

I

Positive capacitor connection for on-chip DC-DC converter.

Negative capacitor connection for on-chip DC-DC converter.

Low battery configuration input.

Negative supply voltage.

C-

LBAT

V-

P

91

V-

P

Negative supply voltage.

92

93

94

95

96

97

98

99

uPVCC

V+

DGND

AGND

CH+

P

Switch 5 for function selection.

Output of on-chip DC-DC converter.

Digital ground.

Analog ground.

O

G

IO Positive connection for reference capacitor of high-speed A/D.

IO Negative connection for reference capacitor of high-speed A/D.

CH-

100

CIH

O

High-speed integrator output. Connect to integral capacitor.

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ES51998(60000counts)

DMM Analog front end/Insulation

Absolute Maximum Ratings

Characteristic

Supply Voltage (V- to AGND)

Analog Input Voltage & EXTSRC pin

V+

Rating

-4V

V- -0.6 to V+ +0.6

V+ ≥ (AGND/DGND+0.5V)

AGND/DGND

AGND/DGND ≥ (V- -0.5V)

V- -0.6 to uPVCC+0.6

500mW

Digital Input (IO_CTRL=V-)

Power Dissipation. Flat Package

Operating Temperature

0℃ to 70℃

Storage Temperature

-55℃ to 125℃

Electrical Characteristics

TA=25℃, V- = -3.0V

Parameter

Power supply

Operating supply current

In DCV mode

SADC²Voltage roll-over error

FADC³Voltage roll-over error

Symbol

V-

I_DD

Test Condition

Min.

-2.8

—

Typ.

-3.0

2.8

Max

-3.2

3.2

Units

V

mA

Normal operation

In sleep mode

I_SS

1

3

µA

—

10MΩ input resistor

±0.01 %F.S¹

±0.5 %F.S¹

—

10MΩ input resistor

Best case straight

line

Best case straight

line

VA+-VA- = 200mV

SADC²voltage nonlinearity

NLV1

NLV2

±0.01 %F.S¹

—

FADC³voltage nonlinearity

±1.0 %F.S¹

Voltage full scale range of SADC²

Voltage full scale range of FADC³

Input Leakage for VR1 input

Zero input reading

600

1

630

—

mV

pA

—

-10

10

10MΩ input resistor -000

000

+000 Count

Band-gap reference voltage

100KΩ resistor

V_RH

between VRH and

AGND

-1.30

-1.22

-1.14

V

Open circuit voltage for 600Ω range

measurement

Open circuit voltage for other Ω

measurement

Open circuit voltage for 60.00nS

range measurement

—

V-

V

V_RH

-0.68

Between V- pin and

CS

Internal pull-high to 0V

current

—

1.2

µA

AC frequency response at 6.000V

range

±1%

40-400

400-2000

200

—

HZ

±5%

C_L=10pF

R_L=10MΩ

OP unity gain bandwidth

OP slew rate at unity gain

OP input offset voltage

OP input bias current

GB

SR

V_IO

I_B

kHz

V/us

mV

pA

3.5

0.1

10

OP input common mode

voltage range

—

V_ICR

+2

V

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ES51998(60000counts)

DMM Analog front end/Insulation

3dB=Full (ADP)

3dB=10k (ADP)

3dB=1k (ADP)

—

10

—

100

—

kHz

V

3dB frequency for LPF⁴active

f_3dB

1

V_t1

V_t2

V_t3

2.15

2.03

1.83

Multi-level low battery detector

Peak-hold mode pulse width

LBAT vs. V-

V

—

ACIN =40 ~ 400Hz

1000

us

—

STBEEP comparator in Diode mode

STBEEP comparator in Cont. mode

OVX to SGND

+9

-7

mV

—

HCF detection voltage

VR2-VR5

1100

—

mV

mVp

Square wave with

Duty cycle 40-60%

Frequency input sensitivity (FREQ)

Fin

500

400

—

Sine wave

mVrms

Reference voltage temperature

coefficient

100KΩ

Between

resister

VRH

—

ppm/℃

TC_RF

50

0℃<TA<70℃

Capacitance measurement

Accuracy⁵

—

-2.5

-30

2.5

30

%F.S

6nF – 60mF

counts

Note:

1. Full Scale (60000 counts for SADC and 600 counts for FADC)

2. SADC = High resolution ADC (slow speed)

3. FADC = High speed ADC (lower resolution)

4. ES51998 built-in 3^rdorder low pass filter available for AC mode

5. Gain calibration is necessary for higher accuracy

ver. 1.7

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ES51998(60000counts)

DMM Analog front end/Insulation

AC electrical characteristics

Parameter

Symbol

Min.

Typ.

Max.

Unit

kHz

SCLK clock frequency

SCLK clock time “L”

SLCK clock time “H”

SDATA output delay time

SDATA output hold time

Start condition setup time

Start condition hold time

Data input setup time

f_SCLK

t_LOW

t_HIGH

t_AA

-

4.7

4.0

0.1

100

4.7

4.0

200

0

4.7

-

4.7

0

-

100

-

3.5

-

us

t_DH

ns

us

t_SU.STA

t_HD.STA

t_{SU. DAT}

t_HD.DAT

t_SU.STO

t_R

t_F

t_BUF

t_SU.EOC

t_HD.EOC

ns

us

Data input hold time

Stop condition setup time

SCLK/SDATA rising time

SCLK/SDATA falling time

Bus release time

EOC setup time in read mode

EOC hold time in read mode

-

1.0

0.3

-

ns

-

MPU I/O timing diagram

SCLK

SDATA IN

SDATA OUT

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ES51998(60000counts)

DMM Analog front end/Insulation

Function Description

1. MPU serial I/O function overview

1.1 Introduction

ES51998 configures a 3-wire serial I/O interface to external microprocessor unit (MPU).

The SDATA pin is bi-directional and SCLK & DATA_NEW are unilateral. The SDATA pin

is configured by open-drain circuit design. The DATA_NEW is used to check the data

buffer of ADC ready or not. When the ADC conversion cycle is finished, the DATA_NEW

pin will be pulled high until MPU send a valid read command to ES51998. After the first ID

byte is confirmed, the DATA_NEW will be driven to low until the next ADC conversion

finished again.

The data communication protocol is shown below. The write protocol is configured by an

ID byte with four command bytes. The read protocol is configured by an ID byte with ten

data bytes.

Write command:

ID byte, Write control byte1, Write control byte2, Write control byte3, Write control byte4

START BIT

B

U

Z

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

1

0

1

0

STOP BIT

WRITE

Read command:

ID byte, Read data byte1, Read data byte2 ~ Read data byte9, Read data byte10

START BIT

B

U

Z

A

C

K

A

C

K

A

C

K

A

C

K

1

0

1

0

1

READ

A

C

K

N

A

K

STOP BIT

DATA_NEW

SDATA

ADC data ready

ID code confirmed

Next ADC data ready

ID code

0

1

0

1

0

1

Read command

SCLK

Start bit

Stop bit

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ES51998(60000counts)

DMM Analog front end/Insulation

The ID byte of ES51998 is header of “110010” followed by a buzzer on/off control bit and

R/W bit. The start/stop bit definition is shown on the diagram below.

1.2 Read/Write command description

The write command includes one ID byte with four command bytes. If the valid write ID

code is received by ES51998 at any time, the write command operation will be enabled.

The next table shows the content of write command.

Byte

ID

W1

W2

W3

W4

Bit7

1

SHBP

B0

AC

PEAK

Bit6

1

F3

B1

0

Bit5

0

F2

B2

0

Bit4

0

F1

Bit3

1

F0

0

IRR

Bit2

0

Q2

FQ2

LPF1

OP0

Bit1

BUZ

Q1

FQ1

LPF0

OP1

Bit0

R/W=0

Q0

FQ0

RP

0

EXT

IRV

PCAL

IRQ

EXT_ADP

Auxiliary low-resistance detection control bit for Continuity and Diode modes: SHBP

Measurement function control bit: F3/F2/F1/F0

Range control bit for V/A/R/C modes: Q2/Q1/Q0

Range control bit for Freq mode: FQ2/FQ1/FQ0

Buzzer frequency selection: B2/B1/B0

Buzzer driver ON/OFF control bit: BUZ

AC mode control enable bit: AC

PEAK/Calibration mode enable bit: PEAK/PCAL

3dB BW for low-pass-filter selection: LPF1/LPF0

External source for Diode mode control bit: EXT

OP configuration control bit: OP1/OP0

Frequency mode input resistance control bit or conductance mode control bit: RP

ADP mode control bit: EXT_ADP

Insulation mode control bit: IRQ/IRV/IRR

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ES51998(60000counts)

DMM Analog front end/Insulation

The read command includes one ID byte with ten data bytes. When DATA_NEW is ready¹,

MPU could send the read data command to get the result of ADC conversion

(D0/D1/D2/D3)²or status flag from ES51998.

The next table shows the content of read command.

Byte

ID

R1

R2

R3

R4

R5

R6

R7

Bit7

1

ASIGN

HF

D0:3

D0:11

D1:0

D1:8

D2:6

D2:14

D3:3

D3:11

Bit6

1

BSIGN

LF

D0:4

D0:12

D1:1

D1:9

D2:7

D2:15

D3:4

D3:12

Bit5

0

PMAX

LDUTY

D0:5

D0:13

D1:2

D2:0

Bit4

0

Bit3

1

Bit2

0

Bit1

BUZ

STA0

D0:1

D0:9

D0:17

D1:6

D2:4

D2:12

D3:1

D3:9

D3:17

Bit0

R/W=1

ALARM

D0:2

D0:10

D0:18

D1:7

D2:5

D2:13

D3:2

PMIN

STA1

D0:6

D0:14

D1:3

D2:1

D2:9

D2:17

D3:6

D3:14

BTS0

F_FIN

D0:7

D0:15

D1:4

D2:2

D2:10

D2:18

D3:7

D3:15

BTS1

D0:0

D0:8

D0:16

D1:5

D2:3

D2:11

D3:0

D3:8

D3:16

D2:8

D2:16

D3:5

R8

R9

R10

D3:10

D3:18

D3:13

¹Note: DATA_NEW will be active with D1 data updated when one fast ADC (FADC) conversion finished. If

MCU access slow ADC output only, ten FADC conversion cycle delay is necessary. DATA_NEW for

frequency or capacitance mode will be active when D0 or D3 data ready.

²Note: D0/D1/D2/D3 all are binary code format. D0 is SADC output and D1 is FADC output. The maximum

data is 63000 counts for SADC and 604 counts for FADC. The maximum counts for PEAK mode is 103000,

so D0 bit 17-18 could be ignored..

The ADC data output for measurement mode: F3/F2/F1/F0

F3

0

1

F2

0

1

0

1

F1

0

1

0

1

0

1

F0

0

1

0

1

0

1

0

1

0

1

0

1

Measurement mode

V mode

Read data bytes

D0(0:18), D1(0:9)

D0(0:18), D1(0:9), D3(0:18)

D0(0:18), D1(0:9)

ACV + Hz(%) mode

A mode

D0(0:18), D1(0:9), D2(0:18), D3(0:18)

D0(0:18), D1(0:9)

ACA + Hz(%) mode

Resistance mode

Continuity mode

Diode mode

D0(0:18), D1(0:9)

D0(0:18), D2(0:18), D2(0:18), D3(0:18)

D0(0:18)

F + duty mode

Capacitance Mode

ADP mode

D0(0:18), D1(0:9)

D0(0:18), D1(0:9), D2(0:18), D3(0:18)

D0(0:18)

ADP + Hz(%) mode

Insulation mode

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ES51998(60000counts)

DMM Analog front end/Insulation

Buzzer frequency selection: B2/B1/B0

B2

0

B1

0

B0

0

Buzzer frequency

1.00kHz

0

1

1.33kHz

0

1

0

2.00kHz

0

1

2.22kHz

1

0

2.67kHz

1

0

1

3.08kHz

1

0

3.33kHz

1

4.00kHz

Set B2-B0 properly to get the target frequency. Use BUZ control bit to enable/disable the

BUZOUT (pin82) driver output. If MPU control BUZ only, it is available to set ID byte with

ending of stop bit.

A

C

K

R

/W

START BIT

1

0

1

0

STOP BIT

Buzzer OFF

R

/W

1

1 0 0 1 0 1

Buzzer ON

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ES51998(60000counts)

DMM Analog front end/Insulation

Status flags for measurement mode: ● = function available

Measurement mode

V mode

ACV + Hz mode

A mode

ACA + Hz mode

Res. mode

ASIGN

●

BSIGN

●

PMAX

●

PMIN

●

BTS0

●

BTS1

●

ALARM

●

Cont. mode

Diode mode

F + duty mode

Cap. Mode

●

ADP mode

●

ADP + Hz mode

Insulation mode

Measurement mode

V mode

●

HF

LF

●

LDUTY

STA0

●

STA1

F_FIN

●

V + Hz mode

A mode

A + Hz mode

Res. mode

●

Cont. mode

Diode mode

F + duty mode

Cap. Mode

ADP mode

ADP + Hz mode

Insulation mode

●

Description of status flags:

ASIGN: Sign bit of SADC output (-1 * D0 if ASIGN=1)

BSIGN: Sign bit of FADC output (-1 * D1 if BSIGN=1)

PMAX: Indicates D0 output is the voltage of the peak maximum capacitor (pin62)

PMIN: Indicates D0 output is the voltage of the peak minimum capacitor (pin61)

BTS0/BTS1: Multi-level battery voltage indication

ALARM: Large capacitor indication/High crest factor signal detection in ACV mode

HF: Higher frequency indication for Hz mode

LF: Lower frequency indication for Hz mode

LDUTY: Low duty indication for Hz + duty mode

STA0/STA1: divider indication for Hz mode

STA0: Status flag for capacitor discharging mode

STA1: Status flag for Insulation R mode/Resistance mode

F_FIN: Measurement cycle finished for Hz mode

ver. 1.7

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ES51998(60000counts)

DMM Analog front end/Insulation

1.3 Power & I/O level selection

The ES51998 provide a flexible I/O level setting for different MPU system configuration.

The uP_VCC should be connected to the same potential of external Vcc of MCU. The

uP_VCC is allowed to be set between DGND ~ V+. The IO_CTRL pin selects the Vss level

of MCU. If IO_CTRL is set to DGND, the Vss level of MCU is the same as DGND. If

IO_CTRL is set to V-, the Vss level of MCU is the same as V-.

ver. 1.7

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ES51998(60000counts)

DMM Analog front end/Insulation

2. Operating Modes

2.1. Voltage Measurement

MPU send write command to select the voltage measurement function. The Hz mode

measurement is available to be enabled with the ACV function (set AC bit to 1)

simultaneously. The measured signal is applied to VR1 terminal (pin25) through 10MΩ.

See the next table of function command:

F3

0

F2

0

F1

0

F0

0

AC

0

Measurement mode

DCV mode

Read data bytes

D0(0:18), D1(0:9)

0

1

ACV mode

D0(0:18), D1(0:9)

D0(0:18), D1(0:9), D2(0:18), D3(0:18)

0

1

ACV + Hz(%) mode

Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Note2: See PEAK mode (section 2.10) also.

Range control for voltage mode (ACV/DCV)

Q2 Q1 Q0

Full Scale Range

600.00mV

6.0000V

Divider Ratio

1

Resister Connection

VR1 (10MΩ)

VR2 (1.111MΩ)

VR3 (101kΩ)

VR4 (10.01kΩ)

VR5 (1kΩ)

0

1

0

1

0

1

0

1

0

1/10

1/100

1/1000

1/10000

60.000V

600.00V

1000.0V

Frequency range control for ACV+Hz(%) mode

FQ2 FQ1 FQ0 Full Scale Range

0

1

0

1

0

1

60.00Hz

600.0Hz

6.000kHz

60.00kHz

20% ~ 80%

Duty Cycle

Note: See frequency mode (section 2.8) also

ALARM bit at voltage mode is used for high crest factor (HCF) signal detection. If MPU

check the ALARM status flag active when data and range are stable, it should consider the

making the existing range up to avoid the signal clamping saturation caused by HCF signal.

There is higher peak voltage with lower RMS value for HCF signal. So if the range is up

according to the ALARM bit, MCU should set the lower under-limit counts temporarily to

avoid the ranging unstable for this case.

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2.2 Current measurement

MPU send write command to select the current measurement function. The Hz mode

measurement is available to be enabled with the ACA function (set AC bit to 1)

simultaneously. The measured signal is applied to IVSL/IVSH terminals (pin37-38).

See the next table of function command:

F3

0

F2

0

F1

1

F0

0

AC

0

Measurement mode

DCA mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

1

ACA mode

D0(0:18), D1(0:9)

D0(0:18), D1(0:9), D2(0:18), D3(0:18)

0

1

ACA + Hz(%) mode

Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Note2: See PEAK mode (section 2.10) also.

Range control for current mode (ACA/DCA)

Q2 Q1 Q0

Full Scale Range

300mV 60000counts

Input terminal

IVSL

0

1

IVSH

Current measurement mode configuration examples: (max. voltage drop 300mV)

90K

600.00 / 6000.0uA

FUSE

1

60.000 / 600.00mA

V - V +

10K

uA / mA

49.5

2

3

-

100K

6

TL061

+

IVSL

IVSH

V -

V +

V -

0.495

100K

Zero Offset

FUSE

1. 5K

6A/ 20A

1

0.1uF

A

0.005

100K

1

COM

(max voltage drop = ~ 1V)

AGND

SGND

0.005

20A

6A

0.045

0.45

mA

4.5

mA

uA

A

100K

45

IVSH

IVSL

mA

uA

450

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Frequency range control for ACA+Hz(%) mode

FQ2 FQ1 FQ0 Full Scale Range

0

1

0

1

0

1

60.00Hz

600.0Hz

6.000kHz

60.00kHz

20% ~ 80%

Duty Cycle

Note: See frequency mode (section 2.8) also.

2.3 Low pass filter (LPF) mode for ACA/ACV mode

A 3^rdorder low pass filter with is built in ES51998. The 3dB bandwidth of the low pass

filter could be selectable by MPU. The LPF mode is active when the LPF control bit is set

to be active. When PEAK mode is active, the LPF mode will be disabled temporarily until

the PEAK mode is cancelled.

The LPF mode is allowed to be enabled in F + duty mode to reject high-frequency noise

for sine wave input, but the 3dB will be fixed at 10kHz only.

LPF1

LPF0

Low pass filter effect

Disable

0

1

0

1

0

1

3dB = 1kHz

3dB = 10kHz

3dB > 100kHz

2.4 Resistance/Conductance Measurement

MPU send write command to select the resistance measurement function. When RP=1, the

command to select the conductance mode.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

Resistance mode

Note1: D0/D1 both are binary format. ASIGN/BSIGN bits are ignored. When RP=1, the D1 data should

be ignored.

Range control for resistance mode (RP=0)

Q2 Q1 Q0 Full Scale Range

Relative Resistor

OR1

Equivalent value

100Ω

0

1

0

1

0

1

0

1

0

1

600.00Ω

6.0000KΩ

60.000KΩ

600.00KΩ

6.0000MΩ

60.000MΩ

VR5

1KΩ

10KΩ

100KΩ

1MΩ

10MΩ

VR4 || VR1

VR3 || VR1

VR2 || VR1

VR1

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DMM Analog front end/Insulation

Set RP=1 when range control is 10MΩ range, the conductance mode is available. The status

STA1 bit is used for converted data indication of reference voltage or input voltage.

Q2 Q1 Q0 Full Scale Range

60.00nS

Relative Resistor

Equivalent value

1

0

1

VR1

10MΩ

The maximum displayed count is 6000 and the resolution should be 0.01nS. The MCU

should check the status bit STA1 and D0 simultaneously. When STA1=1 the D0 data should

be V_D1. If STA1=0, then the D0 data should be V_D2. The DUT conductance value could be

calculated by simple formula.

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2.5 Capacitance Measurement

MPU send write command to select the capacitance measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18)

1

0

Capacitance mode

Note1: D0 is binary format. ASIGN bit is ignored.

Range control for capacitance mode

Measurement Period

0.5 sec

Q2

0

1

Q1

0

1

0

1

Q0

0

1

0

1

0

1

0

1

Full Scale Range Relative Resistor

6.0000nF*

60.000nF*

600.00nF*

6.0000uF*

60.000uF*

600.00uF*

6.0000mF*

60.000mF*

-

0.5 sec

1.25 sec

OVX pin VR

-

0.4 sec max.

0.5 sec max.

1.0 sec max.

1.35 sec max.

6.75 sec max.

R9K / R1K



The displayed counts in ES51998 capacitance mode is recommended to be divided by

10. (6000 counts displayed is recommended)

ALARM bit at capacitance mode is used for increasing the ranging speed. If MPU

check the ALARM=1 at lower range, it could set the next range to 6.000uF directly

and the ADC output should be ignored.



STA0 status bit is used for detection of DUT capacitor voltage. If STA0=1, the internal

capacitor discharging mode is active and the capacitance measurement is inhibited. It is

recommended to discharge the DUT capacitor externally.

2.6 Continuity Check measurement

MPU send write command to select the continuity measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

1

Continuity mode

Note1: D0/D1 both are binary format. ASIGN/BSIGN bits both are ignored.

Continuity mode shares the same configuration with 600.00Ω resistance measurement

circuit and support the low-resistance detection. If the STBEEP output (pin64) is low, it

means the low-resistance status is detected (It means the OVX terminal voltage less than

-7mV). It could be faster than the FADC result, so MPU could monitor the STBEEP output

and FADC (D1) data output make the high speed detection for short circuit detection. Set

SHBP=1 to enable the built-in buzzer driving automatically when STBEEP is active.

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2.7 Diode Measurement

MPU send write command to select the diode measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

D0(0:18), D1(0:9)

0

1

0

Diode mode

Note1: D0/D1 both are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Diode measurement mode shares the same configuration with 6.0000V voltage

measurement circuit and support the low-resistance detection. If the STBEEP output (pin64)

is low, it means the low-resistance status is detected (It means the OVX terminal voltage less

than 9mV). It could be faster than the FADC result, so MPU could monitor the STBEEP

output and FADC (D1) data output make the high speed detection for short circuit detection.

Set SHBP=1 to enable the built-in buzzer driving automatically when STBEEP is active.

The default source voltage at diode mode is the same as V+ potential. MPU could set the

control bit EXT=1 to change the source voltage to external source. The external voltage

source (positive or negative) input applied from EXTSRC (pin16). The available external

source range should be from V+ to V-.

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2.8 Frequency/duty cycle mode measurement

The default typical input impedance of frequency with duty cycle mode is 1MΩ. The MPU

could set control bit RP=1 to change the input impedance down to 100kΩ. MPU send write

command to select the frequency/duty cycle measurement function.

F3

F2

F1

F0

Measurement mode

Read data bytes

0

1

Hz + Duty mode

D0(0:18), D2(0:18), D3(0:18)

Note1: D0/D2/D3 all are binary format. ASIGN bit is ignored.

Note2: Set LPF1 = 1 to enable the smooth function for sine wave input automatically

Range control for frequency mode

FQ2 FQ1 FQ0

Full Scale

60.000Hz

600.00Hz

6.0000KHz

60.000KHz

600.00KHz

6.0000MHz

60.000MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

Available minimum frequency input F_MIN= 4.000Hz

Frequency & duty cycle mode computed by D0/D2/D3 (if F_FIN=1)

Flag

Range*

STA0=0

STA0=1

STA1=1

STA1=0

60.000Hz

600.00Hz

FREQ=1000000000/D3 FREQ=4000000000/D3 FREQ=8000000000/D3

FREQ=100000000/D3 FREQ=400000000/D3 FREQ=1600000000/D3**

6.0000KHz FREQ=20000000/D3

60.000KHz FREQ=2000000/D3

600.00KHz

FREQ=320000000/D3 FREQ=2560000000/D3***

FREQ=256000000/D3 FREQ=2048000000/D3

6.0000MHz

FREQ = D0-1

60.000MHz

*Note: The Hz measurement of AC+Hz mode is recommended to support 6000 counts displayed

**Note: If D3 < 40000, simple arithmetic mean is necessary to get the 0.01Hz resolution

***Note: If D3 < 50000, simple arithmetic mean is necessary to get the 0.0001 KHz resolution

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DMM Analog front end/Insulation

Status Flag

Duty cycle (<60kHz)

LDUTY=1

10000-D2*10000/D3

LDUTY=0

D2*10000/D3

The status flag F_FIN indicate the frequency input signal available (> F_MIN) or not. If the

computed result less than F_MIN, the frequency/duty cycle readings should be set to zero.

The status flags HF & LF are used for fast judgment of proper range. If frequency input is

larger than 7 kHz, HF will be active. If frequency input is floating or frequency detected too

low, LF will be active.

Auto range consideration for MPU by using Status Flags of frequency mode

Flag

Range

60.000Hz

F_FIN=0

LF=0

F_FIN=1

LF=1*

Hz/Duty=0

F_FIN=1

HF=LF=0

HF=1**

Set range to

60.000kHz

range

600.00Hz

6.0000KHz

60.000KHz

600.00KHz

6.0000MHz

60.000MHz

Change range

depends on data

computed

Data and Range

is not necessary

to be updated

Set range to

60.000Hz range

Change range

depends on data

computed

*Note: LF=1 @ 60Hz range implies the frequency is not available to be measured. The Hz/Duty readings

should be set to zero.

**Note: When ACV+Hz/ACA+Hz/ADP+Hz mode is selected, the HF status should be ignored. Change range

depends on data calculation result.

Duty cycle mode range (Input sensitivity > 2Vpp @ duty cycle = 5.0% & 95.0%)

Freq. range

Duty range*

60.000Hz

600.00Hz

5.0% - 95.0%

6.0000KHz

60.000KHz

10.0 % - 90.0%

20.0% – 80.0%

*Note: Duty range for AC+Hz(%) is 20% ~ 80%.

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2.9 ADP mode

MPU send write command to select the ADP mode measurement function. The Hz mode

measurement is available to be enabled with the ADP AC function (set AC bit to 1)

simultaneously. The measured signal is applied to ADP terminal (pin39). The signal full

scale is 600mV for DC mode and 600mVrms for AC mode.

See the next table of function command:

F3

1

F2

0

F1

0

F0

1

AC

0

Measurement mode

ADP DC mode

Read data bytes

D0(0:18), D1(0:9)

1

0

1

ADP AC mode

D0(0:18), D1(0:9)

D0(0:18), D1(0:9), D2(0:18), D3(0:18)

1

0

1

0

1

ADP + Hz(%) mode

Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively.

Note2: See PEAK mode (section 2.10) also.

Frequency range control for ADP+Hz(%) mode

FQ2 FQ1 FQ0 Full Scale Range

0

1

0

1

0

1

60.00Hz

600.0Hz

6.000kHz

60.00kHz

20% ~ 80%

Duty Cycle

Note: See frequency mode (section 2.8) also

If MPU set the control bit EXT_ADP=1, the voltage on EXTSRC pin could be switched to

ADP terminal internally. It is helpful for a voltage pulled application of ADP mode.

External source

pull high or low

EXT_ADP

ADC IN+

ADP_IN

ADC IN-

SGND

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2.10 Peak-hold measurement mode

ES51998 provides a peak hold function to capture the real peak value for voltage or current

measurement mode. In a case of a 1V sine wave input voltage, the peak hold function gets a

maximum peak value of 1.414V and minimum peak value of –1.414V ideally. Set the

control bit PEAK=1 to force the ES51998 entering PEAK measurement mode. Peak Hold

function is divided into two parts of peak maximum and peak minimum conversion. High

resolution SADC performs peak maximum and peak minimum conversion in turn, not at the

same time. The status flag PMAX or PMIN shows which type the peak value is. If

PMAX=1(PMIN=1), the SADC output D0 is the conversion data on PMAX (PMIN)

terminals (pin 61/62). The MPU should make the comparison procedure to get the

maximum value of PMAX data and minimum value of PMIN data. The max counts for D0

is 103000.

Peak calibration mode

At PEAK-Hold measurement mode, the offset voltage of internal operation amplifier will

cause an error. To obtain a more accurate value, the offset error must be canceled. ES51998

provides the peak calibration feature to remove the influence on accuracy by internal offset

voltage. Set the control bit PCAL=1 to enter peak calibration mode. When PCAL mode is

active, the SADC of ES51998 will output the calibration value of peak maximum and

minimum conversion in turn. The offset values should be memorized respectively and

deducted from the data of PMAX/PMIN at the normal peak measurement mode.

Set PCAL=1 or PEAK=1

Status indication

ADC data

PMAX=1, PMIN=0 PMAX=0, PMIN=1

V_PMAX.CV_PMIN.C

V_PMAX.Cand V_PMIN.Care not the real-time value of peak-hold voltage. They are the voltage

stored on terminal capacitor (pin61-62). Because the capacitor will be self-discharging, so

MCU need to compare the V_PMAX.C& V_PMIN.Crespectively and memorize the maximum and

minimum peak values in turn.

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2.11 Insulation resistance measurement mode

The ES51998 is built-in analog switches network to support the insulation resistance

measurement mode. By implementation of external high voltage source, the insulation

resistance could be obtained from SADC output of ES51998 and calculated by

microprocessor easily. The insulation mode is separated into two modes which are

insulation V mode and insulation R mode which are described below.

Insulation V mode configuration

F3

F2

F1

F0

IRV

AC

Measurement mode

Read data bytes

1

0/1

Insulation (DC/AC) V mode D0(0:18)

Note1: D0 is binary format. ASIGN is the sign bit D0.

Insulation V mode

MCU control

HV OFF (Discharging mode)

PTC

10MΩ

V_A

V_ADC

VR2

VR3

VR4

VR5

MCU control

1.11MΩ 101KΩ 10.01KΩ 1KΩ

V_DUT= V_A- V_B= k * V_ADC

V_B

Q1

IRVG

Active in insulation V mode

Note: The on-resistance of internal analog switches could be omitted.

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Before measure insulation resistance, it is necessary to measure V_DUT.If V_DUTis too high,

the resistance measurement should be forbidden. The insulation V mode is implemented by

the same configuration with Voltage mode. The k factor of diagram is depended on the

voltage range. During insulation V mode, an external fast discharging path should be

applied on the HV sourcing part to release the high voltage charge on the DUT if it is

capacitive load.

Range control for insulation V mode

Q2 Q1 Q0

Full Scale Range

60.000V

0

1

0

1

0

600.00V

1000.0V

Note: 600mV – 6V ranges are omitted.

Insulation R mode configuration

F3

F2

F1

F0

IRV

IRR

Measurement mode

Read data bytes

1

0

1

Insulation R mode

D0(0:18)

Insulation R mode

MCU control

HV(25V ~ 1000V)

PTC

10MΩ

V_D1

V_A

ADC

IRVH0

IRVH1

V_A= V_D1/ R_A* (10M+R_A)

I_RX= V_D2/ R_B= V_B/ R_B

R_X= (V_A-V_B) / I_RX

MCU control

5.6KΩ

56KΩ

Rx

I_RX

R_A

V_B

V_D2

100kΩ

ADC

R_B

Q1

Test mode

360kΩ

36kΩ

3.6kΩ

360Ω

IRR1

IRR5

IRR4

IRR3

IRR2

MCU control

Note: ADC full scale is 600mV typically.

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During insulation R mode is setting, the SADC of ES51966 will convert the DUT terminal

voltage V_A(higher voltage side V_D1) & V_B(lower voltage side V_D2) sequentially. Use ohm’s

law calculation {R_X= (V_A-V_B)/I_RX} to get the target DUT insulation resistance easily. The

microprocessor gets the ADC data by checking status bit STA1:

Status indication

ADC data

STA1=1

STA1=0

V_D1

V_D2

The proper range control (R_A/ R_Bselection) depends on the HV source. The R_Aselection is

controlled by IRQ control bit. The R_Bis selected by Q2/Q1/Q0 control bits. The next range

table is an example of HV sourcing from 25V to 1000V.

Set IRQ=1 (IRVH1)

Set IRQ=0 (IRVH0)

R_A

HV=25V

15.0kΩ ~

150.0kΩ

0.150MΩ ~

1.500MΩ

1.50MΩ ~

15.00MΩ

15.0MΩ ~

150.0MΩ

HV=50V

30.0kΩ ~

300.0kΩ

0.300MΩ ~

3.000MΩ

3.00MΩ ~

30.00MΩ

30.0MΩ ~

300.0MΩ

HV=100V

60.0kΩ ~

600.0kΩ

0.600MΩ ~

6.000MΩ

6.00MΩ ~

60.00MΩ

60.0MΩ ~

600.0MΩ

HV=250V

0.150MΩ ~

1.500MΩ

1.50MΩ ~

15.00MΩ

15.0MΩ ~

150.0MΩ

0.150GΩ ~

1.500GΩ

HV=500V

0.300MΩ ~

3.000MΩ

3.00MΩ ~

30.00MΩ

30.0MΩ ~

300.0MΩ

0.300GΩ ~

3.000GΩ

HV=1000V

0.600MΩ ~

6.000MΩ

6.00MΩ ~

60.00MΩ

60.0MΩ ~

600.0MΩ

0.600GΩ ~

6.000GΩ

R_B

IRR1

IRR2

IRR3

IRR4

Q2 Q1 Q0

R_Brange

IRR1

IRR2

IRR3

IRR4

Best resolution*

0

1

0

1

0

1

0

1

0

1

0.1kΩ

1kΩ

0.01MΩ

0.1MΩ

N/A

Test mode (IRR5)

*Note: The best resolution depends on the external high voltage and SADC readings.

2.12 Sleep

Set CS pin (pin 80) to logic low to make the ES51998 entering the sleep mode. The current

consumption will be less than 3uA typically. Set CS pin to logic high or kept floating, the

ES51998 will return to normal operation.

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2.13 Multi-level battery voltage indication

The ES51998 is built-in a comparator for batter voltage indication. The voltage is applied to

LBAT pin (pin 89) vs. V- terminal. MPU could check the status bit BTS1/BTS0 and monitor

the LBAT voltage status.

Battery voltage

V_LBT> V_t1

V_t2< V_LBT< V_t1

V_t3< V_LBT< V_t2

V_LBT< V_t3

BTS1

BST0

1

0

1

0

1

0

Low battery configuration for 9V/1.5V*4/1.5V*3 battery

Low battery test circuit (a)

Low battery test circuit (b)

6V

9V

360K

BA

470K

BA

LBAT

TT

0.1u

TT

0.1u

AGND

V-

AGND

V-

270K

180K

0V

Low battery test circuit (c)

4.5V

360K

BA

LBAT

TT

0.1u

AGND

V-

470K

0V

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2.14 Independent OPAMP

ES51998 is built-in an independent OPAMP with 200kHz unity-gain bandwidth using for

general purpose.

MPU could control the OP1/OP0 to change the OPAMP configuration:

OP1

OP0

OPAMP configuration

Normal

0

1

0

1

0

1

OP disable

Unity gain buffer

Zero calibration

Independent OPAMP configuration

Normal operation

OPIN-

OPIN+

OPOUT

-

+

Zero offset calibration

OPOUT

OPIN-

OPIN+

-

+

Unity gain operation

OPOUT

OPIN-

OPIN+

-

+

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3. Application Circuit

3.1 AVG circuit

Close to IC

+

26

27

100

99

98

97

96

95

94

93

92

91

90

OVX

OVH

OVH1

IRR5

CIH

CH-

C4

10nF

28

1

2

CH+

0

R10 29

AGND

DGND

V+

30

31

32

33

34

360K

36K

3.6K

360

R27

R28

R29

R30

IRR4

IRR3

IRR2

IRR1

V+

VCC

IRVG

IRVL

SGND

IVSH

IVSL

ADP

u PVCC

V-

100K

R31 35

36

R6 37

R7 38

R8 39

40

V-

IVSH 100K

IVSL 100K

ADP 100K

89 L BAT

88 C5

87

86 SDA

85 SCL

84 DATA_new

83

L BAT

C-

470nF

C+

OPIN-

OPIN+

OPOUT

ACVL

ACVH

ADI

ADO

TEST5

CA-

SDATA

SCL K

OPIN+

OPout

ACVL

ACVH

ADI

41

42

43

44

45

46

47

48

49

50

DATA_new

NC

82 BUZOUT

81 VSS

80 CS

79

BZOUT

IO_ CT RL

CS

ADO

TEST5

OSC1

OSC2

NC

78

C8 470nF+/- 10%

77

CA+

OHM C4

76

NC

+

ver. 1.7

29

12/01/12

ES51998(60000counts)

DMM Analog front end/Insulation

3.2 RMS circuit (ES636)

Close to IC

+

S

R M C V A

W S 2

26

27

28

100

OVX

OVH

OVH1

IRR5

CIH

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

C4

10nF

CH-

CH+

1

2

0

R10 29

R27 30

R28 31

R29 32

R30 33

34

R31 35

36

R6 37

R7 38

R8 39

AGND

DGND

V+

360K

36K

3.6K

360

IRR4

IRR3

IRR2

IRR1

V+

VCC

IRVG

IRVL

SGND

IVSH

IVSL

ADP

u PVCC

V-

100K

V-

IVSH 100K

IVSL 100K

ADP 100K

L BAT

C5

L BAT

C-

470nF

C+

OPIN-

40

41

42

43

44

45

46

47

SDA

SCL

OPIN-

OPIN+

OPOUT

ACVL

ACVH

ADI

ADO

TEST5

CA-

SDATA

SCL K

DATA_new

NC

OPIN+

OPout

84 DATA_new

83

82 BUZOUT

81

80

79

78

77

76

ACVH

ADI

BZOUT

IO_ CT RL

CS

VSS

CS

OSC1

OSC2

NC

C8 470nF+/- 10% 48

49

50

CA+

OHM C4

NC

+

C24

2.2uF

ver. 1.7

30

12/01/12

ES51998(60000counts)

DMM Analog front end/Insulation

4. Package Information

4.1 100L LQFP Outline drawing

4.2 Dimension parameters

ver. 1.7

31

12/01/12

型号	制造商	描述	价格	文档
ES51999	CYRUSTEK	4 3/4 and 5 3/4 A/D AUTO	获取价格
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ES51C1A10N-10.000M	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 10 MHz, ROHS COMPLIANT, CERAMIC, SMD, 10 PIN	获取价格
ES51C1A10N-10.245M	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 10.245 MHz, ROHS COMPLIANT, CERAMIC, SMD, 10 PIN	获取价格
ES51C1A10N-10.245MTR	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 10.245 MHz, ROHS COMPLIANT, CERAMIC, SMD, 10 PIN	获取价格
ES51C1A10N-11.0592M	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 11.0592 MHz, ROHS COMPLIANT, CERAMIC, SMD, 10 PIN	获取价格
ES51C1A10N-12.352M	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 12.352 MHz, ROHS COMPLIANT PACKAGE, CERAMIC, SMD, 10 PIN	获取价格
ES51C1A10N-12.352MTR	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 12.352 MHz, ROHS COMPLIANT PACKAGE, CERAMIC, SMD, 10 PIN	获取价格
ES51C1A10N-13.560M	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 13.56 MHz, ROHS COMPLIANT, CERAMIC, SMD, 10 PIN	获取价格
ES51C1A10N-14.000MTR	ECLIPTEK	TCXO, CLIPPED SINE OUTPUT, 14 MHz, ROHS COMPLIANT, CERAMIC, SMD, 10 PIN	获取价格

ES51998

ES51998 概述

ES51998 数据手册

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