DS1013-75 概述
3-in-1 Silicon Delay Line 3合1硅延迟线
DS1013-75 数据手册
通过下载DS1013-75数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载DS1013
3-in-1 Silicon Delay Line
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ All-silicon time delay
IN 1
NC
1
2
14
13
12
11
10
9
VCC
NC
ꢀ 3 independent buffered delays
ꢀ Delay tolerance ±2ns for -10 through –60
ꢀ Stable and precise over temperature and
voltage range
ꢀ Leading and trailing edge accuracy
ꢀ Economical
ꢀ Auto-insertable, low profile
ꢀ Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
IN 1
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
NC
IN 2
NC
3
4
5
6
7
OUT 1
NC
NC
NC
IN 2
OUT 1
NC
NC
IN 3
NC
IN 3
OUT 2
NC
OUT 2
NC
NC
8
GND
OUT 3
GND
OUT 3
DS1013 14-pin DIP (300-mil)
See Mech. Drawings Section
DS1013S 16-pin SOIC
(300-mil)
ꢀ Low-power CMOS
ꢀ TTL/CMOS-compatible
ꢀ Vapor phase, IR and wave solderable
ꢀ Custom delays available
ꢀ Quick turn prototypes
See Mech. Drawings Section
1
VCC
8
7
IN 1
2
IN 2
OUT 1
OUT 2
OUT 3
ꢀ Extended temperature ranges available
3
6
5
IN 3
4
GND
DS1013M 8-pin DIP (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
IN 1, IN 2, IN 3
- Inputs
OUT 1, OUT 2, OUT 3 - Outputs
GND
VCC
NC
- Ground
- +5 Volts
- No Connection
DESCRIPTION
The DS1013 series of delay lines has three independent logic buffered delays in a single package. The
devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines. Alternative
8-pin DIP and surface mount packages are available which save PC board area. Since the DS1013
products are an all silicon solution, better economy is achieved when compared to older methods using
hybrid techniques. The DS1013 series delay lines provide a nominal accuracy of ±2ns for delay times
ranging from 10 ns to 60 ns, increasing to 5% for delays of 150 ns and longer. The DS1013 delay line
reproduces the input logic state at the output after a fixed delay as specified by the dash number extension
of the part number. The DS1013 is designed to reproduce both leading and trailing edges with equal
precision. Each output is capable of driving up to 10 74LS loads. Dallas Semiconductor can customize
standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348.
1 of 6
111799
DS1013
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1
PART NO.
DS1013-10
DS1013-12
DS1013-15
DS1013-20
DS1013-25
DS1013-30
DS1013-35
DS1013-40
DELAY PER OUTPUT (ns)
10/10/10
12/12/12
15/15/15
20/20/20
25/25/25
30/30/30
35/35/35
40/40/40
45/45/45
50/50/50
60/60/60
70/70/70
75/75/75
80/80/80
100/100/100
150/150/150
200/200/200
DS1013-45
DS1013-50
DS1013-60
DS1013-70*
DS1013-75*
DS1013-80*
DS1013-100*
DS1013-150**
DS1013-200**
Custom delays available
* ±3% tolerance
** ±5% tolerance
2 of 6
DS1013
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
TEST CIRCUIT Figure 3
3 of 6
DS1013
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-1.0V to +7.0V
0°C to 70°C
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER
SYM
TEST
MIN TYP
MAX
UNITS NOTES
CONDITION
Supply Voltage
High Level Input
Voltage
Low Level Input
Voltage
Input Leakage
Current
Active Current
VCC
VIH
4.75
2.2
5.00
5.25
VCC + 0.5
V
1
1
VIL
II
-0.5
-1.0
0.8
1.0
70
V
µA
mA
mA
mA
0.0V ≤ VI ≤ VCC
ICC
IOH
IOL
VCC=Max;
Period=Min.
VCC=Min.
VOH=4.0V
VCC=Min.
VOL=0.5V
40
2
High Level Output
Current
Low Level Output
Current
-1.0
12.0
AC ELECTRICAL CHARACTERISTICS
(TA = 25°C; VCC = 5V ± 5%)
PARAMETER
Input Pulse Width
Input to Output Delay
(leading edge)
SYMBOL
tWI
MIN
TYP
MAX UNITS
NOTES
3, 4, 5, 6
3, 4, 5, 6
100% of tPLH
ns
ns
tPLH
Table 1
Table 1
Input to Output Delay
(trailing edge)
tPHL
ns
Power-up Time
tPU
Period
100
ms
ns
3 (tWI)
7
CAPACITANCE
PARAMETER
Input Capacitance
(TA = 25°C)
MAX UNITS
10 pF
SYMBOL
MIN
TYP
5
NOTES
CIN
4 of 6
DS1013
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns for -10 to -60, ±3%
for -70 to 100 and ±5% for -150 and longer delays.
4. See “Test Conditions” section.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional delay shift of ±1.5 ns or ±3%,
whichever is greater.
6. All output delays tend to vary unidirectionally over temperature or voltage ranges (i.e., if OUT 1
slows down, all other outputs also slow down).
7. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
5 of 6
DS1013
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1013.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between each input and corresponding
output. Each output is selected and connected to the counter by a VHF switch control unit. All
measurements are fully automated, with each instrument controlled by a central computer over an IEEE
488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (VCC):
Input Pulse:
25°C ± 3°C
5.0V ± 0.1V
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
50 ohms Max.
3.0 ns Max.
500 ns
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
1 µs
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
6 of 6
DS1013-75 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
DS1013-75* | MAXIM | 3-in-1 Silicon Delay Line | 获取价格 | |
DS1013-75+ | MAXIM | Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDIP14, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001AC, DIP-14 | 获取价格 | |
DS1013-80 | DALLAS | 3-in-1 Silicon Delay Line | 获取价格 | |
DS1013-80* | MAXIM | 3-in-1 Silicon Delay Line | 获取价格 | |
DS1013-90 | MAXIM | Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDIP14, 0.300 INCH, PLASTIC, MS-001AC, DIP-14 | 获取价格 | |
DS1013-90 | DALLAS | Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDIP14, | 获取价格 | |
DS1013G-10 | DALLAS | Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDSO14, | 获取价格 | |
DS1013G-100 | DALLAS | Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDSO14, | 获取价格 | |
DS1013G-12 | ETC | Tapped Delay Line | 获取价格 | |
DS1013G-15 | DALLAS | Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDSO14, | 获取价格 |
DS1013-75 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6