DS1100LM-75 [DALLAS]
Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP8, 0.300 INCH, DIP-8;
| 型号： | DS1100LM-75 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP8, 0.300 INCH, DIP-8 光电二极管 |
| 文件： | 总6页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
DS1100L
3-Volt 5-Tap Economy Timing
Element (Delay Line)
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ All-silicon timing circuit
ꢀ 5-taps equally spaced
IN
TAP 2
TAP 4
GND
1
2
3
4
8
7
6
5
VCC
ꢀ Delays are stable and precise
ꢀ Both leading and trailing edge accuracy
ꢀ 3V version of the DS1100
ꢀ Low-power CMOS
ꢀ TTL/CMOS-compatible
ꢀ Vapor phase, IR and wave solderable
ꢀ Custom delays available
ꢀ Fast turn prototypes
TAP 1
TAP 3
TAP 5
DS1100M 8-PIN DIP (300 MIL)
DS1100Z 8-PIN SOIC (150 MIL)
DS1100U 8-PIN MICRO-SOP
ꢀ Delays specified over both commercial and
industrial temperature ranges
PIN DESCRIPTION
TAP 1-TAP 5
- TAP Output Number
- +5V
- Ground
VCC
GND
IN
- Input
DESCRIPTION
The DS1100L is a 3-volt version of the DS1100. It is characterized for operation over the range 2.7V to
3.6V.
The DS1100L series delay lines have five equally spaced taps providing delays from 4 ns to 300 ns.
These devices are offered in 8-pin DIPs and surface mount packages to save PC board area. Low cost and
superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line
and industry standard DIP and SOIC packaging. The DS1100L 5-Tap Silicon Delay Line reproduces the
input logic state at the output after a fixed delay as specified by the extension of the part number after the
dash. The DS1100L is designed to reproduce both leading and trailing edges with equal precision. Each
tap is capable of driving up to ten 74LS loads.
Dallas Semiconductor can customize standard products to meet special needs. For special requests and
rapid delivery, call (972) 371-4348.
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102600
DS1100L
LOGIC DIAGRAM Figure 1
DS1100L PART NUMBER DELAY TABLE (all values in ns) Table 1
NOMINAL DELAYS
PART #
DS1100L
-20
TAP 1
4
TAP 2
8
TAP 3
12
TAP 4
16
TAP 5
20
25
-25
5
10
15
20
-30
6
12
18
24
30
-35
7
14
21
28
35
-40
8
16
24
32
40
-45
9
18
27
36
45
-50
-60
-75
-100
-125
-150
-175
-200
-250
-300
10
12
15
20
25
30
35
40
50
60
20
24
30
40
50
60
70
80
30
36
45
60
75
90
105
120
150
180
40
48
60
80
100
120
140
160
200
240
50
60
75
100
125
150
175
200
250
300
100
120
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
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DS1100L
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-1.0V to +7.0V
-40°C to +85°C
Storage Temperature
-55°C to +125°C
Soldering Temperature
Short Circuit Output Current
See J-STD-020A Specification
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCC = 2.7 – 3.6V)
PARAMETER
Supply Voltage
High Level
Input Voltage
Low Level
Input Voltage
Input Leakage
Current
SYM
TEST CONDITION
MIN TYP
2.7
MAX
UNITS NOTES
VCC
3.3
3.6
V
5
VIH
VIL
2.0
V
5
VCC ± 0.5
-0.5
-1.0
0.8
V
5
II
1.0
10
-1
uA
mA
mA
0.0V ≤ VI ≤ VCC
VCC=Max; Period=Min.
VCC=Min. VOH=4
Active Current
High Level
Output Current
ICC
IOH
6, 8
Low Level
Output Current
IOL
VCC=Min. VOL=0.5
8
mA
AC ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C; VCC = 2.7 to 3.6V)
PARAMETER
SYM TEST CONDITION
MIN
20% of
Tap 5
tPLH
-2
TYP
MAX UNITS
NOTES
Input
Pulse Width
tWI
ns
Input-to-Tap
25°C 3.3V
tPLH
Table 1
Table 1
Table 1
Table 1
Table 1
Table 1
+2
+3
+4
+5
+3
+8
ns
ns
ns
%
%
%
1, 3, 4, 7
1, 2, 3, 4, 7
1, 2, 3, 4, 7
1, 3, 4, 7
1, 2, 3, 4, 7
1, 2, 3, 4, 7
Delay Tolerance
(Delays ≤ 40 ns)
Input-to-Tap
Delay Tolerance
(Delays > 40 ns)
Output Rise or
Fall Time
0°C to 70°C
tPHL
-3
-4
-5
-3
-40°C to +85°C
25°C 3.3V
tPLH
0°C to 70°C
tPHL
-40°C to +85°C
-8
tOF, tOR
tPU
Period
2.0
2.5
ns
Power-up Time
Input Period
200
us
ns
2(tWI)
CAPACITANCE
PARAMETER
Input Capacitance
(TA = 25°C)
SYMBOL
CIN
MIN
TYP
5
MAX
10
UNITS
pF
NOTES
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DS1100L
NOTES:
1. Initial tolerances are ± with respect to the nominal value at 25°C and VCC = 3.3 volts for both leading
and trailing edge.
2. T & V tolerance is with respect to the actual measured (at 25° C and 3.3V) delay value over the stated
temperature range, and a supply voltage range of 2.7V to 3.6V.
3. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP
1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
4. Intermediate delay values are available on a custom basis. For further information, call
(972) 371-4348.
5. All voltages are referenced to ground.
6. Measured with outputs open.
7. See “Test Conditions” section at the end of this data sheet.
8. ICC values apply to a -20 operating at 1MHz. Longer delays will consume less current.
TESTCIRCUIT Figure 3
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DS1100L
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the
DS1100L. The input waveform is produced by a precision pulse generator under software control. Time
delays are measured by a time interval counter (20 ps resolution) connected between the input and each
tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements
are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT:
Ambient Temperature: 25°C ± 3°C
Supply Voltage (VCC): 53.3V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:
Rise and Fall Time:
Pulse Width:
50 Ohm Max.
3.0 ns Max. (measured between 10% and 90%)
500 ns
1 µs
Period:
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
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DS1100L
ORDERING INFORMATION
DS1100
L
TOTAL TIME DELAY (ns): 20, 25,
30, 35, 40, 45, 50, 60, 75, 100, 125,
150, 175, 200, 250, 300
PACKAGE TYPE:
M = DIP
Z = SOIC (150 MIL)
U = MICRO -SOP
OPERATING VOLTAGE:
BLANK: 5V ± 5%
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