DS1202S [DALLAS]
Serial Timekeeping Chip; 串行时钟芯片
| 型号： | DS1202S |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Serial Timekeeping Chip |
| 文件： | 总11页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1202, DS1202S
DS1202, DS1202S
Serial Timekeeping Chip
FEATURES
PIN ASSIGNMENT
• Real time clock counts seconds, minutes, hours, date
of the month, month, day of the week, and year with
leap year compensation valid up to 2100
NC
1
2
3
4
8
7
6
5
V
CC
X1
X2
SCLK
I/O
• 24 x 8 RAM for scratchpad data storage
• Serial I/O for minimum pin count
• 2.0–5.5 volt full operation
GND
RST
8–PIN DIP
NC
X1
X2
1
2
3
4
8
7
6
5
V
CC
SCLK
I/O
• Uses less than 300 nA at 2 volts
GND
RST
• Single–byteor multiple–byte (burst mode) data trans-
fer for read or write of clock or RAM data
8–PIN SOIC
(208 mil)
• 8–pin DIP or optional 16–pin SOIC for surface mount
• Simple 3–wire interface
NC
NC
X1
1
2
3
4
5
6
7
8
16
V
CC
15
14
13
12
11
10
9
NC
SCLK
NC
• TTL–compatible (V = 5V)
CC
NC
X2
I/O
• Optionalindustrialtemperaturerange–40°Cto+85°C
(IND)
NC
NC
GND
NC
NC
ORDERING INFORMATION
RST
DS1202
8–pin DIP
16–PIN SOIC
DS1202S
16–pin SOIC
DS1202S–8 8–pin SOIC
PIN DESCRIPTION
DS1202N
DS1202SN
DS1202SN–8 8–pin SOIC (IND)
8–pin DIP (IND)
16–pin SOIC (IND)
NC
–
–
–
–
–
–
–
No Connection
32.768 KHz Crystal Input
Ground
Reset
Data Input/Output
Serial Clock
X1, X2
GND
RST
I/O
SCLK
V
CC
Power Supply Pin
DESCRIPTION
The DS1202 Serial Timekeeping Chip contains a real
time clock/calendar and 24 bytes of static RAM. It com-
municates with a microprocessor via a simple serial in-
terface. The real time clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The end of the month date is automatically adjusted for
months with less than 31 days, including corrections for
leap year. The clock operates in either the 24–hour or
12–hourformatwithanAM/PMindicator. Interfacingthe
DS1202 with a microprocessor is simplified by using
synchronous serial communication. Only three wires
are required to communicate with the clock/RAM: (1)
RST (Reset), (2) I/O (Data line), and (3) SCLK (Serial
clock). Data can be transferred to and from the clock/
RAM one byte at a time or in a burst of up to 24 bytes.
The DS1202 is designed to operate on very low power
and retain data and clock information on less than 1 mi-
crowatt.
ECopyright 1997 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
032697 1/11
DS1202, DS1202S
The number of clock pulses equals eight plus eight for
byte mode or eight plus up to 192 for burst mode.
OPERATION
The main elements of the Serial Timekeeper are shown
in Figure 1: shift register, control logic, oscillator, real
time clock, and RAM. To initiate any transfer of data,
RST is taken high and eight bits are loaded into the shift
register providing both address and command informa-
tion.DataisseriallyinputontherisingedgeoftheSCLK.
The first eight bits specify which of 32 bytes will be ac-
cessed, whether a read or write cycle will take place,
and whether a byte or burst mode transfer is to occur.
After the first eight clock cycles have occurred which
loadthe command word into the shift register,additional
clocks will output data for a read or input data for a write.
COMMAND BYTE
The command byte is shown in Figure 2. Each data
transfer is initiated by a command byte. The MSB (Bit 7)
must be a logic 1. If it is zero, further action will be termi-
nated. Bit 6 specifies clock/calendar data if logic 0 or
RAM data if logic 1. Bits one through five specify the
designated registers to be input or output, and the LSB
(Bit 0) specifies a write operation (input) if logic 0 or read
operation (output) if logic 1. The command byte is al-
ways input starting with the LSB (bit 0).
DS1202 BLOCK DIAGRAM Figure 1
32.768 KHz
X1
X2
I/O
OSCILLATOR
AND DIVIDER
REAL TIME
CLOCK
INPUT SHIFT
REGISTERS
DATA BUS
SCLK
RST
COMMAND AND
CONTROL LOGIC
24 X 8 RAM
ADDRESS BUS
ADDRESS/COMMAND BYTE Figure 2
7
6
5
4
3
2
1
0
RAM
RD
1
A4
A3
A2
A1
A0
CK
W
032697 2/11
DS1202, DS1202S
Each byte that is written to will be transferred to RAM
regardless of whether all 24 bytes are written or not.
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input
high. The RST input serves two functions. First, RST
turnsonthecontrollogicwhichallowsaccesstotheshift
register for the address/command sequence. Second,
the RST signal provides a method of terminating either
singlebyteormultiplebytedatatransfer. A clock cycleis
a sequence of a falling edge followed by a rising edge.
For data inputs, data must be valid during the rising
edge of the clock and data bits are output on t he falling
edge of clock. All data transfer terminates if the RST in-
put is low and the I/O pin goes to a high impedance
state. Data transfer is illustrated in Figure 3.
CLOCK/CALENDAR
The clock/calendar is contained in eight write/read reg-
isters as shown in Figure 4. Data contained in the clock/
calendar registers is in binary coded decimal format
(BCD).
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt
flag. When this bit is set to logic 1, the clock oscillator is
stopped and the DS1202 is placed into a low–power
standby mode with a current drain of not more than 100
nanoamps. When this bit is written to logic 0, the clock
will start.
DATA INPUT
Following the eight SCLK cycles that input a write com-
mand byte, a data byte is input on the rising edge of the
next eight SCLK cycles. Additional SCLK cycles are ig-
nored should they inadvertently occur. Data is input
startingwith bit 0. Due to the inherent nature of the logic
state machine, writing times containing an absolute
value of “59” seconds should be avoided.
AM–PM/12–24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hourmode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10 hour bit (20–23 hours).
DATA OUTPUT
Following the eight SCLK cycles that input a read com-
mand byte, a data byte is output on the falling edge of
the next eight SCLK cycles. Note that the first data bit to
be transmitted occurs on the first falling edge after the
last bit of the command byte is written. Additional SCLK
cycles retransmit the data bytes should they inadver-
tently occur so long as RST remains high. This opera-
tion permits continuous burst mode read capability.
Data is output starting with bit 0.
WRITE PROTECT BIT
Bit 7 of the control register is the write protect bit. The
first seven bits (bits 0–6) are forced to zero and will al-
ways read a zero when read. Before any writeoperation
to the clock or RAM, bit 7 must be zero. When high, the
write protect bit prevents a write operation to any other
register.
CLOCK/CALENDAR BURST MODE
BURST MODE
The clock/calendar command byte specifies burst
mode operation. In this mode the eight clock/calendar
registers can be consecutively read or written (see Fig-
ure 4) starting with bit 0 of address 0.
Burst mode may be specified for either the clock/calen-
darortheRAMregistersbyaddressinglocation31deci-
mal (address/command bits one through five = logical
one). As before, bit six specified clock or RAM and bit 0
specifies read or write. There is no data storage capac-
ity at locations 8 through 31 in the Clock/Calendar Reg-
isters or locations 24 through 31 in the RAM registers.
When writing to the clock registers in the burst mode,
the first eight registers must be written in order for the
data to be transferred.
RAM
The static RAM is 24 x 8 bytes addressed consecutively
in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode opera-
tion. In this mode, the 24 RAM registers can be consec-
utively read or written (see Figure 4) starting with bit 0 of
address 0.
However, when writing to RAM in burst mode it is not
necessary to write all 24 bytes for the data to transfer.
032697 3/11
DS1202, DS1202S
pins. There is no need for external capacitors or resis-
tors. Note: X1 and X2 are very high impedance nodes.
It is recommended that they and the crystal be guard–
ringed with ground and that high frequency signals be
kept away from the crystal area. For more information
on crystal selection and crystal layout considerations,
please consult Application Note 58, “Crystal Consider-
ations with Dallas Real Time Clocks”.
REGISTER SUMMARY
A register data format summary is shown in Figure 4.
CRYSTAL SELECTION
A 32.768 KHz crystal, can be directly connected to the
DS1202 via pins 2 and 3 (X1, X2). The crystal selected
foruseshouldhaveaspecifiedloadcapacitance(CL)of
6 pF. The crystal is connected directly to the X1 and X2
DATA TRANSFER SUMMARY Figure 3
SINGLE BYTE TRANSFER
SCLK
RST
0
1
2
3
4
5
6
7
1
0
1
2
3
4
5
6
7
R/W
R/C
I/O
A0
A1
A2
A3
A4
ADDRESS COMMAND
DATA INPUT/OUTPUT
BURST MODE TRANSFER
SCLK
RST
0
1
1
2
1
3
1
4
1
5
1
6
7
1
0
1
2
4
5
6
7
R/W
R/C
I/O
ADDRESS COMMAND
DATA I/O BYTE 1
DATA I/O BYTE N
FUNCTION
BYTE N
SCLK n
72
CLOCK
RAM
8
24
200
032697 4/11
DS1202, DS1202S
REGISTER ADDRESS/DEFINITION Figure 4
REGISTER ADDRESS
A. CLOCK
REGISTER DEFINITION
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
RD
SEC
MIN
00–59 CH
10 SEC
10 MIN
SEC
W
W
W
W
W
W
W
W
W
RD
RD
RD
RD
RD
RD
RD
RD
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
00–59
0
MIN
HR
10
01–12 12/
00–23 24
HR
0
0
0
0
HR
A/P
01–28/29
01–30
01–31
DATE
0
0
0
10 DATE
DATE
MONTH
10
M
MONTH
DAY
01–12
01–07
0–99
0
0
0
0
DAY
YEAR
10 YEAR
YEAR
CONTROL
WP
FORCED TO ZERO
CLOCK
BURST
B. RAM
RD
RAM 0
1
1
0
0
0
0
0
RAM DATA 0
RAM DATA 23
W
RD
RD
RAM 23
1
1
1
1
1
1
0
1
1
1
1
1
1
1
W
W
RAM
BURST
032697 5/11
DS1202, DS1202S
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–0.3V to +7.0V
0°C to 70°C
Storage Temperature
Soldering Temperature
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
Supply Voltage
Logic 1 Input
SYMBOL
MIN
2.0
TYP
MAX
UNITS NOTES
V
5.5
V
V
1
1
CC
V
2.0
V
+0.3
IH
CC
V
=2.0V
–0.3
–0.3
+0.3
CC
Logic 0 Input
V
IL
V
1
V
=5V
+0.8
CC
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 2.0 to 5.5V*)
PARAMETER
Input Leakage
I/O Leakage
SYMBOL
MIN
TYP
MAX
+500
+500
UNITS NOTES
I
µA
µA
6
6
LI
I
LO
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
1.6
2.4
Logic 1 Output
V
V
V
2
3
OH
0.4
0.4
0.4
1.2
0.3
1
Logic 0 Output
V
OL
Active Supply Current
Timekeeping Current
I
mA
µA
nA
5
CC
I
4
CC1
CC2
100
100
Leakage Current
I
10
*Unless otherwise noted.
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL CONDITION
TYP
5
MAX
UNITS
NOTES
Input Capacitance
I/O Capacitance
Crystal Capacitance
C
pF
pF
pF
I
C
10
6
I/O
C
X
032697 6/11
DS1202, DS1202S
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 2.0 to 5.5V*)
PARAMETER
SYMBOL
MIN
200
50
TYP
MAX
UNITS NOTES
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
=2V
=5V
Data to CLK Setup
t
ns
ns
7
7
DC
280
70
CLK to Data Hold
CLK to Data Delay
CLK Low Time
t
t
CDH
CDD
800
200
ns
7, 8, 9
7
1000
250
t
ns
CL
1000
250
CLK High Time
t
ns
7, 12
7, 12
CH
0.5
2.0
CLK Frequency
CLK Rise and Fall
RST to CLK Setup
CLK to RST Hold
RST Inactive Time
f
MHz
ns
CLK
DC
2000
500
t , t
R
F
4
1
t
µs
7
7
7
7
CC
1000
250
4
t
ns
CCH
t
µs
CWH
1
280
70
RST to I/O High Z
t
ns
CDZ
*Unless otherwise noted.
032697 7/11
DS1202, DS1202S
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
RESET
t
CC
CLOCK
t
t
CDD
CDH
t
t
CDZ
DC
DATA INPUT/
OUTPUT
0
1
7
COMMAND BYTE
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
t
CWH
RESET
t
CC
t
CCH
t
R
t
CL
t
F
CLOCK
t
CDH
t
CH
t
DC
DATA INPUT/
OUTPUT
0
1
7
COMMAND BYTE
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at V =5V and 0.4 mA at V =2V, V =V for
CC
CC
OH
CC
capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at V =5V and 1.5 mA at V =2V.
CC
CC
4. I
is specified with I/O open, RST set to a logic 0, and clock halt flag=0 (oscillator enabled).
CC1
5. I is specified with the I/O pin open, RST high, SCLK=2 MHz at V =5V; SCLK=500 KHz, V =2V and clock
CC
CC
CC
halt flag=0 (oscillator enabled).
6. RST, SCLK, and I/O all have 40KΩ pull–down resistors to ground.
7. Measured at V =2.0V or V =0.8V and 10 ms maximum rise and fall time.
IH
IL
8. Measured at V =2.4V or V =0.4V.
OH
OL
9. Load capacitance = 50 pF.
032697 8/11
DS1202, DS1202S
10.I
is specified with RST, I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator disabled).
CC2
11. At power–up, RST must be at a logic 0 until V y2 volts. Also, SCLK must be at a logic 0 when RST is driven
CC
to a logic one state.
12.If t exceeds 100 ms with RST in a logic one state, then I may briefly exceed I specification.
CH
CC
CC
DS1202 SERIAL TIMEKEEPER 8–PIN DIP
8
5
PKG
DIM
8–PIN
MIN
MAX
B
A IN.
MM
0.360
0.240
0.120
0.300
0.015
0.110
0.090
0.320
0.008
0.015
0.400
B IN.
MM
0.260
0.140
0.325
0.040
0.140
0.110
0.370
0.012
0.021
C IN.
MM
1
4
A
D IN.
MM
E IN.
MM
C
F
F IN.
MM
G IN.
MM
K
E
G
H IN.
MM
J IN.
MM
K IN.
MM
D
J
H
032697 9/11
DS1202, DS1202S
DS1202S SERIAL TIMEKEEPER 16–PIN SOIC
K
G
F
phi
B
H
L
J
PKG
16–PIN
MIN
DIM
MAX
1
A IN.
MM
0.500
12.70
0.511
12.99
A
B IN.
MM
0.290
7.37
0.300
7.65
C
C IN.
MM
0.089
2.26
0.095
2.41
E
E IN.
MM
0.004
0.102
0.012
0.30
F IN.
MM
0.094
2.38
0.105
2.68
G IN.
MM
0.050 BSC
1.27 BSC
H IN.
MM
0.398
10.11
0.416
10.57
J IN.
MM
0.009
0.229
0.013
0.33
K IN.
MM
0.013
0.33
0.019
0.48
L IN
MM
0.016
0.406
0.040
1.20
phi
0°
8°
032697 10/11
DS1202, DS1202S
DS1202S8 8–PIN SOIC 200 MIL
K
G
J
F
H
B
0–8 deg. typ.
L
1
PKG
DIM
8–PIN
MIN
MAX
C
A IN.
MM
0.203
5.16
0.213
5.41
A
B IN.
MM
0.203
5.16
0.213
5.41
E
C IN.
MM
0.070
1.78
0.074
1.88
E IN.
MM
0.004
0.102
0.010
0.390
F IN.
MM
0.074
1.88
0.84
2.13
G IN.
MM
0.050 BSC
1.27 BSC
H IN.
MM
0.302
7.67
0.318
8.07
J IN.
MM
0.006
0.152
0.010
0.254
K IN.
MM
0.013
0.33
0.020
0.508
L IN.
MM
0.19
4.83
0.030
0.762
032697 11/11
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