DS1220AB-120-IND [DALLAS]
16k Nonvolatile SRAM; 16K非易失SRAM
| 型号： | DS1220AB-120-IND |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 16k Nonvolatile SRAM |
| 文件： | 总9页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1220AB/AD
16k Nonvolatile SRAM
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ 10 years minimum data retention in the
absence of external power
A7
A6
A5
A4
VCC
24
23
1
A8
A9
2
3
4
ꢀ Data is automatically protected during power
loss
ꢀ Directly replaces 2k x 8 volatile static RAM
or EEPROM
ꢀ Unlimited write cycles
ꢀ Low-power CMOS
ꢀ JEDEC standard 24-pin DIP package
ꢀ Read and write access times as fast as 100 ns
ꢀ Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
22
21
WE
OE
A3
A2
20
19
5
6
A10
CE
DQ7
DQ6
A1
A0
18
17
7
8
DQ0
9
16
DQ1
DQ2
GND
10
DQ5
DQ4
DQ3
15
14
11
12
13
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
ꢀ Full ±10% VCC operating range (DS1220AD)
ꢀ Optional ±5% VCC operating range
(DS1220AB)
ꢀ Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN DESCRIPTION
A0-A10
- Address Inputs
DQ0-DQ7
- Data In/Data Out
CE
- Chip Enable
- Write Enable
WE
OE
VCC
GND
- Output Enable
- Power (+5V)
- Ground
DESCRIPTION
The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs
organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs
directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of
the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance.
There is no limit on the number of write cycles that can be executed and no additional support circuitry is
required for microprocessor interfacing.
1 of 9
111899
DS1220AB/AD
READ MODE
The DS1220AB and DS1220AD execute a read cycle whenever WE (Write Enable) is inactive (high) and
CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11
address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within tACC (Access Time) after the last address input signal is
stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low)
after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE andOE
active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1220AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5V. The DS1220AD provides full functional capability for VCC greater than 4.5 volts and write protects
by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The
nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1220AB and 4.5 volts for the
DS1220AD.
FRESHNESS SEAL
Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP, the lithium
energy source is enabled for battery backup operation.
2 of 9
DS1220AB/AD
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C; -40°C to +85°C for IND parts
-40°C to +70°C; -40°C to +85°C for IND parts
260°C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
DS 1220AB Power Supply Voltage
DS 1220AD Power Supply Voltage
Logic 1
VCC
VCC
VIH
VIL
4.75 5.0
4.50 5.0
2.2
5.25
5.50
VCC
+0.8
V
V
V
V
Logic 0
0.0
(VCC =5V ± 5% for DS1220AB)
(TA: See Note 10)
DC ELECTRICAL CHARACTERISTICS
(VCC =5V ± 10% for DS1220AD)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current
I/O Leakage Current
-1.0
-1.0
IIL
+1.0
µA
IIO
+1.0
µA
CE ≥ VIH ≤ VCC
Output Current @ 2.4V
Output Current @ 0.4V
IOH
IOL
ICCS1
-1.0
2.0
mA
mA
mA
5.0
3.0
10.0
5.0
Standby Current CE = 2.2V
ICCS2
mA
Standby Current CE = VCC-0.5V
Operating Current tCYC=200 ns
(Commercial)
Operating Current tCYC=200ns
(Industrial)
Write Protection Voltage
(DS1220AB)
Write Protection Voltage
(DS1220AD)
ICC01
75
85
mA
ICCO1
VTP
mA
V
4.5
4.62 4.75
4.37 4.5
4.25
VTP
V
CAPACITANCE
(TA =25°C)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance
Input/Output Capacitance
CIN
CI/O
5
5
10
12
pF
pF
3 of 9
DS1220AB/AD
(VCC =5.0V ± 5% for DS1220AB)
(TA: See Note 10)
AC ELECTRICAL CHARACTERISTICS
(VCC =5.0V ± 10% for DS1220AD)
DS1220AB-100 DS1220AB-120
DS1220AD-100 DS1220AD-120
PARAMETER
SYMBOL
UNITS NOTES
MIN
MAX
MIN
MAX
Read Cycle Time
Access Time
tRC
tACC
tOE
100
120
ns
ns
ns
100
50
120
60
OE to Output Valid
CE to Output Valid
100
tCO
120
ns
5
5
tCOE
5
5
ns
5
5
OE or CE to Output Active
Output High Z from
Deselection
Output Hold from Address
Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
35
tOD
35
ns
tOH
tWC
tWP
tAW
tWR1
tWR2
ns
100
75
0
0
10
120
90
0
0
10
ns
ns
ns
ns
ns
3
12
13
35
tODW
tOEW
tDS
tDH1
tDH2
35
ns
ns
ns
ns
ns
5
4
4
12
13
Output High from WE
5
5
50
0
Output Active from WE
Data Setup Time
Data Hold Time
40
0
10
10
4 of 9
DS1220AB/AD
AC ELECTRICAL CHARACTERISTICS
(cont’d)
DS1220AB-150 DS1220AB-200
DS1220AD-150 DS1220AD-200
PARAMETER
SYMBOL
UNITS NOTES
MIN
MAX
MIN
MAX
Read Cycle Time
Access Time
tRC
tACC
tOE
150
200
ns
ns
ns
150
70
200
100
200
OE to Output Valid
CE to Output Valid
150
tCO
ns
5
5
tCOE
5
5
ns
5
5
OE or CE to Output Active
Output High Z from
Deselection
Output Hold from Address
Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
35
tOD
35
ns
tOH
tWC
tWP
tAW
tWR1
tWR2
ns
150
100
0
0
10
200
150
0
0
10
ns
ns
ns
ns
ns
3
12
13
35
tODW
tOEW
tDS
tDH1
tDH2
35
ns
ns
ns
ns
ns
5
4
4
12
13
Output High Z from WE
5
5
50
0
Output Active from WE
Data Setup Time
Data Hold Time
60
0
10
10
5 of 9
DS1220AB/AD
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
6 of 9
DS1220AB/AD
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(tA: See Note 10)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
0
11
tPD
tF
tR
µs
µs
µs
ms
CE at VIH before Power-Down
VCC slew from VTP to 0v
VCC slew from 0V to VTP
300
300
2
tREC
125
CE at VIH after Power-Up
(TA =25°C)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
tDR 10 years
Expected Data Retention Time
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or CE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7 of 9
DS1220AB/AD
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1220AB and each DS1220AD has a built-in switch that disconnects the lithium source until
VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of
VCC starting from the time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power down condition the voltage on any pin may not exceed the voltage on VCC
12. tWR1 , tDH1 are measured from WE going high.
.
13. tWR2 , tDH2 are measured from CE going high.
14. DS1220AB and DS1220AD modules are recognized by Underwriters Laboratory (U.L. ) under file
E99151.
DC TEST CONDITIONS
Outputs Open
All Voltages Are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
8 of 9
DS1220AB/AD
DS1220AB/AD NONVOLATILE SRAM, 24-PIN 720-MIL EXTENDED MODULE
PKG
DIM
24-PIN
MIN
MAX
A IN. 1.320
1.340
34.04
0.720
18.29
0.415
10.54
0.130
3.30
0.030
0.76
0.160
4.06
MM
B IN.
MM
C IN.
MM
33.53
0.695
17.65
0.390
9.91
D IN. 0.100
MM
E IN.
MM
F IN.
MM
2.54
0.017
0.43
0.120
3.05
G IN. 0.090
0.110
2.79
0.630
16.00
0.012
0.30
MM
H IN
MM
J IN.
MM
2.29
0.590
14.99
0.008
0.20
K IN. 0.015
MM 0.38
0.021
0.53
9 of 9
相关型号：
DS1220AB-150+
Non-Volatile SRAM Module, 2KX8, 150ns, CMOS, 0.720 INCH, ROHS COMPLIANT, PLASTIC, DIP-24
MAXIM
DS1220AB-150IND+
2KX8 NON-VOLATILE SRAM MODULE, 150ns, PDIP24, 0.720 INCH, PLASTIC, EXTENDED MODULE, DIP-24
ROCHESTER
DS1220AB-200IND+
Non-Volatile SRAM Module, 2KX8, 200ns, CMOS, 0.720 INCH, ROHS COMPLIANT, PLASTIC, DIP-24
MAXIM
©2020 ICPDF网 联系我们和版权申明