DS1220Y [DALLAS]
16k Nonvolatile SRAM; 16K非易失SRAM
| 型号： | DS1220Y |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | 16k Nonvolatile SRAM |
| 文件： | 总8页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1220Y
16k Nonvolatile SRAM
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ 10 years minimum data retention in the
absence of external power
A7
A6
A5
A4
VCC
24
23
1
A8
A9
2
3
4
ꢀ Data is automatically protected during power
loss
ꢀ Directly replaces 2k x 8 volatile static RAM
or EEPROM
ꢀ Unlimited write cycles
ꢀ Low-power CMOS
ꢀ JEDEC standard 24-pin DIP package
ꢀ Read and write access times as fast as 100 ns
ꢀ Full ±10% operating range
ꢀ Optional industrial temperature range of
-40°C to +85°C, designated IND
22
21
WE
OE
A10
CE
DQ7
DQ6
A3
A2
20
19
5
6
A1
A0
18
17
7
8
DQ0
9
16
DQ1
DQ2
GND
10
DQ5
DQ4
DQ3
15
14
11
12
13
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10
- Address Inputs
DQ0-DQ7
- Data In/Data Out
CE
- Chip Enable
- Write Enable
WE
OE
VCC
GND
- Output Enable
- Power (+5V)
- Ground
DESCRIPTION
The DS1220Y 16k Nonvolatile SRAM is a 16,384-bit, fully static, nonvolatile RAM organized as 2048
words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAM can be used in place of existing 2k x 8 SRAMs directly conforming to
the popular bytewide 24-pin DIP standard. The DS1220Y also matches the pinout of the 2716 EPROM or
the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
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111899
DS1220Y
READ MODE
The DS1220Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs
(A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or
tOE for OE rather than address access.
WRITE MODE
The DS1220Y executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be
kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1220Y provides full-functional capability for VCC greater than 4.5 volts and write protects at 4.25
nominal. Data is maintained in the absence of VCC without any additional support circuitry. The
DS1220Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write
protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 4.5 volts.
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DS1220Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.3V to +7.0V
0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature
Soldering Temperature
-40°C to +70°C; -40°C to +85°C for IND parts
260°C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA : See Note 10)
PARAMETER
Power Supply Voltage
Input Logic 1
SYMBOL
VCC
MIN
4.5
2.2
TYP
5.0
MAX UNITS NOTES
5.5
VCC
+0.8
V
V
V
VIH
Input Logic 0
VIL
0.0
DC ELECTRICAL CHARACTERISTICS
(TA : See Note 10; VCC = 5V ± 10%)
PARAMETER
SYMBOL
MIN
-1.0
-1.0
TYP
MAX UNITS NOTES
Input Leakage Current
IIL
+1.0
µA
µA
I/O Leakage Current
IIO
+1.0
CE ≥ VIH ≤ VCC
Output Current @ 2.4V
Output Current @ 0.4V
IOH
IOL
ICCS1
-1.0
2.0
mA
mA
mA
3.0
2.0
7.0
4.0
75
Standby Current CE =2.2V
ICCS2
ICCO1
mA
mA
Standby Current CE =VCC -0.5V
Operating Current tCYC= 200ns
(Commercial)
Operating Current tCYC=200ns
(Industrial)
Write Protection Voltage
ICCO1
VTP
85
mA
V
4.25
CAPACITANCE
PARAMETER
Input Capacitance
(T A = 25°C)
SYMBOL
CIN
MIN
TYP
5
5
MAX UNITS NOTES
10
12
pF
pF
Input/Output Capacitance
CI/O
3 of 8
DS1220Y
AC ELECTRICAL CHARACTERISTICS
(TA : See Note 10; VCC =5.0V ± 10%)
DS1220Y-100 DS1220Y-120
DS1220Y-150
DS1220Y-200
PARAMETER
SYM
UNITS NOTE
MIN MAX MIN MAX MIN
MAX
MIN
MAX
Read Cycle Time
Access Time
100
120
150
200
ns
ns
t
RC
100
50
120
60
150
70
200
100
t
ACC
OE to Output
Valid
ns
ns
t
OE
CE to Output
Valid
100
120
150
200
t
CO
OE or CE to
Output Active
5
5
5
5
5
5
5
5
ns
5
5
t
COE
Output High Z
from Deslection
Output Hold from
Address Change
Write Cycle Time
35
35
35
35
ns
ns
t
t
OD
OH
100
75
120
90
150
100
200
150
ns
ns
t
WC
Write Pulse Width
3
t
WP
Address Setup
Time
0
0
0
0
ns
t
AW
Write Recovery
Time
t
t
0
10
0
10
0
10
0
10
ns
ns
12
13
WR1
WR2
Output High Z
35
35
35
35
ns
5
t
ODW
from WE
Output Active
5
5
5
5
ns
ns
5
4
t
OEW
from WE
Data Setup Time
40
50
60
80
t
DS
Data Hold Time
t
0
10
0
10
0
10
0
10
ns
ns
12
13
DH1
DH2
t
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DS1220Y
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
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DS1220Y
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
MIN
MAX UNITS NOTES
tPD
0
11
µs
CE at VIH before Power-Down
VCC Slew from VTP to 0V
VCC Slew from 0V to VTP
tF
tR
100
0
µs
µs
tREC
2
ms
CE at VIH after Power-Up
(TA = 25°C)
PARAMETER
Expected Data Retention Time
SYMBOL
MIN
10
MAX UNITS NOTES
years
tDR
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL . If OE = VIH during a write cycle, the output buffers remain in a high impedance
state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in write
cycle 1, the output buffers remain in a high impedance state during this period.
6 of 8
DS1220Y
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS1220Y is marked with a 4-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected tDR is defined as starting at the date of
manufacture.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage of VCC
12. tWR1 , tDH1 are measured from WE going high.
.
13. tWR2 , tDH2 are measured from CE going high.
14. DS1220Y modules are recognized by Underwriters Laboratory (U.L. ) under file E99151 (R).
DC TEST CONDITIONS
Outputs open.
All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0-3.0V
Timing Measurement Reference Levels
Input:1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
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DS1220Y
DS1220Y NONVOLATILE SRAM, 24-PIN 720-MIL EXTENDED MODULE
PKG
DIM
24-PIN
MIN
MAX
A IN. 1.320
1.340
34.04
0.720
18.29
0.415
10.54
0.130
3.30
0.030
0.76
0.160
4.06
MM
B IN.
MM
C IN.
MM
33.53
0.695
17.65
0.390
9.91
D IN. 0.100
MM
E IN.
MM
F IN.
MM
2.54
0.017
0.43
0.120
3.05
G IN. 0.090
0.110
2.79
0.630
16.00
0.012
0.30
MM
H IN
MM
J IN.
MM
2.29
0.590
14.99
0.008
0.20
K IN. 0.015
MM 0.38
0.021
0.53
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